W78E51B
8-BIT MICROCONTROLLER
Publication Release Date: December 2000
- 1 - Revision A3
GENERAL DESCRIPTION
The W78E51B is an 8-bit microcontroller which can accommodate a wider frequency range with low
power consumption. The instruction set for the W78E51B is fully compatible with the standard 8051.
The W78E51B contains an 4K bytes Flash EPROM; a 128 bytes RAM; four 8-bit bi-directional and bit-
addressable I/O ports; an additional 4-bit I/O port P4; two 16-bit timer/counters; a hardware watchdog
timer and a serial port. These peripherals are supported by seven sources two-level interrupt
capability. To facilitate programming and verification, the Flash EPROM inside the W78E51B allows
the program memory to be programmed and read electronically. Once the code is confirmed, the user
can protect the code for security.
The W78E51B microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.
FEATURES
• Fully static design 8-bit CMOS microcontroller
• Wide supply voltage of 4.5V to 5.5V
• 128 bytes of on-chip scratchpad RAM
• 4 KB On-chip Flash EPROM
• 64 KB program memory address space
• 64 KB data memory address space
• Four 8-bit bi-directional ports
• One extra 4-bit bit-addressable I/O port, additional
INT2
/ INT3
(available on 44-pin PLCC/QFP package)
• Two 16-bit timer/counters
• One full duplex serial port(UART)
• Watchdog Timer
• Seven sources, two-level interrupt capability
• EMI reduction mode
• Built-in power management
• Code protection mechanism
• Packages:
− DIP 40: W78E51B-24/40
− PLCC 44: W78E51BP-24/40
− PQFP 44: W78E51BF-24/40
W78E51B
- 2 -
PIN CONFIGURATIONS
VDD1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
39
40
34
35
36
37
38
30
31
32
33
26
27
28
29
21
22
23
24
25
P0.0, AD0
P0.1, AD1
P0.2, AD2
P0.3, AD3
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
ALE
PSEN
P2.5, A13
P2.6, A14
P2.7, A15
P2.0, A8
P2.1, A9
P2.2, A10
P2.3, A11
P2.4, A12
P1.0
40-Pin DIP (W78E51B)
P1.2
P1.3
P1.4
P1.5
P1.6
RXD, P3.0
TXD, P3.1
P1.7
RST
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
WR, P3.6
RD, P3.7
XTAL1
XTAL2
VSS
P1.1
44-Pin PLCC (W78E51BP) 44-Pin QFP (W78E51BF)
34
4039 38 37 36 3544 43 42 41 33
32
31
30
29
28
27
26
25
24
23
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
22212019181716151413
12
11
4
3
2
1
8
7
6
5
10
9
P1.5
P1.6
P1.7
RST
RXD, P3.0
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
X
T
A
L
1
V
S
S
P
2
.
4
,
A
1
2
P
2
.
3
,
A
1
1
P
2
.
2
,
A
1
0
P
2
.
1
,
A
9
P
2
.
0
,
A
8
X
T
A
L
2
P
3
.
7
,
/
R
D
P
3
.
6
,
/
W
R
A
D
3
,
P
0
.
3
P
1
.
0
P
1
.
2
V
D
D
A
D
2
,
P
0
.
2
A
D
1
,
P
0
.
1
A
D
0
,
P
0
.
0
P
1
.
1
P
1
.
3
P
1
.
4
40
2 1 44 43 42 41
6 5 4 3 39
38
37
36
35
34
33
32
31
30
29
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
2827262524232221201918
17
10
9
8
7
14
13
12
11
16
15
P1.5
P1.6
P1.7
RST
RXD, P3.0
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
A
D
3
,
P
0
.
3
P
1
.
0
P
1
.
2
V
A
D
2
,
P
0
.
2
A
D
1
,
P
0
.
1
A
D
0
,
P
0
.
0
P
1
.
1
P
1
.
3
P
1
.
4
X
T
A
L
1
V
S
S
P
2
.
4
,
A
1
2
P
2
.
3
,
A
1
1
P
2
.
2
,
A
1
0
P
2
.
1
,
A
9
P
2
.
0
,
A
8
X
T
A
L
2
P
3
.
7
,
/
R
D
P
3
.
6
,
/
W
R
P
4
.
0
/
I
N
T
3
,
P
4
.
2
P4.1
P4.1
P
4
.
0
INT2, P4.3
INT2, P4.3
/
I
N
T
3
,
P
4
.
2D
D
W78E51B
Publication Release Date: December 2000
- 3 - Revision A3
PIN DESCRIPTION
SYMBOL
DESCRIPTIONS
EA
EXTERNAL ACCESS ENABLE
: This pin forces the processor to execute out of external
ROM. It should be kept high to access internal ROM. The ROM address and data will
not be presented on the bus if
EA
pin is high and the program counter is within on-chip
ROM area.
PSEN
PROGRAM STORE ENABLE:
PSEN
enables the external ROM data onto the Port 0
address/ data bus during fetch and MOVC operations. When internal ROM access is
performed, no
PSEN
strobe signal outputs from this pin.
ALE ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates
the address from the data on Port 0.
RST RESET: A high on this pin for two machine cycles while the oscillator is running resets
the device.
XTAL1 CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an external
clock.
XTAL2 CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1.
VSS GROUND: Ground potential
VDD POWER SUPPLY: Supply voltage for operation.
P0.0−P0.7
PORT 0: Port 0 is a bi-directional I/O port which also provides a multiplexed low order
address/data bus during accesses to external memory. The pins of Port 0 can be
individually configured to open-drain or standard port with internal pull-ups.
P1.0−P1.7
PORT 1: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have alternate
functions which are described below:
T2(P1.0): Timer/Counter 2 external count input
T2EX(P1.1): Timer/Counter 2 Reload/Capture control
P2.0−P2.7
PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides
the upper address bits for accesses to external memory.
P3.0−P3.7
PORT 3: Port 3 is a bi-directional I/O port with internal pull-ups. All bits have alternate
functions, which are described below:
RXD(P3.0) : Serial Port receiver input
TXD(P3.1) : Serial Port transmitter output
INT0 (P3.2) : External Interrupt 0
INT1
(P3.3) : External Interrupt 1
T0(P3.4) : Timer 0 External Input
T1(P3.5) : Timer 1 External Input
WR
(P3.6) : External Data Memory Write Strobe
RD
(P3.7) : External Data Memory Read Strobe
P4.0−P4.3
PORT 4: Another bit-addressable bidirectional I/O port P4. P4.3 and P4.2 are alternative
function pins. It can be used as general I/O port or external interrupt input sources
(
INT2
/INT3 ).
W78E51B
- 4 -
BLOCK DIAGRAM
P3.0
~
P3.7
P1.0
~
P1.7
ALU
Port 0
Latch
Port 1
Latch
Timer
1
Timer
0
Port
1
UART
XTAL1 PSENALE Vss
Vcc
RST
XTAL2
Oscillator
Interrupt
PSW
Instruction
Decoder
&
Sequencer
Reset Block
Bus & Clock
Controller
SFR RAM
Address
Power control
128 bytes
RAM & SFR
Stack
Pointer
B
Addr. Reg.
Incrementor
PC
DPTR
Temp Reg.
T2
T1
ACC
Port 3
Latch
Port 4
Latch
Port
3
Port 2
Latch
P4.0
~
P4.3 Port
4
Port
0
Port
2 P2.0
~
P2.7
P0.0
~
P0.7
INT2
INT3
Watchdog
Timer
ROM
FUNCTIONAL DESCRIPTION
The W78E51B architecture consists of a core controller surrounded by various registers, five general
purpose I/O ports, 128 bytes of RAM, two timer/counters, and a serial port. The processor supports
111 different opcodes and references both a 64K program address space and a 64K data storage
space.
New Defined Peripheral
In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupt
INT2
, INT3 has been added to either the PLCC or QFP 44 pin package. And description follows:
W78E51B
Publication Release Date: December 2000
- 5 - Revision A3
1.
INT2
/ INT3
Two additional external interrupts,
INT2
and INT3 , whose functions are similar to those of external
interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are determined/shown
by the bits in the XICON (External Interrupt Control) register. The XICON register is bit-addressable
but is not a standard register in the standard 80C52. Its address is at 0C0H. To set/clear bits in the
XICON register, one can use the "SETB (/CLR) bit" instruction. For example, "SETB 0C2H" sets the
EX2 bit of XICON.
XICON - external interrupt control (C0H)
PX3 EX3 IE3 IT3 PX2 EX2 IE2 IT2
PX3: External interrupt 3 priority high if set
EX3: External interrupt 3 enable if set
IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced
IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software
PX2: External interrupt 2 priority high if set
EX2: External interrupt 2 enable if set
IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced
IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software
Seven-source interrupt information:
INTERRUPT SOURCE
VECTOR
ADDRESS
POLLING
SEQUENCE WITHIN
PRIORITY LEVEL
ENABLE
REQUIRED
SETTINGS
INTERRUPT
TYPE
EDGE/LEVEL
External Interrupt 0 03H 0 (highest) IE.0 TCON.0
Timer/Counter 0 0BH 1 IE.1 -
External Interrupt 1 13H 2 IE.2 TCON.2
Timer/Counter 1 1BH 3 IE.3 -
Serial Port 23H 4 IE.4 -
External Interrupt 2 33H 5 XICON.2 XICON.0
External Interrupt 3 3BH 6 (lowest) XICON.6 XICON.3
2. PORT4
Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port
address is located at 0D8H with the same function as that of port P1, except the P4.3 and P4.2 are
alternative function pins. It can be used as general I/O pins or external interrupt input sources (
INT2
,
INT3 ).
Example:
P4 REG 0D8H
MOV P4, #0AH ; Output data "A" through P4.0−P4.3.
MOV A, P4 ; Read P4 status to Accumulator.
ORL P4,#00000001B ; Set bit P4.0
ANL P4,#11111101B ; Clear bit P4.1
W78E51B
- 6 -
3. Reduce EMI Emission
Because of on-chip Flash EPROM, when a program is running in internal ROM space, the ALE will be
unused. The transition of ALE will cause noise, so it can be turned off to reduce the EMI emission if it
is useless. Turning off the ALE signal transition only requires setting the bit 0 of the AUXR SFR, which
is located at 08Eh. When ALE is turned off, it will be reactivated when the program accesses external
ROM/RAM data or jumps to execute an external ROM code. The ALE signal will turn off again after it
has been completely accessed or the program returns to internal ROM code space. The AO bit in the
AUXR register, when set, disables the ALE output. In order to reduce EMI emission from oscillation
circuitry, W78E51B allows user to diminish the gain of on-chip oscillator amplifiers by using
programmer to clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be decreased.
Care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain
may effect to external crystal operating improperly at high frequency above 24 MHz. The value of R
and C1, C2 may need adjustment while running at lower gain.
***AUXR - Auxiliary register (8EH)
- - - - - - - AO
AO: Turn off ALE output.
4. Power-off Flag
***PCON - Power control (87H)
- - - POF GF1 GF0 PD IDL
POF: Power off flag. Bit is set by hardware when power on reset. It can be cleared by software
to determine chip reset is a warm boot or cold boot.
GF1, GF0: These two bits are general-purpose flag bits for the user.
PD: Power down mode bit. Set it to enter power down mode.
IDL: Idle mode bit. Set it to enter idle mode.
The power-off flag is located at PCON.4. This bit is set when VDD has been applied to the part. It can
be used to determine if a reset is a warm boot or a cold boot if it is subsequently reset by software.
Watchdog Timer
The Watchdog timer is a free-running timer which can be programmed by the user to serve as a
system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide the
system clock. The divider output is selectable and determines the time-out interval. When the time-out
occurs a system reset can also be caused if it is enabled. The main use of the Watchdog timer is as a
system monitor. This is important in real-time control applications. In case of power glitches or electro-
magnetic interference, the processor may begin to execute errant code. If this is left unchecked the
entire system may crash. The watchdog time-out selection will result in different time-out values
depending on the clock speed. The Watchdog timer will de disabled on reset. In general, software
should restart the Watchdog timer to put it into a known state. The control bits that support the
Watchdog timer are discussed below.
W78E51B
Publication Release Date: December 2000
- 7 - Revision A3
Watchdog Timer Control Register
Bit: 7 6 5 4 3 2 1 0
ENW
CLRW
WIDL
- - PS2 PS1 PS0
Mnemonic: WDTC Address: 8FH
ENW : Enable watch-dog if set.
CLRW: Clear watch-dog timer and prescaler if set. This flag will be cleared automatically
WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is disabled
under IDLE mode. Default is cleared.
PS2, PS1, PS0: Watch-dog prescaler timer select. Prescaler is selected when set PS2~0 as follows:
PS2 PS1 PS0 PRESCALER SELECT
0 0 0 2
0 1 0 4
0 0 1 8
0 1 1 16
1 0 0 32
1 0 1 64
1 1 0 128
1 1 1 256
The time-out period is obtained using the following equation:
1
OSC 2PRESCALER 1000 12 mS
14
× × × ×
Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6
(CLRW). After 1 is written to this bit, the 14-bit timer, prescaler and this bit will be reset on the next
instruction cycle. The Watchdog timer is cleared on reset.
OSC 1/12 PRESCALER 14-BIT TIMER
CLEAR
CLRW
EXTERNAL
RESET
INTERNAL
RESET
WIDL
IDLE
ENW
Watchdog Timer Block Diagram
W78E51B
- 8 -
Typical Watch-dog time-out period when OSC = 20 MHz
PS2 PS1 PS0 WATCHDOG TIME-OUT PERIOD
0 0 0 19.66 mS
0 1 0 39.32 mS
0 0 1 78.64 mS
0 1 1 157.28 mS
1 0 0 314.57 mS
1 0 1 629.14 mS
1 1 0 1.25 S
1 1 1 2.50 S
Clock
The W78E51B is designed to be used with either a crystal oscillator or an external clock. Internally, the
clock is divided by two before it is used. This makes the W78E51B relatively insensitive to duty cycle
variations in the clock. The W78E51B incorporates a built-in crystal oscillator. To make the oscillator
work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load capacitor must
be connected from each pin to ground. An external clock source should be connected to pin XTAL1.
Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as required by the
crystal oscillator.
Power Management
Idle Mode
The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal
clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.
Power-down Mode
When the PD bit of the PCON register is set, the processor enters the power-down mode. In this mode
all of the clocks are stopped, including the oscillator. The only way to exit power-down mode is by a
reset.
Reset
The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to
deglitch the reset line when the W78E51B is used with an external RC network. The reset logic also
has a special glitch removal circuit that ignores glitches on the reset line.
During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit
4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.
ON-CHIP ROM CHARACTERISTICS
The W78E51B has several modes to program the on-chip Flash EPROM. All these operations are
configured by the pins RST, ALE,
PSEN
, A9CTRL(P3.0), A13CTRL(P3.1), A14CTRL(P3.2),
OECTRL(P3.3), CE (P3.6), OE (P3.7), A0(P1.0) and VPP(
EA
). Moreover, the A15−A0(P2.7−P2.0,
P1.7−P1.0) and the D7−D0(P0.7−P0.0) serve as the address and data bus respectively for these
operations.
W78E51B
Publication Release Date: December 2000
- 9 - Revision A3
Read Operation
This operation is supported for customer to read their code and the Security bits. The data will not be
valid if the Lock bit is programmed to low.
Output Disable Condition
When the OE is set to high, no data output appears on the D7..D0.
Program Operation
This operation is used to program the data to ROM and the security bits. Program operation is done
when the VPP is reach to VCP (12.5V) level, CE set to low, and OE set to high.
Program Verify Operation
All the programming data must be checked after program operations. This operation should be
performed after each byte is programmed; it will ensure a substantial program margin.
Erase Operation
An erase operation is the only way to change data from 0 to 1. This operation will erase all the ROM
cells and the security bits from 0 to 1. This erase operation is done when the VPP is reach to VEP level,
CE set to low, and OE set to high.
Erase Verify Operation
After an erase operation, all of the bytes in the chip must be verified to check whether they have been
successfully erased to 1 or not. The erase verify operation automatically ensures a substantial erase
margin. This operation will be done after the erase operation if VPP = VEP (14.5V), CE is high and OE
is low.
Program/Erase Inhibit Operation
This operation allows parallel erasing or programming of multiple chips with different data. When
P3.6(CE ) = VIH, P3.7(OE ) = VIH, erasing or programming of non-targeted chips is inhibited. So,
except for the P3.6 and P3.7 pins, the individual chips may have common inputs.
W78E51B
- 10 -
OPERATIONS
P3.0
(A9
CTRL)
P3.1
(A13
CTRL)
P3.2
(A14
CTRL)
P3.3
(OE
CTRL)
P3.6
(CE)
P3.7
(OE)
EA
(VPP)
P2, P1
(A15..A0)
P0
(D7..D0)
NOTE
Read 0 0 0 0 0 0 1 Address
Data Out
Output Disable
0 0 0 0 0 1 1 X Hi-Z
Program 0 0 0 0 0 1 VCP
Address
Data In
Program Verify
0 0 0 0 1 0 VCP
Address
Data Out
@3
Erase 1 0 0 0 0 1 VEP
A0:0,
others: X
Data In
0FFH @4
Erase Verify 1 0 0 0 1 0 VEP
Address
Data Out
@5
Program/Erase
Inhibit X 0 0 0 1 1 VCP/
VEP
X X
Notes:
1. All these operations happen in RST = VIH, ALE = VIL and PSEN = VIH.
2. VCP = 12.5V, VEP = 14.5V, VIH = VDD, VIL = Vss.
3. The program verify operation follows behind the program operation.
4. This erase operation will erase all the on-chip Flash EPROM cells and the Security bits.
5. The erase verify operation follows behind the erase operation.
SECURITY BITS
During the programmer operation mode, the Flash EPROM can be programmed and verified
repeatedly. Until the code inside the Flash EPROM is confirmed OK, the code can be protected. The
protection of Flash EPROM and those operations on it are described below. The W78E51B has a
Special Setting Register, the Security Register, which can be accessed in normal mode. The
register can only be accessed from the Flash EPROM operation mode. Those bits of the Security
Registers can not be changed once they have been programmed from high to low. They can only be
reset through erase-all operation. The Security Register is addressed in the Flash EPROM operation
mode by address #0FFFFh.
W78E51B
Publication Release Date: December 2000
- 11 - Revision A3
B0B1
B0 : Lock bit, logic 0 : active
B1 : MOVC inhibit,
logic 0 : the MOVC instruction in external memory
cannot access the code in internal memory.
logic 1 : no restriction.
Default 1 for all security bits.
Special Setting Register
D7 D6 D5 D4 D3 D2 D1 D0 Security Bits 4KB Flash EPROM
Program Memory
Reserved
Security Register 0FFFFh
0000h
0FFFh
Reserved B2
B2 : Encryption
logic 0 : the encryption logic enable
logic 1 : the encryption logic disable
Reserved bits must be kept in logic 1.
B7
B7 : Osillator Control
logic 0 : 1/2 gain
logic 1 : Full gain
Lock bit
This bit is used to protect the customer's program code in the W78E51B. It may be set after the
programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the
on-chip ROM data and Special Setting Registers can not be accessed again.
MOVC Inhibit
This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC
instruction in external program memory from reading the internal program code. When this bit is set to
logic 0, a MOVC instruction in external program memory space will be able to access code only in the
external memory, not in the internal memory. A MOVC instruction in internal program memory space
will always be able to access the ROM data in both internal and external memory. If this bit is logic 1,
there are no restrictions on the MOVC instruction.
Encryption
This bit is used to enable/disable the encryption logic for code protection. Once encryption feature is
enabled, the data presented on port 0 will be encoded via encryption logic. Only whole chip erase will
reset this bit.
P1
P3.0
P3.1
P3.2
P3.3
P3.6
P3.7
X'tal1
X'tal2
P0
EA/Vpp
ALE
RST
PSEN
P2
Vss
A0 to A7
VCP
VIL
VIH
VIL
VIL
VIL
VIL
VIL
A8 to A15
PGM DATA
VIH
VIH
+5V
Programming Configuration
VDD
P1
P3.0
P3.1
P3.2
P3.3
P3.6
P3.7
X'tal1
X'tal2
P0
EA/Vpp
ALE
RST
PSEN
P2
Vss
A0 to A7
VCP
VIL
VIH
VIL
VIL
VIL
VIL
VIL
A8 to A15
PGM DATA
VIH
VIH
+5V
Programming Verification
VDD
W78E51B
- 12 -
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL MIN. MAX. UNIT
DC Power Supply VDD−VSS -0.3 +7.0 V
Input Voltage VIN VSS -0.3 VDD +0.3 V
Operating Temperature TA 0 70 °C
Storage Temperature TST -55 +150 °C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
DC CHARACTERISTICS
VCC−VSS = 5V ±10%, TA = 25° C, unless otherwise specified.
PARAMETER SYMBOL
TEST CONDITIONS
SPECIFICATION UNIT
MIN. MAX.
Operating Voltage VDD 4.5 5.5 V
Operating Current IDD No load VDD = 5.5V - 20 mA
Idle Current IIDLE Idle mode VDD = 5.5V
- 6 mA
Power Down Current IPWDN Power-down mode
VDD = 5.5V - 50 µA
Input Current
P1, P2, P3, P4 IIN1 VDD = 5.5V
VIN = 0V or VDD -50 +10 µA
Logical 1-to-0 Transition
Current P1, P2, P3(*1), P4
ITL VDD = 5.5V
VIN = 2.0V (*1)
-550 - µA
Input Current
RST (*2)
IIN2 VDD = 5.5V
VIN = VDD -10 +300 µA
Input Leakage Current
P0,
EA
ILK VDD = 5.5V
0V < VIN < VDD -10 +10 µA
Output Low Voltage
P1, P2, P3, P4 VOL1 VDD = 4.5V
IOL1 = +2 mA - 0.45 V
Output Low Voltage
ALE,
PSEN
, P0 (*3)
VOL2 VDD = 4.5V
IOL2 = +4 mA - 0.45 V
Output High Voltage
P1, P2, P3, P4 VOH1 VDD = 4.5V
IOH1 = -100 µA 2.4 - V
Output High Voltage
ALE,
PSEN
, P0 (*3)
VOH2 VDD = 4.5V
IOH2 = -400 µA 2.4 - V
W78E51B
Publication Release Date: December 2000
- 13 - Revision A3
DC Characteristics, continued
PARAMETER SYMBOL
TEST CONDITIONS
SPECIFICATION UNIT
MIN. MAX.
Input Low Voltage
(Except RST) VIL1 VDD = 4.5V 0 0.8 V
Input Low Voltage
RST (*4)
VIL2 VDD = 4.5V 0 0.8 V
Input Low Voltage
XTAL1 (*4)
VIL3 VDD = 4.5V 0 0.8 V
Input High Voltage
(Except RST) VIH1 VDD = 4.5V 2.4 VDD +0.2
V
Sink Current
P1, P2, P3, P4 ISK1 VDD = 4.5V
Vs = 0.45V 4 12 mA
Input High Voltage
RST (*4)
VIH2 VDD = 4.5V 0.67 VDD
VDD +0.2
V
Input High Voltage
XTAL1 (*4)
VIH3 VDD = 4.5V 0.67 VDD
VDD +0.2
V
Sink Current
P0, ALE, PSEN (*3)
ISK2 VDD = 4.5V
Vs = 0.45V 8 16 mA
Source Current
P1, P2, P3, P4 ISR1 VDD = 4.5V
VS = 2.4V -100 -250 uA
Source Current
P0, ALE, PSEN (*3)
ISR2 VDD = 4.5V
Vs = 2.4V -8 -14 mA
Notes:
*1. Pins P1, P2 and P3 source a transition current when they are being externally driven from 1 to 0. The transition current
reaches its maximum value when VIN is approximately 2V.
*2. RST pin has an internal pull-down resistor.
*3. P0, ALE,
PSEN
are in the external access memory mode.
*4. XTAL1 is a CMOS input and RST is a Schmitt trigger input.
AC CHARACTERISTICS
The AC specifications are a function of the particular process used to manufacture the part, the ratings
of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications
can be expressed in terms of multiple input clock periods (TCP), and actual parts will usually
experience less than a ±20 nS variation. The numbers below represent the performance expected
from a 0.6micron CMOS process when using 2 and 4 mA output buffers.
W78E51B
- 14 -
Clock Input Waveform
T
T
XTAL1
F
CH CL
OP, TCP
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES
Operating Speed FOP 0 - 40 MHz 1
Clock Period TCP 25 - - nS 2
Clock High TCH 10 - - nS 3
Clock Low TCL 10 - - nS 3
Notes:
1. The clock may be stopped indefinitely in either state.
2. The TCP specification is used as a reference in other specifications.
3. There are no duty cycle requirements on the XTAL1 input.
Program Fetch Cycle
PARAMETER SYMBOL MIN. TYP. MAX.
UNIT NOTES
Address Valid to ALE Low TAAS 1 TCP -∆
- - nS 4
Address Hold from ALE Low TAAH 1 TCP -∆
- - nS 1, 4
ALE Low to
PSEN
Low TAPL 1 TCP -∆
- - nS 4
PSEN
Low to Data Valid TPDA - - 2 TCP
nS 2
Data Hold after
PSEN
High TPDH 0 - 1 TCP
nS 3
Data Float after
PSEN
High TPDZ 0 - 1 TCP
nS
ALE Pulse Width TALW 2 TCP -∆
2 TCP
- nS 4
PSEN
Pulse Width TPSW 3 TCP -∆
3 TCP
- nS 4
Notes:
1. P0.0−P0.7, P2.0−P2.7 remain stable throughout entire memory cycle.
2. Memory access time is 3 TCP.
3. Data have been latched internally prior to
PSEN
going high.
4. "∆" (due to buffer driving delay and wire loading) is 20 nS.
Data Read Cycle
PARAMETER SYMBOL
MIN. TYP. MAX. UNIT NOTES
ALE Low to
RD
Low TDAR 3 TCP -∆
- 3 TCP +∆ nS 1, 2
RD
Low to Data Valid TDDA - - 4 TCP nS 1
Data Hold from
RD
High TDDH 0 - 2 TCP nS
Data Float from
RD
High TDDZ 0 - 2 TCP nS
RD
Pulse Width TDRD 6 TCP -∆
6 TCP
- nS 2
Notes:
1. Data memory access time is 8 TCP.
2. "∆" (due to buffer driving delay and wire loading) is 20 nS.
W78E51B
Publication Release Date: December 2000
- 15 - Revision A3
Data Write Cycle
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
ALE Low to
WR
Low TDAW 3 TCP -∆
- 3 TCP +∆
nS
Data Valid to
WR
Low TDAD 1 TCP -∆
- - nS
Data Hold from
WR
High TDWD 1 TCP -∆
- - nS
WR
Pulse Width TDWR 6 TCP -∆
6 TCP
- nS
Note: "∆" (due to buffer driving delay and wire loading) is 20 nS.
Port Access Cycle
PARAMETER SYMBOL MIN. TYP. MAX.
UNIT
Port Input Setup to ALE Low TPDS 1 TCP - - nS
Port Input Hold from ALE Low TPDH 0 - - nS
Port Output to ALE TPDA 1 TCP - - nS
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to
ALE, since it provides a convenient reference.
Program Operation
PARAMETER SYMBOL MIN. TYP. MAX.
UNIT
VPP Setup Time TVPS 2.0 - - µS
Data Setup Time TDS 2.0 - - µS
Data Hold Time TDH 2.0 - - µS
Address Setup Time TAS 2.0 - - µS
Address Hold Time TAH 0 - - µS
CE
Program Pulse Width for
Program Operation TPWP 290 300 310 µS
OECTRL Setup Time TOCS 2.0 - - µS
OECTRL Hold Time TOCH 2.0 - - µS
OE
Setup Time TOES 2.0 - - µS
OE
High to Output Float TDFP 0 - 130 nS
Data Valid from
OE
TOEV - - 150 nS
Note: Flash data can be accessed only in flash mode. The RST pin must pull in VIH status, the ALE pin must pull in VIL status,
and the
PSEN
pin must pull in VIH status.
W78E51B
- 16 -
TIMING WAVEFORMS
Program Fetch Cycle
S1
XTAL1
S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6
ALE
PORT 2
A0-A7
A0-A7 Data
A0-A7 Code
T
A0-A7 DataCode
PORT 0
PSEN
PDH, TPDZ
TPDA
TAAH
TAAS
TPSW
TAPL
TALW
Data Read Cycle
S2 S3S5 S6 S1S2 S3 S4S5 S6 S1S4
XTAL1
ALE
PSEN
DATA
A8-A15
PORT 2
PORT 0 A0-A7
RD TDDH, TDDZ
TDDA
TDRD
TDAR
W78E51B
Publication Release Date: December 2000
- 17 - Revision A3
Timing Waveforms, continued
Data Write Cycle
S2 S3S5 S6 S1S2 S3 S4S1S5 S6S4
XTAL1
ALE
PSEN
A8-A15
DATA OUT
PORT 2
PORT 0 A0-A7
WR T
TDAW
DAD
TDWR
TDWD
Port Access Cycle
XTAL1
ALE
S5 S6 S1
DATA OUT
T
T
PORT
INPUT
T
SAMPLE
PDA
PDHPDS
W78E51B
- 18 -
Timing Waveforms, continued
Program Operation
P2, P1
(A15... A0) Address Stable
VIH
VIL Address Valid
P3.6
(CE)
VIH
VIL
VIH
VIL
VIH
VIL Data In Data Out
Vpp
DOUT
Read Verify
Vcp
VIH
Program Program
Verify
TVPS
TDS
TDH
TAS
TAH
TPWP
TOES TDFP
TOEV
T
OCS
VIH
VIL TOCH
P3.7
(OE)
P0
(A7... A0)
P3.3
(OECTRL)
W78E51B
Publication Release Date: December 2000
- 19 - Revision A3
TYPICAL APPLICATION CIRCUITS
Expanded External Program Memory and Crystal
AD0
A0 A0 A0
10 A1
9 A2
8 A3
7 A4
6 A5
5 A6
4 A7
3 A8
25 A9
24 A10
21 A11
23 A12
2 A13
26 A14
27 A15
1
CE
20
OE
22
O0 11
O1 12
O2 13
O3 15
O4 16
O5 17
O6 18
O7 19
27512
AD0 D0
3 Q0 2
D1
4 Q1 5
D2
7 Q2 6
D3
8 Q3 9
D4
13 Q4 12
D5
14 Q5 15
D6
17 Q6 16
D7
18 Q7 19
OC
1
G
11
74373
AD0
EA
31
XTAL1
19
XTAL2
18
RST
9
INT0
12 INT1
13 T0
14 T1
15
P1.0
1 P1.1
2 P1.2
3 P1.3
4 P1.4
5 P1.5
6 P1.6
7 P1.7
8
39
38
37
36
35
34
33
32
21
22
23
24
25
26
27
28
17
WR
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
RD 16
PSEN 29
ALE 30
TXD 11
RXD 10
W78E51B
10 u
8.2 K
DD
CRYSTAL
C1 C2
R
AD1
AD2
AD3
AD4
AD5
AD6
AD7
A8
AD1
AD2
AD3
AD4
AD5
AD6
AD7
GND
A1
A2
A3
A4
A5
A6
A7
A1
A2
A3
A4
A5
A6
A7
A8
A9
AD1
AD2
AD3
AD4
AD5
AD6
AD7
A10
A11
A12
A13
A14
A15
GND
A9
A10
A11
A12
A13
A14
A15
V
DD
V
Figure A
CRYSTAL C1 C2 R
16 MHz 30P 30P -
24 MHz 15P 15P -
33 MHz 10P 10P 6.8K
40 MHz 5P 5P 4.7K
Above table shows the reference values for crystal applications (full gain).
Note: C1, C2, R components refer to Figure A.
W78E51B
- 20 -
Typical Application Circuits, continued
Expanded External Data Memory and Oscillator
10 u
8.2 K
DD
OSCILLATOR
EA
31
XTAL1
19
XTAL2
18
RST
9
INT0
12 INT1
13 T0
14
T1
15
1
2
3
4
5
6
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
7
P1.7
8
P0.0 39
P0.1 38
P0.2 37
P0.3 36
P0.4 35
P0.5 34
P0.6 33
P0.7 32
P2.0 21
P2.1 22
P2.2 23
P2.3 24
P2.4 25
P2.5 26
P2.6 27
P2.7 28
RD 17
WR 16
PSEN 29
ALE 30
TXD 11
RXD 10
W78E51B
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
A0
A1
A2
A3
A4
A5
A6
A7
D0
3 Q0 2
D1
4 Q1 5
D2
7 Q2 6
D3
8 Q3 9
D4
13 Q4 12
D5
14 Q5 15
D6
17 Q6 16
D7
18 Q7 19
OC
1
G
11
74373
A0
A1
A2
A3
A4
A5
A6
A7
10
9
8
7
6
5
4
3
A0
A1
A2
A3
A4
A5
A6
A7
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
11
12
13
15
16
17
18
19
D0
D1
D2
D3
D4
D5
D6
D7
A8
A9
A10
A11
A12
A13
A14
25
24
21
23
26
1
20
2
A8
A9
A10
A11
A12
A13
A14
CE
GND
A8
A9
A10
A11
A12
A13
A14
GND
22
27 OE
WR
20256
V
DD
V
Figure B
W78E51B
Publication Release Date: December 2000
- 21 - Revision A3
PACKAGE DIMENSIONS
40-pin DIP
Seating Plane
1. Dimension D Max. & S include mold flash or
tie bar burrs.
2. Dimension E1 does not include interlead flash.
3. Dimension D & E1 include mold mismatch and
are determined at the mold parting line.
6. General appearance spec. should be based on
final visual inspection spec.
.
1.3721.219
0.0540.048
Notes:
Symbol Min. Nom. Max. Max.
Nom.
Min.
Dimension in inch Dimension in mm
0.050 1.27
0.210 5.334
0.010
0.150
0.016
0.155
0.018
0.160
0.022
3.81
0.406
0.254
3.937
0.457
4.064
0.559
0.008
0.120
0.670
0.010
0.130
0.014
0.140
0.203
3.048
0.254
3.302
0.356
3.556
0.540 0.550
0.545 13.72 13.97
13.84
17.01
15.24
14.986 15.494
0.6000.590 0.610
2.286 2.54 2.7940.090 0.100 0.110
A
B
c
D
e
A
L
S
A
A1
2
E
B1
1
e
E1
a
2.055 2.070 52.20 52.58
0 15
0.090 2.286
0.650
0.630 16.00 16.51
protrusion/intrusion.
4. Dimension B1 does not include dambar
5. Controlling dimension: Inches.
150
eA
A
a
c
E
Base Plane
1
A
1
e
L
A
S
1
E
D
1
B
B
40 21
20
1
2
44-pin PLCC
44 40
39
29
2818
17
7
6 1
L
c
1b
2
A
H
D
D
eb
EHE
y
A
A1
Seating Plane
D
G
GE
Symbol Min. Nom. Max. Max.
Nom.
Min.
Dimension in inch Dimension in mm
A
e
HE
L
y
b
c
D
A
A1
2
E
b1
HD
G
GD
E
Notes:
on final visual inspection spec.
4. General appearance spec. should be based
3. Controlling dimension: Inches
protrusion/intrusion.
2. Dimension b1 does not include dambar
flash.
1. Dimension D & E do not include interlead
0.020
0.145
0.026
0.016
0.008
0.648
0.590
0.680
0.090
0.150
0.028
0.018
0.010
0.653
0.610
0.690
0.100
0.050 BSC
0.185
0.155
0.032
0.022
0.014
0.658
0.630
0.700
0.110
0.004
0.508
3.683
0.66
0.406
0.203
16.46
14.99
17.27
2.296
3.81
0.711
0.457
0.254
16.59
15.49
17.53
2.54
1.27
4.699
3.937
0.813
0.559
0.356
16.71
16.00
17.78
2.794
0.10
BSC
16.71
16.59
16.46
0.658
0.653
0.648
16.00
15.4914.99
0.6300.610
0.590
17.7817.53
17.27
0.700
0.690
0.680
θ
W78E51B
- 22 -
Package Dimensions, continued
44-pin PQFP
Seating Plane
11
22
12
See Detail F
eb
A
y1
AA
L
L1
c
EEH
1
D
44
H
D
34
33
Detail F
1. Dimension D & E do not include interlead
flash.
2. Dimension b does not include dambar
protrusion/intrusion.
3. Controlling dimension: Millimeter
4. General appearance spec. should be based
on final visual inspection spec.
0.2540.101
0.0100.004
Notes:
Symbol Min. Nom. Max. Max.
Nom.
Min.
Dimension in inch Dimension in mm
A
b
c
D
e
HD
HE
L
y
A
A
L1
1
2
E
0.006 0.152
---
0.002
0.075
0.01
0.081
0.014
0.087
0.018
1.90
0.25
0.05
2.05
0.35
2.20
0.45
0.390
0.025
0.063
0.003
07
0.394
0.031
0.398
0.037
9.9
0.80
0.65
1.6
10.00
0.8
10.1
0.95
0.3980.394
0.390
0.530
0.520
0.510 13.45
13.2
12.95
10.1
10.00
9.9
7
0
0.08
0.031
0.01 0.02 0.25 0.5
---
--- --- --- ---
θ
2
θ
0.025 0.036 0.635 0.952
0.530
0.520
0.510 13.45
13.2
12.95
0.051 0.075 1.295 1.905
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5792766
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd;
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: 408-9436666
FAX: 408-5441798
Note: All data and specifications are subject to change withou t notice.
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5792766
http://www.winbond.com.tw/
Voice & Fax-on-demand: 886-2-27197006
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd.,
Taipei, Taiwan
TEL: 886-2-27190505
FAX: 886-2-27197502
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd;
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Winbond Electronics North America Corp.
Winbond Memory Lab.
Winbond Microelectronics Corp.
Winbond Systems Lab.
2727 N. First Street, San Jose,
CA 95134, U.S.A.
TEL: 408-9436666
FAX: 408-5441798
Note: All data and specifications are subject to change withou t notice.
