INTEL CORPORATION ORDER NUMBER 245108-002
MO BILE PENTIUM
II PROCESSOR IN
MI NI-CARTRIDGE PACKAGE AT 400 MHZ, 366 MHZ,
333 MHZ, 300PE MHZ, AND 266PE M HZ DATASHEET
Availabl e at 400 MHz, 366 MHz, 333 MHz,
300PE M Hz, and 266PE MHz
Supports the Intel Architecture with
Dynamic Execution
Integrated prim ary 16-Kbyte instructi on
cache and 16-Kbyte write back data cache
Integrated second level cache (256 Kbytes)
Mini -cartri dge packagi ng technol ogy
— Supports thin form factor notebook
designs
— Exposed die enables more efficient heat
dissipation
Fully compatible with previous Intel
microprocessors
— Binary compatible with all applications
— Support for MM X ™ technology
Power Managem ent features
— Quick Start and Deep Sleep m odes
provide extremely low pow er
dissipation
Low Power GTL+ processor system bus
interface
Integrated math co-processor
Integrated thermal di ode and sensor
The Intel
mobil e P entium
II processor introduces a higher level of performanc e for today’s mobile
com put i ng envi ronment, i ncluding m ul timedi a enhancement s, and im proved Internet and c omm uni cations
capabilities. It provides an improved perform anc e 1 f or appl i cations runni ng on advanced operating system s
such as Windows* 98. On top of it s built-in power managem ent capabilities, the Pentium II proc essor takes
advantage of software designed for I ntel’s MMX
technology t o unl eash enhanced col or, smoot her graphi cs,
and other m ul t i media and comm uni cations enhancement s.
The mobil e P entium II proces sor may c ontain design def ects or errors know as errata that may caus e the
product to devi ate from publ i shed specificati ons. Current characterized errata are avai l abl e upon request.
1. Refer to the
Mobile Pentium
II Processor Performance Brief
.
MOBILE PENTIUM® II PROCESSOR IN MINI-CARTRIDGE PACKAGE
AT 400 MHZ, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ DATASHEET
ii INTEL CORPORATION
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document or by the sale of Intel products. Except as provided in
Intel's terms and conditions of sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or
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purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving or life sustaining applications.
Intel retains the right to make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions m ark ed “reserved” or “undefi ned.” Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from
future changes to them. Contact your local sales office or your distributor to obtain the latest specifications before placing your
product order.
The mobile Pentium II mini-cartridge processor may contain design defects or errors known as errata that may cause the
product to deviate from published specifications. Current characterized errata are available on request.
Third-party brands and names are the property of their respective ownersI2C is a two-wire communications bus/protocol developed by
Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol or the
SMBus bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips
Corporation. Copyright © Intel Corporation 1999.
* Third party brands and names are the property of their respective owners.
MPEG is an international standard for video compression/decompression promoted by ISO. Implementations of MPEG
CODECs, or MPEG enabled platforms may require licenses from various entities, including Intel Corporation.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained by calling 1-800-548-4725 or by visiting Intel’s website at http://www.intel.com.
MOBILE PENTIUM® II PROCESSOR IN MINI-CARTRIDGE PACKAGE
AT 400 MHZ, 366 MHZ, 333 MHZ, 300 MHZ, AND 266 MHZ DATASHEET
INTEL CORPORATION iii
CONTENTS
PAGE PAGE
1. INTRODUCTION..............................................1
1.1 Overview....................................................2
1.2 Terminology...............................................2
1.3 References ................................................2
2. MOBILE PENTIUM II MINI-CARTRIDGE
PROCESSOR FEATURES...............................4
2.1 New Features i n t he Mobil e Pentium II Mini-
cartridge Processor....................................4
2.1.1 Integrated L2 Cache.........................4
2.1.2 TRST# Pull-down Requirement ........4
2.2 Power Management...................................4
2.2.1 Clock Control Architecture................4
2.2.2 Normal State ....................................6
2.2.3 Auto Halt State .................................6
2.2.4 STOP GRANT State.........................7
2.2.5 QUICK START State........................7
2.2.6 HALT/GRANT SNOOP State............7
2.2.7 SLEEP State ....................................7
2.2.8 Deep Sleep State .............................8
2.2.9 Operat i ng System Im pl i cations of
Quick Start and Sleep States............8
2.3 Low Power GTL+ .......................................8
2.3.1 GTL+ Signals....................................9
2.4 Mobil e P entium II Mini-cartridge Proces sor
CPUID........................................................9
3. ELECTRICAL SPECIFICATIONS .................. 10
3.1 Processor System Signals.......................10
3.1.1 Test Ac cess Port (TAP) Connection11
3.1.2 Thermal Sensor..............................11
3.1.3 SMBus Pins.................................... 12
3.1.4 Catastrophic Thermal Protection ....12
3.1.5 Unused Signals ..............................12
3.1.6 S i gnal S tate in Low Power States... 12
3.2 Power Supply Requirements....................12
3.2.1 Decoupling Recommendations....... 12
3.2.2 P ower Sequenc i ng Requi rements... 13
3.3 Syst em Bus Cl ock and Processor Cl ocking13
3.4 Maxim um Ratings ....................................14
3.5 DC Specifications .....................................14
2.6 AC Specifications.....................................19
2.6.1 System Bus, Clock, APIC, TAP,
CMOS, and Open-drain AC
Specifications .................................19
4. SYSTEM SIGNAL SIMULATIONS.................32
4.1 Syst em Bus Cl ock (BCLK ) Signal Quality
Specifications...........................................32
4.2 Low Power GTL+ Signal Qual i ty
Specifications...........................................34
4.3 Non-Low Power GTL+ Signal Qual i t y
Specifications...........................................36
4.3.1 Overshoot and Undershoot
Guidelines.......................................36
4.3.2 Ringback Specification....................37
4.3.3 Settling Limit Guideline...................37
5. MECHANICAL SPECIFICATIONS .................39
5.1 Connector Mechanical Specifications.......39
5.2 Mini -cartridge As sembly Mechani cal
Specifications...........................................39
5.2 Processor Pin Lists..................................46
6. THERMAL SPECIFICATIONS........................53
7. PROCESSOR INITIALIZATION AND
CONFIGURATION..........................................54
7.1 Description...............................................54
7.1.1 Quick Start Enable..........................54
7.1.2 System Bus Frequency...................54
7.1.3 APIC Disable..................................54
7.2 Clock Frequencies and Ratios ..................54
8. PROCESSOR INTERFACE............................55
8.1 Alphabetical Signal Reference .................55
8.2 Signal Summaries....................................62
MOBILE PENTIUM® II PROCESSOR IN MINI-CARTRIDGE PACKAGE
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iv INTEL CORPORATION
LIST OF FIGURES
PAGE
Figure 1.1 Signal Groups of a Mobile Pent i um II
Mini-cartridge Process or B ased System1
Figure 2.1 Clock Control States.............................5
Figure 3.1 Ramp Rate Requirement.....................13
Figure 3.2 BCLK Connector to Core Offset..........26
Figure 3.3 Generic Clock W aveform.................... 26
Figure 3.4 Valid Delay Timings............................ 27
Figure 3.5 Setup and Hold Timings .....................27
Figure 3.6 Reset and Configuration Timings........28
Figure 3.7 Power-on Reset Timings ....................28
Figure 3.8 Test Timings (Boundary Scan) ........... 29
Figure 3.9 Test Reset Timings.............................29
Figure 3.10 Quick Start and Deep S l eep Ti ming.. 30
Figure 3.11 St op Grant, Sleep, and Deep Sleep
Timing................................................31
Figure 4.1 BCLK Generi c Cl ock Wavef orm at the
Processor Core.................................. 33
Figure 4.2 BCLK Generi c Cl ock Wavef orm at the
Processor Connector.........................34
Figure 4.3 Low to High, Low Power GTL+ Receiver
Ringback Tolerance........................... 35
Figure 4.4 Non-GTL+ Overshoot /Undershoot and
Ringback............................................37
Figure 5.1 Mini-cartridge Cross Sec t ion View...... 40
Figure 5.2. Mini-cartridge Assem bl y, Top Cover (i n
mm)...................................................41
Figure 5.3 Mini-cartridge Assembly, Bottom Cover
and Sides (in mm) .............................42
Figure 5.4 St andoff and Connect or Loc ation, Top
View (in mm)......................................43
Figure 5.5. Mini-cartridge Assem bl y and Connec tor
Keep-out Location, Top Vi ew (in mm) 44
Figure 5.6 Mini-cartridge Cross Section with
Vertical Dimensions...........................45
Figure 8.1 PWRGOOD Relat ionship at Power-on 59
MOBILE PENTIUM® II PROCESSOR IN MINI-CARTRIDGE PACKAGE
AT 400 MHZ, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ DATASHEET
INTEL CORPORATION V
LIST OF TABLES
PAGE PAGE
Table 2.1 Clock State Characteristics....................6
Table 2.2 Mobile Pentium II Processor CPUID.......9
Table 2.3 Mobile Pentium II Processor CPUI D
Cache and TLB Descriptors.................9
Table 3.1 System Signal Groups.........................10
Table 3.2 Recomm ended Resistors for Open-drain
Signals...............................................11
Table3.3 Mobile Pentium II Mini-cart ri dge
Processor Absolute Maximum Rat i ngs
..........................................................14
Table 3.4 Mobile Pentium II Processor Power
Specifications ....................................15
Table 3.5 Mobile Pentium II Processor Power
Specifications ....................................16
Table 3.6 Low Power GTL+ Signal Group DC
Specifications ....................................17
Table 3.7 Low Power GTL+ Bus DC Spec i f i cations
..........................................................18
Table 3.8 Cloc k, APIC, TAP, CMOS, and Open-
drain Signal Group DC S pecific ations 18
Table 3.9 Sys t em Bus Cl ock AC Specific ations. . . 19
Table 3.10 Vali d Mobil e Pentium® II Mini-cartridge
Processor Frequencies......................21
Table 3.11 Low Power GTL+ Signal Groups A C
Specifications ....................................21
Table 3.12 CMOS and Open-drain S i gnal Groups
AC Specifications ..............................22
Table 3.13 Reset Configuration A C S pecific ations
..........................................................22
Table 3.14 AP IC Bus Si gnal AC Specif i cations . ..23
Table 3.15 TAP Signal AC Specifications............ 24
Table 3.16 Quic k Start/Deep Sleep AC
Specifications ....................................25
Table 3.17 St op Grant/Sleep/ Deep Sleep AC
Specifications ....................................25
Table 4.1 BCLK S i gnal Qual i ty Specif i cations at the
Processor Core.................................. 32
Table 4.2 BCLK S i gnal Qual i ty Guidelines at the
Processor Connector.........................33
Table 4.3 Low Power GTL+ Signal Group Ringback
Specif i cation at the Processor Core...34
Table 4.4 Low Power GTL+ Signal Group Ringback
Guideline at the Processor Connector36
Table 4.5 Signal Ri ngback Spec i ficati ons for Non-
GTL+ Signals at the Proces s or Core. .38
Table 5.1 Mechanical Specifications....................40
Table 5.2. Mini-cartridge Vertical Dimensions......45
Table 5.3 Mini-cartridge Verti cal Dim ension
Definitions..........................................46
Table 5.4 Pin Listing in Signal Name Order.........48
Table 6.1 Mobile Pentium II Processor Power
Specifications.....................................53
Table 8.1 Voltage Identification Pin Encoding......62
Table 8.2 Input Signals........................................63
Table 8.3 Output Signals .....................................64
Table 8.4 Input/Output Signals (Single Driver).....64
Table 8.5. I nput/Output S i gnal s (Multiple Drivers) 65
MOBILE PENTIUM® II PROCESSOR IN MINI-CARTRIDGE PACKAGE
AT 400 MHZ, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ DATASHEET
INTEL CORPORATION 1
1. INTRODUCTION
The Mobile Pentium® II Processor is the first mobile
process or with an i nt egrated L2 cache within the
Pentium II processor f amily. The mobile P entium II
process or i s now offered at five speeds: 400 MHz,
366 MHz, 333 MHz, 300PE MHz, and 266PE MHz,
with a system bus s peed of 66 MHz. It c ons i sts of a
mobil e P entium II proces sor core with an integrated
L2 cache and a 64-bit high performance system
bus. The int egrated L2 cache is designed to hel p
improve performanc e, i t com pl ements the system
bus by providing c ri t i cal data faster and reducing
total s ystem power cons umption. The mobile
Pentium II mini-c artridge processor’s 64-bit wide
Low Power Gunning Transceiver Logic (GTL+)
system bus is com patible with the 440B X AGPS et
and provides a glue-less, point-to-point i nt erface for
an I/O bridge/memory control l er. Figure 1.1 shows
the various part s of a m obi l e Pentium II mini-
cartridge processor bas ed system and how the
mobil e P entium II m i ni -cartridge processor connec t s
to them.
Mobile
Pentium® II
Processor Core
443BX
North Br idge
PIIX4E
S outh B ri dge
PCI
ISA/EIO
TAP
CMOS /
Open-Drain
DRAM
System
Bus
Thermal
Sensor
SMBus
System
Controller
V0000-00
Mobile Pentium® II Mini-Cartridge Processor
or
Figure 1.1 Signal Groups of a Mobil e P enti u m II Mi ni-cartridge Processor Based System
MOBILE PENTIUM® II PROCESSOR IN MINI-CARTRIDGE PACKAGE
AT 400 MHZ, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ DATASHEET
2 INTEL CORPORATION
1.1 Overview
• Performance improved over existing mobile
processors
• Support s the Intel Architecture with Dynami c
Execution
• Support s the Intel Architecture MMX
technology
• Int egrated Intel Fl oat i ng-Point Unit
compatible with the IEEE Std 754
• Integrated pri mary (L1) instruction and data
caches
• 4-way set associ at ive, 32-byte li ne size,
1 line per sec tor
• 16-Kbyte instruction c ache and 16-Kbyte
writeback data cache
• Cacheable range programm abl e by
process or programm abl e regi sters
• Integrated on-di e second level (L2) c ache
• 4-way set associ at ive, 32-byte li ne size,
1 line per sec tor
• Operates at full c ore speed
• 256-Kbyte, ECC prot ected cac he data array
• 4-Gbyte c acheable range
• Low Power GTL+ system bus interface
• 64-bit data bus, 66-MHz operation
• Uniprocessor, t wo loads onl y (processor and
I/O bri dge/ memory control l er)
• Short trace length and l ow capac i t ance
allows for si ngl e ended termination
• Voltage reduc tion technol ogy
• Pentium II processor c l ock cont rol
• Quic k Start for low power, low exit lat ency
clock “throttl i ng”
• Deep Sleep mode for extrem el y l ow power
dissipation
• Thermal di ode and sensor for measuring
process or t emperature
1.2 Terminology
In this document a “#” symbol following a signal
name indi cates t hat the signal is active l ow. This
means t hat when the signal is asserted (bas ed on
the nam e of the signal) it is in an el ec trical low st ate.
Otherwise, s i gnal s are dri ven i n an el ectrical hi gh
state when they are as serted. I n state machine
diagrams, a signal name in a condi tion indicates the
conditi on of that signal bei ng asserted. If the si gnal
name is preceded by a “!” symbol, then it indicates
the condit i on of that s i gnal not being asserted. For
example, the condition “!STPCLK # and HS” is
equivalent t o “t he active low signal S T P CLK# is
unassert ed (i . e., it i s at 2.5V) and the HS condit i on
is true. ” The symbols “L” and “H” refer respec t i vel y
to elect ri cal low and electrical high si gnal l evel s. The
symbol s “0” and “1” refer respec tively to logi c al l ow
and logical hi gh signal levels . For example, B D[ 3:0]
= “1010” = “HLHL” refers to a hexadecimal “A”, and
D[3:0]# = “1010” = “LHLH” al so refers t o a
hexadecimal “A .”
1.3 References
Pentium
®
II Processor at 233 M Hz, 266 MHz, 300
MHz, and 333 MHz
(Order Number 243335)
Pentium
®
II Processor Dev el oper’s Manual
(Order Number 243502)
CKDM66-M Cl ock Driv er Specifi cation
(Contact your Intel Field Sales Representative)
CK97 Clock Driver S pecification
(Contact your Intel Field Sales Representative)
Intel A rchitecture Software Developer’s Manual
(Order Number 243193)
Volume I: Basic Architecture
(Order Number 243190)
Volume II: Instruction Set Reference
(Order Number 243191)
Volume III: System Programming Guide
(Order Number 243192)
MOBILE PENTIUM® II PROCESSOR IN MINI-CARTRIDGE PACKAGE
AT 400 MHZ, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ DATASHEET
INTEL CORPORATION 3
Mobile Pentium
®
II Processor I /O Buff er M odel s,
IBIS Format
(Available i n el ectronic f ormat; contact
your Intel Fi el d S al es Representat i ve)
Mobile Pentium
®
II Processor S ystem Bus Layout
Guideline
(Order Number 243672-001)
Mobile Pentium
®
II Mi ni -cartridge Proc essor
Mechanic al and Thermal User Guide (Reference
Number TBD)
Mobile Pentium
®
II Processor and P entium
®
II
Processor Mobile Modul e Thermal Sensor
Programming Interface Specificati ons
(Order
Number 243724-001)
MOBILE PENTIUM® II PROCESSOR IN MINI-CARTRIDGE PACKAGE
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4 INTEL CORPORATION
2. MOBILE PENTIUM
II
MINI-CARTRIDGE
PROCESSOR FEATURES
2.1 New Features in the Mobile
Pentium
II Mini-cartridge
Processor
2.1.1 Integrated L2 Cache
The mobil e P entium II proces sor has a 256-Kbyte
L2 cache integrated onto the processor die. The L2
cache is four-way set associati ve and runs at the
speed of the processor c ore.
2.1.2 TRST# Pull-down Requirement
The pull-down resist or on t he TRST# signal i s no
longer optional, it is now m andat ory. This pull -down
is not on t he mini-cartridge subs trate, it must be put
on the system electronics.
2.2 Power Management
2.2.1 Clock Control Architecture
The mobil e P entium II m i ni -cartridge processor
clock control architecture (Figure 2.1) has been
optimized for leading edge “Deep Green” des ktop
and mobil e comput er designs. The clock control
architecture cons i s ts of s even di fferent cl ock st ates:
Normal, Stop Grant, Auto Halt, Quick Start,
HALT/Grant Snoop, Sleep, and Deep Sleep states.
The Auto Halt state provides a low power clock st ate
that can be controlled t hrough the soft ware
execution of the HLT i nstruct i on. The Qui ck St art
state provi des a very low-power, low-exit lat ency
clock stat e t hat can be used f or hardware cont rol l ed
“idle” computer states. The Deep Sleep state
provides an extremel y l ow power state that can be
used for “Power-on Sus pend” comput er states,
which is an alt ernative to shut ting off t he processor’s
power. Compared to t he Pentium process or exit
latency of 1 msec , the exit latency of the Deep
Sleep st ate has been reduced t o 30
sec in the
mobil e P entium II m i ni -cartridge processor. The
Stop Grant and Sleep stat es shown are intended for
use in “Deep Green” desktop and server s ys tems —
not in mobile systems . Performing state transitions
not shown in Figure 2.1 are nei ther recom mended
nor supported.
The Stop Grant and Qui ck St art clock states are
mut ual l y exclus i ve, i .e., a strapping option on s i gnal
A15# chooses which stat e i s entered when the
STPCLK# signal is as serted. S t rappi ng the A15#
signal t o ground at Reset enables the Quick Start
state; otherwise, as serting the S T PCLK# signal puts
the proces s or i nto the St op Grant state. The S top
Grant state has a higher power level than t he Qui ck
Start state and is designed for S MP pl at forms . The
Quick S tart st ate has a m uch lower power level, but
it can onl y be used in uniproces sor platforms. Tabl e
2.1 provides clock state c harac teristi cs (power
numbers based on estimates f or a mobile P entium II
process or runni ng at 400 MHz), whic h are des cribed
in detail i n the following sec tions.
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INTEL CORPORATION 5
HALT/Grant
Snoop
Normal
HS=false
Stop
Grant
Auto
Halt
HS=true
Quick
Start
Sleep
Deep
Sleep
(!STPCLK#
and !HS) or
stop break
STPCLK# and
!QSE and SGA
Snoop
occurs
Snoop
serviced
STPCLK# and
QSE and SGA
(!STPCLK# and !HS)
or RESET#
Snoop
serviced Snoop
occurs
!STPCLK#
and HS
STPCLK# and
!QSE and SGA
HLT and
halt bus cycle
halt
break
Snoop
serviced
Snoop
occurs
STPCLK# and
QSE and SGA
!STPCLK#
and HS
!SLP# or
RESET#
SLP#
BCLK
stopped
BCLK on
and !QSE
BCLK
stopped
BCLK on
and QSE
V0001-00
NOTES: halt break - A20M#, BINIT#, FLUSH#, INIT#, INTR, NMI, PREQ#, RESET#, SMI#
HLT - HLT instruc t i on executed
HS - Proc essor Halt State
QSE - Quic k Start State Enabl ed
SGA - Stop Grant Acknowledge bus cycle issued
Stop break - BINIT#, FLUSH#, RESET#
Figure 2.1 Clock Control States
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Table 2.1 Clock State Characteristics
Clock State Exit Latency Power Snooping? System Uses
Normal N/A Varies Yes Normal program execution
Auto Halt Approximatel y 10 bus clocks 1.25W Yes S/W control l ed entry idle
mode
Stop Grant Approximatel y 10 bus clocks 1.25W Yes H/W controlled ent ry/exit
mobile throttling
Quick S tart Through snoop, to
HALT/Grant Snoop stat e:
immediate
Through STPCLK#, to Norm al
state: 8 bus clocks
0.5W Yes H/W cont rol l ed entry/exit
mobile throttling
HALT/Grant
Snoop A few bus clocks after the end
of snoop ac tivity. Not spec i f i ed Yes Supports snooping in the low
power states
Sleep To Stop Grant state 10 bus
clocks 0.5W No H/W control led entry/exit
deskt op i dl e mode support
Deep Sleep 30 ms ec 150 mW No H/W controll ed entry/exit
powered-on suspend support
NOTE: Not 100% tested. S pec i fied at 50°C by des i gn/charact eri zation.
2.2.2 Normal State
The Normal state of the process or i s the norm al
operating mode where the processor’ s internal c l ock
is running and t he processor is activel y executi ng
instructions.
2.2.3 Auto Halt State
This is a l ow power mode entered by the process or
through the execution of the HLT instruction. The
power level of this mode is simi l ar to the Stop Grant
state. A trans i t i on to the Norm al state is made by a
halt break event (one of the foll owing si gnal s going
active: NMI, INTR, BINIT#, INIT#, RESET#,
FLUSH#, or SMI#).
Asserting the ST P CLK # signal while in the A uto Halt
state will cause the processor to transition to the
Stop Grant or Qui ck St art state, where a Stop Grant
Acknowledge bus cyc l e will be iss ued. Deasserting
STPCLK# will cause the processor to return to the
Auto Halt state without i s suing a new Halt bus c yc l e.
The SMI# interrupt i s recognized in t he Auto Halt
state. The return from the Sys t em Management
Interrupt (SMI) handler can be to ei ther the Norm al
state or the Auto Halt state. See the
Intel
Archit ecture Sof t ware Developer’s Manual, V ol ume
III: System Programmer’s Guide
for m ore
information. No Hal t bus cycle i s issued when
returning to t he Auto Halt state from System
Management Mode (SMM).
MOBILE PENTIUM® II PROCESSOR IN MINI-CARTRIDGE PACKAGE
AT 400 MHZ, 366 MHZ, 333 MHZ, 300P E MHZ, AND 266PE MHZ DATASHEET
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The FLUSH# signal i s serviced in t he Auto Halt
state. Aft er t he on-chip and off-chip caches have
been flushed, t he processor will return to the A uto
Halt st ate without issuing a Halt bus cycle.
Transiti ons in the A20M# and PRE Q# signals are
recognized while in the Auto Halt s tate.
2.2.4 STOP GRANT State
The process or ent ers this mode with the as sertion
of the ST P CLK# signal when it is configured for
Stop Grant state (via the A15# strappi ng option).
The processor is still able to respond to snoop
requests and l at ch interrupts. Latc hed i nt errupts will
be serviced when the proc essor returns t o the
Normal state. Onl y one occurrence of each interrupt
event will be latched. A transition back to t he
Normal state c an be made by the deassertion of the
STPCLK# signal, or t he occurrence of a stop break
event (a BINIT#, FLUSH#, or RESET# assertion).
The processor will return to the Stop Grant state
after the completion of a BINIT# bus ini t i al i zat i on
unless STPCLK# has been deass erted. RESET#
assertion will cause the processor to immediately
initialize itself, but the processor will stay in the Stop
Grant state after ini tializati on unt i l STPCLK# is
deassert ed. If the FLUSH# signal is asserted, the
processor will flus h the on-chip caches and return to
the Stop Grant stat e. A transit i on to the Sleep state
can be m ade by t he assertion of the SLP# signal.
Assert ions of SMI#, I NI T #, INTR, and NMI will be
latched by t he processor while in the Stop Grant
state. These latched events will not be s ervic ed unt il
the proces s or returns to t he Normal state. Only one
of each event will be recognized upon return to the
Normal state.
2.2.5 QUICK START State
This is a mode entered by t he proc essor with the
assert i on of the STPCLK # s i gnal when it i s
configured f or the Quick Start s t ate (via the A15#
strapping opt i on). In the Quick St art state t he
process or i s only capable of acting on snoop
transactions generated by the system bus priori ty
device. B ecause of its snooping behavi or, Quick
Start can only be used in a uniprocessor
configuration.
A transi tion to the Deep S l eep state c an be made by
stopping t he clock i nput to the proces sor. A
transit i on back to t he Normal state (from the Quick
Start state) is made only i f the STP CLK # signal is
deasserted.
W hile in this state the processor is limited in its
ability to respond to input . I t is incapable of lat c hing
any interrupts , servici ng snoop transac tions from
symmetric bus m asters or res pondi ng t o FLUSH# or
BINIT# assertions. While the process or i s in the
Quick St art state, it will not respond properly to any
input signal other t han STPCLK#, RESET#, or
BPRI#. If any other input signal c hanges, then the
behavior of the proces sor will be unpredictable. No
serial interrupt m essages may begin or be in
progress while the processor is in the Quic k Start
state.
RESET# assertion will cause the processor to
immediatel y i ni tialize itself, but the proces sor will
stay in t he Qui ck St art state after init i al i zat i on until
STPCLK# i s deassert ed.
2.2.6 HALT/GRANT SNOOP State
The processor will respond to snoop transactions on
the system bus while in the Auto Halt , Stop Grant or
Quick S tart st ate. When a snoop t ransaction i s
presented on the system bus the processor will
enter the HALT/Grant Snoop s t ate. The proces sor
will remain in this st at e unt il the snoop has been
serviced and the system bus is quiet. A fter the
snoop has been servic ed, the processor will return
to its previ ous stat e. If the HALT/Grant S noop s tate
is entered f rom the Quick St art state, t hen the input
signal restrictions of t he Quic k Start s t ate still apply
in the HALT/ Grant Snoop st at e, except for thos e
signal t rans i tions that are required to perform the
snoop.
2.2.7 SLEEP State
The Sleep st ate is a very low power state in which
the proces s or maintai ns its context and the phase-
locked l oop (P LL) maintai ns phase loc k . The Sleep
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state can only be entered from the S t op Grant stat e.
After entering the St op Grant stat e t he SLP# signal
can be ass ert ed, causing the process or to enter the
Sleep st ate. The SLP# signal is not recognized in
the Norm al or A uto Halt states.
The processor c an be res et by the RESET# signal
while in the Sleep state. If RESET# is driven act i ve
while the processor is in t he S l eep state t hen S LP#
and STPCLK# must i mm edi ately be driven inact i ve
to ensure that the proces sor correct l y ini tializes
itself.
Input si gnals (ot her than RESET#) may not change
while the processor is in t he S l eep state or
transit i oni ng i nto or out of t he S l eep state. I nput
signal changes at these ti mes will cause
unpredictabl e behavi or. Thus, the proc essor is
incapable of snooping or latc hi ng any event s in the
Sleep st ate.
While in t he Sleep stat e, the proces sor can enter its
lowest power state, the Deep Sleep state. Removing
the proces s or’ s input cl ock puts the process or i n the
Deep Sleep state. P ICCLK m ay be removed in t he
Sleep st ate.
2.2.8 Deep Sleep State
The Deep Sleep st ate is the l owest power m ode the
process or can enter while mai ntaining its context.
The Deep Sleep st ate is entered by stopping the
BCLK input t o the process or, while it is i n the Sleep
or Quick S tart st ate. For proper operation, the BCLK
input shoul d be stopped in the l ow state.
The processor will return to t he Sleep or Quick S t art
state from t he Deep S l eep state when the BCLK
input is restarted. Due to the PLL lock latenc y, there
is a 30-
sec delay after the clocks have started
before this state t ransition happens . PICCLK may
be removed in the Deep Sleep st ate. PICCLK
should be desi gned to turn on when BCLK turns on
when transitioni ng out of the Deep Sleep state.
The input si gnal restrict i ons for the Deep S l eep
state are the sam e as for the S l eep s tate, except
that RESET# assertion will result in unpredictable
behavior.
2.2.9 Operating System Implications of
Quick Start and Sl eep S tates
There are a number of arc hi tectural features of t he
mobil e P entium II m i ni -cartridge processor that are
not available when the Quick Start stat e i s enabled
or do not function in the Quick St art or Sleep st ate
as they do in t he Stop Grant s t ate. These f eatures
are time-stamp counter and perf ormance monitor
counters . The time-stam p counter and the
perform anc e monitor counters are not guaranteed to
count in t he Qui ck St art or Sleep st ates.
2.3 Low Power GTL+
The mobil e P entium II m i ni -cartridge processor
system bus s i gnal s use a variati on of the low
voltage swing GTL si gnal i ng technology. The mobile
Pentium II mini-c artridge process or system bus
specificati on i s similar to t he P entium II proces s or
system bus s pecific ation, which is a version of GTL
with enhanced noise margins and l ess ringing. The
mobil e P entium II mini-cartridge processor system
bus spec i f i cation reduces syst em cos t and power
consumption by raising the terminati on vol t age and
term i nat i on resistance and changing the termination
from dual ended to single ended. Because t he
specificati on i s different from t he s tandard GTL
specificati on and f rom the P ent i um II processor
GTL+ specificati on, i t is referred to as Low Power
GTL+.
The Pentium II processor GTL+ s ys tem bus
depends on inci dent wave switching and uses flight
time for timing cal culations of the GTL+ signals . The
Low Power GTL+ system bus is short and lightly
loaded. With Low Power GTL+ signals, t i ming
calcul ations are based on capaciti ve derat i ng.
Analog si gnal s i mulati on of the sys t em bus including
trace lengt hs is highl y rec omm ended to ensure that
there are no signi f i cant trans mission line effects .
The GTL+ system bus of the Pentium II processor
was designed to s upport hi gh-speed data trans fers
with multiple loads on a l ong bus that behaves l i ke a
transmiss i on l i ne. However, in a mobile s ystem , the
system bus only has two loads (the proc essor and
the chipset) and the bus traces are s hort enough
that transmission li ne ef fects are not signifi c ant. It i s
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possibl e to change the layout and termination of the
system bus t o take advantage of the mobil e
environment using the same GTL+ I/ O buffers. The
benefit i s that it reduces the number of terminati ng
resistors in half and substanti al l y reduces the AC
and DC power dissipati on of the system bus . Low
Power GTL+ uses GTL+ I/ O buffers, but only two
loads are allowed. The t rac e l ength is li mited and
the bus is term i nat ed at one end only. Si nce the
system bus is sm al l and l i ghtly loaded it behaves
like a c apacitor, and t he GTL+ I/O buff ers behave
like high-speed open-drain buffers. Wit h a 66-MHz
bus frequency, the pull-up would be 120
. VTT has
been increased f rom 1.5V t o processor V CC to
elim i nate the need for a 1.5V power plane. If 100
term i nat i on resistors are used rather t han 120
,
then 20% more power will be diss i pat ed in the
term i nat i on resistors. 120
term i nat i on i s
recom mended to c ons erve power.
Refer to the
Mobile Pentium
®
II Processor System
Bus Lay out Gui del i ne
(Order Number 243672-001)
for detail s on l ayi ng out the Low Power GTL+
system bus.
2.3.1 GTL+ Signals
Two signals of the system bus c an potentially not
meet t he Low Power GTL+ layout requirements :
PRDY# and RESET#. These two signals c onnec t to
the debug port and might not meet t he maximum
length requirements . If PRDY# or RESET# do not
meet t he l ayout requirements for Low Power GTL+,
then they must be t erminated using dual-ended
term i nat i on at 120
. Higher resi stor values can be
used if simul ations show that t he signal qualit y
specificati ons in Section 4 are met .
2.4 Mobile Pentium II Mini-
cartridge Processor CPUID
The mobil e P entium II m i ni -cartridge processor has
the same CPUID fami l y and model number as some
Mobile Celeron™ Processors. The mobile P ent i um
II processor can be di s tinguished f rom thes e mobile
Celeron processors by looki ng at the st eppi ng
number and t he CPUID cac he descript or
information. A mobile P entium I I process or has a
stepping number in the range of 0AH to 0FH and an
L2 cache des criptor of 042H (256-K byte L2 cache).
If the stepping number is les s than 0AH or t he L2
cache des criptor is not 042H then the proces sor is a
mobil e Cel eron processor. The L2 cache m ust be
properly initial i zed for the L2 cac he des criptor
information to be correct. After a power-on RESET
or when the CPUID instruction i s executed, the E A X
register contains the values shown in Table 2. 2.
After the L2 cache is initial i zed, the CPUID
cache/TLB descriptors will be the values shown in
Table 2.3.
Table 2.2 Mobi le Pentium II Processor CPUI D
Reserved [31:14] Type [13:12] Family [11:8] Model [7:4] Stepping [3:0]
X066A - F
Table 2.3 Mobi le Pentium II Processor CPUI D Cache and TLB Descri ptors
Cache and TLB Descriptors 01H, 02H, 03H, 04H, 08H, 0CH, 42H
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3. ELECTRICAL SPECIFICATIONS
3.1 Processor System Signals
Table 3.1 lis ts the P ent i um II mini-c artridge
process or system signals by type.
All Low Power GTL+ signals are s ynchronous with
the BCLK s i gnal . All TA P signals are s ynchronous
with the TCK si gnal except TRS T #. All CMOS input
signals can be applied async hronously.
Table 3.1 System Signal Groups
Group Name Signals
Low Power GTL+ Input BPRI#, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY#
Low Power GTL+ Output PRDY#
Low Power GTL+ I/O A[35:3]#, ADS#, AERR#1, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#,
BPM[1:0]#, BREQ0#, D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HIT M#,
LOCK#, REQ[4:0]#, RP#
CMOS Input 2, 3 A20M#, FLUSH#, IGNNE#, I NI T #, INTR, NMI, PREQ#, PWRGOOD, SLP#,
SMI#, STPCLK#
Open Drain Output 3F ERR#, IE RR#
Clock 3BCLK
API C Cl ock 3PICCLK
APIC I/O 3PICD[1:0]
SMBus SMBALERT#, SMBCLK, SMBDATA
TAP Input 3TCK, TDI, TMS, TRST#
TAP Output 3TDO
Power/Other 4VCC, VCC_S,VCCP, VCCP_S, VCC3, VID[3:0], VSS, VSS_S
NOTES:
1. The A ERR# process or bus pin is removed as a processor feat ure for mobil e P entium® II processor at
400 MHz. The pin must s till be terminated to Vcc through a 120
pull-up resistor. But the proces sor mus t
not be confi gured to drive or observe the pi n.
2. S ee S ection 8.1 for inf ormation on the PWRGOOD signal.
3. These signals are tolerant to 2.5V only. S ee Tabl e 3.2 for t he recommended pull-up resi stor.
4. VCC is the power supply for the c ore l ogi c; VCCP is the power supply for the CMOS voltage references ;
VCC3 is the power supply for the thermal sens or; VSS i s syst em ground; VCC_S , VCCP_S and VSS_S are the
voltage sense pins for V CC, VCCP, and VSS, respectively.
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The CMOS, Clock, APIC, and TAP i nputs can be
driven from ground to 2.5V. The APIC and TAP
outputs are open drai n and should be pulled up t o
2.5V usi ng resistors with the values shown in
Table 3.2. I f open-drain drivers are us ed f or i nput
signals , then they shoul d al so be pulled up to 2. 5V
using resi stors with t he val ues shown in Table 3.2.
Table 3.2 Recommended Resistors for Open-drai n Signals
Recommended
Resistor Valu e (W) Open-drain Signal 1
150 pull-up PICD[1:0], TDI, TDO
680 pull-up STPCLK#
1K pull-up INIT#, TCK, TMS
680 - 1K pull-down TRST#
4.7 K pull-up A20M#, FERR#, FLUSH#, IERR#, IGNNE#, LI NT0/INTR, LINT1/NMI, PREQ #,
PWRGOOD, S LP#, SMI#
NOTE: Refer to Section 3.1. 5 for the required pull-up or pul l -down resistors f or signals t hat are not being
used.
3.1.1 Test Access P o rt (TAP) Connection
The TAP int erface is an i mplementation of the
IEEE 1149.1 (“JTAG”) standard. Due t o t he voltage
levels s upported by the TAP i nterface, i t is
recom mended that the mobil e Pentium II mini-
cartridge processor and t he ot her 2.5V JTA G
specificati on compli ant devices be l ast in the J T AG
chain aft er any devi ces with 3.3V or 5V JTAG
interfac es within the system . A translat i on buffer
should be used to reduce the TDO output voltage of
the last 3.3/5V device down to the 2.5V range t hat
the m obi l e P entium II m i ni -cartridge proces sor can
tolerate. Mult i ple copies of TMS and TRS T# must
be provided, one for eac h vol tage level.
A Debug Port and connector may be placed at t he
start and end of the JTAG chain containing the
process or, with TDI to the f i rst component coming
from the Debug Port and TDO f rom the las t
com ponent goi ng to the Debug Port .
There are no requirements for placement of the
mobil e P entium II m i ni -cartridge processor in the
JTAG chain, except for those that are di c tated by
voltage requirements of the TAP s i gnal s .
3.1.2 Thermal Sensor
Within the mobil e Pentium II m i ni -cartridge
process or t here i s a therm al sensor connec ted to
the SMBus pi ns. The program ming int erface for t he
therm al s ensor is des c ri bed i n the
Mobile Pentium II
Processor and Pentium I I Process or M obi l e M odul e
Thermal Sensor Programming Int erface
Specification
. The m obi l e P entium II m i ni -cartridge
process or t hermal s ens or supports an A CP I-
com pl i ant system im pl ementati on for monitoring the
tem perat ure of the proces sor. The thermal sens or
only provides an ac curate reading of t he processor
tem perat ure when the proc essor is fully powered.
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The address of t he thermal sensor on the proc essor
SMBus is 1001101.
3.1.3 SMBus Pi ns
SMBus is a subset of the I2C bus/protocol
developed by Intel. I2C i s a two-wire
communicati ons bus/protocol developed by Philips.
Contact your Intel Field Sales Representative for a
copy of the System Management B us specificati on.
3.1.4 Catastrophic Thermal Protection
The mobil e P entium II m i ni -cartridge processor does
not support catast rophi c therm al protection or t he
THERMTRIP# s i gnal . An external thermal sensor
should use the therm al di ode t o protect t he
process or and t he system against excessive
temperatures.
3.1.5 Unused Signals
All s i gnal s named RSV D must be unconnected.
Unused Low Power GTL+ inputs, out puts, and bi-
directi onal signals s houl d be i ndi vi dual l y c onnected
to VCC with 120
pull-up resistors. Unus ed CMOS
active l ow inputs should be connected to 2.5V and
unused act i ve hi gh i nput s should be connected to
VSS. Unused open-drain out puts should be
unconnect ed. If the proc essor is configured to ent er
the Quick Start state rat her t han the Stop Grant
state, then the S LP # signal should be connected t o
2.5V. When tying any si gnal t o power or ground, a
resistor will allow for system testabilit y. For unused
signals , it is suggested that 10-k
resistors be used
for pull-ups and 1-k
resistors be used f or pul l -
downs.
If the l ocal API C i s hardware disabled, then PICCLK
and PICD[1:0] should be tied to VSS with a 1-k
resistor. Otherwise PICCLK m ust be driven with a
clock that meets specification (see Table 3.14) and
the PICD[1:0] s i gnal s must be pul l ed up to 2.5V with
150
resistors, even if the local A PIC is not used.
3.1.6 Signal S tate i n Low Pow er S tates
3.1.6.1 S ystem Bus Signals
All of the syst em bus s i gnal s have Low Power GTL+
input, out put, or input/output drivers . Except when
servici ng snoops, t he s ystem bus signals are t ri -
stated and pul l ed up by the term i nation resis tors.
Snoops are not permitted in the Sl eep and t he Deep
Sleep st ates.
3.1.6.2 CMOS and Open-Drain Si gnal s
The CMOS input si gnal s are allowed to be in either
the logic hi gh or l ow st at e when the proc essor is i n a
low power state. In t he Auto Halt and S top Grant
states these s i gnal s are allowed to toggle. These
input buff ers have no internal pull -up or pul l -down
resistors and system logi c can use CMOS or open-
drain drivers to dri ve t hem.
The open-drain output s i gnal s have open drain
drivers and external pull-up res i stors are required.
One of the two output signals (I E RR#) i s a
catas t rophi c error indicat or and i s tri-stated (and
pulled up) when the processor is functioning
normall y. The FERR# output can be ei ther tri-stated
or driven to VSS when the proces sor is in a low
power state depending on the condition of the
floati ng poi nt uni t. Since this signal is a DC current
path when it is dri ven t o V SS, it is recommended that
the software clear or mas k any floati ng-poi nt error
conditi on bef ore putting the processor into the Deep
Sleep st ate.
3.1.6.3 Other Signals
The system bus c l ock (BCLK) must be dri ven in al l
of the low power states except t he Deep Sleep
state.
3.2 Power Supply Requirements
3.2.1 Decoupling Recommendations
The amount of bul k decoupling requi red t o meet t he
process or vol t age tolerance requirements i s a
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strong function of the power supply design. Contact
your Intel Fi el d S al es Representat i ve f or tools to
help determine how much dec oupl i ng i s required.
The CMOS voltage reference power plane (VCCP)
requires 50
F to 100
F of bulk dec oupl ing.
For the Low Power GTL+ pull-up resist ors, one 0.1-
F high frequency dec oupl i ng capacitor i s
recom mended per resistor pack . There should be
no more t han ei ght pul l -up resistors per resistor
pack.
3.2.2 Power Sequencing Requirements
The mobil e P entium II m i ni -cartridge processor has
no power sequencing requirements. I t is
recom mended that al l of the proces sor power
planes ris e to their specified values within one
second of eac h other. The VCC power plane must
not rise t oo fast. A t least 200
sec (TR) m ust pass
from the time that VCC is at 10% of its nominal val ue
until t he t i me that V CC i s at 90% of i t s nominal val ue
(See Figure 3.1).
Vcc
Volts
90% Vcc (nom inal)
10% Vcc (nom inal) T
20
R
Time
Figure 3.1 Ramp Rate Requirement
3.3 System Bus Clock and
Processor Clocking
The 2.5V BCLK clock i nput directl y c ontrols the
operating speed of the syst em bus int erface. A l l
system bus t i ming parameters are s pecified with
respect t o the rising edge of the BCLK input . The
process or core frequency is a multi pl e of the
BCLK frequenc y. The ratio between the c ore
frequency and the BCLK frequency i s configured
when the processor i s manuf ac tured. Multipl ying
the bus c l oc k frequency is necess ary to increase
perform anc e while al l owing for easier dist ri but i on
of signal s within the sys tem. Cl ock m ul t i pl i cation
within the processor is provi ded by the internal
Phase Lock Loop (PLL), which requires a
const ant frequency BCLK i nput. During Reset , or
on exit from the Deep Sleep st ate, the P LL
requires some am ount of time to acqui re the
phase of BCLK . This ti me is called the P LL l ock
latency, whic h i s specifi ed i n Section 3.6.1, AC
timing parameters T18 and T47.
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Table3.3 Mobile Pentium II Mini -cartridge Processor Absolute Maximum Rati ngs
Symbol Parameter Min Max Unit Notes
TStorage Storage Temperature –40 85 °C
VCC(Abs) Supply Voltage with respect to VSS –0.5 VID volt age +0. 6 V
VCCP CMOS Reference Vol tage with respect to
VSS
–0.3 VID volt age +0. 6 V
VCC3 Thermal S ensor Supply Vol tage with
respect to VSS
–0.3 4.0 V
VIN GTL+ Buffer DC Input Volt age with respect
to VSS
–0.3 VID volt age +0. 7 V Note 1
VIN25 2. 5V Buffer DC Input Volt age with respect
to VSS`
–0.3 3.3 V Note 2
VSMB SMBus Buff er DC Input Voltage with
respect to VSS
–0.3 6.0 V Note 3
IVID VID Pin Current 5 mA
IVSS_S VSS Sense Pin Current 5 mA Note 4
NOTES:
1. P arameter appli es to the Low Power GTL+ signal groups onl y.
2. P arameter appli es to CMOS, Open-drain, APIC, and TAP bus signal groups onl y.
3. P arameter appli es to SMBus signals.
4. When used as a proc essor presenc e detect s i gnal .
3.4 Maximum Ratings
Table3.3 cont ai ns the m obi l e Pentium II mini-
cartridge processor s t ress ratings. Funct i onal
operation at t he absolute maximum and minimum i s
neither implied nor guaranteed. The process or
should not receive a clock while subjected to these
conditi ons. Functi onal operating condit i ons are
provided in the AC and DC tables. E xtended
exposure to the m aximum rat i ngs may af f ect device
reliability. Furthermore, although t he proc essor
contains protecti ve circuit ry to resist damage f rom
stati c electri c discharge, one should always take
precautions to avoid high s t atic volt ages or electri c
fields.
3.5 DC Specifications
Table 3.4 through Tabl e 3. 8 l i st the DC
specificati ons for the mobile Pent i um II mini-
cartridge processor. S pecific ations are valid onl y
while meeti ng specifi cations for case temperature,
clock frequency and input vol tages. Care s houl d be
taken to read al l notes ass ociated with each
parameter.
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Table 3.4 Mobile Pentium II Processor Pow er S pecifications1
TPROC = 0 to TPROC,max; VCC = 1.6V ±120 mV; VCCP = 1.8V ±90 mV
Symbol Parameter Min Typ Max Unit Notes
VCC VCC for core logi c 1.480 1.6 1.720 V ±120 mV
VCC,LP VCC when ICC < 300 m A 1.480 1.6 1.790 V -120 mV 2
+190 mV
VCCP VCC for CMOS voltage references 1.71 1.8 1.89 V 1.8V ±90 mV
VCC3 VCC for Thermal S ensor 3.135 3.3 3.465 V 3.3V ±165 mV
ICC ICC for VCC at core at 366 MHz
frequency at 333 MHz
at 300PE MHz
at 266PE MHz
8.80
7.95
7.49
6.63
A
A
A
A
Note 5
ICCP Current for V CCP 75 mA Notes 3, 4, 5
ICC3 Current for V CC3 125 m A Note 5
ICC,SG Proc essor Stop Grant and
Auto Halt current 1190 m A Note 5
ICC,QS Processor Qui ck Start and
Sleep current 880 mA Note 5
ICC,DSLP P rocessor Deep Sl eep l eakage
current 650 mA Note 5
dICC/dt VCC power supply current s l ew rate 20 A/
s Notes 6, 7
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NOTES:
1. S pecific ations in t hi s table apply t o the list ed f requencies.
2. A hi gher VCC,MAX is all owed when the processor is in a l ow power state t o enabl e hi gh effici ency, low
current modes in t he power regulator.
3. ICCP i s the current supply for the CMOS vol tage references .
4. Not 100% tes t ed. Specified by design/ c haracterizati on.
5. ICCx,max specif i c ations are specified at VCC,max, VCCP,max, VCC3,max, and 100°C and under m aximum s i gnal
loading conditions. ICCx,max s pecific ations are not specifi ed at VCC,LP,max, if that voltage specifi cation is
used then s l i ght l y hi gher currents c an be expected.
6. B ased on simulations and averaged over the duration of any change in current. Use to c ompute the
maxim um induct ance and reaction time of the voltage regul ator. This parameter is not test ed.
7. Maximum values specifi ed by design/characterizati on at nominal VCC and V CCP.
Table 3.5 Mobile Pentium II Processor Pow er S pecifications1
TPROC = 0 to TPROC,max; VCC = 1.55V ±120 mV; VCCP = 1.8V ±90 mV
Symbol Parameter Min Typ Max Unit Notes
VCC VCC for core logi c 1.430 1.550 1.670 V ±120 mV
VCC,LP VCC when ICC < 300 m A 1.430 1.550 1.740 V -120 mV 2
+190 mV
VCCP VCC for CMOS voltage references 1.710 1.800 1.89 V 1.8V ±90 mV
VCC3 VCC for Thermal S ensor 3.135 3.300 3.465 V 3.3V ±165 mV
ICC ICC for VCC at core frequenc y
at 400 MHz 9.30 A Note 5
ICCP Current for V CCP 75 mA Notes 3, 4, 5
ICC3 Current for V CC3 125 m A Note 5
ICC,SG Proc essor Stop Grant and
Auto Halt current 1190 m A Note 5
ICC,QS Processor Qui ck Start and
Sleep current 880 mA Note 5
ICC,DSLP P rocessor Deep Sl eep l eakage
current 650 mA Note 5
dICC/dt VCC power supply current s l ew rate 20 A/
s Notes 6, 7
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NOTES:
1. Specif i cations i n this tabl e appl y to the lis t ed frequency.
2. A higher VCC,MAX i s allowed when the processor i s i n a l ow power state to enable high eff i ciency, l ow
current modes in t he power regulator.
3. ICCP i s the current s uppl y for the CMOS voltage references.
4. Not 100% t es ted. Spec i f i ed by design/characterizati on.
5. ICCx,max specif i c ations are specified at VCC,max, VCCP,max, VCC3,max, and 100°C and under m aximum s i gnal
loading conditions. ICCx,max s pecific ations are not specifi ed at VCC,LP,max, if that voltage specifi cation is
used then s l i ght l y hi gher currents c an be expected.
6. Based on s i mulations and averaged over the duration of any change in current. Use t o c ompute t he
maxim um induct ance and reaction time of the voltage regul ator. This parameter is not test ed.
7. Maximum values specified by design/ characterization at nominal VCC and VCCP.
The signals on the mobil e P entium II proces sor
system bus are included in the Low Power GTL+
signal group. These signals are specifi ed to be
term i nat ed to VTT (which is VCC.). The DC
specificati ons for these signals are l i s ted in
Table 3.6; t he termination and reference vol tage
specificati ons for these signals are l i s ted in
Table 3.7. The mobile Pentium II m i ni -cartridge
process or requi res external termi nation and a VREF.
Refer to
Mobile Pentium
®
II Processor System Bus
Layout Guidel i ne
for full det ai l s of sys t em VTT and
VREF requirements.
Table 3.6 Low Power GTL+ Signal Group DC Specifications
TPROC = 0 to TPROC,max; VCC = 1.6V ±120 mV , or 1.55 ± 120 mV ; VCCP = 1.8V ±90 mV
Symbol Parameter Min Max Unit Notes
VIL Input Low Voltage –0.3 5/9VTT – 0.2 V See Table 3.7 1
VIH Input High V ol tage 5/9VTT + 0.2 VCC V Note 1
VOH Output High V ol tage — — V See VTT max in Table
3.7.
RON Output Low Drive Strength 35 ohms
ILLeakage Current ±100
A Note 2
ILO Output Leakage Current ±30
A Note 3
NOTES:
1. VREF worst case, not nominal. Noi se on VREF shoul d be accounted f or.
2. (0
VIN
VCC).
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3. (0
VOUT
VCC).
Table 3.7 Low Po wer GTL+ Bus DC Specificati ons
TPROC = 0 to TPROC,max; VCC = 1.6V ±120 mV, or 1.55 ± 120 mV; VCCP = 1.8V ±90 mV
Symbol Parameter Min Typ Max Unit Notes
VTT Bus Termination V ol tage VCC,MIN VCC VCC,MAX V Note 1
VREF Input Reference Volt age 5/9VTT – 2% 5/9VTT 5/9VTT + 2% V ±2% 2
NOTES:
1. The i ntent is t o use the same power supply for VCC and V TT.
2. VREF for the system logi c should be created from VTT by a voltage divi der.
The Clock, CMOS, Open-drain, and TA P signals are
designed to i nt erface at 2. 5V CMOS l evel s to allow
connect i on t o other devices. The DC specificati ons
for these 2.5V tolerant signals are l i sted in
Table 3.8.
Table 3.8 Clock, APIC, TAP, CMOS, and Open-drain Signal Group DC Specifications
TPROC = 0 to TPROC,max; VCC = 1.6V ±120 mV, or 1.55 ± 120 mV; VCCP = 1.8V ±90 mV
Symbol Parameter Min Max Unit Notes
VIL Input Low Voltage –0.3 0.7 V
VIL,BCLK Input Low Voltage, BCLK –0.3 0.6 V Note 1
VIH Input High V ol tage 1.700 2.625 V
VIH,BCLK Input High Voltage, BCLK 1.800 2.625 V
VOL Output Low Voltage 0.4 V Note 2
VOH Output High V ol tage N/A 2.625 V All outputs are open-drai n
IOL Output Low Current 14 mA
ILI Input Leakage Current ±100
A Note 3
ILo Output Leakage Current ±30
A Note 3
NOTES:
1. P arameter measured at 14 mA.
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2. (0
VIN
2.625V).
3. (0
VIN
2.625V).
2.6 AC Specifications
2.6.1 System Bus, Clock, API C, TAP, CMOS,
and Open-drain AC Specifi cati ons
The signal t i mings specifi ed i n this section are
defined at t he processor connector. Tabl e 3.9
Through Table 3.17 Provide AC specif i cations
assoc i at ed with the mobil e Pentium II mini-cartridge
process or. The AC specificati ons are divided into
the foll owing categories: Tabl e 3.9 contai ns the
system bus c l ock specifications; Tabl e 3.10
contains the proces sor core frequencies; Table 3. 11
contains the Low Power GTL+ specifications; Table
3.12 contai ns the CMOS and Open-drain s i gnal
groups spec i ficati ons; Table 3.13 contains timi ngs
for the reset conditi ons; Table 3.14 contains the
APIC specifi cations; Table 3.15 contains the TA P
specificati ons; and Table 3.16 and Tabl e 3.17
contain t he power m anagement t i ming
specifications.
All s ys tem bus A C specifi cations f or the Low Power
GTL+ signal group are relative to the ri sing edge of
the BCLK i nput at VIL,BCLK. A l l Low Power GTL+
timings are referenced to VREF f or both “0” and “1”
logic level s unless otherwise specified.
Table 3.9 System Bus Cl ock AC Specifications1
TPROC = 0 to TPROC,max; VCC = 1.6V ±120 mV, or 1.55 ± 120 mV; VCCP = 1.8V ±90 mV
Symbol Parameter Min Typ Max Unit Figure Notes
System Bus Frequency 66.67 MHz
T1 BCLK Period 15 ns 3.3 Note 2
T1B BCLK offset f rom connec tor
pin to processor core 0.45 0.70 ns 3.3 Note 3
T2 BCLK Period Stability ±250 ps Notes 4, 5
T3 BCLK High Time 4.84 ns 3.3 at>1.8V
T4 BCLK Low Time 5.1 ns 3.3 at<0.6V
T5 BCLK Ris e Ti me 0.52 1.43 ns 3. 3 (0.6V – 1.8) 5
T6 BCLK Fall Time 0.52 1. 43 ns 3.3 (1.8V – 0.6V) 5
NOTES:
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1. A l l AC timings for Low Power GTL+ and CMOS signals are referenced to the BCLK ris i ng edge at
VIL,BCLK. A t the connec t or pi ns. This reference is to account f or trace length and capacitance on the m i ni -
cartridge substrate, allowing for the proc essor core t o receive the signal with a BCLK reference at 1.25V.
All CMOS s i gnal s are referenced at 1.25V at t he c onnector pins. All Low Power GTL+ signals are
referenced at VREF at the connector pins.
2. The B CLK period allows a +0.5 ns tolerance for clock dri ver variation.
3. The B CLK offset is the absolute dif ference needed between the BCLK signal arriving at the pin at VIL,BCLK
vs. arrivi ng at the process or core at 1.25V . The positive offset is needed to acc ount for the delay bet ween
the connec t or and the process or core. The positive offs et ensures t hat both the proces sor core and the
system logic receive the BCLK edge c oncurrently.
4. Not 100% tes t ed. Specified by design/ c haracterizati on.
5. Measured on the rising edge of adj acent BCLKs at 1.25V. The jitt er present m us t be account ed for as a
com ponent of BCLK skew between devices.
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Table 3.10 Valid Mobile Pentium® II Mini-cartri dge P r ocessor Frequenci es
TPROC = 0 to TPROC,max; VCC = 1.6V ±120 mV, or 1.55 ± 120 mV; VCCP = 1.8V ±90 mV
BCLK Frequency (MHz) Frequency Multiplier Core Frequency (M Hz )
66.67 4 266.67
66.67 9/2 300.00
66.67 5 333.33
66.67 11/2 366.67
66.67 6 400.00
NOTE: While other combinations of bus and core frequenci es are defined, operation at frequenci es other
than those listed in Table 3.10 will not be validated by Intel and are not guaranteed. The frequency
multiplier is programm ed i nto the proces s or when it i s manuf actured and it cannot be changed.
Table 3.11 Low Power GTL+ Signal Groups AC Specifications1, 2
RTT = 120
term i nat ed to VCC; VREF = 5/9 VCC; l oad = 0 pF
TPROC = 0 to TPROC,max; VCC = 1.6V ±120 mV, or 1.55 ± 120 mV; VCCP = 1.8V ±90 mV
Symbol Parameter Min Max Unit Figure Notes
T7 Low Power GTL+ Output Valid Delay 0.0 8.0 ns 3.4
T8 Low Power GTL+ Input Setup Time 3.2 ns 3.5 Notes 3, 4
T9 Low Power GTL+ Input Hold Time 0.9 ns 3.5 Note 5
T10 RESET# Pulse Width 1 ms 3.6, 3.7 Note 6
NOTES:
1. A l l AC timings for Low Power GTL+ signals are referenced to the BCLK ris i ng edge at VIL,BCLK at the
connect or pi ns . All Low Power GTL+ signals are referenced at V REF.at t he connector pins.
2. Not 100% tes t ed. Specified by design c haracterizati on. Equivalent s pecific at i ons are test ed at the
process or core.
3. RESET# c an be asserted (act ive) async hronous ly, but must be deasserted s ync hronously.
4. S pecific ation is f or a minimum 0.40V swing.
5. S pecific ation is f or a maximum 1.0V s wing.
6. After VCC, VCCP, and BCLK become stable and PWRGOOD is ass ert ed.
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Table 3.12 CMOS and Open-drain Signal Groups AC Specifications1, 2
TCASE = 0 to TCASE,max; VCC = 1.6V ±120 m V, or 1.55 ± 120 mV; V CCP = 1.8V ±90 mV
Symbol Parameter Min Max Unit Figure Notes
T14 2.5V I nput Pulse Width, except
PWRGOOD and LINT[1:0] 2 BCLKs 3.4 A ctive and
Inactive
states
T15 PWRGOOD Inac t i ve Pulse Width 10 BCLKs 3.7 Notes 9, 10
NOTES:
1. A l l AC timings for CMOS and Open-drai n signals are ref erenced to the BCLK ri sing edge at VIL,BCLK at
the connec t or pi ns. All CMOS signals are ref erenced at 1.25V at the connec tor pins.
2. Mini mum out put pulse width on CMOS outputs is 2 BCLKs.
3. When driven inacti ve, or after VCC, VCCP and BCLK becom e stable. PWRGOOD must remain below
VIL,max from Tabl e 3.8 until all the voltage planes meet t he vol tage tolerance specifi cations i n Tabl e 3.4
and BCLK has met the BCLK AC specifications in Table 3.9 f or at least 10 cl ock cycles. PWRGOOD
mus t ri se glitc h-free and monot oni cally to 2.5V.
4. I f the BCLK s i gnal meets it s AC specif ication within 150 ns of t urning on t hen the PWRGOOD Inac t i ve
Pulse Widt h specific at ion (T15) is waived and BCLK may st art after PWRGOOD is as serted. PWRGOOD
must still remain below VIL,max until all t he vol tage planes meet the voltage tolerance s pecific ations.
Table 3.13 Reset Configuration AC Specifications1
TPROC = 0 to TPROC,max; VCC = 1.6V ±120 mV, or 1.55 ± 120 mV; VCCP = 1.8V ±90 mV
Symbol Parameter Min Max Unit Figure Notes
T16 Reset Conf i guration Signals (A[15:5]#,
BREQ0#, FLUSH#, INIT#, PICD0)
Setup Tim e
4 BCLKs 3.5, 3. 6 Bef ore
deassert i on of
RESET#
T17 Reset Conf i guration Signals (A[15:5]#,
BREQ0#, FLUSH#, INIT#, PICD0)
Hold Time
2 20 B CLKs 3.5, 3. 6 Af ter clock that
deasserts
RESET#
T18 Reset P LL Lock Latenc y 1 ms 3. 6, 3.7 Before
deassert i on of
RESET# 1
NOTES:
1. T19 and T20, although valid for other systems , are not relevant in mobile mini-cart ri dge systems.
2. A t least 1 ms must pas s after PWRGOOD rises above VIH,min from Table 3.6 and B CLK meets t he AC
tim ing specificat ion in Table 3.9 until RESET# may be deass ert ed.
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Table 3.14 APIC Bus Signal AC Specifi cations1, 2
TPROC = 0 to TPROC,max; VCC = 1.6V ±120 mV, or 1.55 ± 120 mV; VCCP = 1.8V ±90 mV
Symbol Parameter Min Max Unit Figure Notes
T21 PICCLK Frequency N/A N/ A MHz Note 2
T22 PICCLK P eri od N/A N/A ns 3. 3
T23 PI CCLK High Time N/A N/A ns 3.3
T24 PICCLK Low Time N/A N/A ns 3.3
T25 PI CCLK Rise Ti me N/A N/A ns 3.3
T26 PICCLK Fall Time N/A N/A ns 3.3
T27 PICD[ 1:0] Setup Ti me N/A N/A ns 3.5 Not e 4
T28 PICD[ 1:0] Hold Time N/A N/A ns 3.5 Not e 4
T29 PICD[1:0] Valid Delay N/A N/A ns 3.4 Notes 4, 5, 6
NOTES:
1. The A PIC has been removed as a feature of the mobile Pent i um II mini-cartridge proces sor.
2. Not 100% tes t ed. Specified by design c haracterizati on. Equivalent s pecific at i ons are test ed at the
process or core.
3. The minimum frequency is 2 MHz when PICD0 is at 2.5V at reset. If PI CD0 i s strapped to VSS at res et
then the minimum frequency is 0 MHz.
4. Referenced to PICCLK Risi ng E dge.
5. For open-drai n signals, V al i d Del ay i s synonym ous with Float Delay.
6. V al i d del ay timi ngs for thes e signals are s pecified into 150
to 2.5V and 50 pF.
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Table 3.15 TAP S ignal AC Specifications1, 2
TPROC = 0 to TPROC,max; VCC = 1.6V ±120 mV , or 1.55 ± 120 mV; VCCP = 1.8V ±90 mV
Symbol Parameter Min Max Unit Figure Notes
T30 TCK Frequency — 16.67 MHz
T31 TCK Peri od 60 — ns 3.3
T32 TCK High Time 25.0 ns 3.3
1.7V 3
T33 TCK Low Time 25.0 ns 3.3
0.7V 3
T34 TCK Ri se Time 5.0 ns 3.3 (0.7V-1.7V) 3, 4
T35 TCK Fall Time 5.0 ns 3.3 (1.7V-0.7V) 3, 4
T36 TRST# Pul se Width 40.0 ns 3.9 Asynchronous 2
T37 TDI, TMS Setup Time 5.0 ns 3.8 Note 5
T38 TDI, TMS Hold Time 14.0 ns 3.8 Note 5
T39 TDO Valid Delay 0.9 10.0 ns 3.8 Notes 6, 7
T40 TDO Float Delay 0.0 25. 0 ns 3.8 Notes 3, 6, 7
T41 All Non-Tes t Outputs V al i d Del ay 2.0 25.0 ns 3. 8 Notes 6, 8, 9
T42 All Non-Tes t Outputs Fl oat Delay 25.0 ns 3. 8 Not es 3, 6, 8, 9
T43 All Non-Tes t Inputs Set up Ti me 5.0 ns 3.8 Notes 5, 8, 9
T44 All Non-Tes t Inputs Hold Time 13. 0 ns 3.8 Notes 5, 8, 9
NOTES:
1. All AC timi ngs for TAP signals are ref erenced to the TCK ri sing edge at VIL at t he connector pins. All
CMOS signals are referenced at 1. 25V at the connec t or pi ns.
2. Not 100% tested. S pecified by des i gn/ characterization. Equi val ent specifi cations are tested at t he
process or core.
3. Not 100% tested. S pecified by des i gn/ characterization.
4. 1 ns can be added t o t he maximum TCK ris e and fall times f or every 1 MHz below 16 MHz.
5. Referenced to TCK rising edge.
6. Referenced to TCK falling edge.
7. Valid delay t i ming for this si gnal i s specified into 150
term i nat ed to 2.5V and 50 pF.
8. Non-test Outputs and I nputs are the normal output or i nput signals (except TCK , TRST#, TDI , TDO, and
TMS). These ti mings c orrespond to the res ponse of thes e s i gnal s due to boundary sc an operations.
9. Duri ng Debug P ort operation use the normal specifi ed timi ngs rather than the TAP signal timi ngs.
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Table 3.16 Quick Start/Deep Sleep AC Specifi cations
TPROC = 0 to TPROC,max; VCC = 1.6V ±120 mV, or 1.55 ± 120 mV; VCCP = 1.8V ±90 mV
Symbol Parameter Min Max Unit Figure
T45 Stop Grant Cycle Compl etion to Cloc k Stop 100 BCLKs 3.10
T46 Stop Grant Cycle Compl etion to Input Signals S t abl e 0 ns 3.10
T47 Deep Sleep PLL Lock Latenc y 30
s3.10
T48 STPCLK# Hol d Time from PLL Lock 0 ns 3. 10
T49 Input S i gnal Hol d Ti me from STPCLK # Deassertion 8 BCLKs 3.10
NOTE: Input signals other than RESET# and BPRI# must be held constant in t he Quick Start s t at e.
Table 3.17 Stop Grant/Sleep/ Deep S l eep AC Specifications
TPROC = 0 to TPROC,max; VCC = 1.6V ±120 mV, or 1.55 ± 120 mV; VCCP = 1.8V ±90 mV
Symbol Parameter Min Max Unit Figure
T50 SLP# S i gnal Hol d Ti me from Stop Grant Cycle Com pl et i on 100 BCLKs 3.11
T51 SLP# A s sertion to Input Signal s Stable 0 ns 3. 11
T52 SLP# A s sertion to Cl ock St op 10 BCLKs 3. 11
T54 SLP# Hold Time from PLL Lock 0 ns 3.11
T55 STPCLK# Hold Time from SLP# Deassertion 10 BCLKs 3.11
T56 Input S i gnal Hol d Ti me from SLP# Deas sertion 10 BCLKs 3.11
NOTE: Input si gnals other than RESET# mus t be held constant in the Sleep stat e.
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Figure 3.2 through Fi gure 3.11 are to be used in conjuncti on with Tabl e 3.9 through Table 3.17.
BCLK at
Connector VIL,BCLK
BCLK at
Core 1.25V
T1B
D0031-00
Figure 3.2 BCLK Connector to Core Offset
CLK VIH VTRIP
Th
Tl
Tp
Tr1
D0003-02
VIL
Tf1
1.6V
0.9V
Tr2
Tf2
NOTES: Tr1 =T5, T
r2 = T34 (Rise Time)
Tf1 =T6, T
f2 = T35 (Fall Time)
Th= T3, T32 (Hi gh Tim e)
Tl= T4, T33 (Low Ti me)
Tp= T1, T31 (Period)
VTRIP = 1.25V f or BCLK and TCK
Figure 3.3 Generic Cl ock Waveform
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CLK
Signal
TxTx
Tpw
V Valid Valid
D0004-00
NOTES: Tx= T7, T11, T29 (Valid Delay)
Tpw = T14, T14B (Pulse Wi dth)
V= V
REF for Low Power GTL+ si gnal group; 1.25V for CMOS , Open-drain,
APIC and TA P signal groups
Figure 3.4 Valid Delay Timings
CLK
Signal V Valid
Th
Ts
D0005-0
0
NOTES: Ts= T8, T12, T27 (S etup Time)
Th= T9, T13, T28 (Hol d Ti m e)
V= V
REF for Low Power GTL+ si gnal s ; 1.25V f or CM OS , APIC, and TAP si gnal s
Figure 3.5 Setup and Hold Timings
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BCLK
RESET#
Configuration
(A[15:5], BREQ0#,
FLUSH#, INIT#,
PICD0)
Tv
Tx
Tt
Tu
Tw
Valid
D0006-01
NOTES: Tt= T9 (Low Power GTL+ Input Hold Time)
Tu= T8 (Low P ower GTL+ I nput Setup Time)
TV= T10 (RESET# Pulse Width)
T18 (Reset PLL Lock Latenc y
TW= T16 (Reset Configurat i on Signals (A [ 15:5]#, BREQ0#, FLUSH#, INIT#, P ICD0) Setup
Time)
TX= T17 (Reset Configurat i on Signals (A [ 15:5]#, BREQ0#, FLUSH#, INIT#, P ICD0) Hold
Time)
Figure 3.6 Reset and Configurati on Timings
BCLK
PWRGOOD
RESET#
TaTb
V ,
CC
VREF
V ,
CCP,
VIL,max VIH,min
D0007-00
NOTES: Ta= T15 (PWRGOOD Inac tive Puls e Widt h)
Tb= T10 (RESET# Pulse Width)
T18 (Reset PLL Lock Latenc y)
Figure 3.7 Power-on Reset Timings
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TCK
TDI, TMS
Input
Signals
TDO
Output
Signals
1.25V
TvTw
TrTs
TxTu
TyTz
D0008-00
NOTES: Tr= T43 (All Non-t est Input s Setup Tim e)
Ts= T44 (A l l Non-test I nput s Hold Time)
Tu= T40 (TDO Float Delay)
Tv= T37 (TDI, TMS Setup Tim e)
Tw= T38 (TDI, TMS Hold Time)
Tx= T39 (TDO Valid Delay)
Ty= T41 (A l l Non-test Out put s Valid Delay)
Tz= T42 (A l l Non-test Out put s Float Delay )
Figure 3.8 Test Timi ngs (Boundary Scan)
TRST# 1.25V
TqD0009-00
NOTE: Tq= T36 (TRST# Pulse Width)
Figure 3.9 Test Reset Timings
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Tw
stpgnt
Running Running
BCLK
STPCLK#
CPU bus
SLP#
Compatibility
Signals Changing
Normal Quick Start Deep Sleep Quick Start Normal
Frozen
Tv
Ty
Tz
Tx
V0010-00
NOTES: Tv= T45 (Stop Grant Ack nowl edge B us Cycle Completion to Cl ock Shut Off Delay)
Tw= T46 (S etup Time to I nput Signal Hold Requi rem ent)
Tx= T47 (Deep S l eep PLL Lock Lat ency)
Ty= T48 (P LL l ock to S T P CLK # Hol d Ti m e)
Tz= T49 (I nput Signal Hold Ti m e)
Figure 3.10 Quick Start and Deep S l eep Tim ing
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Tu
stpgnt
Running
BCLK
STPCLK#
CPU bus
SLP#
Compatibility
Signals FrozenChanging
Normal Stop
Grant Sleep Deep Sleep Sleep Stop
Grant Normal
Running
Tt
Tv
Ty
Tz
TwTx
V0011-00
Changing
NOTES: Tt= T50 (Stop Grant Ack nowl edge B us Cycle Completion to SLP# Assertion Delay )
Tu= T51 (S etup Time to I nput Signal Hold Requi rem ent)
Tv= T52 (S LP# assert i on t o clock s hut off delay)
Tw= T47 (Deep S l eep PLL lock l atency)
Tx= T54 (S LP# Hold Time)
Ty= T55 (STPCLK# Hol d T i me)
Tz= T56 (I nput Signal Hold Ti m e)
Figure 3.11 Stop Grant, S l eep, and Deep Sleep Timing
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4. SYSTEM SIGNAL SIMULATIONS
Many scenarios have been sim ul at ed to generate
a set of Low Power GTL+ processor syst em bus
layout guideli nes which are available in t he
Mobile Pentium
®
II Processor S ystem Bus Layout
Guideline
. All wave terms des cribed in this
sect i on are s i mulated at the pad on the proc essor
core. System s must be simul ated using the IBIS
model to determ i ne i f they are com pl i ant with this
specificati on. A set of signal qualit y gui del i nes is
also provided. V i ol ations of these guidelines are
allowed but if t hey oc cur, then s i mulati ons of
signal quali ty at the proc es sor core shoul d be
perform ed t o ensure that no viol ations of the
signal quali ty specificati ons occur. Meeti ng the
guideline does not guarantee m eet i ng the
specification.
4.1 System Bus Clock (BCLK)
Signal Quality Specifications
Table 4.1 and Figure 4. 1 s how the s i gnal qual i ty
for the system bus clock (BCLK) si gnal as
simulated at the process or core. Table 4.2 and
Figure 4.2 show the s i gnal qual i t y gui del i ne for
the system bus clock (BCLK) signal as meas ured
at the processor connec tor. The timings
illustrated in Figure 4.2 are taken from Table 3.9.
BCLK is a 2. 5V clock.
Table 4.1 BCLK Signal Qual ity Specifications at the Processor Core
Symbol Parameter Min Max Unit Figure Notes
V1 VIL,BCLK 0.7 V 4.1 Note 1
V2 VIH,BCLK 1. 8 V 4.1 Not e 1
V3 VIN Absol ute Voltage Range –0.7 3.5 V 4.1 Undershoot, Overshoot
V4 Ri sing Edge Ringbac k 1.8 V 4.1 Abs ol ute Value 2
V5 Fal l i ng Edge Ringback 0.7 V 4.1 Absol ute Value 2
BCLK ris i ng/ falling s l ew rate 0.8 4.4 V/ns 4.1
NOTES:
1. B CLK mus t ri se/fall monotonically between VIL,BCLK and VIH,BCLK.
2. The ris i ng and falling edge ringback voltage s pecified is the minim um (rising) or maximum (falling)
absolute voltage t he B CLK s i gnal can dip back to after passi ng t he VIH (rising) or V I L (falling) voltage
limits.
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V0012-01
V1
V2
V3
V4
V3
V5
Figure 4.1 BCLK Generic Cl ock Waveform at the Processor Core
Table 4.2 BCLK Signal Qual ity Guidelines at the P rocessor Connector
Symbol Parameter Min Max Unit Figure Notes
V1’ VIL,BCLK 0.6 V 4.2
V2’ VIH,BCLK 1.8 V 4.2
V3’ VIN Absolut e Voltage Range –0.5 3.3 V 4. 2 Unders hoot, Overshoot
V4’ Rising Edge Ri ngback 1.8 V 4.2 A bs ol ute Value 1
V5’ Falling E dge Ri ngbac k 0.6 V 4.2 A bs ol ute Value 1
V6’ Tline Ledge Voltage 0.7 1.8 V 4.2
V7’ Tline Ledge Oscillat i on 0.1 V 4.2
NOTES:
1. The rising and falling edge ringbac k volt age specified is the minimum (rising) or maxim um (falling)
absolute vol t age the BCLK si gnal can dip back to after pas sing the VIH,BCLK (ri sing) or VIL,BCLK (falling)
voltage li mits.
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V0032-00
V1'
V2'
V3'
V4'
V3'
V5'
T3
T4
V7'
V6'
T6 T5
Figure 4.2 BCLK Generic Cl ock Waveform at the Processor Connector
4.2 Low Power GTL+ Signal Quality
Specifications
Table 4.3 and Figure 4.3 illustrate the Low Power
GTL+ signal quali ty specificati ons for the processor
as simulated at the core. Table 4.2 gives t he Low
Power GTL+ signal quality guidelines for the
process or as meas ured at the connect or. Refer to
the
Pentium
®
II Processor Dev el oper’s Manual
for
the GTL+ buffer specifi cation.
Table 4.3 Low Power GTL+ Signal Group Ringback Specification at the Processor Core
Symbol Parameter Min Unit Figure Notes
Overshoot 100 mV 4.3 Notes 1, 2
Minimum Time at High 1 ns 4.3 Notes 1, 2
Ampl i tude of Ringback -100 mV 4.3 Notes 1, 2, 3
Final Settling Voltage 100 mV 4.3 Notes 1, 2
Duration of S equential Ringback N/A ns 4.3 Notes 1, 2
NOTES:
1. Specifi ed for the edge rate of 0.3 – 0.8 V/ns. See Figure 4.3 for the generic waveform.
2. A l l val ues determ i ned by design/characterizati on.
3. Ri ngback below VREF +100 mV is not authorized during low to high t ransitions .
Ringback above VREF –100 mV is not authorized during high t o l ow trans i t i ons.
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VREF+0.2V
Time
VREF-0.2V
VREF
Vstart
Clock
VIL,BCLK
VIH,BCLK
V0014-00
NOTE: High-t o-l ow case is anal ogous.
Figure 4.3 Low to High, Low Po wer GTL+ Receiver Ringback Tolerance
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Table 4.4 Low Power GTL+ Signal Group Ringback Guid el i n e at the P rocessor Connector
Symbol Parameter Min Unit Figure Notes
Overshoot 100 mV 4.3 Notes 1, 2
Minimum Time at High 1.5 ns 4.3 Notes 1, 2
Ampl i tude of Ringback -250 mV 4.3 Notes 1, 2, 3
Final Settling Voltage 250 mV 4.3 Notes 1, 2
Duration of S equential Ringback N/A ns 4.3 Notes 1, 2
NOTES:
1. Specifi ed for the edge rate of 0.3 – 0.8 V/ns. See Figure 4.3 for the generic waveform.
2. A l l val ues determ i ned by design/characterizati on.
3. Ri ngback below VREF +250 mV is not authorized during low to high t ransitions .
Ringback above VREF -250 mV is not authorized during high t o l ow trans i t i ons.
4.3 Non-Low Power GTL+ Signal
Quality Specifications
Signals dri ven t o t he processor s houl d meet s i gnal
quality s pecific at i ons to ensure t hat the proces s or
reads data properly and t hat incoming signals do not
affect the long-term reliability of the proces sor.
There are three signal qual i t y parameters defined:
overshoot/undershoot, ringback, and s ettling li mit.
All three signal-quality paramet ers are shown in
Figure 4.4 for non-GTL+ s i gnal groups. This section
covers t he s i gnal qual i ty specificati on for all non-
GTL+ signals except for BCLK, which i s covered in
Secti on 4.1.
4.3.1 Overshoot and Undershoot Guidelines
Overshoot or unders hoot i s the absolute value of the
maxim um voltage above t he nominal hi gh vol t age or
below VSS. The overshoot/undershoot guidel i ne
lim i ts transi tions beyond VCC or V SS due to the fas t
signal edge rat es. The proces s or can be damaged
by repeated overshoot events on 2.5V t ol erant
buffers i f the charge is large enough (i.e. , if the
overshoot is great enough). However, excessive
ringback i s the dom i nant detrimental syst em timing
effect resulti ng from overs hoot/undershoot (i .e.,
violating the overshoot/undershoot guideli ne will
mak e i t di fficul t to sat i sfy the ringbac k specificati on).
The overshoot/ undershoot guideli ne i s 0.8V and
assumes the absence of diodes on the input. These
guidelines should be verified i n simul ations
without
the on-chip E SD protect i on di odes present
because
the diodes will begin clamping the 2.5V t olerant
signals begi nni ng at approximately 1. 25V above VCC
and 0.5V below VSS. I f the signal s do not reach t he
clam ping voltage, then this will not be an issue. A
system should not rely on the diodes f or
overshoot/undershoot protec tion as thi s will
negatively affect t he l i f e of the components and
mak e meeting t he ri ngback spec i ficati on very
difficult.
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VLO
VHI=2.5V
VSS
Time
Settling Limit
Settling Limit
Undershoot
Overshoot
Rising-Edge
Ringback
Falling-Edge
Ringback
V0015-00
Figure 4.4 Non-GTL+ Overshoot/Undershoot and Ringback
4.3.2 Ringback Specifi cation
Ringback refers to the amount of reflecti on seen
after a si gnal has switched. The ri ngback
specificati on i s the voltage t hat the signal ri ngs back
to after achieving its maxim um absolute value.
Excessive ri ngback can c ause false signal detec tion
or extend the propagation delay. The ri ngback
specificati on appl i es to the input signal of eac h
receiving agent. Violat i ons of the si gnal ri ngback
specificati on are not al l owed under any
circumst ances for the non-GTL+ signals.
Ringback can be simulated with or without the input
protecti on di odes that c an be added to the input
buffer model. However, signal s that reac h the
clamping voltage s houl d be eval uated further.
Table 4.5 shows t he s i gnal ri ngback spec i ficati ons
for non-GTL+ signal s at the proc essor core. Tabl e
4.6 shows the s i gnal ri ngback guideli nes for non-
GTL+ signals at the proces s or connector.
4.3.3 Settling Limit Guideline
Settl i ng l i mit defines the maximum amount of
ringing at t he rec ei vi ng signal that a signal m ay
reach before it s next transit i on. The amount all owed
is 10% of the total signal swing (VHI – VLO) above
and below its fi nal val ue. A signal s houl d be withi n
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the settling limits of its final value when either in i t s
high stat e or l ow st ate, before its next transition.
Signals t hat are not within thei r settli ng l i mit bef ore
transitioning are at risk of unwanted oscillations that
could jeopardize signal integri ty. Simulati ons to
verify settling l i mit may be done either wit h or
without the input protection di odes present. V i ol ation
of the settling li mit gui del i ne i s accept abl e i f
simulations of 5 to 10 suc c essive transitions do not
show the ampl i t ude of the ringing increasing in t he
subsequent t ransitions .
Table 4.5 Signal Ri ngback S pecifications for Non-GTL+ Signals at the P rocessor Core
Input Signal Group Transition M axim um Ringback
(with I nput Di odes P r esent) Figure
Non-GTL+ Signals 0
1 1.7 V 4.4
Non-GTL+ Signals 1
0 0.7 V 4.4
Table 4.6 Signal Ri ngback S pecifications for Non-GTL+ Signals at the P rocessor Connector
Input Signal Group Transition M axim um Ringback
(with I nput Di odes P r esent) Figure
Non-GTL+ Signals 0
1 1.7 V 4.4
Non-GTL+ Signals 1
0 0.7 V 4.4
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5. MECHANICAL SPECIFICATIONS
5.1 Connector Mechanical
Specifications
The mobil e P entium II m i ni -cartridge processor
board-to-board stacking c onnec tor consists of a
plug and a receptacle. A plug surface mounts to the
process or and mates t o the receptac l e, which
surfac e mounts to the m otherboard. Each hal f of the
connect or us es ball grid array (BGA) technology for
surfac e mount. The processor c onnector has 240
pins in an 8 x 30 array. A s ol der bal l i s attac hed t o
the tail of each contac t for surf ac e mount and t he
center-to-center distance between solder ball s
(pitch) i s 1.27 m m.
The plug mounted on the proces s or i s available in
one height. The rec eptacle mounted on the
mot herboard i s avai l abl e from an out side vendor in
two heights to al l ow for c omponent placement
flexibility within the package k eep-out line on the
system electronics. The board-to-board spac i ng i s
defined as t he spacing between the proc essor
subst rat e and the system electronics substrat e af ter
both halves of the connect or are reflowed onto their
respect i ve boards and mated. The board-to-board
spacing i s not to be c onf used with the bott om
clearance, which is the space below the cart ri dge.
For the m obi l e P entium II m i ni -cartridge proces sor
the available board-to-board spacings are 3.4 and 4
mm. These spacings are dependent on the height of
the receptacle, which is a functi on of the system
manuf ac turer’s mounting technique. The sys tem
manuf ac turer chooses the board-to-board spac i ng
to use for a particular s ystem design.
5.2 Mini-cartridge Assembly
Mechanical Specifications
The mobil e P entium II m i ni -cartridge processor is
enclosed by stainles s steel (300-series) covers;
however, the connect or and the process or di e are
exposed in order to accomm odate instal l ation into a
system. A s shown in Figure 5.5, the overall footpri nt
of the area reserved for the proces sor is 56.0 mm
by 60.0 mm. Note that the bottom cover is metallic,
so caut i on s houl d be taken to prevent shorting when
placing c omponents under t he processor.
Component s pl aced within the package keep-out
line should not contac t the process or. The
receptac l e and cover outline is shown in Figure 5.5
so that i t can be sil k screened ont o the system
electroni c s subst rate, to as s i st in manual placement
of the receptacle. The actual shape of the
receptac l e and c ap assem bl y i s more c omplic ated
than a rectangl e, but a rect angl e i s suff i c i ent for the
purpose of manual placement. Fi gure 5.4 and
Figure 5.5 show the location of t he l arge key of the
connector.
The process or should be securel y mounted to the
system board to prevent pot ential dam age due to
shock and vi brat i on. Four mount i ng hol es are
provided in order to facilitate mount ing f asteners
(M2 screws are recommended) t hrough the
process or and i nt o the standof fs on the s ys tem
board. Due to EMI concerns, i t is recomm ended that
a mount i ng s ystem t hat provides a low impedance
ground between the process or and the syst em
board be used.
As noted previ ously, the proc essor die is exposed in
order to acc omm odat e system therm al i nterface.
Table 5.2 cont ai ns the spec i ficati on for bond-line
thickness, which i s the dist ance between the top
surfac e of the die and the top surface of t he
processor. To facilitate this solution, the top cover is
recess ed around t he di e. More inform at i on about
EMI, mounting, standoff s, and thermal solut i on
attachment is provided in the
Mobile Pentium
II
Mini-cartridge Mechani cal and Thermal User Guide.
It is i mportant that the proc es sor not be
disassembled or permanently al t ered i n any way
(e.g., adding extra holes) in order t o f acilitate
system thermal solution attachment . Functionality of
a process or i s not guaranteed if i ts cover has been
removed. The addi t i on of adhesives and greases to
the exterior surfaces of t he product is not
considered to be permanent .
Figure 5.1 shows a c ros s-sect i on vi ew of t he
processor. Figure 5.2 and Figure 5.3 illustrate the
process or assem bl y t op and bottom c over
dimensions. Figure 5.4 illustrates the standoff and
connector locations and Figure 5. 5 illustrates t he
process or assem bl y keep-out areas. Table 5.1 and
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Table 5.2 cont ai ns the m echanical s pecific ations
for the min-cartri dge assem bl y.
OEM Thermal
Plate Top Cover
(recess) Processor
Core Die
Bottom
Cover
System
Electronics
Substrate
Processor
Substrate
V0029-00
Figure 5.1 M ini-cartridge Cross Section View
Table 5.1 Mechani cal Specificati ons
Symbol Parameter Max Unit Notes
X,YDIE Proc essor Core Die Dimensi ons 10.36
17.36 mm
mm Note 1
FINS Processor Ins ert i on Force 133 N
FEXT Processor Extraction Force 100 N
PDIE Allowable Press ure on Top of Di e for Thermal Attac h P l ate 413 kPa
PTOP Allowable Pres sure on Recess ed Part of the Top Cover 413 kPa
Shock Mechanical Shock Under Non-Operating Conditi ons 50 G
Vibration Mechanical Vi brat i on Under Non-Operating
Conditions Si ne Sweep
Random 1.0
3.1 G rm s
G rms
Humidi ty Relative Humidity Under Non-Operat i ng Condi tions 85 % non-
condensing
NOTE:
1. The long edge of the processor c ore di e i s parallel to the long edge of the mini-c art ri dge. These lengths
are approximate and will change from s tepping to stepping of the process or c ore.
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50.80
17.02
2.3 TYP
2.3 TYP
46.89 3. 93 TYP
3.93 TYP
23.44
20.99
25.01
4X Ø 4.4
Through Top Cover
2X Ø 2.4
Through Top Cove
r
6X Ø 2.41±0.025
Through Internal PCB
32.1
35.37
Ø 0.1 BL
- B -
- L -
V0033-00
Figure 5.2. Mini-cartridge Assembly, Top Cover (in mm)
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5.6 ± 0.10
Figure 5.3 M ini-cartridge Assembl y, Bottom Cover and Sides (in mm )
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50.80
29X 1.27
41.91
7X 1.27
1.02
-L-
-B-
LARGE KEY
PIN A1
Ø0.15 B L
46.89
V0035-00
Ø0.11 LB
STANDOFF LOCATION
4 PLACES
Figure 5.4 Standoff and Connector Location, Top View (in mm)
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42.5
15.012.9
2.04
56.0
60.0
2.25
LARGE KEY
PLUG
KEEPOUT
OUTLINE
RECEPTACLE AND
CAP OUTLINE
PIN A1
V0034-00
PACKAGE
KEEPOUT
OUTLINE
4.6
4.56
Figure 5.5. Mini-cartridge Assembly and Connector Keep-out Location, Top View (i n m m)
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Table 5.2. Mini-cartridge Vertical Dimensions1,2,3
Symbol Parameter Min Nom Max Unit Figure
H Processor Height 4.40 4.55 4.70 mm 5.6
M Plug Height 0.91 1.03 1.15 mm 5.6
P Bottom Cover Hei ght 2.81 REF mm 5.6
BLT B ond-Li ne Thi ckness 0.01 0.12 0.23 mm 5.6
NOTES:
1. For parameter definitions and illustration, s ee Table 5.3 and Figure 5.6.
2. Processor height, pl ug hei ght, bottom cover height and bond-line thickness are the only moni tored
vertical di mensions. The other dimensions in Table 5.3 and Figure 5.6 are dependent on the rec eptacle
height. Refer to the
Mobile Pentium
®
II Mi ni -cartridge Proc essor Mec hani c al and Thermal User Guide
for
information on the ef fect of receptacle mounting t echnique on these other dimensions.
3. These dimensions are subject to change.
Table 5.3 and Table 5. 3 def i ne the mini -cartridge
dimensions illustrated in Figure 5.6. The assembly
stac k hei ght (SH), board-t o-board s pacing (BS), and
bottom clearanc e (B C) di mensions are dependent
on the receptacle height. Refer to the
Mobile
Pentium II Mini-cartridge Processor Mechani cal and
Thermal User Guide
for information on t he effect of
receptac l e mounting t echnique on these
dimensions.
SH
BS
BLT
BC
P
M
H
V0030-00
Figure 5.6 Mini-cartridge Cross Section with Vertical Dimensions
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Table 5.3 Mini-cartridge Vertical Dimension Definitions
Symbol Parameter Definition
H Processor Height Distanc e from t he top surfac e of the process or to the m at i ng
surfac e of the plug.
M Plug Height Distance from the bottom of the proc essor subs trate to the
mat i ng s urface of t he pl ug.
P Bottom Cover Height Distanc e from t he bot tom s i de of the proces sor subst rat e to the
outer surface of the bot tom c over.
BLT Bond-Line Thickness Distanc e between the top surface of the die and t he top surfac e
of the processor.
SH Assembly S tack Height Distance from t he t op surface of the process or t o the system
electroni c s subst rate.
BS Board-to-Board Spacing Distance from the proces sor subst rat e to the sys t em electronics
substrate.
BC Bott om Clearance Distance from the bot t om surf ace of the proc essor to the
system electronics substrate.
5.2 Processor Pin Lists
Table 5.4 shows eac h signal by pin loc ation on
the m obi l e P entium II m i ni -cartridge proces sor.
Table 5.5 lists t he s i gnal s in alphabeti c al order.
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Table 5.4 Pin M ap
Pin A B C D E F G H
1 VSS VCC3 PREQ# VSS_S PRDY# BP2# BPM0# VSS
2 VCC3 VCC3 SMBALERT# VSS VCC_S VSS PICD0 PICCLK
3 BINIT# BP3# BPM1# VID0 VSS INTR VSS VCC
4 VCC VSS VCCP_S D49# D57# D55# DEP6# VID1
5 VSS D41# D42# VSS D53# VSS D56# DEP2#
6 D40# D52# D45# D46# D51# D62# D63# DEP1#
7 D34# D39# D47# D48# D54# D59# D58# DEP4#
8 VSS D44# D36# VSS D37# VSS D61# DEP7#
9 D38# D33# D35# D43# DEP0# VCC D60# DEP3#
10 VCC D31# D26# D27# D32# D28# D50# DEP5#
11 VSS D25# D22# D19# D29# VSS D30# VCC
12 D17# D16# D20# D21# D18# D24# PICD1 VSS
13 D14# D12# D10# D15# D23# D11# D13# VCC
14 VSS RSVD D4# D8# D9# D6# D7# VSS
15 VID3 D3# RSVD D1# D0# D5# D2# VCC
16 RSVD RSVD RSVD RSVD PWRGOOD TRST# TDO VSS
17 RSVD TMS TDI SLP# IGNNE# TCK FLUSH# VCC
18 FERR# STPCLK# A20M# INIT# RESET# RS0# RS1# VSS
19 IERR# SMI# BERR# VCC A35# A33# RP# VCC
20 VSS A32# A34# VSS A29# VSS VCC VSS
21 VCC A26# A30# A31# A25# BPRI# A3# BNR#
22 A24# A27# A22# A15# RSVD VCC A5# REQ2#
23 VSS A28# A23# VSS LOCK# VSS A6# REQ0#
24 A20# A21# VSS A17# A13# A10# A9# RSVD
25 VCC A19# REQ4# A16# A11# A8# A4# ADS#
26 VSS VSS RSP# VSS A12# VSS TRDY# DEFER#
27 DBSY# VCC VCC A18# A14# A7# RSVD REQ1#
28 REQ3# AERR# VSS DRDY# VSS RS2# VCC VCC
29 AP0# SMBDATA VID2 VSS BREQ0# VSS BCLK VCCP
30 VSS SMBCLK NMI AP1# HITM# HIT# VCCP VSS
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Table 5.4 Pin Listing in Signal Name Order
Pin Name Pin Signal Type Pin Name Pin Signal Type
A3# G21 Low Power GTL+ I/O A33# F19 Low Power GTL+ I/O
A4# G25 Low Power GTL+ I/O A34# C20 Low Power GTL+ I/ O
A5# G22 Low Power GTL+ I/O A35# E19 Low Power GTL+ I/O
A6# G23 Low Power GTL+ I/O A20M# C18 CMOS Input
A7# F27 Low Power GTL+ I/O ADS# H25 Low Power GTL+ I/O
A8# F25 Low Power GTL+ I/O AERR# B28 Low Power GTL+ I/O
A9# G24 Low Power GTL+ I/O AP0# A29 Low Power GTL+ I/O
A10# F24 Low Power GTL+ I/O AP1# D30 Low Power GTL+ I/O
A11# E25 Low Power GTL+ I/ O BCLK G29 System Bus Clock
A12# E26 Low Power GTL+ I/ O BE RR# C19 Low Power GTL+ I/O
A13# E24 Low Power GTL+ I/ O BINIT# A3 Low Power GTL+ I/O
A14# E27 Low Power GTL+ I/ O BNR# H21 Low Power GTL+ I/O
A15# D22 Low Power GTL+ I/O BP2# F1 Low Power GTL+ I/O
A16# D25 Low Power GTL+ I/O BP3# B3 Low Power GTL+ I/O
A17# D24 Low Power GTL+ I/O BPM0# G1 Low Power GTL+ I/O
A18# D27 Low Power GTL+ I/O B P M1# C3 Low Power GTL+ I/O
A19# B25 Low Power GTL+ I/ O BP RI # F21 Low Power GTL+ Input
A20# A24 Low Power GTL+ I/ O BREQ0# E29 Low Power GTL+ I/O
A21# B24 Low Power GTL+ I/ O D0# E15 Low Power GTL+ I/O
A22# C22 Low Power GTL+ I/O D1# D15 Low Power GTL+ I/ O
A23# C23 Low Power GTL+ I/O D2# G15 Low Power GTL+ I/ O
A24# A22 Low Power GTL+ I/ O D3# B15 Low Power GTL+ I/O
A25# E21 Low Power GTL+ I/ O D4# C14 Low Power GTL+ I/O
A26# B21 Low Power GTL+ I/ O D5# F 15 Low Power GTL+ I/O
A27# B22 Low Power GTL+ I/ O D6# F 14 Low Power GTL+ I/O
A28# B23 Low Power GTL+ I/ O D7# G14 Low Power GTL+ I/O
A29# E20 Low Power GTL+ I/ O D8# D14 Low Power GTL+ I/O
A30# C21 Low Power GTL+ I/O D9# E14 Low Power GTL+ I/O
A31# D21 Low Power GTL+ I/O D10# C13 Low Power GTL+ I/O
A32# B20 Low Power GTL+ I/ O D11# F13 Low Power GTL+ I/O
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Table 5.4 Pin Listing in Signal Name Order
Pin Name Pin Signal Type Pin Name Pin Signal Type
D12# B13 Low Power GTL+ I/O D42# C5 Low Power GTL+ I/O
D13# G13 Low Power GTL+ I/O D43# D9 Low Power GTL+ I/O
D14# A13 Low Power GTL+ I/O D44# B8 Low Power GTL+ I/O
D15# D13 Low Power GTL+ I/O D45# C6 Low Power GTL+ I/O
D16# B12 Low Power GTL+ I/O D46# D6 Low Power GTL+ I/O
D17# A12 Low Power GTL+ I/O D47# C7 Low Power GTL+ I/O
D18# E12 Low Power GTL+ I/O D48# D7 Low Power GTL+ I/O
D19# D11 Low Power GTL+ I/O D49# D4 Low Power GTL+ I/O
D20# C12 Low Power GTL+ I/O D50# G10 Low Power GTL+ I/O
D21# D12 Low Power GTL+ I/O D51# E6 Low Power GTL+ I/O
D22# C11 Low Power GTL+ I/O D52# B6 Low Power GTL+ I/O
D23# E13 Low Power GTL+ I/O D53# E5 Low Power GTL+ I/O
D24# F12 Low Power GTL+ I/O D54# E7 Low Power GTL+ I/O
D25# B11 Low Power GTL+ I/O D55# F4 Low Power GTL+ I/ O
D26# C10 Low Power GTL+ I/O D56# G5 Low Power GTL+ I/O
D27# D10 Low Power GTL+ I/O D57# E4 Low Power GTL+ I/O
D28# F10 Low Power GTL+ I/O D58# G7 Low Power GTL+ I/O
D29# E11 Low Power GTL+ I/O D59# F7 Low Power GTL+ I/ O
D30# G11 Low Power GTL+ I/O D60# G9 Low Power GTL+ I/O
D31# B10 Low Power GTL+ I/O D61# G8 Low Power GTL+ I/O
D32# E10 Low Power GTL+ I/O D62# F6 Low Power GTL+ I/ O
D33# B9 Low Power GTL+ I/O D63# G6 Low Power GTL+ I/O
D34# A7 Low Power GTL+ I/O DBSY# A27 Low Power GTL+ I/O
D35# C9 Low Power GTL+ I/O DEFER# H26 Low Power GTL+ Input
D36# C8 Low Power GTL+ I/O DEP0# E9 Low Power GTL+ I/O
D37# E8 Low Power GTL+ I/O DEP1# H6 Low Power GTL+ I/O
D38# A9 Low Power GTL+ I/O DEP2# H5 Low Power GTL+ I/O
D39# B7 Low Power GTL+ I/O DEP3# H9 Low Power GTL+ I/O
D40# A6 Low Power GTL+ I/O DEP4# H7 Low Power GTL+ I/O
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Table 5.4 Pin Listing in Signal Name Order
Pin Name Pin Signal Type Pin Name Pin Signal Type
D41# B5 Low Power GTL+ I/O DE P 5# H10 Low Power GTL+ I/O
DEP6# G4 Low Power GTL+ I/O RSVD A16 Reserved
DEP7# H8 Low Power GTL+ I/O RSVD A17 Reserved
DRDY# D28 Low Power GTL+ I/O RSVD B14 Reserved
FERR# A18 Open Drain Output RSVD B16 Reserved
FLUSH# G17 CMOS Input RSVD C15 Reserved
HIT# F30 Low Power GTL+ I/O RSVD C16 Reserved
HITM# E 30 Low Power GTL+ I/O RSVD D16 Reserved
IERR# A19 Open Drain Out put RSVD E22 Reserved
IGNNE# E17 CMOS Input RSVD G27 Reserved
INIT# D18 CMOS I nput RSVD H24 Reserved
INTR F3 CMOS Input SLP# D17 CMOS Input
LOCK# E23 Low Power GTL+ I/O SMBALERT# C2 SMBus Alert
NMI C30 CMOS Input SMBCLK B30 SMBus Clock
PICCLK H2 API C Cl ock Input SMBDATA B29 SMBus I/O
PICD0 G2 CMOS I/O SMI# B19 CMOS Input
PICD1 G12 CMOS I/O STPCLK# B 18 CMOS Input
PRDY# E1 Low Power GTL+ Output TCK F17 TAP Clock Input
PREQ# C1 CMOS Input TDI C17 TAP Input
PWRGOOD E16 CMOS I nput TDO G16 TAP Output
REQ0# H23 Low Power GTL+ I/O TMS B17 TAP Input
REQ1# H27 Low Power GTL+ I/O TRDY# G26 Low Power GTL+ Input
REQ2# H22 Low Power GTL+ I/O TRST# F16 TAP Input
REQ3# A28 Low Power GTL+ I/O VCC A4 Core VCC
REQ4# C25 Low Power GTL+ I/O VCC A10 Core VCC
RESET# E18 Low Power GTL+ Input VCC A21 Core VCC
RP# G19 Low Power GTL+ I/O VCC A25 Core VCC
RS0# F18 Low Power GTL+ Input VCC B27 Core VCC
RS1# G18 Low Power GTL+ Input VCC C27 Core VCC
RS2# F28 Low Power GTL+ Input VCC D19 Core VCC
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Table 5.4 Pin Listing in Signal Name Order
Pin Name Pin Signal Type Pin Name Pin Signal Type
RSP# C26 Low Power GTL+ Input VCC F 9 Core VCC
VCC F22 Core VCC VSS B4 Ground
VCC G20 Core VCC VSS B26 Ground
VCC G28 Core VCC VSS C24 Ground
VCC H3 Core VCC VSS C28 Ground
VCC H11 Core VCC VSS D2 Ground
VCC H13 Core VCC VSS D5 Ground
VCC H15 Core VCC VSS D8 Ground
VCC H17 Core VCC VSS D20 Ground
VCC H19 Core VCC VSS D23 Ground
VCC H28 Core VCC VSS D26 Ground
VCC_S E2 Core VCC Sense VSS D29 Ground
VCC3 A2 Cache Core VCC VSS E3 Ground
VCC3 B1 Cache Core VCC VSS E28 Ground
VCC3 B2 Cache Core VCC VSS F2 Ground
VCCP G30 Cache I/O V CC VSS F5 Ground
VCCP H29 Cache I/O V CC VSS F8 Ground
VCCP_S C4 Cache I/O V CC Sense VSS F11 Ground
VID0 D3 Voltage Identificat i on VSS F20 Ground
VID1 H4 Voltage Identificat i on VSS F23 Ground
VID2 C29 Voltage Ident i ficati on VSS F26 Ground
VID3 A15 Voltage Identifi cation VSS F29 Ground
VSS A1 Ground VSS G3 Ground
VSS A5 Ground VSS H1 Ground
VSS A8 Ground VSS H12 Ground
VSS A11 Ground VSS H14 Ground
VSS A14 Ground VSS H16 Ground
VSS A20 Ground VSS H18 Ground
VSS A23 Ground VSS H20 Ground
VSS A26 Ground VSS H30 Ground
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Table 5.4 Pin Listing in Signal Name Order
Pin Name Pin Signal Type Pin Name Pin Signal Type
VSS A30 Ground VSS_S D1 Ground Sense
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6. THERMAL SPECIFICATIONS
The mobil e P entium II m i ni -cartridge processor
contains an enclosure that allows for a number of
different thermal managem ent soluti ons for the
system m anufacturer. Thi s section contains the
therm al c haracteristics of the proces sor. In order to
achieve proper cool i ng of the proces s or, a therm al
soluti on (e. g., heat s preader, heat pipe, or ot her
heat transfer system) m ust be sec urel y at tached to
the proces s or’ s top cover and make fi rm cont act to
the exposed process or di e. The process or di e must
be clean before t he thermal solution i s attached or
the proces s or may be dam aged.
During all operati ng envi ronments , the process or
case t emperature, T PROC, must be within the
specified range of 0 °C to 100 °C. The thermal
sensor c an be used to m eas ure the process or
tem perat ure to ensure compliance with this
specificati on. See Sect i on 3. 2 for a description of
the thermal sens or. The thermal sensor m easures
the temperature of t he processor c ore with an
accuracy of ±3 °C.
Table 6.1 Mobile Pentium II Processor Pow er S pecifications
Symbol Parameter Min Typ1Max Unit Notes
TDP Thermal Desi gn Power at 400 MHz
at 366 MHz
at 333 MHz
at 300PE MHz
at 266PE MHz
—
—
—
—
—
13.15
13.1
11.8
11.1
9.8
W
W
W
W
W
at 100°C 2, 3
PSGNT Stop Grant and Auto Halt power 1.25 W at 50°C 3
PQS Quick S tart and Sleep power 500 mW at 50°C 3
PDSLP Deep Sl eep power 150 mW at 50°C 3
TCASE Process or Temperature 0 100 °C
NOTES:
1. TDPTYP is a recommendation bas ed on the power dissipati on of the proces s or while executi ng publ i cly
available software under normal operat i ng conditions at nominal vol t ages. Contac t your Intel Fiel d Sales
Representati ve for further inf ormation.
2. TDPMAX i s a specificati on of the total power dis s i pation of the processor while executing a worst -case
instruction mix under normal operati ng c ondi tions at nominal voltages. I t i ncludes the power dis s i pated by
all of t he c omponents withi n the process or. Specif i ed by design/characterizati on.
3. Not 100% tes t ed or guaranteed. The power specif i cations are compos ed of the current of t he processor
on the various vol t age pl anes. These c urrents are m easured and specified at high t emperature in
Table 3.4. The 50° C power spec i f i cations are determined by characterization of the processor c urrent s at
higher temperatures.
4. The ±3°C accuracy of the thermal sensor is not 100% tested. It is specified by design/ characterizat i on.
5. Refer to Table 3.5 f or the VCC and power specif i c ations of the 400 MHz processor.
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7. PROCESSOR INITIALIZATION
AND CONFIGURATION
7.1 Description
The mobil e P entium II proces sor mini -cartridge
has some confi gurat i on options that are
determ i ned by hardware and some that are
determ i ned by s oftware. The processor sam pl es
its hardware conf i gurat i on at reset, on t he active-
to-inactive transition of RESET#. Most of the
configurat i on options for the mobil e Pentium II
mini -cartridge processor are identi cal to thos e of
the Penti um II processor. The
Pentium
®
II
Processor Developer’s Manual
describes these
configurat i on options. New conf i guration options
for the mobile Pent i um II mini-c art ri dge processor
are described i n t he remainder of this section.
7.1.1 Quick Start Enabl e
The process or normally enters the St op Grant
state when the S T P CLK # signal is asserted but i t
will enter the Quick Start state ins t ead if A15# is
sampled ac t i ve on the RESET# s i gnal’s active-to-
inacti ve t ransition. The Qui ck St art state s upport s
snoops f rom the bus pri ori ty device like the Stop
Grant state but it does not support symmetric
mas t er snoops nor is t he l atching of i nterrupts
supported. A “1” in bit pos i tion 5 of the P ower-on
Configurati on regi s ter indicat es that t he Qui ck
Start state has been enabl ed.
7.1.2 System Bus Frequency
The current generati on mobile P entium II m i ni -
cartridge processor will only function with a
syst em bus f requency of 66 MHz, but future
generations may operate at 100 MHz. Bit posi tion
19 of the Power-on Configuration regist er
indicates at which s peed a proc essor will run. A
“0” in bit 19 indi cates a 66-MHz bus f requenc y
and a “1” indicates a 100-MHz bus frequency.
7.1.3 APIC Di sable
If the PICD0 signal i s sam pl ed l ow on the ac t i ve-
to-inactive trans it ion of the RESET# signal then
the PICCLK signal c an be tied to VSS. This is
required sinc e the APIC has been removed as a
feature of the mobil e Pentium II mini-cart ri dge
process or. Dri vi ng P ICD0 low at reset also has
the effect of c l eari ng the APIC Gl obal E nabl e bi t
in the APIC Base MSR. This bit is normally set
when the processor i s reset, but when it is
cleared the A PIC is completely disabled unt i l the
next reset.
7.2 Clock Frequencies and
Ratios
The mobil e P entium II m i ni -cartridge processor
uses a c l ock design i n which the bus clock is
multiplied by a rati o to produce the proc es sor’s
internal (or “c ore”) clock. The ratio used i s
programmed into t he proc essor when it is
manufactured.
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8. PROCESSOR INTERFACE
8.1 Alphabetical Signal Reference
A[35:3]# (I/O - Low Pow er GTL+)
The A[35:3]# (Address ) s i gnal s define a 236-byte
physical mem ory address spac e. When ADS# is
active t hese signals transmit the address of a
transaction; when ADS# is i nactive these signals
transmit transaction i nformat i on. These signals must
be connect ed t o the appropriate pins of both agents
on the system bus . The A[35:24]# signals are
protected with the AP1# parit y signal, and t he
A[23:3]# signals are protected with t he A P0# parity
signal.
On the active-to-inactive transition of RESET#, each
process or bus agent samples A[35:3]# s i gnal s to
determ i ne i ts power-on configurat i on. See Section 4
of this document and the
Pentium
®
II Processor
Developer’s Manual
for detail s .
A20M# (I - 2.5V tolerant)
If the A20M# (Address-20 Mask ) i nput signal is
asserted, the processor masks physical addres s bit
20 (A20#) before look i ng up a l i ne i n any i nternal
cache and bef ore dri ving a read/write transaction on
the bus. Assert i ng A 20M# emulates the 8086
process or' s address wrap-around at the 1-Mbyte
boundary. Assertion of A20M# is only support ed i n
real mode.
ADS# (I/O - Low Power GTL+)
The ADS# (Addres s Strobe) s i gnal i s assert ed t o
indicat e t he val i di ty of a trans action address on the
A[35:3]# signals . Both bus agents observe t he
ADS# act i vation to begin parity check i ng, protocol
check i ng, address decode, i nternal snoop, or
deferred reply ID match operations associated with
the new transact i on. This si gnal must be connected
to the appropriat e pi ns on both agents on the
system bus.
AERR# (I/O - Low Power GTL+)
The AERR# (Address Parit y E rror) signal is
observed and driven by both s ys tem bus agents,
and if used, must be connected t o the appropriate
pins of bot h agents on the s ys tem bus . AERR#
observation i s optionally enabled duri ng power-on
configurat i on; if enabled, a val i d assertion of AERR#
aborts the current trans action.
If AERR# observation i s disabled during power-on
configurat i on, a central agent may handle an
assert i on of AERR# as appropriat e to the error
handling architecture of t he system.
The AERR# processor bus pin i s removed as a
process or f eature for m obi l e Pentium® II processor
at 400 MHz. The pin mus t still be terminated to V CC
through a 120
pull-up resistor, but the process or
mus t not be configured to drive or observe the pi n.
AP[1:0]# (I /O - Low Power GTL+)
The AP[1:0]# (Address Parity) s i gnal s are driven by
the request i ni tiator along with A DS #, A[35:3]#,
REQ[4:0]# and RP#. AP1# covers A[35:24]#. A P0#
covers A[23:3]#. A correct parity signal is high if an
even number of c overed signals are l ow and low if
an odd number of c overed signals are l ow. This
allows parity t o be hi gh when all t he covered signals
are high. AP [1:0]# shoul d be connected t o the
appropriate pins on bot h agents on the s ys tem bus .
BCLK (I - 2.5V tolerant)
The BCLK (Bus Cl ock) signal determines the
system bus f requency. Both system bus agents
mus t receive this signal to drive t hei r outputs and
latch t hei r i nputs on the B CLK ri sing edge. Al l
external tim i ng parameters are specifi ed with
respect t o the BCLK si gnal .
BERR# (I/O - Low Power GTL+)
The BERR# (Bus Error) signal i s asserted t o
indicat e an unrecoverable error without a bus
protocol vi ol at i on. Either system bus agent may
drive BERR#, and i t mus t be connect ed to the
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appropriate pins of both agents, i f used. However,
mobil e P entium II m i ni -cartridge processors do not
observe ass ert i ons of the B E RR# signal.
BERR# assertion condi tions are defi ned by the
system conf i guration. Confi gurat i on options enable
the BERR# driver as foll ows:
Enabled or disabl ed
Asserted optionally f or i nternal errors along with
IERR#
Asserted optionally by t he request init i ator of a
bus transaction after it observes an error
Asserted by any bus agent when it obs erves an
error in a bus trans action
BINIT# (I/O - Low Power GTL+)
The BINIT# (Bus Init i al i zation) signal may be
observed and driven by both s ys tem bus agents,
and it must be c onnec ted to the appropriate pins of
both agents, if used. If t he B INIT# driver is enabl ed
during the power-on configurat i on, BINI T# i s
assert ed t o signal any bus c ondi tion that prevents
reliable future information.
If BINIT# is enabl ed duri ng power-on conf i gurat i on
and BINIT# i s sam pl ed asserted, al l bus state
mac hi nes are reset and any data whic h was in
transit i s lost. All agent s reset thei r rotating ID f or
bus arbitrat i on to the st at e after reset , and internal
count inf ormation i s lost. The L1 and L2 caches are
not affected.
If BINIT# is di sabled during power-on configurat i on,
a central agent may handle an as s ertion of BINIT#
as appropriate t o the Machine Check A rchitecture
(MCA) of the s ystem .
BNR# (I/O - Lo w Pow er GTL+)
The BNR# (Bloc k Next Request) signal i s used to
assert a bus stall by any bus agent that is unable to
accept new bus transactions. During a bus stall, the
current bus owner cannot i ssue any new
transactions.
Since multi pl e agent s may need t o request a bus
stall simul taneously, B NR# i s a wired-OR signal
which mus t be connect ed t o the appropriate pins of
both agents on the syst em bus. In order to avoid
wire-OR errors assoc i ated with simultaneous edge
transitions driven by multiple drivers, BNR# is
activat ed on specifi c cloc k edges and sam pl ed on
specific cl ock edges.
BP[3:2]# (I / O - L ow Power GTL+)
The BP[3:2]# (Breakpoi nt) signals are the System
Support group Breakpoint si gnal s. They are outputs
from the process or that indic ate the status of
breakpoints.
BPM[1:0]# (I/O - Low Power GTL+)
The BPM[1:0]# (Breakpoint Monitor) signals are
breakpoint and perf ormance monitor s i gnal s. They
are outputs from t he processor t hat i ndi cate the
status of breakpoints and program mable counters
used for monitoring processor perf ormance.
BPRI# (I - Low Power GTL+)
The BPRI# (B us Priorit y Reques t) signal is used to
arbitrate f or ownership of the system bus . It must be
connect ed t o the appropriate pins on both agents on
the system bus . Observing BP RI # active (as
assert ed by t he pri ori ty agent) causes the proces sor
to stop i ssuing new requests , unless such request s
are part of an ongoing l oc ked operation. The pri ori ty
agent keeps B PRI# asserted until all of its requests
are com pl et ed and then releases the bus by
deassert i ng B PRI#.
BREQ0# (I/O - Low Power GTL+)
The BREQ0# (Bus Request) si gnal i s a process or
Arbitrat i on B us signal. The processor indi cates t hat
it wants ownership of t he system bus by asserting
the BREQ0# signal.
During power-up configurati on, the central agent
mus t assert t he BREQ0# bus si gnal . The process or
sam pl es BREQ0# on the active-to-i nactive trans i tion
of RESET#.
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D[63:0]# (I/O - Low Pow er GTL+)
The D[63:0]# (Data) signals are the data signal s.
These signal s provide a 64-bit dat a pat h between
both system bus agents and m ust be connected to
the appropriate pi ns on both agents. The data driver
assert s DRDY# to i ndi cate a valid data transf er.
DBSY# (I/O - Low Power GTL+)
The DBSY# (Data Bus Busy) signal is asserted by
the agent responsible for dri ving data on the system
bus to indi cate that the data bus is in use. The data
bus is released after DBSY# is deas s erted. This
signal must be connected t o t he appropri ate pins on
both agents on the syst em bus.
DEFER# (I - Low Power GTL+)
The DEFER# (Defer) signal is asserted by an agent
to indic at e that the t rans action cannot be
guaranteed in-order completi on. Assert i on of
DEFER# is normally the responsibilit y of t he
addressed memory agent or I/O agent . Thi s signal
mus t be connected t o the appropriate pins on both
agents on the system bus.
DEP[7:0]# (I /O - Low Power GTL+)
The DEP[7:0]# (Data Bus ECC Protection) si gnal s
provide optional E CC protection for the data bus .
They are driven by the agent res ponsible for drivi ng
D[63:0]#, and they m ust be connec t ed to the
appropriate pins on bot h agents on the s ys tem bus
if they are us ed. During power-on configurati on,
DEP[7:0]# signal s can be enabled for E CC checking
or disabled f or no checking.
DRDY# (I/O - Lo w Pow er GTL+)
The DRDY# (Data Ready) signal is asserted by t h e
data driver on each dat a transfer, i ndi cating valid
data on the data bus. In a multi-cycle data t ransfer,
DRDY# can be deas serted to i nsert idle clocks. This
signal must be connected t o t he appropri ate pins on
both agents on the syst em bus.
FERR# (O - 2.5V tolerant open-drain)
The FERR# (Floating-poi nt Error) signal i s assert ed
when the processor det ects an unmasked floating-
point error. FE RR# i s similar to t he ERROR# signal
on the Intel 387 coprocess or, and it is i ncluded for
compatibility with systems using DOS-type floating-
point error reporti ng.
FLUSH# (I - 2.5V tolerant)
When the FLUSH# (Fl us h) i nput signal i s asserted
the proces s or writes back all i nternal cache l i nes in
the Modified s tate and invalidates all internal cache
lines. A t the completion of a flush operat i on, the
process or i ssues a Flush Ack nowledge trans action.
The process or stops c ac hi ng any new data while the
FLUSH# signal remains asserted.
On the active-to-inactive transition of RESET#, each
process or bus agent samples FLUSH# to determ i ne
its power-on conf i gurat i on.
HIT# (I/O - Low Power GTL+), HITM# (I/O - Low
Power GTL+)
The HIT# (Snoop Hit ) and HITM# (Hit Modified)
signals convey transac t i on snoop operation resul ts,
and they m us t be connect ed to the appropriate pi ns
on both agents on the syst em bus. Either bus agent
can ass ert both HIT# and HITM# toget her to
indicat e t hat it requires a snoop stall , which can be
continued by reasserting HI T# and HITM# together.
IERR# (O - 2.5V tolerant open-drain)
The IERR# (Internal Error) si gnal i s assert ed by t he
process or as the result of an internal error.
Assertion of IERR# is usual l y ac companied by a
SHUTDOWN trans action on the system bus. This
transaction may optionally be converted to an
external error signal (e.g., NMI) by sys t em logic. The
processor will keep IERR# asserted until it is
handled in sof t ware or with the as sertion of
RESET#, BINIT, or INIT#.
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IGNNE# (I - 2.5V tolerant)
The IGNNE# (Ignore Numeric E rror) signal is
assert ed t o force the proc essor to ignore a numeric
error and continue t o execut e non-control fl oat i ng-
point ins t ructions. If I GNNE# is deasserted, the
process or f reezes on a non-control floating-point
instruction if a previ ous i nstruct i on caused an error.
IGNNE# has no ef fect when the NE bi t i n control
register 0 (CR0) i s set.
INIT# (I - 2.5V tolerant)
The INIT# (I ni t i al i zation) signal i s assert ed to reset
integer regis t ers inside t he processor without
affecting the int ernal (L1 or L2) caches or t he
floati ng-poi nt regi sters. The processor begins
execution at the power-on reset vector conf i gured
during power-on configurati on. The processor
continues to handle snoop requests during I NIT#
assert i on. INIT# is an as ynchronous input.
If INIT# is sampled active on RESET#'s active-to-
inacti ve t ransition, then the proces sor executes its
built-in self test (BIST).
INTR (I - 2.5V tolerant)
The INTR (Interrupt) signal indi cates t hat an
external interrupt has been generated. INTR
becom es the LINT0 si gnal when the A P IC is
enabled. The int errupt i s mas kable using t he IF bit
in the EFLAGS register. If the IF bit is set, the
process or vectors to the interrupt handl er after
com pl et i ng the current instruct i on executi on. Upon
recognizing t he i nt errupt request, the process or
issues a single I nterrupt Acknowledge (INTA) bus
transaction. INTR must remain act i ve until the I NTA
bus transaction to guarantee its recognition.
INTR must be deass erted for a m i ni mum of two
clocks to guarantee its inac tive recognit i on. If APIC
is enabled at Reset, then LINT[1:0] i s the default
configuration.
LINT[1:0] (I - 2.5V toleran t)
The LINT[1:0] (Local AP IC Interrupt ) signals must
be connect ed t o the appropriate pins of all APIC bus
agents, i ncluding the proc essor and the s ystem
logic or I /O APIC com ponent. When APIC is
disabled t he LI NT0 signal becomes I NTR, a
mas kable interrupt reques t signal, and LINT1
becom es NMI, a non-m askable int errupt. INTR and
NMI are backward compatible with t he same s i gnal s
of the Pentium processor. B oth signals are
asynchronous i nput s.
Both of these signal s mus t be software conf i gured
by programming the APIC register space t o be us ed
either as NMI/INTR or LINT[1:0] in the BIOS. If the
APIC i s enabled at reset, then LINT[1:0] is the
default c onfiguration.
LOCK# (I/O - Low Pow er GTL+)
The LOCK# (Lock) signal indicates to the system
that a sequence of trans actions must oc cur
atom i c al l y. This si gnal must be connected to the
appropriate pins on bot h agents on the s ys tem bus .
For a locked sequence of t rans actions, LOCK# is
assert ed f rom the beginni ng of the first transaction
through the end of the last transact i on.
When the priority agent asserts BPRI# to arbitrat e
for bus ownership, i t waits until it observes LOCK #
deassert ed. Thi s enables the processor t o retain
bus ownership throughout t he bus locked operation
and guarantee the atomici ty of lock.
NMI (I - 2.5V tolerant)
The NMI (Non-mas kable Interrupt) indicat es that an
external interrupt has been generated. NMI
becom es the LINT1 si gnal when the A P IC is
disabled. A sserting NMI c auses an interrupt with an
internally s uppl i ed vector value of 2. An external
interrupt-ac knowledge transact i on i s not generated.
If NMI is assert ed duri ng t he execut i on of an NMI
service routine, it remains pendi ng and i s
recognized aft er the IRET is executed by the NMI
service routine. At most , one asserti on of NMI is
held pending.
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NMI is ris i ng-edge sensiti ve. If ass erted
asynchronous l y, active and inac tive pulse widths
must be a minimum of two clocks.
PICCLK (I - 2.5V tolerant)
The PICCLK (A PIC Clock) signal is an input cl ock to
the proces s or and system logic or I/O APIC that is
required for operati on of the process or, system logic
and I/O APIC components on the APIC bus.
PICD[1:0] (I/O - 2.5V tolerant open-drain)
The PICD[1:0] (APIC Data) signal s are used for bi-
directi onal serial m essage pass i ng on the APIC bus.
They mus t be connected t o the appropriate pins of
all APIC bus agents , including the process or and
the system logi c or I/O A P IC com ponents. If the
PICD0 si gnal i s sam pl ed l ow on the ac tive-to-
inactive transit ion of the RESET# signal, t hen t he
APIC i s hardware disabled.
PRDY# (O - Low Pow er GTL+)
The PRDY# (Probe Ready) signal is a processor
output used by debug tools to determine processor
debug readiness.
PREQ# (I - 2.5V tolerant)
The PREQ# (Probe Request) signal i s used by
debug tools t o request debug operation of the
processor.
PWRGOOD (I - 2.5V tolerant)
PWRGOOD (Power Good) is a 2.5V t olerant input.
The process or requi res this signal to be a c l ean
indication that clocks and the power supplies (V CC,
VCCP, etc.) are st abl e and withi n t hei r specifi cations.
Clean implies t hat the signal will remain low,
(capable of sinking leakage current) and without
errors, from the t i me that t he power suppli es are
turned on, unti l they com e withi n specifi cation. The
signal will then transition monotonically to a high
(2.5V) state. Figure 8.1 illustrates the relationship of
PWRGOOD to other system signals. P WRGOOD
can be driven inactive at any time, but clocks and
power must agai n be stable before t he ri sing edge
of PWRGOOD. I t must also meet the mi nimum
pulse width specified in Tabl e 3.12 (Sect i on 3.6.1)
and be followed by a 1 ms RESET# pulse.
BCLK
PWRGOOD
RESET#
D0026-00
1 msec
VIH,min
VCC,
VCCP,
VREF
Figure 8.1 PWRGOOD Relationshi p at P o wer-on
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The PWRGOOD signal, which must be supplied to
the proces s or, is used to protect i nternal circ ui t s
against voltage sequencing issues. The PWRGOOD
signal s houl d be dri ven high throughout boundary
scan operat i on.
REQ[4:0]# (I/O - Low Power GTL+)
The REQ[4:0]# (Request Command) signals must
be connect ed t o the appropriate pins on both agents
on the system bus . They are assert ed by t he current
bus owner when it drives A[35:3]# to defi ne the
currently ac tive transaction type.
RESET# (I - Low Power GTL+)
Asserting the RESET# s i gnal reset s the process or
to a known stat e and i nval i dates the L1 and L2
caches without writi ng back Modified (M state) lines .
For a power-on type reset, RESET# must stay
active f or at least 1 msec after VCC and BCLK have
reached their proper DC and A C specifi cations and
after PWRGOOD has been ass erted. When
observing active RESET#, all bus agent s will
deassert their outputs within two clocks.
A number of bus signal s are sam pl ed at the act i ve-
to-inactive transition of RESET# for the power-on
configurat i on. The configuration options are
described i n Section 4 and i n t he
Pentium
®
II
Processor Developer’s Manual
.
Unless i ts outputs are tri-stated during power-on
configurat i on, after an ac tive-to-inac t i ve transiti on of
RESET#, the process or opt ionally executes it s built-
in self -t est (BI S T) and begi ns program executi on at
reset-vector 000FFFF0H or FFFFFFF0H. RESET#
mus t be connected t o the appropriate pins on both
agents on the system bus.
RP# (I/O - Low Pow er GTL+)
The RP# (Request Parity) signal i s driven by the
request ini t i ator, and it provi des parity protection on
ADS# and REQ[ 4:0]#. RP# should be connected to
the appropriate pi ns on both agents on t he system
bus.
A correct parity si gnal i s high if an even number of
covered signal s are low and low if an odd number of
covered signal s are low. This defi ni tion allows parity
to be high when all covered s i gnal s are high.
RS[2:0]# (I - L ow Power GTL+)
The RS[2:0]# (Response S t atus) signal s are driven
by the respons e agent (the agent respons i bl e for
com pl et i on of the current transacti on), and they
mus t be connected t o the appropriate pins on both
agents on the system bus.
RSP# (I - Low Power GTL+)
The RSP# (Response Parity) s i gnal i s driven by the
response agent (t he agent responsibl e for
com pl et i on of the current transacti on) duri ng
assert i on of RS[2: 0 ] # . RSP# provides pari ty
protecti on for RS[2: 0] #. RSP# shoul d be connected
to the appropriat e pi ns on both agents on the
system bus.
A correct parity si gnal i s high if an even number of
covered signal s are low and low if an odd number of
covered signal s are low. During Idle s tate of
RS[2:0]# (RS[2:0]#=000), RSP# i s also high s i nce it
is not dri ven by any agent guaranteeing correct
parity.
SLP# (I - 2. 5V tolerant)
The SLP# (Sl eep) signal when asserted i n the Stop
Grant state causes the process or to enter the Sl eep
state. During the Sl eep state, the process or stops
providing internal clock signals t o al l uni ts, leavi ng
only the Phase-Loc k ed Loop (PLL) still running. The
processor will not recognize s noop and interrupts in
the Sleep s t ate. The processor will only recognize
changes in the SLP#, STPCLK#, and RESET#
signals while in the Sleep state. If SLP# is
deassert ed, the process or exits Sleep st ate and
returns to the Stop Grant s tate in which it restarts i t s
internal c l ock to the bus and API C proc essor units.
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SM BALERT# (O - 5V tolerant)
The SMBALERT# (S MBus Alert) signal is used by
the thermal sens or on t he processor t o i ndi cate that
it requires at tention. It is compli ant with the
SMBALERT# s i gnal of the System Management
Bus Specific ation. To use the process or’ s thermal
sensor, t hi s pin must be connec ted to the
appropriate pin on an SMB us host cont rol l er.
SMBCLK (I/O - 5V tolerant)
The SMBCLK (SMBus Clock) signal is compli ant
with the SMBCLK signal of t he S ys tem
Management B us Specif i cation. To use the
process or’ s therm al s ensor, this pin must be
connect ed t o the appropriate pin on an S MBus host
controller.
SMBDATA (I/O - 5V tolerant)
The SMBDATA (SMBus Data) s i gnal i s com pl i ant
with the SMBDAT A signal of t he S ystem
Management B us Specif i cation. To use the
process or’ s therm al s ensor, this pin must be
connect ed t o the appropriate pin on an S MBus host
controller.
SMI# (I - 2.5V tolerant)
The System Management Interrupt (SMI #) i s
assert ed as ynchronously by sys tem logi c. On
accept i ng a S MI# the process or saves the c urrent
state and enters System Management Mode (SMM).
An SMI Acknowledge transac tion is issued, and t he
process or begi ns program execution from t he S MM
handler.
STPCLK# (I - 2.5V tol erant)
The STPCLK# (Stop Clock) signal, when ass ert ed,
causes t he processor t o enter a low-power Stop
Grant state. The proces sor issues a Stop Grant
Acknowledge s pec i al transact i on, and it st ops
providing internal clock signals t o al l uni ts except
the bus and APIC units. The proces s or continues to
snoop bus t rans actions and service int errupts while
in the St op Grant stat e. When STPCLK # i s
deassert ed, the process or restarts i t s internal c l ock
to all units and resumes execution. The assertion of
STPCLK# has no effec t on the bus c l oc k.
TCK (I - 2.5V tolerant)
The TCK (Test Cl ock) signal provi des the clock
input for t he test bus (al so known as the test access
port).
TDI (I - 2.5V to l eran t)
The TDI (Test Data In) signal transfers serial tes t
data to the processor. TDI provides the serial input
needed for JTA G support.
TDO (O - 2.5V tolerant open-drain)
The TDO (Test Data Out) signal t ransfers s eri al t est
data from the proces sor. TDO provides the serial
output needed for JTAG support.
TMS (I - 2.5V toleran t)
The TMS (Test Mode Select) signal is a JTAG
support s i gnal us ed by debug tools.
TRDY# (I - Low Pow er GTL+)
The TRDY# (Target Ready) si gnal i s assert ed by
the target to indicat e that the target is ready to
receive write or implici t writeback data t rans fer.
TRDY# must be connec ted to the appropriate pins
on both agents on the syst em bus.
TRST# (I - 2.5V tolerant)
The TRST# (Test Reset) signal resets the Test
Access Port (TA P) logic. mobile P ent i um II mini-
cartridge processors do not self-reset during power-
on; therefore, it is necessary t o dri ve t hi s signal low
during power-on reset.
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VID[3:0] (O - open drain)
The VID[3:0] (Volt age ID) pins can be used to
support automatic selec t i on of power supply
voltages. These pins are not signals but are ei ther
an open circui t or a short to VSS on the processor
subst rat e. The com bi nation of opens and shorts
encodes t he vol t age requi red by the process or. The
VID pins are needed to cleanly s upport voltage
specificati on changes on m obi l e P entium II m i ni -
cartridge processors . These pins (VID3 through
VID0) are defi ned i n Table 8.1. A “1” i n this tabl e
refers to an open pi n and “0” refers to a s hort to
ground. The power supply m ust supply t he vol tage
that is requested or disabl e i tself.
8.2 Signal Summaries
Table 8.1 through Tabl e 8. 5 l i st the at t ri butes of t he
process or i nput , output, and I /O signals.
Table 8.1 Voltage Identi fication Pin En codi ng
VID[3:0] Vcc VID[3:0] Vcc VID[3:0] Vcc VID[3:0] Vcc
0000 2.00 0100 1.80 1000 1.60 1100 1.40
0001 1.95 0101 1.75 1001 1.55 1101 1.35
0010 1.90 0110 1.70 1010 1.50 1110 1.30
0011 1.85 0111 1. 65 1011 1.45 1111 No CP U
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Table 8.2 Input Signals
Name Active Level Clock S ignal Group Qualified
A20M# Low Asynch CMOS Always
BCLK High — S ystem Bus Always
BPRI# Low BCLK System Bus Always
DEFER# Low BCLK System Bus Always
FLUSH# Low Asynch CMOS Always
IGNNE# Low Asynch CMOS Always
INIT# Low Async h Syst em Bus A l ways
INTR High Asynch CMOS APIC dis abl ed mode
LINT[1:0] High Asynch AP I C APIC enabl ed mode
NMI High Asynch CMOS APIC disabled mode
PICCLK High — APIC Always
PREQ# Low Asynch Implementation Always
PWRGOOD High Asynch Implementation Always
RESET# Low BCLK System Bus Always
RS[2: 0]# Low BCLK System Bus Always
RSP# Low BCLK System Bus Always
SLP# Low Asynch I mplementation St op Grant state
SMI# Low Asynch CMOS Always 2
STPCLK# Low Asynch Implementation Always
TCK High — JTAG
TDI TCK JTAG
TMS TCK JTAG
TRDY# Low BCLK System Bus Respons e phase
TRST# Low Asynch JTAG
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Table 8.3 Output Signals
Name Active Level Cl ock Signal Group
FERR# Low Asynch Open-Drain
IERR# Low Asynch Open-Drain
PRDY# Low BCLK Implementation
SMBALERT# Low Asynch SMBus
TDO High TCK JTAG
VID[3:0] High Asynch Implementation
Table 8.4 Input/Output Signals (Single Driver)
Name Active Level Clock Si gnal Group Qualified
A[35:3]# Low BCLK System Bus ADS#, ADS #+1
ADS# Low BCLK System Bus Always
AP[1:0]# Low B CLK Syst em Bus ADS#, A DS#+1
BREQ0# Low BCLK System Bus Always
BP[3:2]# Low B CLK Syst em Bus Always
BPM[1:0]# Low BCLK System Bus Always
D[63:0] # Low B CLK Syst em Bus DRDY#
DBSY# Low BCLK System Bus Always
DEP[7:0]# Low BCLK System Bus DRDY#
DRDY# Low BCLK System B us Always
LOCK# Low BCLK System Bus Always
REQ[4:0]# Low BCLK System Bus ADS#, ADS #+1
RP# Low BCLK System Bus ADS#, ADS#+1
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Table 8.5. Input/Output Signals (Multiple Drivers)
Name Active Level Clock Si gnal Group Qualified
AERR# Low B CLK System B us ADS #+3
BERR# Low B CLK System B us Always
BINIT# Low BCLK System Bus Always
BNR# Low BCLK System Bus Always
HIT# Low BCLK Syst em Bus Always
HITM# Low B CLK Syst em Bus Always
PICD[1:0] High PICCLK APIC Always
SMBCLK High — SMBus Always
SMBDATA High SMBCLK SMBus Always
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