1
Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-tech.com
DUAL IN-LINE PACKAGES
CRYSTAL CLOCK OSCILLATORS
-5.2 to -4.5Vdc & 1.8 to 15Vdc - 0.01Hz to 200MHz
Dual In-line Packages (Revision D, June 2010 ) (ECO# 9855)
Q-TECH
CORPORATION
Description
Q-Tech’s Dual In-line (DIP) crystal oscillators
consist of a source clock square wave generator, logic
output buffers and/or logic divider stages, and a
round AT high-precision quartz crystal built in a metal
through-hole package in DIP-8 or DIP-14
configurations.
Features
• Made in the USA
• ECCN: 3A001.b.10
• DFARS 252-225-7014 Compliant:
Electronic Component Exemption
• USML Registration # M17677
• Wide frequency range from 0.01Hz to 200MHz
• Available as QPL MIL-PRF-55310/8, /11, /14, /15,
/16, /17, /18, /25, and /26
• Wide operating temperature range
• Choice of output logic options
• Supply voltages from 1.8Vdc to 15Vdc
• Lower or higher supply voltages available
• All metal hermetically sealed package
• Tight or custom symmetry available
• Fast rise and fall times
• Fast start-up time
• Capacitive load drive capability (Z output)
• Multiple outputs available
• Fundamental and third overtone designs
• High operating temperature up to +225ºC
• Custom design available tailors to meet customer’s
needs
• Q-Tech does not use pure lead or pure tin in its
products
• RoHS compliant
Applications
• Designed to meet today’s requirements for all
voltage applications
• Wide military clock applications
• Smart munitions
• Navigation
• Industrial controls
• Microcontroller driver
• Down-hole applications up to +225ºC
Ordering Information
Output frequency
Screened to
MIL-PRF-55310,level B
(Left blank if no screening)
1 = ± 100ppm at 0ºC to +70ºC
3(***) = ± 5ppm at 0ºC to +50ºC
4 = ± 50ppm at 0ºC to +70ºC
5 = ± 25ppm at -20ºC to +70ºC
6 = ± 50ppm at -55ºC to +105ºC
9 = ± 50ppm at -55ºC to +125ºC
10 = ± 100ppm at -55ºC to +125ºC
11 = ± 50ppm at -40ºC to +85ºC
12 = ± 100ppm at -40ºC to +85ºC
Tristate Option D
(Left blank if no Tristate)
For Non-Standard requirements, contact Q-Tech Corporation at Sales@Q-Tech.com
C = CMOS +5V to +15V (**)
AC = ACMOS +5V
HC = HCMOS +5V
T = TTL +5V
L = LVHCMOS +3.3V
N = LVHCMOS +2.5V
R = LVHCMOS +1.8V
E = 10K ECL -5.2V
EH = 10KH ECL -5.2V
EF = 100K/300K ECL -4.5V
PE = PECL +5V
LP = PECL +3.3V
Z = Z output
Specifications subject to change without prior notice.
All DIP packages are available in surface mount form.
Packaging Options
Other Options Available For An Additional Charge
• Standard packaging in black foam
• Optional anti-static plastic tube
• Lead forming available on all packages. Please contact for details.
• P. I. N. D. test (MIL-STD 883, Method 2020)
• Lead trimming
Frequency stability vs. temperature codes may not be available in all frequencies.
Q-Tech will assign a custom part number for custom specifications and all high
temperature applications with typical frequency stability at ± 250ppm up to +200ºC.
QT6HCD9M-20.000MHz
QT 6 HC D9M-20.000MHz
Sample part number
T = Standard
S = Solder Dip (*)
(**) Please specify supply voltage when ordering CMOS
(*** ) Requires an external capacitor
(*) Hot Solder Dip Sn60 per MIL-PRF 55310 is optional for an additional cost
Model #
(See page 3)
2
Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-tech.com
DUAL IN-LINE PACKAGES
CRYSTAL CLOCK OSCILLATORS
-5.2 to -4.5Vdc & 1.8 to 15Vdc - 0.01Hz to 200MHz
Dual In-line Packages (Revision D, June 2010 ) (ECO# 9855)
Electrical Characteristics
DIP 14: QT6, QT18, QT41, QT42, QT47
DIP 8: QT50, QT51, QT55
Parameters C AC HC T L (*) ECL / PECL (**)
Output freq. range (Fo) DIP 14 0.01Hz — 15MHz 0.01Hz — 160MHz 0.01Hz — 160MHz 0.01Hz — 160MHz 0.01Hz — 160MHz 1MHz — 200MHz
DIP 8 245Hz — 15MHz 0.01Hz — 85MHz 0.01Hz — 85MHz 10Hz — 85MHz 0.01Hz — 100MHz 1MHz — 110MHz
Supply voltage (Vdd) 5V ~ 15Vdc ± 10% 5.0Vdc ± 10% 3.3Vdc ± 10% -5.2Vdc ± 5% (10K / 10KHECL)
5Vdc ± 5% (PECL)
3.3Vdc ± 5% (LVPECL)
Maximum Applied Voltage (Vdd max.) -0.5 to +18Vdc -0.5 to +7.0Vdc -0.5 to +5.0Vdc
0 to -8.0Vdc (10K / 10KHECL)
0 to +8.0Vdc (PECL)
0 to +5.0Vdc (LVPECL)
Freq. stability (∆F/∆T) See Option codes
Operating temp. (Topr) See Option codes
Storage temp. (Tsto) -62ºC to + 125ºC
Operating supply current
(Idd) (No Load)
F and Vdd dependent
3 mA max. at 5V up to 5MHz
25 mA max. at 15V up to 15MHz
20 mA max. - 0.01Hz ~ < 16MHz
25 mA max. - 16MHz ~ < 40MHz
35 mA max. - 40MHz ~ < 60MHz
45 mA max. - 60MHz ~ < 85MHz
55 mA max. - 85MHz ~ < 110MHz
65 mA max. - 110MHz ~ < 125MHz
75 mA max. - 125MHz ~ 160MHz
3 mA max. - 0.01Hz ~ < 500kHz
6 mA max. - 500kHz ~ < 16MHz
10 mA max. - 16MHz ~ < 32MHz
20 mA max. - 32MHz ~ < 60MHz
30 mA max. - 60MHz ~ < 100MHz
40 mA max. - 100MHz ~ < 130MHz
50 mA max. - 130MHz ~ 160MHz
45 mA max. - 1MHz ~ < 125MHz
75 mA max. - 125MHz ~ 200MHz
Symmetry
(50% of ouput waveform or 1.4Vdc for
TTL)
45/55% max. Fo < 4MHz
40/60% max. Fo ≥ 4MHz
45/55% max. Fo < 12MHz
40/60% max. Fo ≥ 12MHz
45/55% max. Fo < 12MHz
40/60% max. Fo ≥ 12MHz
Rise and Fall times (Tr/Tf)
(with typical load)
30ns max.
(Measured from 10% to 90%)
15ns max. Fo < 15kHz
6ns max. Fo 15kHz ~ 39.999MHz
3ns max. Fo 40MHz ~ 160MHz
(Measured from 10% to 90% CMOS or from 0.8V to 2.0V TTL)
3.5ns max. Fo < 125MHz
3ns max. Fo 125MHz ~ 200MHz
(Measured from 20% to 80%)
Output Load 15pF // 10kΩ 10TTL Fo < 20MHz
6TTL Fo ≥ 20MHz
15pF // 10kΩ 50Ω to -2V (10K / 10KH)
50Ω to Vcc -2V (P & LP)
Start-up time (Tstup) 10ms max.
Output voltage (Voh/Vol)
0.9 x Vdd min.; 0.1 x Vdd max. 2.4V min.; 0.4V max. 0.9 x Vdd min.; 0.1 x Vdd max. -1.15V min; -1.54V max. (E)
4V min.; 3.37V max. (PE)
2.27V min.; 1.68V max. (LP)
Output Current (Ioh/Iol) ± 1mA typ. at 5V
± 6.8mA typ. at 15V
± 24mA ±8 mA -1.6mA / TTL
+40μA / TTL
± 4mA . -50mA
Enable/Disable
Tristate function Pin 1 Call for details VIH ≥ 2.2V Oscillation;
VIL ≤ 0.8V High Impedance
VIH ≥ 0.7 x Vdd Oscillation;
VIL ≤ 0.3 x Vdd High Impedance Call for details
Jitter RMS 1σ (at 25ºC) 8ps typ. - < 40MHz
5ps typ. - ≥ 40MHz
15ps typ. - < 40MHz
8ps typ. - ≥ 40MHz
Integrated phase jitter
12kHz - 20MHz 1ps typ.
Aging (at 70ºC) ± 5ppm max. first year / ± 2ppm typ. per year thereafter
(*) Available in 2.5Vdc (N) or 1.8Vdc (R)
(**) Please contact Q-Tech for details on 100KECL logic (EF)
Z Output logic can drive up to 200 pF load with typical 6ns rise & fall times (tr, tf)
Q-TECH
CORPORATION
3
Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-tech.com
DUAL IN-LINE PACKAGES
CRYSTAL CLOCK OSCILLATORS
-5.2 to -4.5Vdc & 1.8 to 15Vdc - 0.01Hz to 200MHz
Dual In-line Packages (Revision D, June 2010 ) (ECO# 9855)
Q-TECH
CORPORATION
Package Configuration Versus Pin Connections
QT # Conf Vcc GND Case Output
(*)
E/D
or
N/C
Ext.
Cap
Equivalent
MIL-PRF-55310
Configuration
QT4 A 4 7 7 5 1 10 & 11 /14 = QT4T
QT6 A 14 7 7 8 1 10 & 11
/16 = QT6T
/17 = QT6T
/18 = QT6C
/26A = QT6HC
**
QT10 A 14 8 2 1 N/A 10 & 11
/08 = QT10T
/11 = QT10C
/15 = QT10C
QT12 A 14 7 7 4 1 10 & 11 N/A
QT18 B 14 7 7 8 1 10 & 11 N/A
QT41 C 14 7 7 8 1 N/A /26B = QT41HC
QT42 D 14 7 7 8 1 N/A N/A
QT47 E 14 7 7 8 1 N/A N/A
QT50 F 8 4 4 5 1 N/A N/A
QT51 G 8 4 4 5 1 N/A N/A
QT55 H 8 4 4 5 1 N/A N/A
1 4
58
Q-TECH
P/N
FREQ.
D/C S/N
.200
(5.08)
.250
(6.35)
(.508)
.020
(7.62)
.300
.505
(12.83)
(.457)
.018
MAX.
MIN.
SQ. MAX.
SQ.
ø .060
(ø 1.52)
F
QT50
.011
.024
(7.366)
FREQ.
D/C S/N
.300
.505
(7.62)
.200
85
41
P/N
Q-TECH
(5.080) .290
.080 ± .010
(2.032±.254)
.020
(.508)(.279)
(12.83)
.300
SQ. MAX.
SQ.
(.609)
(7.62)
MAX.
MAX.
G
QT51
14
58
Q-TECH
P/N
FREQ.
D/C S/N
.200
(5.08)
.250
(6.35)
(7.62)
.300
.505
(12.83)
(.457)
.018
MAX.
MIN.
SQ. MAX.
SQ.
H
QT55
17
814
Q-TECH
P/N
FREQ.
D/C S/N
(22.35)
(15.24)
.880
.600
.300
(7.62)
(2.54)
.100
.505
(12.83)
MAX.
(.457)
.018
MIN.
(5.08)
.200
.200
(5.08)
MAX.
MAX.
A
QT6
14 8
71
FREQ.
P/N
Q-TECH
.800
(20.32)
(7.62)
.300
.100
(2.54)
.600
(15.24)
(12.83)
.505
.018
(.457)
.200
(5.08) MIN.
MAX.
(5.08)
.200
MAX.
D/C S/N
MAX.
B
QT18
14 8
71
FREQ.
D/C S/N
P/N
Q-TECH
.600
(15.24)
(7.62)
.300
.200
(5.08) MAX.
MIN.
(5.08)
.200
(.457)
.018
MAX.
(20.32)
.800
.505
(12.83)
MAX.
C
QT41
D
QT42
.600
.011
.200
MAX.
.024
P/N
FREQ.
D/C S/N
.800
.505
(7.62)
Q-TECH
(5.08)
MAX.
(15.24)
MAX
.290
(7.36)
(.279)
(12.83)
MAX.
.300
(20.32)
MAX.
(.609)
14
58
.080 ± .010
(2.032±.254)
.020
(.508)
E
QT47
Dimensions are in inches (mm)
(*) ECL / PECL complimentary output available on pin 9 (For QT6
and QT18 only) with a Q-Tech custom part number
(**) Gated Output, gate control pin 9
DIP 14
DIP 8
Package Information
• Package material (header and leads): Kovar
• Lead finish: Gold Plated – 50µ ~ 80µ inches
Nickel Underplate – 100µ ~ 250µ inches
• Package to lid attachment: Resistance weld
• Cover (DIP-14): Pure Nickel Grade A (DIP-8): Stainless Steel
• Weight (DIP-14): 3.4g typ.,14.2g max. (DIP-8): 2.0g typ., 14.2g max.
4
Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-tech.com
DUAL IN-LINE PACKAGES
CRYSTAL CLOCK OSCILLATORS
-5.2 to -4.5Vdc & 1.8 to 15Vdc - 0.01Hz to 200MHz
Dual In-line Packages (Revision D, June 2010 ) (ECO# 9855)
Q-TECH
CORPORATION
Vdd
GND
0.1xVdd
0.9xVdd
VOH
VOL
TrTf
TH
T
0.5xVdd
SYMMETRY = x 100%
TH
T
Ts
Start-up box
Oscilloscope
DUT
Variable Ramp
54616B Agilent
TYPICAL SET-UP FOR START-UP TIME
14
7
8
10 11
QT6T3
+5VDC
GND
OUTPUT
0.01uF
12pF(*)
10k
D1
D2
D3
D4
Cext
D1-D4: 1N4148 or equivalent
TYPICAL TEST CIRCUIT FOR QT6T3 (6TTL)
430
(*) CL includes scope probe capacitance
Output Waveform (Typical) Startup Time
Frequency vs. Temperature Curve
Test Circuit
-
-
Output
Ground
Vdd Out
GND
0.1µF
15pF
E/D
Tristate Function
Power
supply 10k
mA
Vdc
+
+
+
(*)
or
0.01µF
(*) CL includes probe and jig capacitance
Typical test circuit for CMOS logic
POWER
SUPPLY
+
-
mA
0.1µF
Vdc
-
Vdd OUT
OUT
GND
Typical test circuit for TTL logic.
0.01µF Rs
(*) CL inclides the loading effect of the oscilloscope probe.
E/D
CL
+
+
-
RL
LOAD
6 TTL
10 TTL
CL(*)
12pF
20pF
RL
430Ω
270Ω
RS
10kΩ
6kΩ
or
Vdd
POWER
SUPPLY
+
-
mA
Vdc
+
-
GND OUT
OUT
Vcc
Typical test circuit for ECL logic.
0.1µF
or
0.01µF
50Ω
-2Vdc
-4.5V
or
-5.2V
FREQUENCY VERSUS TEMPERATURE QT6L9M-64.5MHz
-40
-30
-20
-10
0
10
20
30
40
-55 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125
Temperature (°C)
1_5 2_5 3_5
Frequency Stability (PPM)
The Tristate function on pin 1 has a built-in pull-up resistor typical 50kΩ, so it
can be left floating or tied to Vdd without deteriorating the electrical performance.
5
Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-tech.com
DUAL IN-LINE PACKAGES
CRYSTAL CLOCK OSCILLATORS
-5.2 to -4.5Vdc & 1.8 to 15Vdc - 0.01Hz to 200MHz
Dual In-line Packages (Revision D, June 2010 ) (ECO# 9855)
Q-TECH
CORPORATION
Environmental Specifications
Q-Tech Standard Screening/QCI (MIL-PRF55310) is available for all of our DIP packages. Q-Tech can also customize screening and
test procedures to meet your specific requirements. The DIP packages are designed and processed to exceed the following test
conditions:
Environmental Test Test Conditions
Temperature cycling MIL-STD-883, Method 1010, Cond. B
Constant acceleration MIL-STD-883, Method 2001, Cond. A, Y1
Seal: Fine and Gross Leak MIL-STD-883, Method 1014, Cond. A and C
Burn-in 160 hours, 125°C with load
Aging 30 days, 70°C, ± 0.7ppm max
Vibration sinusoidal MIL-STD-202, Method 204, Cond. D
Shock, non operating MIL-STD-202, Method 213, Cond. I
Thermal shock, non operating MIL-STD-202, Method 107, Cond. B
Ambient pressure, non operating MIL-STD-202, 105, Cond. C, 5 minutes dwell time minimum
Resistance to solder heat MIL-STD-202, Method 210, Cond. C
Moisture resistance MIL-STD-202, Method 106
Terminal strength MIL-STD-202, Method 211, Cond. C
Resistance to solvents MIL-STD-202, Method 215
Solderability MIL-STD-202, Method 208
ESD Classification MIL-STD-883, Method 3015, Class 1HBM 0 to 1,999V
Moisture Sensitivity Level J-STD-020, MSL=1
Please contact Q-Tech for higher shock requirements
45º 45º
Hybrid Case
Substrate
Die
D/A epoxy
D/A epoxy
Heat
Die
R1
D/A epoxy Substrate D/A epoxy Hybrid Case
R2 R3 R4 R5
Thermal Characteristics
JA JC CA
Die
T
T
TC
A
J
CA
JC
(Figure 1)
(Figure 2)
The heat transfer model in a hybrid package is described in
figure 1 (Based on single ASIC design) .
Heat spreading occurs when heat flows into a material layer of
increased cross-sectional area. It is adequate to assume that
spreading occurs at a 45° angle.
The total thermal resistance is calculated by summing the
thermal resistances of each material in the thermal path
between the device and hybrid case.
RT = R1 + R2 + R3 + R4 + R5
The total thermal resistance RT (see figure 2) between the heat
source (die) to the hybrid case is the Theta Junction to Case
(Theta JC) in°C/W.
• Theta junction to case (Theta JC) for this product is 24°C/W.
• Theta case to ambient (Theta CA) for this part is 105°C/W.
• Theta Junction to ambient (Theta JA) is 130°C/W.
Maximum power dissipation PD for this package at 25°C is:
• PD(max) = (TJ (max) – TA)/Theta JA
• With TJ = 175°C (Maximum junction temperature of die)
• PD(max) = (175 – 25)/130 = 1.15W
6
Q-TECH Corporation - 10150 W. Jefferson Boulevard, Culver City 90232 - Tel: 310-836-7900 - Fax: 310-836-2157 - www.q-tech.com
DUAL IN-LINE PACKAGES
CRYSTAL CLOCK OSCILLATORS
-5.2 to -4.5Vdc & 1.8 to 15Vdc - 0.01Hz to 200MHz
Dual In-line Packages (Revision D, June 2010 ) (ECO# 9855)
Q-TECH
CORPORATION
Phase noise is measured in the frequency domain, and is expressed as a ratio of signal power to noise power measured in a 1Hz
bandwidth at an offset frequency from the carrier, e.g. 10Hz, 100Hz, 1kHz, 10kHz, 100kHz, etc. Phase noise measurement is made
with an Agilent E5052A Signal Source Analyzer (SSA) with built-in outstanding low-noise DC power supply source. The DC source
is floated from the ground and isolated from external noise to ensure accuracy and repeatability.
In order to determine the total noise power over a certain frequency range (bandwidth), the time domain must be analyzed in the
frequency domain, and then reconstructed in the time domain into an rms value with the unwanted frequencies excluded. This may be
done by converting L(f) back to Sφ(f) over the bandwidth of interest, integrating and performing some calculations.
The value of RMS jitter over the bandwidth of interest, e.g. 10kHz to 20MHz, 10Hz to 20MHz, represents 1 standard deviation of
phase jitter contributed by the noise in that defined bandwidth.
Figure below shows a typical Phase Noise/Phase jitter of a QT6AC8, 5.0Vdc, 24MHz and a QT50T, 5.0Vdc, 60 MHz clock at offset
frequencies 10Hz to 5MHz, and phase jitter integrated over the bandwidth of 12kHz to 1MHz.
Phase Noise and Phase Jitter Integration
Period Jitter
As data rates increase, effects of jitter become critical with
its budgets tighter. Jitter is the deviation of a timing event
of a signal from its ideal position. Jitter is complex and is
composed of both random and deterministic jitter
components. Random jitter (RJ) is theoretically un-
bounded and Gaussian in distribution. Deterministic jitter
(DJ) is bounded and does not follow any predictable
distribution. DJ is also referred to as systematic jitter. A
technique to measure period jitter (RMS) one standard
deviation (1σ) and peak-to-peak jitter in time domain is to
use a high sampling rate (>8G samples/s) digitizing
oscilloscope. Figure shows an example of peak-to-peak
jitter and RMS jitter (1σ) of a QT6AC8-24MHz, at 5.0Vdc.
RMS jitter (1σ): 5.86ps Peak-to-peak jitter: 52.4ps
Symbol
Definition
∫L(f) Integrated single side band phase noise (dBc)
Sφ (f)=(180/Π)x√2 ∫L(f)df Spectral density of phase modulation, also known as RMS phase error (in degrees)
RMS jitter = Sφ (f)/(fosc.360°) Jitter(in seconds) due to phase noise. Note Sφ (f) in degrees.
QT6AC8, 5.0Vdc, 24MHz QT50T, 5.0Vdc, 60 MHz