1/15
¡ Semiconductor MSM514212
¡ Semiconductor
MSM514212
5,048-Word ¥ 8-Bit Line Memory
DESCRIPTION
The OKI MSM514212 is a high-performance serial-line memory. It is designed for use in NTSC,
PAL or SECAM Video line buffer applications such as digital comb filters in TVs/VTRs, IDTV
(Improved Definition Television), time based correction, or other applications that use serial
data including facsimiles, digital copy machines, etc. High-reliability and low-power consumption
are accomplished by using CMOS dynamic memory cells.
It has separate 8-bit-wide serial input and serial output ports that use independent data clocks
to support asynchronous read and write operations. Different clock rates are also supported that
allow alternate data rates between input and output data streams.
A wide range of variable delay bits (40 bits to 5,048 bits) are supported offering greater design
flexibility. Internal logic keeps all asynchronous accesses from being delayed by arbitrating the
data storage, and data retrieval requirements to provide maximum performance at all times.
All input and output signals are TTL compatible, and the MSM514212 is packaged in a standard
400 mil 28-pin plastic ZIP.
FEATURES
• Single power supply: 5 V ±10%
• Capacity: 5,048 words ¥ 8 bits
• Access: I/O asynchronous
• Access time: 28 ns (min.)
• Cycle time : 28 ns (min.)
• Delay bits: Variable (40 to 5,048)
• Low current consumption: 30 mA (max.)
• Operating voltage range: 4.5 V to 5.5 V
• Operating temperature range : 0°C to 70°C
• Package :
28-pin 400 mil plastic ZIP (ZIP28-P-400-1.27) (Product : MSM514212-xxZS)
xx indicates speed rank.
PRODUCT FAMILY
Cycle Time (Min.) Access Time (Min.)
Power Dissipation (Max.)
28 ns 28 ns 230 mA
34 ns 34 ns 200 mA
50 ns 40 ns 170 mA
Family
MSM514212-28
MSM514212-34
MSM514212-50
E2L0028-17-Y1
This version: Jan. 1998
Previous version: Dec. 1996
2/15
¡ Semiconductor MSM514212
PIN CONFIGURATION (TOP VIEW)
VSS
DIN3
DIN1
VCC
DOUT1
DOUT3
RR
RCK
DOUT4
DOUT6
VCC
WR
DIN6
DIN4
VSS
DIN2
DIN0
DOUT0
DOUT2
VSS
RE
VSS
DOUT5
DOUT7
WE
DIN7
DIN5
WCK
28-Pin Plastic ZIP
1
3
5
7
9
11
13
15
17
19
21
23
25
27
2
4
6
8
10
12
14
16
18
20
22
24
26
28
WCK
WR
WE
D
IN
0 - 7
RCK
RR
RE
D
OUT
0 - 7
V
CC
V
SS
Pin Name
Write Clock
Write Address Reset
Write Enable
Data Input
Read Clock
Read Address Reset
Read Enable
Data Output
Power Supply (5 V)
Ground (0 V)
Function
Note: The same power supply voltage must be provided to every VCC pin, and the same GND
voltage level must be provided to every VSS pin.
3/15
¡ Semiconductor MSM514212
BLOCK DIAGRAM
Read Timing
Controller
RCK
Data-out
Buffer
32-Word
Data Register
5032
Memory
Array
32-Word
Data Register
16-Word
Sub-Register
Data-in
Buffer
16-Word
Sub-Register
Read Reset
Controller
Read/Write
Select Controller
Write Reset
Controller
Write Timing
Controller
Data-out
Buffer
32-Word
Data Register
5032
Memory
Array
32-Word
Data Register
16-Word
Sub-Register
Data-in
Buffer
16-Word
Sub-Register
Data-out
Buffer
32-Word
Data Register
5032
Memory
Array
32-Word
Data Register
16-Word
Sub-Register
Data-in
Buffer
16-Word
Sub-Register
Data-out
Buffer
32-Word
Data Register
5032
Memory
Array
32-Word
Data Register
16-Word
Sub-Register
Data-in
Buffer
16-Word
Sub-Register
Data-out
Buffer
32-Word
Data Register
5032
Memory
Array
32-Word
Data Register
16-Word
Sub-Register
Data-in
Buffer
16-Word
Sub-Register
Data-out
Buffer
32-Word
Data Register
5032
Memory
Array
32-Word
Data Register
16-Word
Sub-Register
Data-in
Buffer
16-Word
Sub-Register
Data-out
Buffer
32-Word
Data Register
5032
Memory
Array
32-Word
Data Register
16-Word
Sub-Register
Data-in
Buffer
16-Word
Sub-Register
Data-out
Buffer
32-Word
Data Register
5032
Memory
Array
32-Word
Data Register
16-Word
Sub-Register
Data-in
Buffer
16-Word
Sub-Register
X
Decoder
Read/Write
Controller
RR
WR
WCK
D
IN
0
D
OUT
0
D
IN
1
D
OUT
1
D
IN
2
D
OUT
2
D
IN
3
D
OUT
3
D
IN
4
D
OUT
4
D
IN
5
D
OUT
5
D
IN
6
D
OUT
6
D
IN
7
D
OUT
7
V
BB
Generator
WE
RE
4/15
¡ Semiconductor MSM514212
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Pin Voltage Relative to Vss
Power Supply Voltage
Circuit Output Current
Operating Temperature
Storage Temperature
Symbol Condition Rating Unit
V
V
I
T
T
T
CC
O
opr
stg
at Ta = 25°C, Vss
at Ta = 25°C, Vcc
Ta = 25°C
—
—
–1.0 to 7.0
–1.0 to 7.0
20
0 to 70
–55 to 150
V
V
mA
°C
°C
Recommended Operating Conditions
Parameter
Power Supply Voltage
Input High Voltage
Input Low Voltage
Temperature Around
Symbol Condition Unit
V
V
V
Ta
CC
IH
IL
—
—
—
—
V
V
V
°C
Min. Typ. Max.
5.5
5.5
0.8
70
5.0
—
—
—
4.5
2.4
–1.5
0
DC Characteristics (On the Recommended Operating Conditions)
Parameter
Power Supply Current
Input Leakage Current
Output High Level Voltage
Output Low Level Voltage
Symbol Condition Unit
I
I
V
V
CC
I
OH
OL
—
V
I
=
0 to Vcc, Other pins are 0 V
V
O
= 0 to 5.5 V, D
OUT
high
impedance
I
OH
= –1 mA
I
OL
= 2 mA
mA
µA
V
V
Min. Typ. Max.
30
10
—
0.4
—
—
—
—
—
–10
2.4
—
Output Leakage Current
O
I –10 — 10 µA
Capacitance
(VCC = 5 V ±10%, Ta = 25°C, f = 1 MHz)
Parameter
Input Capacitance
Output Capacitance
Symbol Condition Unit
C
C
I
O
—
—pF
pF
Min. Typ. Max.
5
7
—
—
—
—
5/15
¡ Semiconductor MSM514212
AC Characteristics (On the Recommended Operating Conditions)
Parameter
Write Clock Cycle Time
Write Clock Pulse Width
Write Clock Precharge Time
Read Clock Cycle Time
Read Clock Pulse Width
Read Clock Precharge Time
Access Time
Cycle Access Time Right After Reset
Output Hold Time
Output Hold Time Right After Reset
Output Low Impedance Period
Output High Impedance Period
Input Data Setup Time
Input Data Hold Time
WR/RR Setup Time from WCK/RCK
WR/RR Hold Time from WCK/RCK
WR/RR Nonselective Time 1 from
WCK/RCK
WR/RR Nonselective Time 2 from
WCK/RCK
WE Setup Time from WCK
WE Hold Time from WCK
WE Nonselective Time 1 from WCK
WE Nonselective Time 2 from WCK
RE Setup Time from RCK
RE Hold Time from RCK
RE Nonselective Time 1 from RCK
RE Nonselective Time 2 from RCK
WE High Level Period
RE High Level Period
WR Low Level Period (Write Reset
Period)
WR Low Level Period (Read Reset
Period)
Transition Time
Symbol Unit
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WCK
WCW
WCP
RCK
RCW
RCP
AC
ACR
OH
OHR
LZ
HZ
DS
DH
RS
RH
WES
WEH
WEN1
WEN2
RES
REH
REN1
REN2
WEW
REW
T
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
28
11
11
28
11
11
—
—
5
5
5
5
11
5
11
5
11
5
5
11
11
5
5
11
0
0
3
-28
Min. Max. -34
Min. Max. -50
Min. Max.
5
11
0
0
1980
—
—
1980
—
—
28
28
—
—
28
28
—
—
—
—
—
—
—
—
—
—
—
—
—
—
35
—
—
—
—
34
14
14
34
14
14
—
—
5
5
5
5
14
5
14
5
14
5
5
14
14
5
5
14
0
0
3
5
14
0
0
1980
—
—
1980
—
—
34
34
—
—
34
34
—
—
—
—
—
—
—
—
—
—
—
—
—
—
35
—
—
—
—
50
20
20
50
20
20
—
—
5
5
5
5
15
5
15
5
15
5
5
15
15
5
5
15
0
0
3
5
15
0
0
1980
—
—
1980
—
—
40
40
—
—
40
40
—
—
—
—
—
—
—
—
—
—
—
—
—
—
35
—
—
—
—
ns
ns
ns
ns
t
t
RN1
RN2
t
t
RSTW
RSTR
6/15
¡ Semiconductor MSM514212
Notes: 1. The input voltage reference levels stipulated in the timing specification are VIH =
3.0 V and VIL = 0 V. The tT is the transition time between VIH = 3.0 V and VIL = 0
V.
2. Rise and fall time tT of all the cycles is specified as 5 ns.
3. During asynchronous execution of write and read operation, the difference between
the write address and read address must be greater than 40.
4. Since the MSM514212 uses a dynamic memory cell, it can read the data of the
written address within 10 ms after the write cycle at that address is completed.
5. The load condition for measurement is based on 1 TTL + 30 pF.
6. All the potential to the power supply/grounding terminals needs to be supplied.
7/15
¡ Semiconductor MSM514212
SIGNAL DESCRIPTIONS
Data Inputs (DIN0 - DIN7)
Data on these inputs is shifted in on the rising edge of WCK while WE is held at a low level. The
data setup and hold times tDS and tDH are referenced to the rising edge of WCK.
Data Outputs (DOUT0 - DOUT7)
Data is shifted out on these outputs during the rising edge of RCK while RE is held at a low level.
The data becomes valid after the access time interval tAC which begins at the rising edge of RCK.
Write Address Pointer Reset (WR)
If WR is brought to a low level, the next rising edge of WCK resets the write address pointer to
the first address location. The write address pointer is automatically reset when the last address
location (5048) is clocked. The WR setup, and hold times tRS and tRH are referenced to the rising
edge of WCK. Each write operation, which begins after WR, must contain at least 18 active write
cycles, i.e. WCK cycles while WE is high.
Read Address Pointer Reset (RR)
If RR is brought to a low level, the next rising edge of RCK resets the read address pointer to the
first address location. The read address pointer is automatically reset when the last address
location (5048) is clocked. The RR setup, and hold times tRS and tRH are referenced to the rising
edge of WCK. Each read operation, which begins after RR, must contain at least 18 active read
cycles, i.e. RCK cycles while RE is high.
Write Enable (WE)
This pin is used as a gating function for the WCK input. If WE is held low, normal write cycles
can occur. If WE is brought to a high level before the next rising edge of WCK, all subsequent
write cycles will be inhibited, and the write address pointer remains unchanged. The WE setup
and hold times tWES and tWEH are referenced to the rising edge of WCK.
Read Enable (RE)
This pin is used as a gating function for the RCK input. If RE is brought to a high level before the
next rising edge of RCK, all subsequent read cycles are inhibited, and the read address pointer
remains unchanged. The data outputs will tri-state after the output buffer turn off delay time tHZ,
which begins at the rising edge of RCK. After the disabled cycles are completed, and the RE signal
is brought back to a low level, the data output buffers are re-enabled by the next rising edge of
RCK. The RE setup, and hold times tRES and tREH are referenced to the rising edge of RCK.
Write Clock (WCK)
The rising edge of the WCK input latches the data into the internal registers, and also increments
the write address pointer when WE is held low.
Read Clock (RCK)
The rising edge of the RCK input shifts out the data from the internal registers and increments
the read address pointer when RE is held low.
8/15
¡ Semiconductor MSM514212
OPERATION MODE
Write Cycle
When WE input is enabled (at the "L" level), the write cycle is executed by synchronizing it with
the WCK clock input. Read and write data is processed by the same clock in the write cycle to
carry out the video processing. Data is input after a delay of oneline (5048 bits) is input at the
rising edge of the clock in the write cycle.
In addition, when the length of the delay is controlled by WE, the value of the delay bits is from
40 to 5048. The WR operation must be performed now to write the last data to memory cell.
Read Cycle
When RE input is enabled (at the "L" level), the read cycle is executed by synchronizing it with
the RCK clock input. Data is output at tAC (or tACR). In addition, when the length of the delay
is controlled by RE, the value of the delay bits is from 40 to 5048.
Write Reset Cycle
Read Reset Cycle
When the power supply is on, the address values of the read and write address pointers are at
random. Thus, each pointer must be initialized by the RR signal and the WR signal beforehand.
Data can be input (to address 0) with the first cycle after this reset operation.
Power-up and Initialization
On power-up, the device is designed to begin proper operation after at least 100 ms after VCC has
stabilized to a value within the range of recommended operating conditions. After this 100 ms
stabilization interval, the following initialization sequence must be performed.
Because the read and write address counters are not valid after power-up, a minimum of 18
dummy write operations (WCK cycles) and read operations (RCK cycles) must be performed,
followed by a WR operation and an RR operation, to properly initialize the write and the read
address pointer. Dummy write cycles/WR and dummy read cycles/RR may occur simultaneously.
If these dummy read and write operations start while VCC and/or the substrate voltage has not
stabilized, it is necessary to perform an RR operation plus a minimum of 18 RCK cycles plus
another RR operation, and a WR operation plus a minimum of 18 WCK cycles plus another WR
operation to properly initialize read and write address pointers.
9/15
¡ Semiconductor MSM514212
RCK
RE
D
OUT
n cycle n+1 cycle n+2 cycle disable cycle n+3 cycle
t
RCK
t
RCP
t
RCW
t
REN1
t
RES
t
REH
t
REN2
(n) (n + 1) (n + 2) (n + 3)
RR = "H" Level
t
REW
,
t
LZ
t
AC
t
OH
t
HZ
t
LZ
HIGH-Z
t
AC
t
T
– V
IH
– V
IL
– V
IH
– V
IL
– V
IH
– V
IL
WCK
WE
D
IN
,
n cycle n+1 cycle n+2 cycle disable cycle n+3 cycle
t
WCK
t
WCP
t
WCW
t
WEN1
t
WES
t
WEH
t
WEN2
(n) (n + 1) (n + 2) (n + 3)
t
DS
t
DH
t
DS
t
DH
WR = "H" Level
t
WEW
t
T
– V
IH
– V
IL
– V
IH
– V
IL
– V
IH
– V
IL
TIMING WAVEFORM
Write Cycle
Read Cycle
10/15
¡ Semiconductor MSM514212
WCK
WR
DIN
n cycle reset cycle 0 cycle 1 cycle
(n) (0)
WE = "L" Level
tRS tRSTR tRH
(1)(n – 1)
tRN1 tRN2
tDS tDH tDS tDH
– VIH
– VIL
– VIH
– VIL
– VIH
– VIL
tRN1
RCK
RR
DOUT
MN
n cycle reset cycle 0 cycle 1 cycle
(n) (0) (0)
RE = "L" Level
KL
O
tRS tRSTW tRH
P
JK
(1)(n – 1)
tRN1
tAC tACR tACR tAC
tRN2
tOHR tOHR tOH tOH
– VIH
– VIL
– VIH
– VIL
– VIH
– VIL
Write Reset Cycle
Read Reset Cycle
Note: In the write reset and read reset cycles, the reset cycle (for the duration of tRSTW, tRSTR) is
not necessarily required for the reset operation.
11/15
¡ Semiconductor MSM514212
WCK
RCK
WR
RR
D
IN
0 cycle
t
RCK
(0)
t
DS
t
DH
1 cycle 2 cycle n-1 cycle n cycle (0') n+1 cycle
(1') n+2 cycle
(2') n+3 cycle
(3')
t
WCP
t
RCP
t
WCK
12
t
RH
t
RS
(1) (2)
(n-2) (n-1)
(0') (1') (2') (3')
t
DS
D
OUT
(0) (1) (2) (3)
t
DH
t
OHR
t
ACR
n cycle
t
WCW
t
RCW
– V
IH
– V
IL
– V
IH
– V
IL
– V
IH
– V
IL
– V
OH
– V
OL
n Bit Delay Line Timing (1)
RE, WE = "L" Level
12/15
¡ Semiconductor MSM514212
WCK
RCK
D
IN
"
0 cycle
t
RCK
(0)
t
DS
t
DH
1 cycle 2 cycle n-1 cycle n cycle n+1 cycle n+2 cycle n+3 cycle
t
WCP
t
RCP
t
WCK
(1) (2)
(n-2) (n-1)
(n) (n+1) (n+2) (n+3)
t
DS
D
OUT
(0) (1) (2) (3)
t
DH
t
OHR
t
ACR
n cycle
t
WCW
t
RCW
!
!"
"
– V
IH
– V
IL
– V
IH
– V
IL
– V
IH
– V
IL
– V
OH
– V
OL
WR
t
RH
t
RS
RR
t
RS
t
RH
– V
IH
– V
IL
n Bit Delay Line Timing (2)
RE, WE = "L" Level
13/15
¡ Semiconductor MSM514212
WCK
RCK
DIN
"
0 cycle
tRCK
(0)
tDS tDH
1 cycle 2 cycle n-1 cycle n cycle n+1 cycle n+2 cycle n+3 cycle
tWCP
tRCP
tWCK
(1) (2) (n-2) (n-1) (n) (n+1) (n+2) (n+3)
tDS
DOUT (0) (1) (2) (3)
tDH
tOHR
tACR
n cycle
tWCW
tRCW
!
!"
"
– V
IH
– V
IL
– V
IH
– V
IL
– V
IH
– V
IL
– V
OH
– V
OL
WR
RR
tRH
tRS
RE
tREH tREN2
– V
IH
– V
IL
HIGH-Z
n Bit Delay Line Timing (3)
WE = "L" Level
14/15
¡ Semiconductor MSM514212
1 H Delay Line Timing
WCK
RCK
WR
RR
D
IN
0 cycle
t
RCK
(0)
t
DS
t
DH
1 cycle 2 cycle 5047 cycle 5048 cycle
(0') 5049 cycle
(1') 5050 cycle
(2') 5051 cycle
(3')
t
WCP
t
RCP
t
WCK
1H 2H
t
RH
t
RS
(1) (2)
5046 5047
(0') (1') (2') (3')
t
DS
D
OUT
(0) (1) (2) (3)
t
DH
t
OH
t
AC
5048 cycle
t
WCW
t
RCW
– V
IH
– V
IL
– V
IH
– V
IL
– V
IH
– V
IL
– V
OH
– V
OL
RE, WE = "L" Level
15/15
¡ Semiconductor MSM514212
(Unit : mm)
PACKAGE DIMENSIONS
ZIP28-P-400-1.27
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.85 TYP.
Mirror finish
