HCS08
Microcontrollers
freescale.com
MC9S08QD4
MC9S08QD2
S9S08QD4
S9S08QD2
Data Sheet
MC9S08QD4
Rev. 5
11/2008
8-Bit HCS08 Central Processor Unit (CPU)
• 16 MHz HCS08 CPU (central processor
unit)
• HC08 instruction set with added BGND
instruction
• Background debugging system
• Breakpoint capability to allow single
breakpoint setting during in-circuit
debugging (plus two more breakpoints in
on-chip debug module)
• Support for up to 32 interrupt/reset sources
Memory
• Flash read/program/erase over full
operating voltage and temperature
• Flash size:
— MC9S08QD4/S9S08QD4: 4096 bytes
— MC9S08QD2/S9S08QD2: 2048 bytes
•RAM size
— MC9S08QD4/S9S08QD4: 256 bytes
— MC9S08QD2/S9S08QD2: 128 bytes
Power-Saving Modes
• Wait plus three stops
Clock Source Options
•ICS — Internal clock source module (ICS)
containing a frequency-locked-loop (FLL)
controlled by internal. Precision trimming
of internal reference allows 0.2% resolution
and 2% deviation over temperature and
voltage.
System Protection
• Watchdog computer operating properly
(COP) reset with option to run from
dedicated 32 kHz internal clock source or
bus clock
• Low-voltage detection with reset or
interrupt
• Illegal opcode detection with reset
• Illegal address detection with reset
• Flash block protect
Peripherals
•ADC — 4-channel, 10-bit analog-to-digital
converter with automatic compare
function, asynchronous clock source,
temperature sensor and internal bandgap
reference channel. ADC is hardware
triggerable using the RTI counter.
•TIM1 — 2-channel timer/pulse-width
modulator; each channel can be used for
input capture, output compare, buffered
edge-aligned PWM, or buffered
center-aligned PWM
•TIM2 — 1-channel timer/pulse-width
modulator; each channel can be used for
input capture, output compare, buffered
edge-aligned PWM, or buffered
center-aligned PWM
•KBI — 4-pin keyboard interrupt module
with software selectable polarity on edge or
edge/level modes
Input/Output
• Four General-purpose input/output (I/O)
pins, one input-only pin and one
output-only pin. Outputs 10 mA each, 60
mA maximum for package.
• Software selectable pullups on ports when
used as input
• Software selectable slew rate control and
drive strength on ports when used as output
• Internal pullup on RESET and IRQ pin to
reduce customer system cost
Development Support
• Single-wire background debug interface
Package Options
• 8-pin SOIC package
• 8-pin PDIP (Only for MC9S08QD4 and
MC9S08QD2)
• All package options are RoHS compliant
MC9S08QD4 Series Features
MC9S08QD4 Data Sheet
Covers: MC9S08QD4
MC9S08QD2
S9S08QD4
S9S08QD2
MC9S08QD4
Rev. 5
11/2008
MC9S08QD4 Series MCU Data Sheet, Rev. 5
6Freescale Semiconductor
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will
be the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Revision
Number
Revision
Date Description of Changes
1 15 Sep 06 Initial public release
2 09 Jan 07 Added MC9S08QD2 information; added “M” temperature range (–40 °C to 125 °C); updated
temperature sensor equation in the ADC chapter.
3 19 Nov. 07 Added S9S08QD4 and S9S08QD2 information for automotive applications. Revised "Accessing
(read or write) any flash control register..." to “ Writing any flash control register...” in Section 4.5.5,
“Access Errors.”
4 9 Sep 08 Changed the SPMSC3 in Section 5.6, “Low-Voltage Detect (LVD) System,” and Section 5.6.4,
“Low-Voltage Warning (LVW),” to SPMSC2.
Added VPOR to Ta ble A- 5 .
Updated “How to Reach Us” information.
5 24 Nov 08 Revised dc injection current in Ta bl e A -5.
This product incorporates SuperFlash® technology licensed from SST.
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
© Freescale Semiconductor, Inc., 2006-2008. All rights reserved.
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 7
List of Chapters
Chapter 1 Device Overview ...................................................................... 17
Chapter 2 External Signal Description .................................................... 21
Chapter 3 Modes of Operation................................................................. 27
Chapter 4 Memory Map and Register Definition .................................... 33
Chapter 5 Resets, Interrupts, and General System Control.................. 53
Chapter 6 Parallel Input/Output Control.................................................. 69
Chapter 7 Central Processor Unit (S08CPUV2) ...................................... 75
Chapter 8 Analog-to-Digital Converter (ADC10V1) ................................ 95
Chapter 9 Internal Clock Source (S08ICSV1)........................................ 123
Chapter 10 Keyboard Interrupt (S08KBIV2) ............................................ 137
Chapter 11 Timer/Pulse-Width Modulator (S08TPMV2) ......................... 145
Chapter 12 Development Support ........................................................... 161
Appendix A Electrical Characteristics...................................................... 175
Appendix B Ordering Information and Mechanical Drawings................ 193
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 9
Contents
Section Number Title Page
Chapter 1
Device Overview
1.1 Introduction .....................................................................................................................................17
1.2 Devices in the MC9S08QD4 Series ................................................................................................17
1.2.1 MCU Block Diagram ........................................................................................................19
1.3 System Clock Distribution ..............................................................................................................20
Chapter 2
External Signal Description
2.1 Device Pin Assignment ...................................................................................................................21
2.2 Recommended System Connections ...............................................................................................21
2.2.1 Power ................................................................................................................................22
2.2.2 Oscillator ...........................................................................................................................23
2.2.3 Reset (Input Only) ............................................................................................................23
2.2.4 Background / Mode Select (BKGD/MS) ..........................................................................23
2.2.5 General-Purpose I/O and Peripheral Ports ........................................................................24
Chapter 3
Modes of Operation
3.1 Introduction .....................................................................................................................................27
3.2 Features ...........................................................................................................................................27
3.3 Run Mode ........................................................................................................................................27
3.4 Active Background Mode ...............................................................................................................27
3.5 Wait Mode .......................................................................................................................................28
3.6 Stop Modes ......................................................................................................................................28
3.6.1 Stop2 Mode .......................................................................................................................29
3.6.2 Stop3 Mode .......................................................................................................................30
3.6.3 Active BDM Enabled in Stop Mode .................................................................................30
3.6.4 LVD Enabled in Stop Mode ..............................................................................................31
3.6.5 On-Chip Peripheral Modules in Stop Modes ....................................................................31
Chapter 4
Memory Map and Register Definition
4.1 MC9S08QD4 Series Memory Maps ...............................................................................................33
4.2 Reset and Interrupt Vector Assignments .........................................................................................34
4.3 Register Addresses and Bit Assignments ........................................................................................35
4.4 RAM ................................................................................................................................................38
4.5 Flash ................................................................................................................................................39
4.5.1 Features .............................................................................................................................39
MC9S08QD4 Series MCU Data Sheet, Rev. 5
10 Freescale Semiconductor
4.5.2 Program and Erase Times .................................................................................................39
4.5.3 Program and Erase Command Execution .........................................................................40
4.5.4 Burst Program Execution ..................................................................................................41
4.5.5 Access Errors ....................................................................................................................43
4.5.6 Flash Block Protection ......................................................................................................44
4.5.7 Vector Redirection ............................................................................................................45
4.6 Security ............................................................................................................................................45
4.7 Flash Registers and Control Bits .....................................................................................................46
4.7.1 Flash Clock Divider Register (FCDIV) ............................................................................46
4.7.2 Flash Options Register (FOPT and NVOPT) ....................................................................48
4.7.3 Flash Configuration Register (FCNFG) ...........................................................................49
4.7.4 Flash Protection Register (FPROT and NVPROT) ..........................................................49
4.7.5 Flash Status Register (FSTAT) ..........................................................................................50
4.7.6 Flash Command Register (FCMD) ...................................................................................51
Chapter 5
Resets, Interrupts, and General System Control
5.1 Introduction .....................................................................................................................................53
5.2 Features ...........................................................................................................................................53
5.3 MCU Reset ......................................................................................................................................53
5.4 Computer Operating Properly (COP) Watchdog .............................................................................54
5.5 Interrupts .........................................................................................................................................55
5.5.1 Interrupt Stack Frame .......................................................................................................56
5.5.2 External Interrupt Request (IRQ) Pin ...............................................................................56
5.5.3 Interrupt Vectors, Sources, and Local Masks ...................................................................57
5.6 Low-Voltage Detect (LVD) System ................................................................................................58
5.6.1 Power-On Reset Operation ...............................................................................................59
5.6.2 LVD Reset Operation ........................................................................................................59
5.6.3 LVD Interrupt Operation ...................................................................................................59
5.6.4 Low-Voltage Warning (LVW) ...........................................................................................59
5.7 Real-Time Interrupt (RTI) ...............................................................................................................59
5.8 Reset, Interrupt, and System Control Registers and Control Bits ...................................................60
5.8.1 Interrupt Pin Request Status and Control Register (IRQSC) ............................................60
5.8.2 System Reset Status Register (SRS) .................................................................................61
5.8.3 System Background Debug Force Reset Register (SBDFR) ............................................62
5.8.4 System Options Register 1 (SOPT1) ................................................................................63
5.8.5 System Options Register 2 (SOPT2) ................................................................................64
5.8.6 System Device Identification Register (SDIDH, SDIDL) ................................................64
5.8.7 System Real-Time Interrupt Status and Control Register (SRTISC) ................................65
5.8.8 System Power Management Status and Control 1 Register (SPMSC1) ...........................66
5.8.9 System Power Management Status and Control 2 Register (SPMSC2) ...........................67
Chapter 6
Parallel Input/Output Control
6.1 Port Data and Data Direction ..........................................................................................................69
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 11
6.2 Pin Control — Pullup, Slew Rate and Drive Strength ....................................................................70
6.3 Pin Behavior in Stop Modes ............................................................................................................70
6.4 Parallel I/O Registers ......................................................................................................................71
6.4.1 Port A Registers ................................................................................................................71
6.4.2 Port A Control Registers ...................................................................................................72
Chapter 7
Central Processor Unit (S08CPUV2)
7.1 Introduction .....................................................................................................................................75
7.1.1 Features .............................................................................................................................75
7.2 Programmer’s Model and CPU Registers .......................................................................................76
7.2.1 Accumulator (A) ...............................................................................................................76
7.2.2 Index Register (H:X) ........................................................................................................76
7.2.3 Stack Pointer (SP) .............................................................................................................77
7.2.4 Program Counter (PC) ......................................................................................................77
7.2.5 Condition Code Register (CCR) .......................................................................................77
7.3 Addressing Modes ...........................................................................................................................79
7.3.1 Inherent Addressing Mode (INH) .....................................................................................79
7.3.2 Relative Addressing Mode (REL) ....................................................................................79
7.3.3 Immediate Addressing Mode (IMM) ................................................................................79
7.3.4 Direct Addressing Mode (DIR) ........................................................................................79
7.3.5 Extended Addressing Mode (EXT) ..................................................................................80
7.3.6 Indexed Addressing Mode ................................................................................................80
7.4 Special Operations ...........................................................................................................................81
7.4.1 Reset Sequence .................................................................................................................81
7.4.2 Interrupt Sequence ............................................................................................................81
7.4.3 Wait Mode Operation ........................................................................................................82
7.4.4 Stop Mode Operation ........................................................................................................82
7.4.5 BGND Instruction .............................................................................................................83
7.5 HCS08 Instruction Set Summary ....................................................................................................84
Chapter 8
Analog-to-Digital Converter (ADC10V1)
8.1 Introduction .....................................................................................................................................95
8.1.1 Module Configurations .....................................................................................................96
8.1.2 Features .............................................................................................................................99
8.1.3 Block Diagram ..................................................................................................................99
8.2 External Signal Description ..........................................................................................................100
8.2.1 Analog Power (VDDAD) ..................................................................................................101
8.2.2 Analog Ground (VSSAD) .................................................................................................101
8.2.3 Voltage Reference High (VREFH) ...................................................................................101
8.2.4 Voltage Reference Low (VREFL) ....................................................................................101
8.2.5 Analog Channel Inputs (ADx) ........................................................................................101
8.3 Register Definition ........................................................................................................................101
8.3.1 Status and Control Register 1 (ADCSC1) ......................................................................101
MC9S08QD4 Series MCU Data Sheet, Rev. 5
12 Freescale Semiconductor
8.3.2 Status and Control Register 2 (ADCSC2) ......................................................................103
8.3.3 Data Result High Register (ADCRH) .............................................................................104
8.3.4 Data Result Low Register (ADCRL) ..............................................................................104
8.3.5 Compare Value High Register (ADCCVH) ....................................................................105
8.3.6 Compare Value Low Register (ADCCVL) .....................................................................105
8.3.7 Configuration Register (ADCCFG) ................................................................................105
8.3.8 Pin Control 1 Register (APCTL1) ..................................................................................107
8.3.9 Pin Control 2 Register (APCTL2) ..................................................................................108
8.3.10 Pin Control 3 Register (APCTL3) ..................................................................................109
8.4 Functional Description ..................................................................................................................110
8.4.1 Clock Select and Divide Control ....................................................................................110
8.4.2 Input Select and Pin Control ...........................................................................................111
8.4.3 Hardware Trigger ............................................................................................................ 111
8.4.4 Conversion Control .........................................................................................................111
8.4.5 Automatic Compare Function .........................................................................................114
8.4.6 MCU Wait Mode Operation ............................................................................................114
8.4.7 MCU Stop3 Mode Operation ..........................................................................................114
8.4.8 MCU Stop1 and Stop2 Mode Operation .........................................................................115
8.5 Initialization Information ..............................................................................................................115
8.5.1 ADC Module Initialization Example .............................................................................115
8.6 Application Information ................................................................................................................117
8.6.1 External Pins and Routing ..............................................................................................117
8.6.2 Sources of Error ..............................................................................................................119
Chapter 9
Internal Clock Source (S08ICSV1)
9.1 Introduction ...................................................................................................................................123
9.1.1 ICS Configuration Information .......................................................................................123
9.1.2 Features ...........................................................................................................................125
9.1.3 Modes of Operation ........................................................................................................125
9.1.4 Block Diagram ................................................................................................................126
9.2 External Signal Description ..........................................................................................................127
9.3 Register Definition ........................................................................................................................127
9.3.1 ICS Control Register 1 (ICSC1) .....................................................................................127
9.3.2 ICS Control Register 2 (ICSC2) .....................................................................................128
9.3.3 ICS Trim Register (ICSTRM) .........................................................................................129
9.3.4 ICS Status and Control (ICSSC) .....................................................................................129
9.4 Functional Description ..................................................................................................................130
9.4.1 Operational Modes ..........................................................................................................130
9.4.2 Mode Switching ..............................................................................................................132
9.4.3 Bus Frequency Divider ...................................................................................................132
9.4.4 Low Power Bit Usage .....................................................................................................133
9.4.5 Internal Reference Clock ................................................................................................133
9.4.6 Optional External Reference Clock ................................................................................133
9.4.7 Fixed Frequency Clock ...................................................................................................134
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 13
9.5 Module Initialization ....................................................................................................................134
9.5.1 ICS Module Initialization Sequence ...............................................................................134
Chapter 10
Keyboard Interrupt (S08KBIV2)
10.1 Introduction ...................................................................................................................................137
10.1.1 Features ...........................................................................................................................139
10.1.2 Modes of Operation ........................................................................................................139
10.1.3 Block Diagram ................................................................................................................139
10.2 External Signal Description ..........................................................................................................140
10.3 Register Definition ........................................................................................................................140
10.3.1 KBI Status and Control Register (KBISC) .....................................................................140
10.3.2 KBI Pin Enable Register (KBIPE) ..................................................................................141
10.3.3 KBI Edge Select Register (KBIES) ................................................................................141
10.4 Functional Description ..................................................................................................................142
10.4.1 Edge Only Sensitivity .....................................................................................................142
10.4.2 Edge and Level Sensitivity .............................................................................................142
10.4.3 KBI Pullup/Pulldown Resistors ......................................................................................143
10.4.4 KBI Initialization ............................................................................................................143
Chapter 11
Timer/Pulse-Width Modulator (S08TPMV2)
11.1 Introduction ...................................................................................................................................145
11.1.1 TPM2 Configuration Information ...................................................................................145
11.1.2 TCLK1 and TCLK2 Configuration Information ............................................................145
11.1.3 Features ...........................................................................................................................147
11.1.4 Block Diagram ................................................................................................................147
11.2 External Signal Description ..........................................................................................................149
11.2.1 External TPM Clock Sources .........................................................................................149
11.2.2 TPMxCHn — TPMx Channel n I/O Pins .......................................................................149
11.3 Register Definition ........................................................................................................................149
11.3.1 Timer Status and Control Register (TPMxSC) ...............................................................150
11.3.2 Timer Counter Registers (TPMxCNTH:TPMxCNTL) ...................................................151
11.3.3 Timer Counter Modulo Registers (TPMxMODH:TPMxMODL) ..................................152
11.3.4 Timer Channel n Status and Control Register (TPMxCnSC) .........................................153
11.3.5 Timer Channel Value Registers (TPMxCnVH:TPMxCnVL) .........................................154
11.4 Functional Description ..................................................................................................................155
11.4.1 Counter ............................................................................................................................155
11.4.2 Channel Mode Selection .................................................................................................156
11.4.3 Center-Aligned PWM Mode ...........................................................................................158
11.5 TPM Interrupts ..............................................................................................................................159
11.5.1 Clearing Timer Interrupt Flags .......................................................................................159
11.5.2 Timer Overflow Interrupt Description ............................................................................159
11.5.3 Channel Event Interrupt Description ..............................................................................160
11.5.4 PWM End-of-Duty-Cycle Events ...................................................................................160
MC9S08QD4 Series MCU Data Sheet, Rev. 5
14 Freescale Semiconductor
Chapter 12
Development Support
12.1 Introduction ...................................................................................................................................161
12.1.1 Forcing Active Background ............................................................................................161
12.1.2 Module Configuration .....................................................................................................161
12.1.3 Features ...........................................................................................................................162
12.2 Background Debug Controller (BDC) ..........................................................................................162
12.2.1 BKGD Pin Description ...................................................................................................163
12.2.2 Communication Details ..................................................................................................163
12.2.3 BDC Commands .............................................................................................................166
12.2.4 BDC Hardware Breakpoint .............................................................................................169
12.3 Register Definition ........................................................................................................................169
12.3.1 BDC Registers and Control Bits .....................................................................................170
12.3.2 System Background Debug Force Reset Register (SBDFR) ..........................................172
Appendix A
Electrical Characteristics
A.1 Introduction ...................................................................................................................................175
A.2 Absolute Maximum Ratings ..........................................................................................................175
A.3 Thermal Characteristics .................................................................................................................176
A.4 ESD Protection and Latch-Up Immunity ......................................................................................177
A.5 DC Characteristics .........................................................................................................................177
A.6 Supply Current Characteristics ......................................................................................................184
A.7 Internal Clock Source Characteristics ...........................................................................................186
A.8 AC Characteristics .........................................................................................................................188
A.8.1 Control Timing ...............................................................................................................188
A.8.2 Timer/PWM (TPM) Module Timing ..............................................................................189
A.9 ADC Characteristics ......................................................................................................................190
A.10 Flash Specifications .......................................................................................................................191
Appendix B
Ordering Information and Mechanical Drawings
B.1 Ordering Information ....................................................................................................................193
B.1.1 Device Numbering Scheme ............................................................................................193
B.2 Mechanical Drawings ....................................................................................................................194
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 15
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 17
Chapter 1
Device Overview
1.1 Introduction
MC9S08QD4 series MCUs are members of the low-cost, high-performance HCS08 family of 8-bit
microcontroller units (MCUs). All MCUs in the family use the enhanced HCS08 core and are available
with a variety of modules, memory sizes, memory types, and package types.
1.2 Devices in the MC9S08QD4 Series
This data sheet covers:
• MC9S08QD4
• MC9S08QD2
• S9S08QD4
• S9S08QD2
NOTE
• The MC9S08QD4 and MC9S08QD2 devices are qualified for, and are
intended to be used in, consumer and industrial applications.
• The S9S08QD4 and S9S08QD2 devices are qualified for, and are
intended to be used in, automotive applications.
Table 1-1 summarizes the features available in the MCUs.
Chapter 1 Device Overview
MC9S08QD4 Series MCU Data Sheet, Rev. 5
18 Freescale Semiconductor
Table 1-1. Features by MCU and Package
Consumer and Industrial Devices
Feature MC9S08QD4 MC9S08QD2
Flash 4 KB 2 KB
RAM 256 B 128 B
ADC 4-ch, 10-bit
Bus speed 8 MHz at 5 V
Operating voltage 2.7 to 5.5 V
16-bit Timer One 1-ch; one 2-ch
GPIO Four I/O; one input-only; one output-only
LVI Yes
Package options 8-pin PDIP; 8-pin NB SOIC
Consumer & Industrial Qualified yes yes
Automotive Qualified no no
Automotive Devices
Feature S9S08QD4 S9S08QD2
Flash 4 KB 2 KB
RAM 256 B 128 B
ADC 4-ch, 10-bit
Bus speed 8 MHz at 5 V
Operating voltage 2.7 to 5.5 V
16-bit Timer One 1-ch; one 2-ch
GPIO Four I/O; one input-only; one output-only
LVI Yes
Package options 8-pin NB SOIC
Consumer & Industrial Qualified no no
Automotive Qualified yes yes
Chapter 1 Device Overview
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 19
1.2.1 MCU Block Diagram
Figure 1-1. MC9S08QD4 Series Block Diagram
Table 1-2 provides the functional versions of the on-chip modules.
NOTES:
1Port pins are software configurable with pullup device if input port.
2Port pins are software configurable for output drive strength.
3Port pins are software configurable for output slew rate control.
4IRQ contains a software configurable (IRQPDD) pullup/pulldown device if PTA5 enabled as IRQ pin function (IRQPE = 1).
5RESET contains integrated pullup device if PTA5 enabled as reset pin function (RSTPE = 1).
6PTA5 does not contain a clamp diode to VDD and must not be driven above VDD. The voltage measured on this pin when
internal pullup is enabled may be as low as VDD – 0.7 V. The internal gates connected to this pin are pulled to VDD.
7PTA4 contains integrated pullup device if BKGD enabled (BKGDPE = 1).
8When pin functions as KBI (KBIPEn = 1) and associated pin is configured to enable the pullup device, KBEDGn can be used
to reconfigure the pullup as a pulldown device.
USER RAM
HCS08 CORE
CPU
BDC
2-CH 16-BIT TIMER/PWM
MODULE (TPM1)
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
RTI COP
IRQ LVD
VOLTAGE REGULATOR
PORT A
PTA5/TPM2CH0I/IRQ/RESET
PTA4/TPM2CH0O/BKGD/MS
PTA3/KBI1P3/TCLK2/ADC1P3
PTA2/KBI1P2/TCLK1/ADC1P2
PTA1/KBI1P1/TPM1CH1/ADC1P1
PTA0/KBI1P0/TPM1CH0/ADC1P0
4-BIT KEYBOARD
INTERRUPT MODULE (KBI)
256 / 128 BYTES
16 MHz INTERNAL CLOCK
SOURCE (ICS)
VSS
VDD
VSSA
VDDA
VREFL
VREFH
4
ANALOG-TO-DIGITAL
CONVERTER (ADC)
10-BIT
TPM1CH0
TPM1CH1
BKGD/MS
IRQ
4
1-CH 16-BIT TIMER/PWM
MODULE (TPM2)
TPM2CH0
USER FLASH
4096 / 2048 BYTES
TCLK2
TCLK1
Chapter 1 Device Overview
MC9S08QD4 Series MCU Data Sheet, Rev. 5
20 Freescale Semiconductor
1.3 System Clock Distribution
Figure 1-2 shows a simplified clock connection diagram. Some modules in the MCU have selectable clock
inputs as shown. The clock inputs to the modules indicate the clock(s) that are used to drive the module
function. All memory mapped registers associated with the modules are clocked with BUSCLK.
Figure 1-2. System Clock Distribution Diagram
Table 1-2. Versions of On-Chip Modules
Module Version
Analog-to-Digital Converter (ADC) 1
Central Processing Unit (CPU) 2
Internal Clock Source (ICS) 1
Keyboard Interrupt (KBI) 2
Timer Pulse-Width Modulator (TPM) 2
TPM1 TPM2
CPU
BDC ADC2FLASH3
ICS ICSOUT ÷2
SYSTEM CONTROL LOGIC
BUSCLK
ICSLCLK1
RTI
1ICSLCLK is the alternate BDC clock source for the MC9S08QD4 series.
2ADC has min. and max frequency requirements. See ADC chapter and Appendix A, “Electrical Characteristics.”
3Flash has frequency requirements for program and erase operation.See Appendix A, “Electrical Characteristics.”
÷2
ICSFFCLK
COP
TCLK1 TCLK2
ICSIRCLK
FIXED FREQ CLOCK (XCLK)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 21
Chapter 2
External Signal Description
This chapter describes signals that connect to package pins. It includes pinout diagrams, table of signal
properties, and detailed discussions of signals.
2.1 Device Pin Assignment
Figure 2-1 shows the pin assignments for the 8-pin packages.
Figure 2-1. 8-Pin Packages
2.2 Recommended System Connections
Figure 2-2 shows pin connections that are common to almost all MC9S08QD4 series application systems.
1
2
3
4
8
7
6
5
PTA0/KBI1P0/TPM1CH0/ADC1P0
PTA1/KBI1P1/TPM1CH1/ADC1P1
PTA2/KBI1P2/TCLK1/ADC1P2
PTA3/KBI1P3/TCLK2/ADC1P3
VSS
VDD
PTA4/TPM2CH0O/BKGD/MS
PTA5/TPM2CH0I/IRQ/RESET
Chapter 2 External Signal Description
MC9S08QD4 Series MCU Data Sheet, Rev. 5
22 Freescale Semiconductor
Figure 2-2. Basic System Connections
2.2.1 Power
VDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to all
I/O buffer circuitry, the ADC module, and to an internal voltage regulator. The internal voltage regulator
provides regulated lower-voltage source to the CPU and other internal circuitry of the MCU.
Typically, application systems have two separate capacitors across the power pins: a bulk electrolytic
capacitor, such as a 10μF tantalum capacitor, to provide bulk charge storage for the overall system, and a
bypass capacitor, such as a 0.1μF ceramic capacitor, located as near to the MCU power pins as practical
to suppress high-frequency noise.
VDD
VSS
RESET
OPTIONAL
MANUAL
RESET
PORT
A
V
DD
BACKGROUND HEADER
CBY
0.1 μF
CBLK
10 μF
+
5 V
+
SYSTEM
POWER
I/O AND
PERIPHERAL
INTERFACE TO
SYSTEM
APPLICATION
PTA0/KBI1P0/TPM1CH0/ADC1P0
PTA1/KBI1P1/TPM1CH1/ADC1P1
PTA2/KBI1P2/TCLK1/ADC1P2
PTA3/KBI1P3/TCLK2/ADC1P3
VDD
PTA4/TPM2CH0O/BKGD/MS
PTA5/TPM2CH0I/IRQ/RESET
MC9S08QD4
BKGD
NOTE 2
NOTES:
1. RESET pin can only be used to reset into user mode, you can not enter BDM using RESET pin. BDM can
be entered by holding MS low during POR or writing a 1 to BDFR in SBDFR with MS low after issuing BDM
command.
2. IRQ has optional internal pullup/pulldown device
IRQ
ASYNCHRONOUS
INTERRUPT
INPUT
NOTE 1
Chapter 2 External Signal Description
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 23
2.2.2 Oscillator
Out of reset the MCU uses an internally generated clock provided by the internal clock source (ICS)
module. The internal frequency is nominally 16 MHz and the default ICS settings will provide for a 4 MHz
bus out of reset. For more information on the ICS, see the Internal Clock Source chapter.
2.2.3 Reset (Input Only)
After a power-on reset (POR) into user mode, the PTA5/TPM2CH0I/IRQ/RESET pin defaults to a
general-purpose input port pin, PTA5. Setting RSTPE in SOPT1 configures the pin to be the RESET input
pin. Once configured as RESET, the pin will remain RESET until the next POR. The RESET pin can be
used to reset the MCU from an external source when the pin is driven low. When enabled as the RESET
pin (RSTPE = 1), an internal pullup device is automatically enabled.
After a POR into active background mode, the PTA5/TPM2CH0I/IRQ/RESET pin defaults to the RESET
pin.
When TPM2 is configured for input capture, the pin will be the input capture pin TPM2CH0I.
NOTE
This pin does not contain a clamp diode to VDD and must not be driven
above VDD.
The voltage measured on the internally pulled up RESET pin may be as low
as VDD – 0.7 V. The internal gates connected to this pin are pulled to VDD.
2.2.4 Background / Mode Select (BKGD/MS)
During a power-on-reset (POR) or background debug force reset (see Section 5.8.3, “System Background
Debug Force Reset Register (SBDFR)” for more information), the PTA4/TPM2CH0O/BKGD/MS pin
functions as a mode select pin. Immediately after any reset, the pin functions as the background pin and
can be used for background debug communication. When enabled as the BKGD/MS pin (BKGDPE = 1),
an internal pullup device is automatically enabled.
The background debug communication function is enabled when BKGDPE in SOPT1 is set. BKGDPE is
set following any reset of the MCU and must be cleared to use the PTA4/TPM2CH0O/BKGD/MS pins
alternative pin functions.
If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of the
internal reset after a POR or force BDC reset. If a debug system is connected to the 6-pin standard
background debug header, it can hold BKGD/MS low during a POR or immediately after issuing a
background debug force reset, which will force the MCU to active background mode.
The BKGD pin is used primarily for background debug controller (BDC) communications using a custom
protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC
clock could be as fast as the maximum bus clock rate, so there must never be any significant capacitance
connected to the BKGD/MS pin that could interfere with background serial communications.
Chapter 2 External Signal Description
MC9S08QD4 Series MCU Data Sheet, Rev. 5
24 Freescale Semiconductor
Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol
provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from
cables and the absolute value of the internal pullup device play almost no role in determining rise and fall
times on the BKGD pin.
2.2.5 General-Purpose I/O and Peripheral Ports
The MC9S08QD4 series of MCUs support up to 4 general-purpose I/O pins, 1 input-only pin and 1
output-only pin, which are shared with on-chip peripheral functions (timers, serial I/O, ADC, keyboard
interrupts, etc.). On each of the MC9S08QD4 series devices there is one input-only and one output-only
port pin.
When a port pin is configured as a general-purpose output or a peripheral uses the port pin as an output,
software can select one of two drive strengths and enable or disable slew rate control. When a port pin is
configured as a general-purpose input or a peripheral uses the port pin as an input, software can enable a
pullup device.
For information about controlling these pins as general-purpose I/O pins, see the Chapter 6, “Parallel
Input/Output Control.” For information about how and when on-chip peripheral systems use these pins,
see the appropriate chapter referenced in Table 2-1.
Immediately after reset, all pins that are not output-only are configured as high-impedance,
general-purpose inputs with internal pullup devices disabled. After reset, the output-only port function is
not enabled but is configured for low output drive strength with slew rate control enabled. The PTA4 pin
defaults to BKGD/MS on any reset.
NOTE
To avoid extra current drain from floating input pins, the reset initialization
routine in the application program must either enable on-chip pullup devices
or change the direction of unused pins to outputs so the pins do not float.
2.2.5.1 Pin Control Registers
To select drive strength or enable slew rate control or pullup devices, the user writes to the appropriate pin
control register located in the high-page register block of the memory map. The pin control registers
operate independently of the parallel I/O registers and allow control of a port on an individual pin basis.
2.2.5.1.1 Internal Pullup Enable
An internal pullup device can be enabled for each port pin by setting the corresponding bit in one of the
pullup enable registers (PTxPEn). The pullup device is disabled if the pin is configured as an output by the
parallel I/O control logic or any shared peripheral function, regardless of the state of the corresponding
pullup enable register bit. The pullup device is also disabled if the pin is controlled by an analog function.
The KBI module and IRQ function when enabled for rising edge detection causes an enabled internal pull
device to be configured as a pulldown.
Chapter 2 External Signal Description
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 25
2.2.5.2 Output Slew Rate Control
Slew rate control can be enabled for each port pin by setting the corresponding bit in one of the slew rate
control registers (PTxSEn). When enabled, slew control limits the rate at which an output can transition in
order to reduce EMC emissions. Slew rate control has no effect on pins that are configured as inputs.
2.2.5.3 Output Drive Strength Select
An output pin can be selected to have high output drive strength by setting the corresponding bit in one of
the drive strength select registers (PTxDSn). When high drive is selected, a pin is capable of sourcing and
sinking greater current. Even though every I/O pin can be selected as high drive, the user must ensure that
the total current source and sink limits for the chip are not exceeded. Drive strength selection is intended
to affect the DC behavior of I/O pins. However, the AC behavior is also affected. High drive allows a pin
to drive a greater load with the same switching speed as a low drive enabled pin into a smaller load.
Because of this, the EMC emissions may be affected by enabling pins as high drive.
Table 2-1. Pin Sharing Priority
Lowest <- Pin Function Priority -> Highest
Reference1
1See the module section listed for information on modules that share these pins.
Port Pins Alternative
Function
Alternative
Function
Alternative
Function
PTA0
PTA1
PTA2
PTA3
PTA4
PTA52
2Pin does not contain a clamp diode to VDD and must not be driven above VDD. The voltage measured on this
pin when internal pullup is enabled may be as low as VDD – 0.7 V. The internal gates connected to this pin are
pulled to VDD.
KBI1P0
KBI1P1
KBI1P2
KBI1P3
TPM2CH0O
TPM2CH0I
TPM1CH0
TPM1CH1
TCLK1
TCLK2
BKGD/MS
IRQ
ADC1P03
ADC1P13
ADC1P23
ADC1P33
RESET
3If both of these analog modules are enabled both will have access to the pin.
KBI1, ADC1, and TPM1 Chapters
KBI1, ADC1, and TPM1 Chapters
KBI1, ADC1, and TPM1 Chapters
KBI1, ADC1, and TPM2 Chapters
TPM2 Chapters
IRQ4, and TPM2 Chapters
4See Section 5.8, “Reset, Interrupt, and System Control Registers and Control Bits,” for information on
configuring the IRQ module.
Chapter 2 External Signal Description
MC9S08QD4 Series MCU Data Sheet, Rev. 5
26 Freescale Semiconductor
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 27
Chapter 3
Modes of Operation
3.1 Introduction
The operating modes of the MC9S08QD4 series are described in this chapter. Entry into each mode, exit
from each mode, and functionality while in each of the modes are described.
3.2 Features
• Active background mode for code development
• Wait mode:
— CPU shuts down to conserve power
— System clocks running
— Full voltage regulation maintained
• Stop modes:
— CPU and bus clocks stopped
— Stop2 — Partial power down of internal circuits, RAM contents retained
— Stop3 — All internal circuits powered for fast recovery
3.3 Run Mode
This is the normal operating mode for the MC9S08QD4 series. This mode is selected when the BKGD/MS
pin is high at the rising edge of reset. In this mode, the CPU executes code from internal memory with
execution beginning at the address fetched from memory at 0xFFFE:0xFFFF after reset.
3.4 Active Background Mode
The active background mode functions are managed through the background debug controller (BDC) in
the HCS08 core. The BDC provides the means for analyzing MCU operation during software
development.
Active background mode is entered in any of five ways:
• When the BKGD/MS pin is low at the rising edge of reset
• When a BACKGROUND command is received through the BKGD pin
• When a BGND instruction is executed
• When encountering a BDC breakpoint
Chapter 3 Modes of Operation
MC9S08QD4 Series MCU Data Sheet, Rev. 5
28 Freescale Semiconductor
After entering active background mode, the CPU is held in a suspended state waiting for serial background
commands rather than executing instructions from the user’s application program.
Background commands are of two types:
• Non-intrusive commands, defined as commands that can be issued while the user program is
running. Non-intrusive commands can be issued through the BKGD pin while the MCU is in run
mode; non-intrusive commands can also be executed when the MCU is in the active background
mode. Non-intrusive commands include:
— Memory access commands
— Memory-access-with-status commands
— BDC register access commands
— The BACKGROUND command
• Active background commands, which can only be executed while the MCU is in active background
mode. Active background commands include commands to:
— Read or write CPU registers
— Trace one user program instruction at a time
— Leave active background mode to return to the user’s application program (GO)
The active background mode is used to program a bootloader or user application program into the flash
program memory before the MCU is operated in run mode for the first time. When MC9S08QD4 series
devices are shipped from the Freescale Semiconductor factory, the flash program memory is erased by
default unless specifically noted, so no program can be executed in run mode until the flash memory is
initially programmed. The active background mode can also be used to erase and reprogram the flash
memory after it has been previously programmed.
For additional information about the active background mode, refer to Chapter 12, “Development
Support.”
3.5 Wait Mode
Wait mode is entered by executing a WAIT instruction. Upon execution of the WAIT instruction, the CPU
enters a low-power state in which it is not clocked. The I bit in CCR is cleared when the CPU enters the
wait mode, enabling interrupts. When an interrupt request occurs, the CPU exits the wait mode and
resumes processing, beginning with the stacking operations leading to the interrupt service routine.
While the MCU is in wait mode, there are some restrictions on which background debug commands can
be used. Only the BACKGROUND command and memory-access-with-status commands are available
when the MCU is in wait mode. The memory-access-with-status commands do not allow memory access,
but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND
command can be used to wake the MCU from wait mode and enter active background mode.
3.6 Stop Modes
One of two stop modes is entered upon execution of a STOP instruction when the STOPE bit in the system
option register is set. In both stop modes, all internal clocks are halted. If the STOPE bit is not set when
Chapter 3 Modes of Operation
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 29
the CPU executes a STOP instruction, the MCU will not enter either of the stop modes and an illegal
opcode reset is forced. The stop modes are selected by setting the appropriate bits in SPMSC2.
HCS08 devices that are designed for low voltage operation (1.8V to 3.6V) also include stop1 mode. The
MC9S08QD4 series does not include stop1 mode.
Table 3-1 summarizes the behavior of the MCU in each of the stop modes.
3.6.1 Stop2 Mode
The stop2 mode provides very low standby power consumption and maintains the contents of RAM and
the current state of all of the I/O pins. To enter stop2, the user must execute a STOP instruction with stop2
selected (PPDC = 1) and stop mode enabled (STOPE = 1). In addition, the LVD must not be enabled to
operate in stop (LVDSE = 0 or LVDE = 0). If the LVD is enabled in stop, then the MCU enters stop3 upon
the execution of the STOP instruction regardless of the state of PPDC.
Before entering stop2 mode, the user must save the contents of the I/O port registers, as well as any other
memory-mapped registers which they want to restore after exit of stop2, to locations in RAM. Upon exit
of stop2, these values can be restored by user software before pin latches are opened.
When the MCU is in stop2 mode, all internal circuits that are powered from the voltage regulator are turned
off, except for the RAM. The voltage regulator is in a low-power standby state, as is the ADC. Upon entry
into stop2, the states of the I/O pins are latched. The states are held while in stop2 mode and after exiting
stop2 mode until a logic 1 is written to PPDACK in SPMSC2.
Exit from stop2 is done by asserting either of the wake-up pins: RESET or IRQ, or by an RTI interrupt.
IRQ is always an active low input when the MCU is in stop2, regardless of how it was configured before
entering stop2.
NOTE
Although this IRQ pin is automatically configured as active low input, the
pullup associated with the IRQ pin is not automatically enabled. Therefore,
if an external pullup is not used, the internal pullup must be enabled by
setting IRQPE in IRQSC.
Upon wake-up from stop2 mode, the MCU will start up as from a power-on reset (POR) except pin states
remain latched. The CPU will take the reset vector. The system and all peripherals will be in their default
reset states and must be initialized.
Table 3-1. Stop Mode Behavior
Mode PPDC
CPU, Digital
Peripherals,
Flash
RAM ICS ADC1 Regulator I/O Pins RTI
Stop2 1 Off Standby Off Disabled Standby States held Optionally on
Stop3 0 Standby Standby Off1
1ICS can be configured to run in stop3. Please see the ICS registers.
Optionally on Standby States held Optionally on
Chapter 3 Modes of Operation
MC9S08QD4 Series MCU Data Sheet, Rev. 5
30 Freescale Semiconductor
After waking up from stop2, the PPDF bit in SPMSC2 is set. This flag may be used to direct user code to
go to a stop2 recovery routine. PPDF remains set and the I/O pin states remain latched until a logic 1 is
written to PPDACK in SPMSC2.
To maintain I/O state for pins that were configured as general-purpose I/O, the user must restore the
contents of the I/O port registers, which have been saved in RAM, to the port registers before writing to
the PPDACK bit. If the port registers are not restored from RAM before writing to PPDACK, then the
register bits will assume their reset states when the I/O pin latches are opened and the I/O pins will switch
to their reset states.
For pins that were configured as peripheral I/O, the user must reconfigure the peripheral module that
interfaces to the pin before writing to the PPDACK bit. If the peripheral module is not enabled before
writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O
latches are opened.
3.6.2 Stop3 Mode
Stop3 mode is entered by executing a STOP instruction under the conditions as shown in Table 3-1. The
states of all of the internal registers and logic, RAM contents, and I/O pin states are maintained.
Stop3 can be exited by asserting RESET, or by an interrupt from one of the following sources: the real-time
interrupt (RTI), LVD, ADC, IRQ, or the KBI.
If stop3 is exited by means of the RESET pin, then the MCU is reset and operation will resume after taking
the reset vector. Exit by means of one of the internal interrupt sources results in the MCU taking the
appropriate interrupt vector.
3.6.3 Active BDM Enabled in Stop Mode
Entry into the active background mode from run mode is enabled if the ENBDM bit in BDCSCR is set.
This register is described in Chapter 12, “Development Support,” of this data sheet. If ENBDM is set when
the CPU executes a STOP instruction, the system clocks to the background debug logic remain active
when the MCU enters stop mode so background debug communication is still possible. In addition, the
voltage regulator does not enter its low-power standby state but maintains full internal regulation. If the
user attempts to enter stop2 with ENBDM set, the MCU will instead enter stop3.
Most background commands are not available in stop mode. The memory-access-with-status commands
do not allow memory access, but they report an error indicating that the MCU is in either stop or wait
mode. The BACKGROUND command can be used to wake the MCU from stop and enter active
background mode if the ENBDM bit is set. After entering background debug mode, all background
commands are available. Table 3-2 summarizes the behavior of the MCU in stop when entry into the
background debug mode is enabled.
Chapter 3 Modes of Operation
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 31
3.6.4 LVD Enabled in Stop Mode
The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below
the LVD voltage. If the LVD is enabled in stop by setting the LVDE and the LVDSE bits, then the voltage
regulator remains active during stop mode. If the user attempts to enter stop2 with the LVD enabled for
stop, the MCU will instead enter stop3. Table 3-3 summarizes the behavior of the MCU in stop when the
LVD is enabled.
3.6.5 On-Chip Peripheral Modules in Stop Modes
When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even
in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate,
clocks to the peripheral systems are halted to reduce power consumption. Refer to Section 3.6.1, “Stop2
Mode,” and Section 3.6.2, “Stop3 Mode,” for specific information on system behavior in stop modes.
Table 3-2. BDM Enabled Stop Mode Behavior
Mode PPDC
CPU, Digital
Peripherals,
Flash
RAM ICS ADC1 Regulator I/O Pins RTI
Stop3 0 Standby Standby Active Optionally on Active States held Optionally on
Table 3-3. LVD Enabled Stop Mode Behavior
Mode PPDC
CPU, Digital
Peripherals,
Flash
RAM ICS ADC1 Regulator I/O Pins RTI
Stop3 0 Standby Standby Off1
1ICS can be configured to run in stop3. Please see the ICS registers.
Optionally on Active States held Optionally on
Table 3-4. Stop Mode Behavior
Peripheral
Mode
Stop2 Stop3
CPU Off Standby
RAM Standby Standby
Flash Off Standby
Parallel Port Registers Off Standby
ADC1 Off Optionally On1
1Requires the asynchronous ADC clock and LVD to be enabled, else in standby.
ICS Off Standby
TPM1 & TPM2 Off Standby
Voltage Regulator Standby Standby
I/O Pins States Held States Held
Chapter 3 Modes of Operation
MC9S08QD4 Series MCU Data Sheet, Rev. 5
32 Freescale Semiconductor
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 33
Chapter 4
Memory Map and Register Definition
4.1 MC9S08QD4 Series Memory Maps
As shown in Figure 4-1, on-chip memory in the MC9S08QD4 series MCU consists of RAM, flash
program memory for non-volatile data storage, and I/O and control/status registers. The registers are
divided into these groups:
• Direct-page registers (0x0000 through 0x005F)
• High-page registers (0x1800 through 0x184F)
• Non-volatile registers (0xFFB0 through 0xFFBF)
Figure 4-1. MC9S08QD4 Series Memory Maps
DIRECT PAGE REGISTERS
RAM
HIGH PAGE REGISTERS
256 BYTES
0x0000
0x005F
0x0060
0x1800
0x17FF
0x184F
0xFFFF
FLASH
4096 BYTES
0x1850
0x015F
0x0160 UNIMPLEMENTED
5,792 BYTES
UNIMPLEMENTED
55,216 BYTES
0xF000
0xEFFF
DIRECT PAGE REGISTERS
RESERVED — 32 BYTES
HIGH PAGE REGISTERS
0x0000
0x005F
0x0060–0x07F
0x1800
0x17FF
0x184F
0xFFFF
FLASH
2048 BYTES
0x1850
0x0100–0x015F
UNIMPLEMENTED
5,792 BYTES
UNIMPLEMENTED
55,216 BYTES
0xF000
0xEFFF
RESERVED — 96 BYTES
RESERVED — 2048 BYTES
0xF800
0xF7FF
MC9S08QD4 MC9S08QD2
RAM — 128 BYTES
0x0080–0x0FF
Chapter 4 Memory Map and Register Definition
MC9S08QD4 Series MCU Data Sheet, Rev. 5
34 Freescale Semiconductor
4.2 Reset and Interrupt Vector Assignments
Table 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table
are the labels used in the Freescale Semiconductor-provided equate file for the MC9S08QD4 series.
Table 4-1. Reset and Interrupt Vectors
Address
(High/Low) Vector Vector Name
0xFFC0:FFC1
0xFFCE:FFCF
Unused Vector Space
(available for user program)
0xFFD0:FFD1 RTI Vrti
0xFFD2:FFD3 Reserved —
0xFFD4:FFD5 Reserved —
0xFFD6:FFD7 Reserved —
0xFFD8:FFD9 ADC1 Conversion Vadc1
0xFFDA:FFDB KBI Interrupt Vkeyboard1
0xFFDC:FFDD Reserved —
0xFFDE:FFDF Reserved —
0xFFE0:FFE1 Reserved —
0xFFE2:FFE3 Reserved —
0xFFE4:FFE5 Reserved —
0xFFE6:FFE7 Reserved —
0xFFE8:FFE9 Reserved —
0xFFEA:FFEB TPM2 Overflow Vtpm2ovf
0xFFEC:FFED Reserved —
0xFFEE:FFEF TPM2 Channel 0 Vtpm2ch0
0xFFF0:FFF1 TPM1 Overflow Vtpm1ovf
0xFFF2:FFF3 TPM1 Channel 1 Vtpm1ch1
0xFFF4:FFF5 TPM1 Channel 0 Vtpm1ch0
0xFFF6:FFF7 Reserved —
0xFFF8:FFF9 IRQ IRQ
0xFFFA:FFFB Low Voltage Detect Vlvd
0xFFFC:FFFD SWI Vswi
0xFFFE:FFFF Reset Vreset
Chapter 4 Memory Map and Register Definition
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 35
4.3 Register Addresses and Bit Assignments
The registers in the MC9S08QD4 series are divided into these groups:
• Direct-page registers are located in the first 96 locations in the memory map; these are accessible
with efficient direct addressing mode instructions.
• High-page registers are used much less often, so they are located above 0x1800 in the memory
map. This leaves more room in the direct page for more frequently used registers and RAM.
• The nonvolatile register area consists of a block of 16 locations in flash memory at
0xFFB0–0xFFBF. Nonvolatile register locations include:
— NVPROT and NVOPT are loaded into working registers at reset
— An 8-byte backdoor comparison key that optionally allows a user to gain controlled access to
secure memory
Because the nonvolatile register locations are flash memory, they must be erased and programmed
like other flash memory locations.
Direct-page registers can be accessed with efficient direct addressing mode instructions. Bit manipulation
instructions can be used to access any bit in any direct-page register. Table 4-2 is a summary of all
user-accessible direct-page registers and control bits.
The direct page registers in Table 4-2 can use the more efficient direct addressing mode that requires only
the lower byte of the address. Because of this, the lower byte of the address in column one is shown in bold
text. In Table 4-3 and Table 4-4, the whole address in column one is shown in bold. In Table 4-2, Table 4-3,
and Table 4-4, the register names in column two are shown in bold to set them apart from the bit names to
the right. Cells that are not associated with named bits are shaded. A shaded cell with a 0 indicates this
unused bit always reads as a 0. Shaded cells with dashes indicate unused or reserved bit locations that could
read as 1s or 0s.
Table 4-2. Direct-Page Register Summary
AddressRegister NameBit 7654321Bit 0
0x0000 PTAD 0 0 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0
0x0001 PTADD 00 PTADD5 PTADD4 PTADD3 PTADD2 PTADD1 PTADD0
0x0002–
0x000B Reserved —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0x000C KBISC 0000 KBF KBACK KBIE KBIMOD
0x000D KBIPE KBIPE7 KBIPE6 KBIPE5 KBIPE4 KBIPE3 KBIPE2 KBIPE1 KBIPE0
0x000E KBIES KBEDG7 KBEDG6 KBEDG5 KBEDG4 KBEDG3 KBEDG2 KBEDG1 KBEDG0
0x000F IRQSC 0 IRQPDD IRQEDG IRQPE IRQF IRQACK IRQIE IRQMOD
0x0010 ADCSC1 COCO AIEN ADCO ADCH
0x0011 ADCSC2 ADACT ADTRG ACFE ACFGT — — — —
0x0012 ADCRH 000000 ADR9 ADR8
0x0013 ADCRL ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
0x0014 ADCCVH 000000 ADCV9 ADCV8
0x0015 ADCCVL ADCV7 ADCV6 ADCV5 ADCV4 ADCV3 ADCV2 ADCV1 ADCV0
0x0016 ADCCFG ADLPC ADIV ADLSMP MODE ADICLK
Chapter 4 Memory Map and Register Definition
MC9S08QD4 Series MCU Data Sheet, Rev. 5
36 Freescale Semiconductor
High-page registers, shown in Table 4-3, are accessed much less often than other I/O and control registers
so they have been located outside the direct addressable memory space, starting at 0x1800.
0x0017 APCTL1 ———— ADPC3 ADPC2 ADPC1 ADPC0
0x0018 Reserved ————————
0x0019 Reserved ————————
0x001A–
0x001F Reserved —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0x0020 TPM2SC TOF TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0
0x0021 TPM2CNTH Bit 15 14 13 12 11 10 9 Bit 8
0x0022 TPM2CNTL Bit 7654321Bit 0
0x0023 TPM2MODH Bit 15 14 13 12 11 10 9 Bit 8
0x0024 TPM2MODL Bit 7654321Bit 0
0x0025 TPM2C0SC CH0F CH0IE MS0B MS0A ELS0B ELS0A 0 0
0x0026 TPM2C0VH Bit 15 14 13 12 11 10 9 Bit 8
0x0027 TPM2C0VL Bit 7654321Bit 0
0x0028–
0x0037 Reserved —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0x0038 ICSC1 0CLKS00011IREFSTEN
0x0039 ICSC2 BDIV 00LP000
0x003A ICSTRM TRIM
0x003B ICSSC 00000CLKST0FTRIM
0x003C Reserved ————————
0x0040 TPMSC TOF TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0
0x0041 TPMCNTH Bit 15 14 13 12 11 10 9 Bit 8
0x0042 TPMCNTL Bit 7654321Bit 0
0x0043 TPMMODH Bit 15 14 13 12 11 10 9 Bit 8
0x0044 TPMMODL Bit 7654321Bit 0
0x0045 TPMC0SC CH0F CH0IE MS0B MS0A ELS0B ELS0A 0 0
0x0046 TPMC0VH Bit 15 14 13 12 11 10 9 Bit 8
0x0047 TPMC0VL Bit 7654321Bit 0
0x0048 TPMC1SC CH1F CH1IE MS1B MS1A ELS1B ELS1A 0 0
0x0049 TPMC1VH Bit 15 14 13 12 11 10 9 Bit 8
0x004A TPMC1VL Bit 7654321Bit 0
0x004B–
0x005F Reserved —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Table 4-2. Direct-Page Register Summary (continued)
AddressRegister NameBit 7654321Bit 0
Chapter 4 Memory Map and Register Definition
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 37
Nonvolatile flash registers, shown in Table 4-4, are located in the flash memory. These registers include
an 8-byte backdoor key that optionally can be used to gain access to secure memory resources. During
reset events, the contents of NVPROT and NVOPT in the nonvolatile register area of the flash memory
are transferred into corresponding FPROT and FOPT working registers in the high-page registers to
control security and block protection options.
Table 4-3. High-Page Register Summary
AddressRegister NameBit 7654321Bit 0
0x1800 SRS POR PIN COP ILOP ILAD 0LVD0
0x1801 SBDFR 0000000BDFR
0x1802 SOPT1 COPE COPT STOPE 000 BKGDPE RSTPE
0x1803 SOPT2 COPCLKS 0000000
0x1804 Reserved ————————
0x1805 Reserved ————————
0x1806 SDIDH REV3 REV2 REV1 REV0 ID11 ID10 ID9 ID8
0x1807 SDIDL ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
0x1808 SRTISC RTIF RTIACK RTICLKS RTIE 0RTIS
0x1809 SPMSC1 LVDF LVDACK LVDIE LVDRE LVDSE LVDE 01
1This reserved bit must always be written to 0.
BGBE
0x180A SPMSC2 LVWF LVWACK LVDV LVWV PPDF PPDACK —PPDC
0x180B–
0x181F Reserved —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0x1820 FCDIV DIVLD PRDIV8 DIV
0x1821 FOPT KEYEN FNORED 0000 SEC01 SEC00
0x1822 Reserved ————————
0x1823 FCNFG 00 KEYACC 00000
0x1824 FPROT FPS FPDIS
0x1825 FSTAT FCBEF FCCF FPVIOL FACCERR 0 FBLANK 0 0
0x1826 FCMD FCMD
0x1827–
0x183F Reserved —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0x1840 PTAPE 00 PTAPE5 PTAPE4 PTAPE3 PTAPE2 PTAPE1 PTAPE0
0x1841 PTASE 00 PTASE5 PTASE4 PTASE3 PTASE2 PTASE1 PTASE0
0x1842 PTADS 00 PTADS5 PTADS4 PTADS3 PTADS2 PTADS1 PTADS0
0x1843–
0x1847 Reserved —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Chapter 4 Memory Map and Register Definition
MC9S08QD4 Series MCU Data Sheet, Rev. 5
38 Freescale Semiconductor
Provided the key enable (KEYEN) bit is 1, the 8-byte comparison key can be used to temporarily
disengage memory security. This key mechanism can be accessed only through user code running in secure
memory. (A security key cannot be entered directly through background debug commands.) This security
key can be disabled completely by programming the KEYEN bit to 0. If the security key is disabled, the
only way to disengage security is by mass erasing the flash if needed (normally through the background
debug interface) and verifying that flash is blank. To avoid returning to secure mode after the next reset,
program the security bits (SEC01:SEC00) to the unsecured state (1:0).
The ICS factory-trimmed value will be stored in 0xFFAE (bit-0) and 0xFFAF. Development tools, such as
programmers can trim the ICS and the internal temperature sensor (via the ADC) and store the values in
0xFFAD–0xFFAF.
4.4 RAM
The MC9S08QD4 series includes static RAM. The locations in RAM below 0x0100 can be accessed using
the more efficient direct addressing mode, and any single bit in this area can be accessed with the bit
manipulation instructions (BCLR, BSET, BRCLR, and BRSET). Locating the most frequently accessed
program variables in this area of RAM is preferred.
The RAM retains data when the MCU is in low-power wait, stop2, or stop3 mode. At power-on or after
wakeup from stop1, the contents of RAM are uninitialized. RAM data is unaffected by any reset provided
that the supply voltage does not drop below the minimum value for RAM retention (VRAM).
Table 4-4. Nonvolatile Register Summary
AddressRegister NameBit 7654321Bit 0
0xFFAA –
0xFFAC
Reserved —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0xFFAD Reserved for
ADCRL of AD26
value during ICS
trim
ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
0xFFAE Reserved for
ADCRH of AD26
value during ICS
trim and ICS Trim
value “FTRIM”
ADR9 ADR8 —————FTRIM
0xFFAF Reserved for
ICS Trim value
“TRIM”
TRIM
0xFFB0 –
0xFFB7
NVBACKKEY 8-Byte Comparison Key
0xFFB8 –
0xFFBC
Reserved —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0xFFBD NVPROT FPS FPDIS
0xFFBE Unused ————————
0xFFBF NVOPT KEYEN FNORED 0000 SEC01 SEC00
Chapter 4 Memory Map and Register Definition
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 39
For compatibility with M68HC05 MCUs, the HCS08 resets the stack pointer to 0x00FF. In the
MC9S08QD4 series, it is usually best to reinitialize the stack pointer to the top of the RAM so the direct
page RAM can be used for frequently accessed RAM variables and bit-addressable program variables.
Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated
to the highest address of the RAM in the Freescale Semiconductor-provided equate file).
LDHX #RamLast+1 ;point one past RAM
TXS ;SP<-(H:X-1)
When security is enabled, the RAM is considered a secure memory resource and is not accessible through
BDM or through code executing from non-secure memory. See Section 4.6, “Security,” for a detailed
description of the security feature.
4.5 Flash
The flash memory is intended primarily for program storage. In-circuit programming allows the operating
program to be loaded into the flash memory after final assembly of the application product. It is possible
to program the entire array through the single-wire background debug interface. Because no special
voltages are needed for flash erase and programming operations, in-application programming is also
possible through other software-controlled communication paths. For a more detailed discussion of
in-circuit and in-application programming, refer to the HCS08 Family Reference Manual, Volume I,
Freescale Semiconductor document order number HCS08RMv1.
4.5.1 Features
Features of the flash memory include:
• Flash size
— MC9S08QD4/S9S08QD4: 4096 bytes (8 pages of 512 bytes each)
— MC9S08QD2/S9S08QD2: 2048 bytes (4 pages of 512 bytes each)
• Single power supply program and erase
• Command interface for fast program and erase operation
• Up to 100,000 program/erase cycles at typical voltage and temperature
• Flexible block protection
• Security feature for flash and RAM
• Auto power-down for low-frequency read accesses
4.5.2 Program and Erase Times
Before any program or erase command can be accepted, the flash clock divider register (FCDIV) must be
written to set the internal clock for the flash module to a frequency (fFCLK) between 150 kHz and 200 kHz
(see Section 4.7.1, “Flash Clock Divider Register (FCDIV).”) This register can be written only once, so
normally this write is performed during reset initialization. FCDIV cannot be written if the access error
flag, FACCERR in FSTAT, is set. The user must ensure that FACCERR is not set before writing to the
FCDIV register. One period of the resulting clock (1/fFCLK) is used by the command processor to time
Chapter 4 Memory Map and Register Definition
MC9S08QD4 Series MCU Data Sheet, Rev. 5
40 Freescale Semiconductor
program and erase pulses. An integer number of these timing pulses is used by the command processor to
complete a program or erase command.
Table 4-5 shows program and erase times. The bus clock frequency and FCDIV determine the frequency
of FCLK (fFCLK). The time for one cycle of FCLK is tFCLK =1/f
FCLK. The times are shown as a number
of cycles of FCLK and as an absolute time for the case where tFCLK =5μs. Program and erase times
shown include overhead for the command state machine and enabling and disabling of program and erase
voltages.
4.5.3 Program and Erase Command Execution
The steps for executing any of the commands are listed below. The FCDIV register must be initialized and
any error flags cleared before beginning command execution. The command execution steps are:
1. Write a data value to an address in the flash array. The address and data information from this write
is latched into the flash interface. This write is a required first step in any command sequence. For
erase and blank check commands, the value of the data is not important. For page erase commands,
the address can be any address in the 512-byte page of flash to be erased. For mass erase and blank
check commands, the address can be any address in the flash memory. Whole pages of 512 bytes
are the smallest block of flash that can be erased.
NOTE
• A mass or page erase of the last page in flash will erase the factory
programmed internal reference clock trim value.
• Do not program any byte in the flash more than once after a successful
erase operation. Reprogramming bits in a byte which is already
programmed is not allowed without first erasing the page in which the
byte resides or mass erasing the entire flash memory. Programming
without first erasing may disturb data stored in the flash.
2. Write the command code for the desired command to FCMD. The five valid commands are blank
check (0x05), byte program (0x20), burst program (0x25), page erase (0x40), and mass erase
(0x41). The command code is latched into the command buffer.
3. Write a 1 to the FCBEF bit in FSTAT to clear FCBEF and launch the command (including its
address and data information).
A partial command sequence can be aborted manually by writing a 0 to FCBEF any time after the write to
the memory array and before writing the 1 that clears FCBEF and launches the complete command.
Table 4-5. Program and Erase Times
Parameter Cycles of FCLK Time if FCLK = 200 kHz
Byte program 9 45 μs
Byte program (burst) 4 20 μs1
1Excluding start/end overhead
Page erase 4000 20 ms
Mass erase 20,000 100 ms
Chapter 4 Memory Map and Register Definition
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 41
Aborting a command in this way sets the FACCERR access error flag which must be cleared before
starting a new command.
A strictly monitored procedure must be obeyed or the command will not be accepted. This minimizes the
possibility of any unintended changes to the flash memory contents. The command complete flag (FCCF)
indicates when a command is complete. The command sequence must be completed by clearing FCBEF
to launch the command. Figure 4-2 is a flowchart for executing all of the commands except for burst
programming. The FCDIV register must be initialized following any reset before using any flash
commands.
Figure 4-2. Flash Program and Erase Flowchart
4.5.4 Burst Program Execution
The burst program command is used to program sequential bytes of data in less time than would be
required using the standard program command. This is possible because the high voltage to the flash array
does not need to be disabled between program operations. Ordinarily, when a program or erase command
is issued, an internal charge pump associated with the flash memory must be enabled to supply high
voltage to the array. Upon completion of the command, the charge pump is turned off. When a burst
START
WRITE TO FLASH
TO BUFFER ADDRESS AND DATA
WRITE COMMAND TO FCMD
NO
YES
FPVIO OR
WRITE 1 TO FCBEF
TO LAUNCH COMMAND
AND CLEAR FCBEF (2)
1
0
FCCF ?
ERROR EXIT
DONE
(2) Wait at least four bus cycles before
checking FCBEF or FCCF.
0
FACCERR ?
CLEAR ERROR
FACCERR ?
WRITE TO FCDIV(1) (1) Required only once
after reset.
Chapter 4 Memory Map and Register Definition
MC9S08QD4 Series MCU Data Sheet, Rev. 5
42 Freescale Semiconductor
program command is issued, the charge pump is enabled and then remains enabled after completion of the
burst program operation if these two conditions are met:
• The next burst program command has been queued before the current program operation has
completed.
• The next sequential address selects a byte on the same physical row as the current byte being
programmed. A row of flash memory consists of 64 bytes. A byte within a row is selected by
addresses A5 through A0. A new row begins when addresses A5 through A0 are all 0s.
The first byte of a series of sequential bytes being programmed in burst mode will take the same amount
of time to program as a byte programmed in standard mode. Subsequent bytes will program in the burst
program time provided that the conditions above are met. In the case the next sequential address is the
beginning of a new row, the program time for that byte will be the standard time instead of the burst time.
This is because the high voltage to the array must be disabled and then enabled again. If a new burst
command has not been queued before the current command completes, then the charge pump will be
disabled and high voltage removed from the array.
Chapter 4 Memory Map and Register Definition
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 43
Figure 4-3. Flash Burst Program Flowchart
4.5.5 Access Errors
An access error occurs whenever the command execution protocol is violated.
Any of the following specific actions will cause the access error flag (FACCERR) in FSTAT to be set.
FACCERR must be cleared by writing a 1 to FACCERR in FSTAT before any command can be
processed.
• Writing to a flash address before the internal flash clock frequency has been set by writing to the
FCDIV register
• Writing to a flash address while FCBEF is not set (A new command cannot be started until the
command buffer is empty.)
1
0
FCBEF ?
START
WRITE TO FLASH
TO BUFFER ADDRESS AND DATA
WRITE COMMAND TO FCMD
NO
YES
FPVIO OR
WRITE 1 TO FCBEF
TO LAUNCH COMMAND
AND CLEAR FCBEF (2)
NO
YES
NEW BURST COMMAND ?
1
0
FCCF ?
ERROR EXIT
DONE
(2) Wait at least four bus cycles before
checking FCBEF or FCCF.
1
0
FACCERR ?
CLEAR ERROR
FACCERR ?
WRITE TO FCDIV(1) (1) Required only once
after reset.
Chapter 4 Memory Map and Register Definition
MC9S08QD4 Series MCU Data Sheet, Rev. 5
44 Freescale Semiconductor
• Writing a second time to a flash address before launching the previous command (There is only
one write to flash for every command.)
• Writing a second time to FCMD before launching the previous command (There is only one write
to FCMD for every command.)
• Writing to any flash control register other than FCMD after writing to a flash address
• Writing any command code other than the five allowed codes (0x05, 0x20, 0x25, 0x40, or 0x41)
to FCMD
• Writing any flash control register other than to write to FSTAT (to clear FCBEF and launch the
command) after writing the command to FCMD.
• The MCU enters stop mode while a program or erase command is in progress (The command is
aborted.)
• Writing the byte program, burst program, or page erase command code (0x20, 0x25, or 0x40) with
a background debug command while the MCU is secured (The background debug controller can
do blank check and mass erase commands only when the MCU is secure.)
• Writing 0 to FCBEF to cancel a partial command
4.5.6 Flash Block Protection
The block protection feature prevents the protected region of flash from program or erase changes. Block
protection is controlled through the flash protection register (FPROT). When enabled, block protection
begins at any 512 byte boundary below the last address of flash, 0xFFFF. (see Section 4.7.4, “Flash
Protection Register (FPROT and NVPROT).”)
After exit from reset, FPROT is loaded with the contents of the NVPROT location which is in the
nonvolatile register block of the flash memory. FPROT cannot be changed directly from application
software so a runaway program cannot alter the block protection settings. Because NVPROT is within the
last 512 bytes of flash, if any amount of memory is protected, NVPROT is itself protected and cannot be
altered (intentionally or unintentionally) by the application software. FPROT can be written through
background debug commands, which allows a way to erase and reprogram a protected flash memory.
The block protection mechanism is illustrated in Figure 4-4. The FPS bits are used as the upper bits of the
last address of unprotected memory. This address is formed by concatenating FPS7:FPS1 with logic 1 bits
as shown. For example, in order to protect the last 8192 bytes of memory (addresses 0xE000 through
0xFFFF), the FPS bits must be set to 1101 111, which results in the value 0xDFFF as the last address of
unprotected memory. In addition to programming the FPS bits to the appropriate value, FPDIS (bit 0 of
NVPROT) must be programmed to logic 0 to enable block protection. Therefore the value 0xDE must be
programmed into NVPROT to protect addresses 0xE000 through 0xFFFF.
Figure 4-4. Block Protection Mechanism
FPS7 FPS6 FPS5 FPS4 FPS3 FPS2 FPS1
A15 A14 A13 A12 A11 A10 A9 A8
1
A7 A6 A5 A4 A3 A2 A1 A0
11111111
Chapter 4 Memory Map and Register Definition
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 45
One use for block protection is to block protect an area of flash memory for a bootloader program. This
bootloader program then can be used to erase the rest of the flash memory and reprogram it. Because the
bootloader is protected, it remains intact even if MCU power is lost in the middle of an erase and
reprogram operation.
4.5.7 Vector Redirection
Whenever any block protection is enabled, the reset and interrupt vectors will be protected. Vector
redirection allows users to modify interrupt vector information without unprotecting bootloader and reset
vector space. Vector redirection is enabled by programming the FNORED bit in the NVOPT register
located at address 0xFFBF to 0. For redirection to occur, at least some portion but not all of the flash
memory must be block protected by programming the NVPROT register located at address 0xFFBD. All
of the interrupt vectors (memory locations 0xFFC0–0xFFFD) are redirected, though the reset vector
(0xFFFE:FFFF) is not.
For example, if 512 bytes of flash are protected, the protected address region is from 0xFE00 through
0xFFFF. The interrupt vectors (0xFFC0–0xFFFD) are redirected to the locations 0xFDC0–0xFDFD. For
example, vector redirection is enabled and an interrupt occurs, the values in the locations 0xFDE0:FDE1
are used for the vector instead of the values in the locations 0xFFE0:FFE1. This allows the user to
reprogram the unprotected portion of the flash with new program code including new interrupt vector
values while leaving the protected area, which includes the default vector locations, unchanged.
4.6 Security
The MC9S08QD4 series includes circuitry to prevent unauthorized access to the contents of flash and
RAM memory. When security is engaged, flash and RAM are considered secure resources. Direct-page
registers, high-page registers, and the background debug controller are considered unsecured resources.
Programs executing within secure memory have normal access to any MCU memory locations and
resources. Attempts to access a secure memory location with a program executing from an unsecured
memory space or through the background debug interface are blocked (writes are ignored and reads return
all 0s).
Security is engaged or disengaged based on the state of two register bits (SEC01:SEC00) in the FOPT
register. During reset, the contents of the nonvolatile location NVOPT are copied from flash into the
working FOPT register in high-page register space. A user engages security by programming the NVOPT
location, which can be performed at the same time the flash memory is programmed. The 1:0 state
disengages security and the other three combinations engage security. Notice the erased state (1:1) makes
the MCU secure. During development, whenever the flash is erased, it is good practice to immediately
program the SEC00 bit to 0 in NVOPT so SEC01:SEC00 = 1:0. This would allow the MCU to remain
unsecured after a subsequent reset.
The on-chip debug module cannot be enabled while the MCU is secure. The separate background debug
controller can be used for background memory access commands, but the MCU cannot enter active
background mode except by holding BKGD/MS low at the rising edge of reset.
A user can choose to allow or disallow a security unlocking mechanism through an 8-byte backdoor
security key. If the nonvolatile KEYEN bit in NVOPT/FOPT is 0, the backdoor key is disabled and there
Chapter 4 Memory Map and Register Definition
MC9S08QD4 Series MCU Data Sheet, Rev. 5
46 Freescale Semiconductor
is no way to disengage security without completely erasing all flash locations. If KEYEN is 1, a secure
user program can temporarily disengage security by:
1. Writing 1 to KEYACC in the FCNFG register. This makes the flash module interpret writes to the
backdoor comparison key locations (NVBACKKEY through NVBACKKEY+7) as values to be
compared against the key rather than as the first step in a flash program or erase command.
2. Writing the user-entered key values to the NVBACKKEY through NVBACKKEY+7 locations.
These writes must be performed in order starting with the value for NVBACKKEY and ending
with NVBACKKEY+7. STHX must not be used for these writes because these writes cannot be
performed on adjacent bus cycles. User software normally would get the key codes from outside
the MCU system through a communication interface such as a serial I/O.
3. Writing 0 to KEYACC in the FCNFG register. If the 8-byte key that was written matches the key
stored in the flash locations, SEC01:SEC00 are automatically changed to 1:0 and security will be
disengaged until the next reset.
The security key can be written only from secure memory (either RAM or flash), so it cannot be entered
through background commands without the cooperation of a secure user program.
The backdoor comparison key (NVBACKKEY through NVBACKKEY+7) is located in flash memory
locations in the nonvolatile register space so users can program these locations exactly as they would
program any other flash memory location. The nonvolatile registers are in the same 512-byte block of flash
as the reset and interrupt vectors, so block protecting that space also block protects the backdoor
comparison key. Block protects cannot be changed from user application programs, so if the vector space
is block protected, the backdoor security key mechanism cannot permanently change the block protect,
security settings, or the backdoor key.
Security can always be disengaged through the background debug interface by taking these steps:
1. Disable any block protections by writing FPROT. FPROT can be written only with background
debug commands, not from application software.
2. Mass erase flash if necessary.
3. Blank check flash. Provided flash is completely erased, security is disengaged until the next reset.
To avoid returning to secure mode after the next reset, program NVOPT so SEC01:SEC00 = 1:0.
4.7 Flash Registers and Control Bits
The flash module has nine 8-bit registers in the high-page register space, two locations (NVOPT,
NVPROT) in the nonvolatile register space in flash memory are copied into corresponding high-page
control registers (FOPT, FPROT) at reset. There is also an 8-byte comparison key in flash memory. Refer
to Table 4-3 and Table 4-4 for the absolute address assignments for all flash registers. This section refers
to registers and control bits only by their names. A Freescale Semiconductor-provided equate or header
file normally is used to translate these names into the appropriate absolute addresses.
4.7.1 Flash Clock Divider Register (FCDIV)
Before any erase or programming operations are possible, write to this register to set the frequency of the
clock for the nonvolatile memory system within acceptable limits.
Chapter 4 Memory Map and Register Definition
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 47
if PRDIV8 = 0 – fFCLK = fBus ÷ (DIV + 1) Eqn. 4-1
if PRDIV8 = 1 – fFCLK = fBus ÷ (8 × (DIV + 1)) Eqn. 4-2
Table 4-7 shows the appropriate values for PRDIV8 and DIV for selected bus frequencies.
76543210
RDIVLD
PRDIV8 DIV
W
Reset00000000
= Unimplemented or Reserved
Figure 4-5. Flash Clock Divider Register (FCDIV)
Table 4-6. FCDIV Register Field Descriptions
Field Description
7
DIVLD
Divisor Loaded Status Flag — When set, this read-only status flag indicates that the FCDIV register has been
written since reset. Reset clears this bit and the first write to this register causes this bit to become set regardless
of the data written.
0 FCDIV has not been written since reset; erase and program operations disabled for flash.
1 FCDIV has been written since reset; erase and program operations enabled for flash.
6
PRDIV8
Prescale (Divide) Flash Clock by 8
0 Clock input to the flash clock divider is the bus rate clock.
1 Clock input to the flash clock divider is the bus rate clock divided by 8.
5:0
DIV
Divisor for Flash Clock Divider — The flash clock divider divides the bus rate clock (or the bus rate clock
divided by 8 if PRDIV8 = 1) by the value in the 6-bit DIV field plus one. The resulting frequency of the internal
flash clock must fall within the range of 200 kHz to 150 kHz for proper flash operations. Program/Erase timing
pulses are one cycle of this internal flash clock which corresponds to a range of 5 μs to 6.7 μs. The automated
programming logic uses an integer number of these pulses to complete an erase or program operation. See
Equation 4-1 and Equation 4-2.
Table 4-7. Flash Clock Divider Settings
fBus
PRDIV8
(Binary)
DIV
(Decimal) fFCLK
Program/Erase Timing Pulse
(5 μs Min, 6.7 μs Max)
8 MHz 0 39 200 kHz 5 μs
4 MHz 0 19 200 kHz 5 μs
2 MHz 0 9 200 kHz 5 μs
1 MHz 0 4 200 kHz 5 μs
200 kHz 0 0 200 kHz 5 μs
150 kHz 0 0 150 kHz 6.7 μs
Chapter 4 Memory Map and Register Definition
MC9S08QD4 Series MCU Data Sheet, Rev. 5
48 Freescale Semiconductor
4.7.2 Flash Options Register (FOPT and NVOPT)
During reset, the contents of the nonvolatile location NVOPT are copied from flash into FOPT. To change
the value in this register, erase and reprogram the NVOPT location in flash memory as usual and then issue
a new MCU reset.
76543210
R KEYEN FNORED 0 0 0 0 SEC01 SEC00
W
Reset This register is loaded from nonvolatile location NVOPT during reset.
= Unimplemented or Reserved
Figure 4-6. Flash Options Register (FOPT)
Table 4-8. FOPT Register Field Descriptions
Field Description
7
KEYEN
Backdoor Key Mechanism Enable — When this bit is 0, the backdoor key mechanism cannot be used to
disengage security. The backdoor key mechanism is accessible only from user (secured) firmware. BDM
commands cannot be used to write key comparison values that would unlock the backdoor key. For more detailed
information about the backdoor key mechanism, refer to Section 4.6, “Security.”
0 No backdoor key access allowed.
1 If user firmware writes an 8-byte value that matches the nonvolatile backdoor key (NVBACKKEY through
NVBACKKEY+7 in that order), security is temporarily disengaged until the next MCU reset.
6
FNORED
Vector Redirection Disable — When this bit is 1, then vector redirection is disabled.
0 Vector redirection enabled.
1 Vector redirection disabled.
1:0
SEC0[1:0]
Security State Code — This 2-bit field determines the security state of the MCU as shown in Tabl e 4 - 9. When
the MCU is secure, the contents of RAM and flash memory cannot be accessed by instructions from any
unsecured source including the background debug interface. SEC01:SEC00 changes to 1:0 after successful
backdoor key entry or a successful blank check of flash.
For more detailed information about security, refer to Section 4.6, “Security.”
Table 4-9. Security States1
1SEC01:SEC00 changes to 1:0 after successful backdoor
key entry or a successful blank check of flash.
SEC01:SEC00 Description
0:0 secure
0:1 secure
1:0 unsecured
1:1 secure
Chapter 4 Memory Map and Register Definition
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 49
4.7.3 Flash Configuration Register (FCNFG)
4.7.4 Flash Protection Register (FPROT and NVPROT)
During reset, the contents of the nonvolatile location NVPROT is copied from flash into FPROT. This
register can be read at any time, but user program writes have no meaning or effect.
76543210
R0 0
KEYACC
00000
W
Reset00000000
= Unimplemented or Reserved
Figure 4-7. Flash Configuration Register (FCNFG)
Table 4-10. FCNFG Register Field Descriptions
Field Description
5
KEYACC
Enable Writing of Access Key — This bit enables writing of the backdoor comparison key. For more detailed
information about the backdoor key mechanism, refer to Section 4.6, “Security.”
0 Writes to 0xFFB0–0xFFB7 are interpreted as the start of a flash programming or erase command.
1 Writes to NVBACKKEY (0xFFB0–0xFFB7) are interpreted as comparison key writes.
76543210
R
FPS(1) FPDIS(1)
W
Reset This register is loaded from nonvolatile location NVPROT during reset.
1Background commands can be used to change the contents of these bits in FPROT.
Figure 4-8. Flash Protection Register (FPROT)
Table 4-11. FPROT Register Field Descriptions
Field Description
7:1
FPS
Flash Protect Select Bits — When FPDIS = 0, this 7-bit field determines the ending address of unprotected
flash locations at the high address end of the flash. Protected flash locations cannot be erased or programmed.
0
FPDIS
Flash Protection Disable
0 Flash block specified by FPS7:FPS1 is block protected (program and erase not allowed).
1 No flash block is protected.
Chapter 4 Memory Map and Register Definition
MC9S08QD4 Series MCU Data Sheet, Rev. 5
50 Freescale Semiconductor
4.7.5 Flash Status Register (FSTAT)
76543210
R
FCBEF
FCCF
FPVIOL FACCERR
0FBLANK0 0
W
Reset11000000
= Unimplemented or Reserved
Figure 4-9. Flash Status Register (FSTAT)
Table 4-12. FSTAT Register Field Descriptions
Field Description
7
FCBEF
Flash Command Buffer Empty Flag — The FCBEF bit is used to launch commands. It also indicates that the
command buffer is empty so that a new command sequence can be executed when performing burst
programming. The FCBEF bit is cleared by writing a 1 to it or when a burst program command is transferred to
the array for programming. Only burst program commands can be buffered.
0 Command buffer is full (not ready for additional commands).
1 A new burst program command can be written to the command buffer.
6
FCCF
Flash Command Complete Flag — FCCF is set automatically when the command buffer is empty and no
command is being processed. FCCF is cleared automatically when a new command is started (by writing 1 to
FCBEF to register a command). Writing to FCCF has no meaning or effect.
0 Command in progress
1 All commands complete
5
FPVIOL
Protection Violation Flag — FPVIOL is set automatically when FCBEF is cleared to register a command that
attempts to erase or program a location in a protected block (the erroneous command is ignored). FPVIOL is
cleared by writing a 1 to FPVIOL.
0 No protection violation.
1 An attempt was made to erase or program a protected location.
4
FACCERR
Access Error Flag — FACCERR is set automatically when the proper command sequence is not obeyed exactly
(the erroneous command is ignored), if a program or erase operation is attempted before the FCDIV register has
been initialized, or if the MCU enters stop while a command was in progress. For a more detailed discussion of
the exact actions that are considered access errors, see Section 4.5.5, “Access Errors.” FACCERR is cleared by
writing a 1 to FACCERR. Writing a 0 to FACCERR has no meaning or effect.
0 No access error.
1 An access error has occurred.
2
FBLANK
Flash Verified as All Blank (erased) Flag — FBLANK is set automatically at the conclusion of a blank check
command if the entire flash array was verified to be erased. FBLANK is cleared by clearing FCBEF to write a new
valid command. Writing to FBLANK has no meaning or effect.
0 After a blank check command is completed and FCCF = 1, FBLANK = 0 indicates the flash array is not
completely erased.
1 After a blank check command is completed and FCCF = 1, FBLANK = 1 indicates the flash array is completely
erased (all 0xFF).
Chapter 4 Memory Map and Register Definition
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 51
4.7.6 Flash Command Register (FCMD)
Only five command codes are recognized in normal user modes as shown in Table 4-13. Refer to
Section 4.5.3, “Program and Erase Command Execution,” for a detailed discussion of flash programming
and erase operations.
All other command codes are illegal and generate an access error.
It is not necessary to perform a blank check command after a mass erase operation. Only blank check is
required as part of the security unlocking mechanism.
76543210
R00000000
WFCMD
Reset00000000
= Unimplemented or Reserved
Figure 4-10. Flash Command Register (FCMD)
Table 4-13. Flash Commands
Command FCMD Equate File Label
Blank check 0x05 mBlank
Byte program 0x20 mByteProg
Byte program — burst mode 0x25 mBurstProg
Page erase (512 bytes/page) 0x40 mPageErase
Mass erase (all flash) 0x41 mMassErase
Chapter 4 Memory Map and Register Definition
MC9S08QD4 Series MCU Data Sheet, Rev. 5
52 Freescale Semiconductor
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 53
Chapter 5
Resets, Interrupts, and General System Control
5.1 Introduction
This chapter discusses basic reset and interrupt mechanisms and the various sources of reset and interrupts
in the MC9S08QD4 series. Some interrupt sources from peripheral modules are discussed in greater detail
within other sections of this data sheet. This section gathers basic information about all reset and interrupt
sources in one place for easy reference. A few reset and interrupt sources, including the computer
operating properly (COP) watchdog and real-time interrupt (RTI), are not part of on-chip peripheral
systems with their own chapters but are part of the system control logic.
5.2 Features
Reset and interrupt features include:
• Multiple sources of reset for flexible system configuration and reliable operation
• Reset status register (SRS) to indicate source of most recent reset
• Separate interrupt vectors for each module (reduces polling overhead) (see Table 5-2)
5.3 MCU Reset
Resetting the MCU provides a way to start processing from a known set of initial conditions. During reset,
most control and status registers are forced to initial values and the program counter is loaded from the
reset vector (0xFFFE:0xFFFF). On-chip peripheral modules are disabled and I/O pins are initially
configured as general-purpose high-impedance inputs with pullup devices disabled. The I bit in the
condition code register (CCR) is set to block maskable interrupts so the user program has a chance to
initialize the stack pointer (SP) and system control settings. SP is forced to 0x00FF at reset.
The MC9S08QD4 series has the following sources for reset:
• External pin reset (PIN) - enabled using RSTPE in SOPT1
• Power-on reset (POR)
• Low-voltage detect (LVD)
• Computer operating properly (COP) timer
• Illegal opcode detect (ILOP)
• Illegal address detect (ILAD)
• Background debug forced reset
Each of these sources, with the exception of the background debug forced reset, has an associated bit in
the system reset status register.
Chapter 5 Resets, Interrupts, and General System Control
MC9S08QD4 Series MCU Data Sheet, Rev. 5
54 Freescale Semiconductor
5.4 Computer Operating Properly (COP) Watchdog
The COP watchdog is intended to force a system reset when the application software fails to execute as
expected. To prevent a system reset from the COP timer (when it is enabled), application software must
reset the COP counter periodically. If the application program gets lost and fails to reset the COP counter
before it times out, a system reset is generated to force the system back to a known starting point.
After any reset, the COPE becomes set in SOPT1 enabling the COP watchdog (see Section 5.8.5, “System
Options Register 2 (SOPT2),” for additional information). If the COP watchdog is not used in an
application, it can be disabled by clearing COPE. The COP counter is reset by writing any value to the
address of SRS. This write does not affect the data in the read-only SRS. Instead, the act of writing to this
address is decoded and sends a reset signal to the COP counter.
The COPCLKS bit in SOPT2 (see Section 5.8.5, “System Options Register 2 (SOPT2),” for additional
information) selects the clock source used for the COP timer. The clock source options are either the bus
clock or an internal 32 kHz clock source. With each clock source, there is an associated short and long
time-out controlled by COPT in SOPT1. Table 5-1 summaries the control functions of the COPCLKS and
COPT bits. The COP watchdog defaults to operation from the 32 kHz clock source and the associated long
time-out (28 cycles).
Even if the application will use the reset default settings of COPE, COPCLKS and COPT, the user must
write to the write-once SOPT1 and SOPT2 registers during reset initialization to lock in the settings. That
way, they cannot be changed accidentally if the application program gets lost. The initial writes to SOPT1
and SOPT2 will reset the COP counter.
The write to SRS that services (clears) the COP counter must not be placed in an interrupt service routine
(ISR) because the ISR could continue to be executed periodically even if the main application program
fails.
In Background debug mode, the COP counter will not increment.
When the bus clock source is selected, the COP counter does not increment while the system is in stop
mode. The COP counter resumes once the MCU exits stop mode.
When the 32 kHz clock source is selected, the COP counter is re-initialized to zero upon entry to stop
mode. The COP counter begins from zero once the MCU exits stop mode.
Table 5-1. COP Configuration Options
Control Bits
Clock Source COP Overflow Count
COPCLKS COPT
00
~32 kHz 210 cycles (32 ms)1
1Values are shown in this column based on tRTI =1ms. See t
RTI in the Section A.8.1,
“Control Timing,” for the tolerance of this value.
01
~32 kHz 213 cycles (256 ms)1
10
Bus 213 cycles
11
Bus 218 cycles
Chapter 5 Resets, Interrupts, and General System Control
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 55
5.5 Interrupts
Interrupts provide a way to save the current CPU status and registers, execute an interrupt service routine
(ISR), and then restore the CPU status so processing resumes where it was before the interrupt. Other than
the software interrupt (SWI), which is a program instruction, interrupts are caused by hardware events
such as an edge on the IRQ pin or a timer-overflow event. The debug module can also generate an SWI
under certain circumstances.
If an event occurs in an enabled interrupt source, an associated read-only status flag will become set. The
CPU will not respond until and unless the local interrupt enable is a 1 to enable the interrupt. The I bit in
the CCR is 0 to allow interrupts. The global interrupt mask (I bit) in the CCR is initially set after reset
which masks (prevents) all maskable interrupt sources. The user program initializes the stack pointer and
performs other system setup before clearing the I bit to allow the CPU to respond to interrupts.
When the CPU receives a qualified interrupt request, it completes the current instruction before responding
to the interrupt. The interrupt sequence obeys the same cycle-by-cycle sequence as the SWI instruction
and consists of:
• Saving the CPU registers on the stack
• Setting the I bit in the CCR to mask further interrupts
• Fetching the interrupt vector for the highest-priority interrupt that is currently pending
• Filling the instruction queue with the first three bytes of program information starting from the
address fetched from the interrupt vector locations
While the CPU is responding to the interrupt, the I bit is automatically set to avoid the possibility of
another interrupt interrupting the ISR itself (this is called nesting of interrupts). Normally, the I bit is
restored to 0 when the CCR is restored from the value stacked on entry to the ISR. In rare cases, the I bit
can be cleared inside an ISR (after clearing the status flag that generated the interrupt) so that other
interrupts can be serviced without waiting for the first service routine to finish. This practice is not
recommended for anyone other than the most experienced programmers because it can lead to subtle
program errors that are difficult to debug.
The interrupt service routine ends with a return-from-interrupt (RTI) instruction which restores the CCR,
A, X, and PC registers to their pre-interrupt values by reading the previously saved information off the
stack.
NOTE
For compatibility with M68HC08 devices, the H register is not
automatically saved and restored. It is good programming practice to push
H onto the stack at the start of the interrupt service routine (ISR) and restore
it immediately before the RTI that is used to return from the ISR.
When two or more interrupts are pending when the I bit is cleared, the highest priority source is serviced
first (see Table 5-2).
Chapter 5 Resets, Interrupts, and General System Control
MC9S08QD4 Series MCU Data Sheet, Rev. 5
56 Freescale Semiconductor
5.5.1 Interrupt Stack Frame
Figure 5-1 shows the contents and organization of a stack frame. Before the interrupt, the stack pointer
(SP) points at the next available byte location on the stack. The current values of CPU registers are stored
on the stack starting with the low-order byte of the program counter (PCL) and ending with the CCR. After
stacking, the SP points at the next available location on the stack which is the address that is one less than
the address where the CCR was saved. The PC value that is stacked is the address of the instruction in the
main program that would have executed next if the interrupt had not occurred.
Figure 5-1. Interrupt Stack Frame
When an RTI instruction is executed, these values are recovered from the stack in reverse order. As part
of the RTI sequence, the CPU fills the instruction pipeline by reading three bytes of program information,
starting from the PC address recovered from the stack.
The status flag causing the interrupt must be acknowledged (cleared) before returning from the ISR.
Typically, the flag is cleared at the beginning of the ISR so that if another interrupt is generated by this
same source, it will be registered so it can be serviced after completion of the current ISR.
5.5.2 External Interrupt Request (IRQ) Pin
External interrupts are managed by the IRQ status and control register, IRQSC. When the IRQ function is
enabled, synchronous logic monitors the pin for edge-only or edge-and-level events. When the MCU is in
stop mode and system clocks are shut down, a separate asynchronous path is used so the IRQ (if enabled)
can wake the MCU.
5.5.2.1 Pin Configuration Options
The IRQ pin enable (IRQPE) control bit in IRQSC must be 1 in order for the IRQ pin to act as the interrupt
request (IRQ) input. As an IRQ input, the user can choose the polarity of edges or levels detected
(IRQEDG), whether the pin detects edges-only or edges and levels (IRQMOD), and whether an event
causes an interrupt or only sets the IRQF flag which can be polled by software.
CONDITION CODE REGISTER
ACCUMULATOR
INDEX REGISTER (LOW BYTE X)
PROGRAM COUNTER HIGH
* High byte (H) of index register is not automatically stacked.
*
PROGRAM COUNTER LOW
70
UNSTACKING
ORDER
STACKING
ORDER
5
4
3
2
1
1
2
3
4
5
TOWARD LOWER ADDRESSES
TOWARD HIGHER ADDRESSES
SP BEFORE
SP AFTER
INTERRUPT STACKING
THE INTERRUPT
Chapter 5 Resets, Interrupts, and General System Control
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 57
The IRQ pin when enabled defaults to use an internal pull device (IRQPDD = 0), the device is a pullup or
pulldown depending on the polarity to detect. If the user desires to use an external pullup or pulldown, the
IRQPDD can be written to a 1 to turn off the internal device.
BIH and BIL instructions may be used to detect the level on the IRQ pin when the pin is configured to act
as the IRQ input.
NOTE
This pin does not contain a clamp diode to VDD and must not be driven
above VDD.
The voltage measured on the internally pulled up IRQ pin may be as low as
VDD – 0.7 V. The internal gates connected to this pin are pulled all the way
to VDD.
5.5.2.2 Edge and Level Sensitivity
The IRQMOD control bit reconfigures the detection logic so it detects edge events and pin levels. In this
edge detection mode, the IRQF status flag becomes set when an edge is detected (when the IRQ pin
changes from the deasserted to the asserted level), but the flag is continuously set (and cannot be cleared)
as long as the IRQ pin remains at the asserted level.
5.5.3 Interrupt Vectors, Sources, and Local Masks
Table 5-2 provides a summary of all interrupt sources. Higher-priority sources are located toward the
bottom of the table. The high-order byte of the address for the interrupt service routine is located at the
first address in the vector address column, and the low-order byte of the address for the interrupt service
routine is located at the next higher address.
When an interrupt condition occurs, an associated flag bit becomes set. If the associated local interrupt
enable is 1, an interrupt request is sent to the CPU. Within the CPU, if the global interrupt mask (I bit in
the CCR) is 0, the CPU will finish the current instruction; stack the PCL, PCH, X, A, and CCR CPU
registers; set the I bit; and then fetch the interrupt vector for the highest priority pending interrupt.
Processing then continues in the interrupt service routine.
Chapter 5 Resets, Interrupts, and General System Control
MC9S08QD4 Series MCU Data Sheet, Rev. 5
58 Freescale Semiconductor
5.6 Low-Voltage Detect (LVD) System
The MC9S08QD4 series includes a system to protect against low voltage conditions in order to protect
memory contents and control MCU system states during supply voltage variations. The system is
comprised of a power-on reset (POR) circuit and an LVD circuit with a user selectable trip voltage, either
high (VLVDH) or low (VLVDL). The LVD circuit is enabled when LVDE in SPMSC1 is high and the trip
voltage is selected by LVDV in SPMSC2. The LVD is disabled upon entering any of the stop modes unless
LVDSE is set in SPMSC1. If LVDSE and LVDE are both set, then the MCU cannot enter stop1 or stop2,
and the current consumption in stop3 with the LVD enabled will be greater.
Table 5-2. Vector Summary
Vector
Priority
Vector
Number
Address
(High:Low) Vector Name Module Source Enable Description
Lower
Higher
31
through
24
0xFFC0:FFC1
through
0xFFCE:FFCF
Unused Vector Space
(available for user program)
23 0xFFD0:FFD1 Vrti System
control RTIF RTIE Real-time interrupt
22 0xFFD2:FFD3 — — — — —
21 0xFFD4:FFD5 — — — — —
20 0xFFD6:FFD7 — — — — —
19 0xFFD8:FFD9 Vadc1 ADC1 COCO AIEN ADC1
18 0xFFDA:FFDB Vkeyboard1 KBI1 KBF KBIE Keyboard pins
17 0xFFDC:FFDD — — — — —
16 0xFFDE:FFDF — — — — —
15 0xFFE0:FFE1 — — — — —
14 0xFFE2:FFE3 — — — — —
13 0xFFE4:FFE5 — — — — —
12 0xFFE6:FFE7 — — — — —
11 0xFFE8:FFE9 — — — — —
10 0xFFEA:FFEB Vtpm2ovf TPM2 TOF TOIE TPM2 overflow
9 0xFFEC:FFED — — — — —
8 0xFFEE:FFEF Vtpm2ch0 TPM2 CH0F CH0IE TPM2 channel 0
7 0xFFF0:FFF1 Vtpm1ovf TPM1 TOF TOIE TPM1 overflow
6 0xFFF2:FFF3 Vtpm1ch1 TPM1 CH1F CH1IE TPM1 channel 1
5 0xFFF4:FFF5 Vtpm1ch0 TPM1 CH0F CH0IE TPM1 channel 0
4 0xFFF6:FFF7 — — — — —
3 0xFFF8:FFF9 Virq IRQ IRRQF IRQIE IRQ pin
2 0xFFFA:FFFB Vlvd System
control LVDF LVDIE Low voltage detect
1 0xFFFC:FFFD Vswi CPU SWI
Instruction — Software interrupt
0 0xFFFE:FFFF Vreset System
control
COP
LVD
RESET pin
Illegal opcode
Illegal address
POR
COPE
LVDRE
RSTPE
—
—
—
Watchdog timer
Low-voltage detect
External pin
Illegal opcode
Illegal address
power-on-reset
Chapter 5 Resets, Interrupts, and General System Control
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 59
5.6.1 Power-On Reset Operation
When power is initially applied to the MCU, or when the supply voltage drops below the VPOR level, the
POR circuit will cause a reset condition. As the supply voltage rises, the LVD circuit will hold the MCU
in reset until the supply has risen above the VLVDL level. Both the POR bit and the LVD bit in SRS are set
following a POR.
5.6.2 LVD Reset Operation
The LVD can be configured to generate a reset upon detection of a low voltage condition by setting
LVDRE to 1. After an LVD reset has occurred, the LVD system will hold the MCU in reset until the supply
voltage has risen above the level determined by LVDV. The LVD bit in the SRS register is set following
either an LVD reset or POR.
5.6.3 LVD Interrupt Operation
When a low voltage condition is detected and the LVD circuit is configured using SPMSC1 for interrupt
operation (LVDE set, LVDIE set, and LVDRE clear), then LVDF in SPMSC1 will be set and an LVD
interrupt request will occur.
5.6.4 Low-Voltage Warning (LVW)
The LVD system has a low voltage warning flag to indicate to the user that the supply voltage is
approaching, but is above, the LVD voltage. The LVW does not have an interrupt associated with it. There
are two user selectable trip voltages for the LVW, one high (VLVWH) and one low (VLVWL). The trip
voltage is selected by LVWV in SPMSC2.
5.7 Real-Time Interrupt (RTI)
The real-time interrupt function can be used to generate periodic interrupts. The RTI can accept two
sources of clocks, the 1 kHz internal clock or an 32 kHz ICS clock if available. The RTICLKS bit in
SRTISC is used to select the RTI clock source.
Both clock source can be used when the MCU is in run, wait or stop3 mode. When using the 32 kHz ICS
clock in stop3, it must be enabled in stop (EREFSTEN = 1) and configured for low frequency operation
(RANGE = 0). Only the internal 1 kHz clock source can be selected to wake the MCU from stop1 or stop2
modes.
The SRTISC register includes a read-only status flag, a write-only acknowledge bit, and a 3-bit control
value (RTIS) used to select one of seven wakeup periods. The RTI has a local interrupt enable, RTIE, to
allow masking of the real-time interrupt. The RTI can be disabled by writing each bit of RTIS to zeroes,
and no interrupts will be generated. See Section 5.8.7, “System Real-Time Interrupt Status and Control
Register (SRTISC),” for detailed information about this register.
Chapter 5 Resets, Interrupts, and General System Control
MC9S08QD4 Series MCU Data Sheet, Rev. 5
60 Freescale Semiconductor
5.8 Reset, Interrupt, and System Control Registers and Control Bits
One 8-bit register in the direct page register space and eight 8-bit registers in the high-page register space
are related to reset and interrupt systems.
Refer to the direct-page register summary in Chapter 3, “Modes of Operation,” for the absolute address
assignments for all registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
Some control bits in the SOPT1, SOPT2 and SPMSC2 registers are related to modes of operation.
Although brief descriptions of these bits are provided here, the related functions are discussed in greater
detail in Chapter 3, “Modes of Operation.”
5.8.1 Interrupt Pin Request Status and Control Register (IRQSC)
This direct page register includes status and control bits which are used to configure the IRQ function,
report status, and acknowledge IRQ events.
76543210
R0
IRQPDD IRQEDG IRQPE
IRQF 0
IRQIE IRQMOD
W IRQACK
Reset00000000
= Unimplemented or Reserved
Figure 5-2. Interrupt Request Status and Control Register (IRQSC)
Table 5-3. IRQSC Register Field Descriptions
Field Description
6
IRQPDD
Interrupt Request (IRQ) Pull Device Disable— This read/write control bit is used to disable the internal
pullup/pulldown device when the IRQ pin is enabled (IRQPE = 1) allowing for an external device to be used.
0 IRQ pull device enabled if IRQPE = 1.
1 IRQ pull device disabled if IRQPE = 1.
5
IRQEDG
Interrupt Request (IRQ) Edge Select — This read/write control bit is used to select the polarity of edges or
levels on the IRQ pin that cause IRQF to be set. The IRQMOD control bit determines whether the IRQ pin is
sensitive to both edges and levels or only edges. When the IRQ pin is enabled as the IRQ input and is configured
to detect rising edges. When IRQEDG = 1 and the internal pull device is enabled, the pullup device is
reconfigured as an optional pulldown device.
0 IRQ is falling edge or falling edge/low-level sensitive.
1 IRQ is rising edge or rising edge/high-level sensitive.
4
IRQPE
IRQ Pin Enable — This read/write control bit enables the IRQ pin function. When this bit is set the IRQ pin can
be used as an interrupt request.
0 IRQ pin function is disabled.
1 IRQ pin function is enabled.
3
IRQF
IRQ Flag — This read-only status bit indicates when an interrupt request event has occurred.
0 No IRQ request.
1 IRQ event detected.
Chapter 5 Resets, Interrupts, and General System Control
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 61
5.8.2 System Reset Status Register (SRS)
This high-page register includes read-only status flags to indicate the source of the most recent reset. When
a debug host forces reset by writing 1 to BDFR in the SBDFR register, all of the status bits in SRS will be
cleared. Writing any value to this register address clears the COP watchdog timer without affecting the
contents of this register. The reset state of these bits depends on what caused the MCU to reset.
2
IRQACK
IRQ Acknowledge — This write-only bit is used to acknowledge interrupt request events (write 1 to clear IRQF).
Writing 0 has no meaning or effect. Reads always return 0. If edge-and-level detection is selected (IRQMOD = 1),
IRQF cannot be cleared while the IRQ pin remains at its asserted level.
1
IRQIE
IRQ Interrupt Enable — This read/write control bit determines whether IRQ events generate an interrupt
request.
0 Interrupt request when IRQF set is disabled (use polling).
1 Interrupt requested whenever IRQF = 1.
0
IRQMOD
IRQ Detection Mode — This read/write control bit selects either edge-only detection or edge-and-level
detection. The IRQEDG control bit determines the polarity of edges and levels that are detected as interrupt
request events. See Section 5.5.2.2, “Edge and Level Sensitivity,” for more details.
0 IRQ event on falling edges or rising edges only.
1 IRQ event on falling edges and low levels or on rising edges and high levels.
76543210
R POR PIN COP ILOP ILAD 0 LVD 0
W Writing any value to SRS address clears COP watchdog timer.
POR:10000010
LVR:00000010
Any
other
reset:
0(1)(1)(1)(1) 000
1Any of these reset sources that are active at the time of reset entry will cause the corresponding bit(s) to be set; bits
corresponding to sources that are not active at the time of reset entry will be cleared.
Figure 5-3. System Reset Status (SRS)
Table 5-4. SRS Register Field Descriptions
Field Description
7
POR
Power-On Reset — Reset was caused by the power-on detection logic. Because the internal supply voltage was
ramping up at the time, the low-voltage reset (LVR) status bit is also set to indicate that the reset occurred while
the internal supply was below the LVR threshold.
0 Reset not caused by POR.
1 POR caused reset.
6
PIN
External Reset Pin — Reset was caused by an active-low level on the external reset pin.
0 Reset not caused by external reset pin.
1 Reset came from external reset pin.
Table 5-3. IRQSC Register Field Descriptions (continued)
Field Description
Chapter 5 Resets, Interrupts, and General System Control
MC9S08QD4 Series MCU Data Sheet, Rev. 5
62 Freescale Semiconductor
5.8.3 System Background Debug Force Reset Register (SBDFR)
This high-page register contains a single write-only control bit. A serial background command such as
WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are
ignored. Reads always return 0x00.
5
COP
Computer Operating Properly (COP) Watchdog — Reset was caused by the COP watchdog timer timing out.
This reset source can be blocked by COPE = 0.
0 Reset not caused by COP timeout.
1 Reset caused by COP timeout.
4
ILOP
Illegal Opcode — Reset was caused by an attempt to execute an unimplemented or illegal opcode. The STOP
instruction is considered illegal if stop is disabled by STOPE = 0 in the SOPT register. The BGND instruction is
considered illegal if active background mode is disabled by ENBDM = 0 in the BDCSC register.
0 Reset not caused by an illegal opcode.
1 Reset caused by an illegal opcode.
3
ILAD
Illegal Address — Reset was caused by an attempt to access either data or an instruction at an unimplemented
memory address.
0 Reset not caused by an illegal address
1 Reset caused by an illegal address
1
LVD
Low Voltage Detect — If the LVDRE bit is set and the supply drops below the LVD trip voltage, an LVD reset will
occur. This bit is also set by POR.
0 Reset not caused by LVD trip or POR.
1 Reset caused by LVD trip or POR.
76543210
R00000000
WBDFR1
Reset:00000000
= Unimplemented or Reserved
1BDFR is writable only through serial background debug commands, not from user programs.
Figure 5-4. System Background Debug Force Reset Register (SBDFR)
Table 5-5. SBDFR Register Field Descriptions
Field Description
0
BDFR
Background Debug Force Reset — A serial background command such as WRITE_BYTE can be used to allow
an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot
be written from a user program. To enter user mode, PTA4/TPM2CH0O/BKGD/MS must be high immediately
after issuing WRITE_BYTE command. To enter BDM, PTA4/TPM2CH0O/BKGD/MS must be low immediately
after issuing WRITE_BYTE command. See A.8.1, “Control Timing,” for more information.
Table 5-4. SRS Register Field Descriptions (continued)
Field Description
Chapter 5 Resets, Interrupts, and General System Control
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 63
5.8.4 System Options Register 1 (SOPT1)
This high-page register is a write-once register so only the first write after reset is honored. It can be read
at any time. Any subsequent attempt to write to SOPT1 (intentionally or unintentionally) is ignored to
avoid accidental changes to these sensitive settings. SOPT1 must be written during the user’s reset
initialization program to set the desired controls even if the desired settings are the same as the reset
settings.
7654
13210
R
COPE COPT STOPE
00
BKGDPE RSTPE
W
Reset:1101001U
POR:11010010
= Unimplemented or Reserved U = unaffected
1Bit 4 is reserved, writes will change the value but will have no effect on this MCU.
Figure 5-5. System Options Register 1 (SOPT1)
Table 5-6. SOPT1 Register Field Descriptions
Field Description
7
COPE
COP Watchdog Enable — This write-once bit selects whether the COP watchdog is enabled.
0 COP watchdog timer disabled.
1 COP watchdog timer enabled (force reset on timeout).
6
COPT
COP Watchdog Timeout — This write-once bit selects the timeout period of the COP. COPT along with
COPCLKS in SOPT2 defines the COP timeout period.
0 Short timeout period selected.
1 Long timeout period selected.
5
STOPE
Stop Mode Enable — This write-once bit is used to enable stop mode. If stop mode is disabled and a user
program attempts to execute a STOP instruction, an illegal opcode reset is forced.
0 Stop mode disabled.
1 Stop mode enabled.
1
BKGDPE
Background Debug Mode Pin Enable — This write-once bit when set enables the
PTA4/TPM2CH0O/BKGD/MS pin to function as BKGD/MS. When clear, the pin functions as one of its output only
alternative functions. This pin defaults to the BKGD/MS function following any MCU reset.
0 PTA4/TPM2CH0O/BKGD/MS pin functions as PTA4 or TPM2CH0O.
1 PTA4/TPM2CH0O/BKGD/MS pin functions as BKGD/MS.
0
RSTPE
RESET Pin Enable — This write-once bit when set enables the PTA5/TPM2CH0I/IRQ/RESET pin to function as
RESET. When clear, the pin functions as one of its input only alternative functions. This pin defaults to its
input-only port function following an MCU POR. When RSTPE is set, an internal pullup device is enabled on
RESET.
0 PTA5/TPM2CH0I/IRQ/RESET pin functions as PTA5, IRQ or TPM2CH0I.
1 PTA5/TPM2CH0I/IRQ/RESET pin functions as RESET.
Chapter 5 Resets, Interrupts, and General System Control
MC9S08QD4 Series MCU Data Sheet, Rev. 5
64 Freescale Semiconductor
5.8.5 System Options Register 2 (SOPT2)
This high-page register contains bits to configure MCU-specific features on MC9S08QD4 series devices.
5.8.6 System Device Identification Register (SDIDH, SDIDL)
These high-page read-only registers are included so host development systems can identify the HCS08
derivative and revision number. This allows the development software to recognize where specific
memory blocks, registers, and control bits are located in a target MCU.
76543210
R
COPCLKS10000000
W
Reset:00000000
= Unimplemented or Reserved
1This bit can be written only one time after reset. Additional writes are ignored.
Figure 5-6. System Options Register 2 (SOPT2)
Table 5-7. SOPT2 Register Field Descriptions
Field Description
7
COPCLKS
COP Watchdog Clock Select — This write-once bit selects the clock source of the COP watchdog.
0 Internal 32 kHz clock is source to COP.
1 Bus clock is source to COP.
76543210
R REV3 REV2 REV1 REV0 ID11 ID10 ID9 ID8
W
Reset: 010101010000
= Unimplemented or Reserved
1The revision number that is hard coded into these bits reflects the current silicon revision level.
Figure 5-7. System Device Identification Register — High (SDIDH)
Table 5-8. SDIDH Register Field Descriptions
Field Description
7:4
REV[3:0]
Revision Number — The high-order 4 bits of address SDIDH are hard coded to reflect the current mask set
revision number (0–F).
3:0
ID[11:8]
Part Identification Number — Each derivative in the HCS08 family has a unique identification number. The
MC9S08QD4 series is hard coded to the value 0x011. See also ID bits in Ta bl e 5-9 .
Chapter 5 Resets, Interrupts, and General System Control
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 65
5.8.7 System Real-Time Interrupt Status and Control Register (SRTISC)
This high-page register contains status and control bits for the RTI.
76543210
R ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
W
Reset:00001001
= Unimplemented or Reserved
Figure 5-8. System Device Identification Register — Low (SDIDL)
Table 5-9. SDIDL Register Field Descriptions
Field Description
7:0
ID[7:0]
Part Identification Number — Each derivative in the HCS08 family has a unique identification number. The
MC9S08QD4 series is hard coded to the value 0x011. See also ID bits in Ta bl e 5-8 .
76543210
RRTIF 0
RTICLKS RTIE
0
RTIS
WRTIACK
Reset:00000000
= Unimplemented or Reserved
Figure 5-9. System RTI Status and Control Register (SRTISC)
Table 5-10. SRTISC Register Field Descriptions
Field Description
7
RTIF
Real-Time Interrupt Flag — This read-only status bit indicates the periodic wakeup timer has timed out.
0 Periodic wakeup timer not timed out.
1 Periodic wakeup timer timed out.
6
RTIACK
Real-Time Interrupt Acknowledge — This write-only bit is used to acknowledge real-time interrupt request
(write 1 to clear RTIF). Writing 0 has no meaning or effect. Reads always return 0.
5
RTICLKS
Real-Time Interrupt Clock Select — This read/write bit selects the clock source for the real-time interrupt.
0 Real-time interrupt request clock source is internal 1 kHz oscillator.
1 Real-time interrupt request clock source is 32 kHz ICS clock.
4
RTIE
Real-Time Interrupt Enable — This read-write bit enables real-time interrupts.
0 Real-time interrupts disabled.
1 Real-time interrupts enabled.
2:0
RTIS
Real-Time Interrupt Delay Selects — These read/write bits select the period for the RTI. See Tabl e 5 -11
Chapter 5 Resets, Interrupts, and General System Control
MC9S08QD4 Series MCU Data Sheet, Rev. 5
66 Freescale Semiconductor
5.8.8 System Power Management Status and Control 1 Register
(SPMSC1)
This high-page register contains status and control bits to support the low voltage detect function, and to
enable the bandgap voltage reference for use by the ADC module. To configure the low voltage detect trip
voltage, see Table 5-13 for the LVDV bit description in SPMSC2.
Table 5-11. Real-Time Interrupt Period
RTIS2:RTIS1:RTIS0 Using Internal 1 kHz Clock Source1 2
1Values are shown in this column based on tRTI =1ms. See t
RTI in the Section A.8.1, “Control Timing,” for the tolerance of this
value.
2The initial RTI timeout period will be up to one 1 kHz clock period less than the time specified.
Using 32 kHz ICS Clock Source
Period = text3
3text is the period of the 32 kHz ICS frequency.
0:0:0 Disable RTI Disable RTI
0:0:1 8 ms text × 256
0:1:0 32 ms text × 1024
0:1:1 64 ms text × 2048
1:0:0 128 ms text × 4096
1:0:1 256 ms text × 8192
1:1:0 512 ms text × 16384
1:1:1 1.024 s text × 32768
7654321
10
RLVDF 0
LVDIE LVDRE2LVDSE LV DE 20
BGBE
WLVDACK
Reset:00011100
= Unimplemented or Reserved
1Bit 1 is a reserved bit that must always be written to 0.
2This bit can be written only one time after reset. Additional writes are ignored.
Figure 5-10. System Power Management Status and Control 1 Register (SPMSC1)
Table 5-12. SPMSC1 Register Field Descriptions
Field Description
7
LVD F
Low-Voltage Detect Flag — Provided LVDE = 1, this read-only status bit indicates a low-voltage detect event.
6
LVDACK
Low-Voltage Detect Acknowledge — This write-only bit is used to acknowledge low voltage detection errors
(write 1 to clear LVDF). Reads always return 0.
Chapter 5 Resets, Interrupts, and General System Control
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 67
5.8.9 System Power Management Status and Control 2 Register
(SPMSC2)
This high-page register contains status and control bits to configure the stop mode behavior of the MCU.
See Section 3.6, “Stop Modes,” for more information on stop modes.
Figure 5-11. System Power Management Status and Control 2 Register (SPMSC2)
5
LVD I E
Low-Voltage Detect Interrupt Enable — This bit enables hardware interrupt requests for LVDF.
0 Hardware interrupt disabled (use polling).
1 Request a hardware interrupt when LVDF = 1.
4
LVDRE
Low-Voltage Detect Reset Enable — This write-once bit enables LVDF events to generate a hardware reset
(provided LVDE = 1).
0 LVDF does not generate hardware resets.
1 Force an MCU reset when LVDF = 1.
3
LVD SE
Low-Voltage Detect Stop Enable — Provided LVDE = 1, this read/write bit determines whether the low-voltage
detect function operates when the MCU is in stop mode.
0 Low-voltage detect disabled during stop mode.
1 Low-voltage detect enabled during stop mode.
2
LVD E
Low-Voltage Detect Enable — This write-once bit enables low-voltage detect logic and qualifies the operation
of other bits in this register.
0 LVD logic disabled.
1 LVD logic enabled.
0
BGBE
Bandgap Buffer Enable — This bit enables an internal buffer for the bandgap voltage reference for use by the
ADC module on one of its internal channels.
0 Bandgap buffer disabled.
1 Bandgap buffer enabled.
76543210
RLVWF 0
LVDV LV WV
PPDF 0
PPDC1
1This bit can be written only one time after reset. Additional writes are ignored.
WLVWAC K PPDACK
POR: 02
2LVWF will be set in the case when Vsupply transitions below the trip point or after reset and Vsupply is already below VLV W.
0000000
LVDR: 020UU0000
Other
Reset 020UU0000
= Unimplemented or Reserved U = Unaffected by reset
Table 5-12. SPMSC1 Register Field Descriptions (continued)
Field Description
Chapter 5 Resets, Interrupts, and General System Control
MC9S08QD4 Series MCU Data Sheet, Rev. 5
68 Freescale Semiconductor
Table 5-13. SPMSC2 Register Field Descriptions
Field Description
7
LVWF
Low-Voltage Warning Flag — The LVWF bit indicates the low voltage warning status.
0 Low voltage warning not preset.
1 Low voltage warning is present or was present.
6
LVWACK
Low-Voltage Warning Acknowledge — The LVWACK bit is the low-voltage warning acknowledge.
Writing a 1 to LVWACK clears LVWF to a 0 if a low voltage warning is not present.
5
LVDV
Low-Voltage Detect Voltage Select — The LVDV bit selects the LVD trip point voltage (VLVD ).
0 Low trip point selected (VLV D = VLVD L).
1 High trip point selected (VLVD = VLV D H ).
4
LVWV
Low-Voltage Warning Voltage Select — The LVWV bit selects the LVW trip point voltage (VLVW).
0 Low trip point selected (VLV W = VLV W L ).
1 High trip point selected (VLVW = VLV WH).
3
PPDF
Partial Power Down Flag — The PPDF bit indicates that the MCU has exited the stop2 mode.
0 Not stop2 mode recovery.
1 Stop2 mode recovery.
2
PPDACK
Partial Power Down Acknowledge — Writing a 1 to PPDACK clears the PPDF bit.
0
PPDC
Partial Power Down Control — The write-once PPDC bit controls whether stop2 or stop3 mode is selected.
0 Stop3 mode enabled.
1 Stop2, partial power down, mode enabled.
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 69
Chapter 6
Parallel Input/Output Control
This section explains software controls related to parallel input/output (I/O) and pin control. The
MC9S08QD4 series has one parallel I/O port which include a total of 4 I/O pins, one output-only pin, and
one input-only pin. See Section Chapter 2, “External Signal Description,” for more information about pin
assignments and external hardware considerations of these pins.
All of these I/O pins are shared with on-chip peripheral functions as shown in Table 2-1. The peripheral
modules have priority over the I/Os so that when a peripheral is enabled, the I/O functions associated with
the shared pins are disabled. After reset, the shared peripheral functions are disabled so that the pins are
controlled by the I/O. All of the I/Os are configured as inputs (PTxDDn = 0) with pullup devices disabled
(PTxPEn = 0), except for output-only pin PTA4 which defaults to BKGD/MS pin.
NOTE
Not all general-purpose I/O pins are available on all packages. To avoid
extra current drain from floating input pins, the user’s reset initialization
routine in the application program must either enable on-chip pullup devices
or change the direction of unconnected pins to outputs so the pins do not
float.
6.1 Port Data and Data Direction
Reading and writing of parallel I/Os is performed through the port data registers. The direction, either input
or output, is controlled through the port data direction registers. The parallel I/O port function for an
individual pin is illustrated in the block diagram shown in Figure 6-1.
Chapter 6 Parallel Input/Output Control
MC9S08QD4 Series MCU Data Sheet, Rev. 5
70 Freescale Semiconductor
Figure 6-1. Parallel I/O Block Diagram
The data direction control bit (PTxDDn) determines whether the output buffer for the associated pin is
enabled, and also controls the source for port data register reads. The input buffer for the associated pin is
always enabled unless the pin is enabled as an analog function or is an output-only pin.
When a shared digital function is enabled for a pin, the output buffer is controlled by the shared function.
However, the data direction register bit will continue to control the source for reads of the port data register.
When a shared analog function is enabled for a pin, both the input and output buffers are disabled. A value
of 0 is read for any port data bit where the bit is an input (PTxDDn = 0) and the input buffer is disabled. In
general, whenever a pin is shared with both an alternate digital function and an analog function, the analog
function has priority such that if both the digital and analog functions are enabled, the analog function
controls the pin.
It is a good programming practice to write to the port data register before changing the direction of a port
pin to become an output. This ensures that the pin will not be driven momentarily with an old data value
that happened to be in the port data register.
6.2 Pin Control — Pullup, Slew Rate and Drive Strength
Associated with the parallel I/O ports is a set of registers located in the high-page register space that
operate independently of the parallel I/O registers. These registers are used to control pullups, slew rate
and drive strength for the pins.
6.3 Pin Behavior in Stop Modes
Pin behavior following execution of a STOP instruction depends on the stop mode that is entered. An
explanation of pin behavior for the various stop modes follows:
QD
QD
1
0
Port Read
PTxDDn
PTxDn
Output Enable
Output Data
Input Data
Synchronizer
Data
BUSCLK
Chapter 6 Parallel Input/Output Control
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 71
• In stop1 mode, all internal registers including parallel I/O control and data registers are powered
off. Each of the pins assumes its default reset state (output buffer and internal pullup disabled).
Upon exit from stop1, all pins must be re-configured the same as if the MCU had been reset.
• Stop2 mode is a partial power-down mode, whereby latches maintain the pin state as before the
STOP instruction was executed. CPU register status and the state of I/O registers must be saved in
RAM before the STOP instruction is executed to place the MCU in stop2 mode. Upon recovery
from stop2 mode, before accessing any I/O, the user must examine the state of the PPDF bit in the
SPMSC2 register. If the PPDF bit is 0, I/O must be initialized as if a power on reset had occurred.
If the PPDF bit is 1, I/O data previously stored in RAM, before the STOP instruction was executed,
peripherals previously enabled will require being initialized and restored to their pre-stop
condition. The user must then write a 1 to the PPDACK bit in the SPMSC2 register. Access of pins
is now permitted again in the user’s application program.
• In stop3 mode, all pin states are maintained because internal logic stays powered up. Upon
recovery, all pin functions are the same as before entering stop3.
6.4 Parallel I/O Registers
6.4.1 Port A Registers
This section provides information about the registers associated with the parallel I/O ports.
Refer to tables in Chapter 4, “Memory Map and Register Definition,” for the absolute address assignments
for all parallel I/O. This section refers to registers and control bits only by their names. A Freescale
Semiconductor-provided equate or header file normally is used to translate these names into the
appropriate absolute addresses.
6.4.1.1 Port A Data (PTAD)
76543210
R00
PTAD51PTAD42PTAD3 PTAD2 PTAD1 PTAD0
W
Reset:00000000
1Reads of bit PTAD5 always return the pin value of PTA5, regardless of the value stored in bit PTADD5.
2Reads of bit PTAD4 always return the contents of PTAD4, regardless of the value stored in bit PTADD4.
Figure 6-2. Port A Data Register (PTAD)
Chapter 6 Parallel Input/Output Control
MC9S08QD4 Series MCU Data Sheet, Rev. 5
72 Freescale Semiconductor
6.4.1.2 Port A Data Direction (PTADD)
6.4.2 Port A Control Registers
The pins associated with port A are controlled by the registers in this section. These registers control the
pin pullup, slew rate and drive strength of the Port A pins independent of the parallel I/O register.
Table 6-1. PTAD Register Field Descriptions
Field Description
5:0
PTAD[5:0]
Port A Data Register Bits — For port A pins that are inputs, reads return the logic level on the pin. For port A
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pullups disabled.
76543210
R00
PTADD51PTADD42PTADD3 PTADD2 PTADD1 PTADD0
W
Reset:00000000
1PTADD5 has no effect on the input-only PTA5 pin. Read this bit is always equal to zero.
2PTADD4 has no effect on the output-only PTA4 pin.
Figure 6-3. Port A Data Direction Register (PTADD)
Table 6-2. PTADD Register Field Descriptions
Field Description
5:0
PTADD[5:0]
Data Direction for Port A Bits — These read/write bits control the direction of port A pins and what is read for
PTAD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn.
Chapter 6 Parallel Input/Output Control
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 73
6.4.2.1 Port A Internal Pullup Enable (PTAPE)
An internal pullup device can be enabled for each port pin by setting the corresponding bit in the pullup
enable register (PTAPEn). The pullup device is disabled if the pin is configured as an output by the parallel
I/O control logic or any shared peripheral function regardless of the state of the corresponding pullup
enable register bit. The pullup device is also disabled if the pin is controlled by an analog function.
6.4.2.2 Port A Slew Rate Enable (PTASE)
Slew rate control can be enabled for each port pin by setting the corresponding bit in the slew rate control
register (PTASEn). When enabled, slew control limits the rate at which an output can transition in order to
reduce EMC emissions. Slew rate control has no effect on pins which are configured as inputs.
76543210
R00
PTAPE5 PTAPE41PTAPE3 PTAPE2 PTAPE1 PTAPE0
W
Reset:00000000
1PTAPE4 has no effect on the output-only PTA4 pin.
Figure 6-4. Internal Pullup Enable for Port A Register (PTAPE)
Table 6-3. PTAPE Register Field Descriptions
Field Description
5:0
PTAPE[5:0]
Internal Pullup Enable for Port A Bits — Each of these control bits determines if the internal pullup device is
enabled for the associated PTA pin. For port A pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port A bit n.
1 Internal pullup device enabled for port A bit n.
76543210
R00
PTASE51PTASE4 PTASE3 PTASE2 PTASE1 PTASE0
W
Reset:00111111
1PTASE5 has no effect on the input-only PTA5 pin.
Figure 6-5. Slew Rate Enable for Port A Register (PTASE)
Table 6-4. PTASE Register Field Descriptions
Field Description
5:0
PTASE[5:0]
Output Slew Rate Enable for Port A Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port A bit n.
1 Output slew rate control enabled for port A bit n.
Chapter 6 Parallel Input/Output Control
MC9S08QD4 Series MCU Data Sheet, Rev. 5
74 Freescale Semiconductor
6.4.2.3 Port A Drive Strength Select (PTADS)
An output pin can be selected to have high output drive strength by setting the corresponding bit in the
drive strength select register (PTADSn). When high drive is selected a pin is capable of sourcing and
sinking greater current. Even though every I/O pin can be selected as high drive, the user must ensure that
the total current source and sink limits for the chip are not exceeded. Drive strength selection is intended
to affect the DC behavior of I/O pins. However, the AC behavior is also affected. High drive allows a pin
to drive a greater load with the same switching speed as a low drive enabled pin into a smaller load.
Because of this the EMC emissions may be affected by enabling pins as high drive.
6.4.2.4 Port A Drive Strength Select (PTADS)
76543210
R00
PTADS51PTADS4 PTADS3 PTADS2 PTADS1 PTADS0
W
Reset:00000000
1PTADS5 has no effect on the input-only PTA5 pin.
Figure 6-6. Drive Strength Selection for Port A Register (PTADS)
Table 6-5. PTADS Register Field Descriptions
Field Description
5:0
PTADS[5:0]
Output Drive Strength Selection for Port A Bits — Each of these control bits selects between low and high
output drive for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port A bit n.
1 High output drive strength selected for port A bit n.
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 75
Chapter 7
Central Processor Unit (S08CPUV2)
7.1 Introduction
This section provides summary information about the registers, addressing modes, and instruction set of
the CPU of the HCS08 Family. For a more detailed discussion, refer to the HCS08 Family Reference
Manual, volume 1, Freescale Semiconductor document order number HCS08RMV1/D.
The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU. Several
instructions and enhanced addressing modes were added to improve C compiler efficiency and to support
a new background debug system which replaces the monitor mode of earlier M68HC08 microcontrollers
(MCU).
7.1.1 Features
Features of the HCS08 CPU include:
• Object code fully upward-compatible with M68HC05 and M68HC08 Families
• All registers and memory are mapped to a single 64-Kbyte address space
• 16-bit stack pointer (any size stack anywhere in 64-Kbyte address space)
• 16-bit index register (H:X) with powerful indexed addressing modes
• 8-bit accumulator (A)
• Many instructions treat X as a second general-purpose 8-bit register
• Seven addressing modes:
— Inherent — Operands in internal registers
— Relative — 8-bit signed offset to branch destination
— Immediate — Operand in next object code byte(s)
— Direct — Operand in memory at 0x0000–0x00FF
— Extended — Operand anywhere in 64-Kbyte address space
— Indexed relative to H:X — Five submodes including auto increment
— Indexed relative to SP — Improves C efficiency dramatically
• Memory-to-memory data move instructions with four address mode combinations
• Overflow, half-carry, negative, zero, and carry condition codes support conditional branching on
the results of signed, unsigned, and binary-coded decimal (BCD) operations
• Efficient bit manipulation instructions
• Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
• STOP and WAIT instructions to invoke low-power operating modes
Chapter 7 Central Processor Unit (S08CPUV2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
76 Freescale Semiconductor
7.2 Programmer’s Model and CPU Registers
Figure 7-1 shows the five CPU registers. CPU registers are not part of the memory map.
Figure 7-1. CPU Registers
7.2.1 Accumulator (A)
The A accumulator is a general-purpose 8-bit register. One operand input to the arithmetic logic unit
(ALU) is connected to the accumulator and the ALU results are often stored into the A accumulator after
arithmetic and logical operations. The accumulator can be loaded from memory using various addressing
modes to specify the address where the loaded data comes from, or the contents of A can be stored to
memory using various addressing modes to specify the address where data from A will be stored.
Reset has no effect on the contents of the A accumulator.
7.2.2 Index Register (H:X)
This 16-bit register is actually two separate 8-bit registers (H and X), which often work together as a 16-bit
address pointer where H holds the upper byte of an address and X holds the lower byte of the address. All
indexed addressing mode instructions use the full 16-bit value in H:X as an index reference pointer;
however, for compatibility with the earlier M68HC05 Family, some instructions operate only on the
low-order 8-bit half (X).
Many instructions treat X as a second general-purpose 8-bit register that can be used to hold 8-bit data
values. X can be cleared, incremented, decremented, complemented, negated, shifted, or rotated. Transfer
instructions allow data to be transferred from A or transferred to A where arithmetic and logical operations
can then be performed.
For compatibility with the earlier M68HC05 Family, H is forced to 0x00 during reset. Reset has no effect
on the contents of X.
SP
PC
CONDITION CODE REGISTER
CARRY
ZERO
NEGATIVE
INTERRUPT MASK
HALF-CARRY (FROM BIT 3)
TWO’S COMPLEMENT OVERFLOW
H X
0
0
0
7
15
15
70
ACCUMULATOR A
INDEX REGISTER (LOW)INDEX REGISTER (HIGH)
STACK POINTER
87
PROGRAM COUNTER
16-BIT INDEX REGISTER H:X
CCR
CV11HINZ
Chapter 7 Central Processor Unit (S08CPUV2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 77
7.2.3 Stack Pointer (SP)
This 16-bit address pointer register points at the next available location on the automatic last-in-first-out
(LIFO) stack. The stack may be located anywhere in the 64-Kbyte address space that has RAM and can
be any size up to the amount of available RAM. The stack is used to automatically save the return address
for subroutine calls, the return address and CPU registers during interrupts, and for local variables. The
AIS (add immediate to stack pointer) instruction adds an 8-bit signed immediate value to SP. This is most
often used to allocate or deallocate space for local variables on the stack.
SP is forced to 0x00FF at reset for compatibility with the earlier M68HC05 Family. HCS08 programs
normally change the value in SP to the address of the last location (highest address) in on-chip RAM
during reset initialization to free up direct page RAM (from the end of the on-chip registers to 0x00FF).
The RSP (reset stack pointer) instruction was included for compatibility with the M68HC05 Family and
is seldom used in new HCS08 programs because it only affects the low-order half of the stack pointer.
7.2.4 Program Counter (PC)
The program counter is a 16-bit register that contains the address of the next instruction or operand to be
fetched.
During normal program execution, the program counter automatically increments to the next sequential
memory location every time an instruction or operand is fetched. Jump, branch, interrupt, and return
operations load the program counter with an address other than that of the next sequential location. This
is called a change-of-flow.
During reset, the program counter is loaded with the reset vector that is located at 0xFFFE and 0xFFFF.
The vector stored there is the address of the first instruction that will be executed after exiting the reset
state.
7.2.5 Condition Code Register (CCR)
The 8-bit condition code register contains the interrupt mask (I) and five flags that indicate the results of
the instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the
functions of the condition code bits in general terms. For a more detailed explanation of how each
instruction sets the CCR bits, refer to the HCS08 Family Reference Manual, volume 1, Freescale
Semiconductor document order number HCS08RMv1.
Chapter 7 Central Processor Unit (S08CPUV2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
78 Freescale Semiconductor
Figure 7-2. Condition Code Register
Table 7-1. CCR Register Field Descriptions
Field Description
7
V
Two’s Complement Overflow Flag — The CPU sets the overflow flag when a two’s complement overflow occurs.
The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag.
0 No overflow
1Overflow
4
H
Half-Carry Flag — The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during
an add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for binary-coded
decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C condition code bits to
automatically add a correction value to the result from a previous ADD or ADC on BCD operands to correct the
result to a valid BCD value.
0 No carry between bits 3 and 4
1 Carry between bits 3 and 4
3
I
Interrupt Mask Bit — When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts
are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but before the first instruction of the interrupt service
routine is executed.
Interrupts are not recognized at the instruction boundary after any instruction that clears I (CLI or TAP). This
ensures that the next instruction after a CLI or TAP will always be executed without the possibility of an intervening
interrupt, provided I was set.
0 Interrupts enabled
1 Interrupts disabled
2
N
Negative Flag — The CPU sets the negative flag when an arithmetic operation, logic operation, or data
manipulation produces a negative result, setting bit 7 of the result. Simply loading or storing an 8-bit or 16-bit value
causes N to be set if the most significant bit of the loaded or stored value was 1.
0 Non-negative result
1 Negative result
1
Z
Zero Flag — The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation
produces a result of 0x00 or 0x0000. Simply loading or storing an 8-bit or 16-bit value causes Z to be set if the
loaded or stored value was all 0s.
0 Non-zero result
1Zero result
0
C
Carry/Borrow Flag — The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit
7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and
branch, shift, and rotate — also clear or set the carry/borrow flag.
0 No carry out of bit 7
1 Carry out of bit 7
CONDITION CODE REGISTER
CARRY
ZERO
NEGATIVE
INTERRUPT MASK
HALF-CARRY (FROM BIT 3)
TWO’S COMPLEMENT OVERFLOW
70
CCR
CV11HINZ
Chapter 7 Central Processor Unit (S08CPUV2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 79
7.3 Addressing Modes
Addressing modes define the way the CPU accesses operands and data. In the HCS08, all memory, status
and control registers, and input/output (I/O) ports share a single 64-Kbyte linear address space so a 16-bit
binary address can uniquely identify any memory location. This arrangement means that the same
instructions that access variables in RAM can also be used to access I/O and control registers or nonvolatile
program space.
Some instructions use more than one addressing mode. For instance, move instructions use one addressing
mode to specify the source operand and a second addressing mode to specify the destination address.
Instructions such as BRCLR, BRSET, CBEQ, and DBNZ use one addressing mode to specify the location
of an operand for a test and then use relative addressing mode to specify the branch destination address
when the tested condition is true. For BRCLR, BRSET, CBEQ, and DBNZ, the addressing mode listed in
the instruction set tables is the addressing mode needed to access the operand to be tested, and relative
addressing mode is implied for the branch destination.
7.3.1 Inherent Addressing Mode (INH)
In this addressing mode, operands needed to complete the instruction (if any) are located within CPU
registers so the CPU does not need to access memory to get any operands.
7.3.2 Relative Addressing Mode (REL)
Relative addressing mode is used to specify the destination location for branch instructions. A signed 8-bit
offset value is located in the memory location immediately following the opcode. During execution, if the
branch condition is true, the signed offset is sign-extended to a 16-bit value and is added to the current
contents of the program counter, which causes program execution to continue at the branch destination
address.
7.3.3 Immediate Addressing Mode (IMM)
In immediate addressing mode, the operand needed to complete the instruction is included in the object
code immediately following the instruction opcode in memory. In the case of a 16-bit immediate operand,
the high-order byte is located in the next memory location after the opcode, and the low-order byte is
located in the next memory location after that.
7.3.4 Direct Addressing Mode (DIR)
In direct addressing mode, the instruction includes the low-order eight bits of an address in the direct page
(0x0000–0x00FF). During execution a 16-bit address is formed by concatenating an implied 0x00 for the
high-order half of the address and the direct address from the instruction to get the 16-bit address where
the desired operand is located. This is faster and more memory efficient than specifying a complete 16-bit
address for the operand.
Chapter 7 Central Processor Unit (S08CPUV2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
80 Freescale Semiconductor
7.3.5 Extended Addressing Mode (EXT)
In extended addressing mode, the full 16-bit address of the operand is located in the next two bytes of
program memory after the opcode (high byte first).
7.3.6 Indexed Addressing Mode
Indexed addressing mode has seven variations including five that use the 16-bit H:X index register pair
and two that use the stack pointer as the base reference.
7.3.6.1 Indexed, No Offset (IX)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of
the operand needed to complete the instruction.
7.3.6.2 Indexed, No Offset with Post Increment (IX+)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of
the operand needed to complete the instruction. The index register pair is then incremented
(H:X = H:X + 0x0001) after the operand has been fetched. This addressing mode is only used for MOV
and CBEQ instructions.
7.3.6.3 Indexed, 8-Bit Offset (IX1)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus an unsigned
8-bit offset included in the instruction as the address of the operand needed to complete the instruction.
7.3.6.4 Indexed, 8-Bit Offset with Post Increment (IX1+)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus an unsigned
8-bit offset included in the instruction as the address of the operand needed to complete the instruction.
The index register pair is then incremented (H:X = H:X + 0x0001) after the operand has been fetched. This
addressing mode is used only for the CBEQ instruction.
7.3.6.5 Indexed, 16-Bit Offset (IX2)
This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus a 16-bit offset
included in the instruction as the address of the operand needed to complete the instruction.
7.3.6.6 SP-Relative, 8-Bit Offset (SP1)
This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus an unsigned 8-bit
offset included in the instruction as the address of the operand needed to complete the instruction.
Chapter 7 Central Processor Unit (S08CPUV2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 81
7.3.6.7 SP-Relative, 16-Bit Offset (SP2)
This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus a 16-bit offset
included in the instruction as the address of the operand needed to complete the instruction.
7.4 Special Operations
The CPU performs a few special operations that are similar to instructions but do not have opcodes like
other CPU instructions. In addition, a few instructions such as STOP and WAIT directly affect other MCU
circuitry. This section provides additional information about these operations.
7.4.1 Reset Sequence
Reset can be caused by a power-on-reset (POR) event, internal conditions such as the COP (computer
operating properly) watchdog, or by assertion of an external active-low reset pin. When a reset event
occurs, the CPU immediately stops whatever it is doing (the MCU does not wait for an instruction
boundary before responding to a reset event). For a more detailed discussion about how the MCU
recognizes resets and determines the source, refer to the Resets, Interrupts, and System Configuration
chapter.
The reset event is considered concluded when the sequence to determine whether the reset came from an
internal source is done and when the reset pin is no longer asserted. At the conclusion of a reset event, the
CPU performs a 6-cycle sequence to fetch the reset vector from 0xFFFE and 0xFFFF and to fill the
instruction queue in preparation for execution of the first program instruction.
7.4.2 Interrupt Sequence
When an interrupt is requested, the CPU completes the current instruction before responding to the
interrupt. At this point, the program counter is pointing at the start of the next instruction, which is where
the CPU should return after servicing the interrupt. The CPU responds to an interrupt by performing the
same sequence of operations as for a software interrupt (SWI) instruction, except the address used for the
vector fetch is determined by the highest priority interrupt that is pending when the interrupt sequence
started.
The CPU sequence for an interrupt is:
1. Store the contents of PCL, PCH, X, A, and CCR on the stack, in that order.
2. Set the I bit in the CCR.
3. Fetch the high-order half of the interrupt vector.
4. Fetch the low-order half of the interrupt vector.
5. Delay for one free bus cycle.
6. Fetch three bytes of program information starting at the address indicated by the interrupt vector
to fill the instruction queue in preparation for execution of the first instruction in the interrupt
service routine.
After the CCR contents are pushed onto the stack, the I bit in the CCR is set to prevent other interrupts
while in the interrupt service routine. Although it is possible to clear the I bit with an instruction in the
Chapter 7 Central Processor Unit (S08CPUV2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
82 Freescale Semiconductor
interrupt service routine, this would allow nesting of interrupts (which is not recommended because it
leads to programs that are difficult to debug and maintain).
For compatibility with the earlier M68HC05 MCUs, the high-order half of the H:X index register pair (H)
is not saved on the stack as part of the interrupt sequence. The user must use a PSHH instruction at the
beginning of the service routine to save H and then use a PULH instruction just before the RTI that ends
the interrupt service routine. It is not necessary to save H if you are certain that the interrupt service routine
does not use any instructions or auto-increment addressing modes that might change the value of H.
The software interrupt (SWI) instruction is like a hardware interrupt except that it is not masked by the
global I bit in the CCR and it is associated with an instruction opcode within the program so it is not
asynchronous to program execution.
7.4.3 Wait Mode Operation
The WAIT instruction enables interrupts by clearing the I bit in the CCR. It then halts the clocks to the
CPU to reduce overall power consumption while the CPU is waiting for the interrupt or reset event that
will wake the CPU from wait mode. When an interrupt or reset event occurs, the CPU clocks will resume
and the interrupt or reset event will be processed normally.
If a serial BACKGROUND command is issued to the MCU through the background debug interface while
the CPU is in wait mode, CPU clocks will resume and the CPU will enter active background mode where
other serial background commands can be processed. This ensures that a host development system can still
gain access to a target MCU even if it is in wait mode.
7.4.4 Stop Mode Operation
Usually, all system clocks, including the crystal oscillator (when used), are halted during stop mode to
minimize power consumption. In such systems, external circuitry is needed to control the time spent in
stop mode and to issue a signal to wake up the target MCU when it is time to resume processing. Unlike
the earlier M68HC05 and M68HC08 MCUs, the HCS08 can be configured to keep a minimum set of
clocks running in stop mode. This optionally allows an internal periodic signal to wake the target MCU
from stop mode.
When a host debug system is connected to the background debug pin (BKGD) and the ENBDM control
bit has been set by a serial command through the background interface (or because the MCU was reset into
active background mode), the oscillator is forced to remain active when the MCU enters stop mode. In this
case, if a serial BACKGROUND command is issued to the MCU through the background debug interface
while the CPU is in stop mode, CPU clocks will resume and the CPU will enter active background mode
where other serial background commands can be processed. This ensures that a host development system
can still gain access to a target MCU even if it is in stop mode.
Recovery from stop mode depends on the particular HCS08 and whether the oscillator was stopped in stop
mode. Refer to the Modes of Operation chapter for more details.
Chapter 7 Central Processor Unit (S08CPUV2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 83
7.4.5 BGND Instruction
The BGND instruction is new to the HCS08 compared to the M68HC08. BGND would not be used in
normal user programs because it forces the CPU to stop processing user instructions and enter the active
background mode. The only way to resume execution of the user program is through reset or by a host
debug system issuing a GO, TRACE1, or TAGGO serial command through the background debug
interface.
Software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the
BGND opcode. When the program reaches this breakpoint address, the CPU is forced to active
background mode rather than continuing the user program.
Chapter 7 Central Processor Unit (S08CPUV2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
84 Freescale Semiconductor
7.5 HCS08 Instruction Set Summary
Table 7-2 provides a summary of the HCS08 instruction set in all possible addressing modes. The table
shows operand construction, execution time in internal bus clock cycles, and cycle-by-cycle details for
each addressing mode variation of each instruction.
Table 7-2. Instruction Set Summary (Sheet 1 of 9)
Source
Form
Operation
Address
Mode
Object Code
Cycles
Cyc-by-Cyc
Details
Affect
on CCR
VH I N Z C
ADC #opr8i
ADC opr8a
ADC opr16a
ADC oprx16,X
ADC oprx8,X
ADC ,X
ADC oprx16,SP
ADC oprx8,SP
Add with Carry
A ← (A) + (M) + (C)
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A9
B9
C9
D9
E9
F9
9E D9
9E E9
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
pp
rpp
prpp
prpp
rpp
rfp
pprpp
prpp
–
ADD #opr8i
ADD opr8a
ADD opr16a
ADD oprx16,X
ADD oprx8,X
ADD ,X
ADD oprx16,SP
ADD oprx8,SP
Add without Carry
A ← (A) + (M)
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
AB
BB
CB
DB
EB
FB
9E DB
9E EB
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
pp
rpp
prpp
prpp
rpp
rfp
pprpp
prpp
–
AIS #opr8i
Add Immediate Value (Signed) to
Stack Pointer
SP ← (SP) + (M)
IMM A7 ii 2pp – – – – – –
AIX #opr8i
Add Immediate Value (Signed) to
Index Register (H:X)
H:X ← (H:X) + (M)
IMM AF ii 2pp – – – – – –
AND #opr8i
AND opr8a
AND opr16a
AND oprx16,X
AND oprx8,X
AND ,X
AND oprx16,SP
AND oprx8,SP
Logical AND
A ← (A) & (M)
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A4
B4
C4
D4
E4
F4
9E D4
9E E4
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
pp
rpp
prpp
prpp
rpp
rfp
pprpp
prpp
0 – – –
ASL opr8a
ASLA
ASLX
ASL oprx8,X
ASL ,X
ASL oprx8,SP
Arithmetic Shift Left
(Same as LSL)
DIR
INH
INH
IX1
IX
SP1
38
48
58
68
78
9E 68
dd
ff
ff
5
1
1
5
4
6
rfwpp
p
p
rfwpp
rfwp
prfwpp
––
ASR opr8a
ASRA
ASRX
ASR oprx8,X
ASR ,X
ASR oprx8,SP
Arithmetic Shift Right DIR
INH
INH
IX1
IX
SP1
37
47
57
67
77
9E 67
dd
ff
ff
5
1
1
5
4
6
rfwpp
p
p
rfwpp
rfwp
prfwpp
––
BCC rel Branch if Carry Bit Clear
(if C = 0) REL 24 rr 3ppp – – – – – –
C
b0
b7
0
b0
b7
C
Chapter 7 Central Processor Unit (S08CPUV2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 85
BCLR n,opr8a Clear Bit n in Memory
(Mn ← 0)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
rfwpp
rfwpp
rfwpp
rfwpp
rfwpp
rfwpp
rfwpp
rfwpp
– – – – – –
BCS rel Branch if Carry Bit Set (if C = 1)
(Same as BLO) REL 25 rr 3ppp – – – – – –
BEQ rel Branch if Equal (if Z = 1) REL 27 rr 3ppp – – – – – –
BGE rel Branch if Greater Than or Equal To
(if N ⊕ V = 0) (Signed) REL 90 rr 3ppp – – – – – –
BGND
Enter active background if ENBDM=1
Waits for and processes BDM commands
until GO, TRACE1, or TAGGO
INH 82 5+ fp...ppp – – – – – –
BGT rel Branch if Greater Than (if Z | (N ⊕ V) = 0)
(Signed) REL 92 rr 3ppp – – – – – –
BHCC rel Branch if Half Carry Bit Clear (if H = 0) REL 28 rr 3ppp – – – – – –
BHCS rel Branch if Half Carry Bit Set (if H = 1) REL 29 rr 3ppp – – – – – –
BHI rel Branch if Higher (if C | Z = 0) REL 22 rr 3ppp – – – – – –
BHS rel Branch if Higher or Same (if C = 0)
(Same as BCC) REL 24 rr 3ppp – – – – – –
BIH rel Branch if IRQ Pin High (if IRQ pin = 1) REL 2F rr 3ppp – – – – – –
BIL rel Branch if IRQ Pin Low (if IRQ pin = 0) REL 2E rr 3ppp – – – – – –
BIT #opr8i
BIT opr8a
BIT opr16a
BIT oprx16,X
BIT oprx8,X
BIT ,X
BIT oprx16,SP
BIT oprx8,SP
Bit Test
(A) & (M)
(CCR Updated but Operands Not Changed)
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A5
B5
C5
D5
E5
F5
9E D5
9E E5
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
pp
rpp
prpp
prpp
rpp
rfp
pprpp
prpp
0 – – –
BLE rel Branch if Less Than or Equal To
(if Z | (N ⊕ V) = 1) (Signed) REL 93 rr 3ppp – – – – – –
BLO rel Branch if Lower (if C = 1) (Same as BCS) REL 25 rr 3ppp – – – – – –
BLS rel Branch if Lower or Same (if C | Z = 1) REL 23 rr 3ppp – – – – – –
BLT rel Branch if Less Than (if N ⊕ V = 1) (Signed) REL 91 rr 3ppp – – – – – –
BMC rel Branch if Interrupt Mask Clear (if I = 0) REL 2C rr 3ppp – – – – – –
BMI rel Branch if Minus (if N = 1) REL 2B rr 3ppp – – – – – –
BMS rel Branch if Interrupt Mask Set (if I = 1) REL 2D rr 3ppp – – – – – –
BNE rel Branch if Not Equal (if Z = 0) REL 26 rr 3ppp – – – – – –
BPL rel Branch if Plus (if N = 0) REL 2A rr 3ppp – – – – – –
Table 7-2. Instruction Set Summary (Sheet 2 of 9)
Source
Form
Operation
Address
Mode
Object Code
Cycles
Cyc-by-Cyc
Details
Affect
on CCR
VH I N Z C
Chapter 7 Central Processor Unit (S08CPUV2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
86 Freescale Semiconductor
BRA rel Branch Always (if I = 1) REL 20 rr 3ppp – – – – – –
BRCLR n,opr8a,rel Branch if Bit n in Memory Clear (if (Mn) = 0)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
rpppp
rpppp
rpppp
rpppp
rpppp
rpppp
rpppp
rpppp
– – – – –
BRN rel Branch Never (if I = 0) REL 21 rr 3ppp – – – – – –
BRSET n,opr8a,rel Branch if Bit n in Memory Set (if (Mn) = 1)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
rpppp
rpppp
rpppp
rpppp
rpppp
rpppp
rpppp
rpppp
– – – – –
BSET n,opr8a Set Bit n in Memory (Mn ← 1)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
rfwpp
rfwpp
rfwpp
rfwpp
rfwpp
rfwpp
rfwpp
rfwpp
– – – – – –
BSR rel
Branch to Subroutine
PC ← (PC) + $0002
push (PCL); SP ← (SP) – $0001
push (PCH); SP ← (SP) – $0001
PC ← (PC) + rel
REL AD rr 5ssppp – – – – – –
CBEQ opr8a,rel
CBEQA #opr8i,rel
CBEQX #opr8i,rel
CBEQ oprx8,X+,rel
CBEQ ,X+,rel
CBEQ oprx8,SP,rel
Compare and... Branch if (A) = (M)
Branch if (A) = (M)
Branch if (X) = (M)
Branch if (A) = (M)
Branch if (A) = (M)
Branch if (A) = (M)
DIR
IMM
IMM
IX1+
IX+
SP1
31
41
51
61
71
9E 61
dd rr
ii rr
ii rr
ff rr
rr
ff rr
5
4
4
5
5
6
rpppp
pppp
pppp
rpppp
rfppp
prpppp
– – – – – –
CLC Clear Carry Bit (C ← 0) INH 98 1p– – – – – 0
CLI Clear Interrupt Mask Bit (I ← 0) INH 9A 1p– – 0 – – –
CLR opr8a
CLRA
CLRX
CLRH
CLR oprx8,X
CLR ,X
CLR oprx8,SP
Clear M ← $00
A ← $00
X ← $00
H ← $00
M ← $00
M ← $00
M ← $00
DIR
INH
INH
INH
IX1
IX
SP1
3F
4F
5F
8C
6F
7F
9E 6F
dd
ff
ff
5
1
1
1
5
4
6
rfwpp
p
p
p
rfwpp
rfwp
prfwpp
0 – – 0 1 –
Table 7-2. Instruction Set Summary (Sheet 3 of 9)
Source
Form
Operation
Address
Mode
Object Code
Cycles
Cyc-by-Cyc
Details
Affect
on CCR
VH I N Z C
Chapter 7 Central Processor Unit (S08CPUV2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 87
CMP #opr8i
CMP opr8a
CMP opr16a
CMP oprx16,X
CMP oprx8,X
CMP ,X
CMP oprx16,SP
CMP oprx8,SP
Compare Accumulator with Memory
A – M
(CCR Updated But Operands Not Changed)
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A1
B1
C1
D1
E1
F1
9E D1
9E E1
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
pp
rpp
prpp
prpp
rpp
rfp
pprpp
prpp
––
COM opr8a
COMA
COMX
COM oprx8,X
COM ,X
COM oprx8,SP
Complement M ← (M)= $FF – (M)
(One’s Complement) A ← (A) = $FF – (A)
X ← (X) = $FF – (X)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
DIR
INH
INH
IX1
IX
SP1
33
43
53
63
73
9E 63
dd
ff
ff
5
1
1
5
4
6
rfwpp
p
p
rfwpp
rfwp
prfwpp
0 – – 1
CPHX opr16a
CPHX #opr16i
CPHX opr8a
CPHX oprx8,SP
Compare Index Register (H:X) with Memory
(H:X) – (M:M + $0001)
(CCR Updated But Operands Not Changed)
EXT
IMM
DIR
SP1
3E
65
75
9E F3
hh ll
jj kk
dd
ff
6
3
5
6
prrfpp
ppp
rrfpp
prrfpp
––
CPX #opr8i
CPX opr8a
CPX opr16a
CPX oprx16,X
CPX oprx8,X
CPX ,X
CPX oprx16,SP
CPX oprx8,SP
Compare X (Index Register Low) with
Memory
X – M
(CCR Updated But Operands Not Changed)
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A3
B3
C3
D3
E3
F3
9E D3
9E E3
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
pp
rpp
prpp
prpp
rpp
rfp
pprpp
prpp
––
DAA Decimal Adjust Accumulator
After ADD or ADC of BCD Values INH 72 1pU– –
DBNZ opr8a,rel
DBNZA rel
DBNZX rel
DBNZ oprx8,X,rel
DBNZ ,X,rel
DBNZ oprx8,SP,rel
Decrement A, X, or M and Branch if Not Zero
(if (result) ≠ 0)
DBNZX Affects X Not H
DIR
INH
INH
IX1
IX
SP1
3B
4B
5B
6B
7B
9E 6B
dd rr
rr
rr
ff rr
rr
ff rr
7
4
4
7
6
8
rfwpppp
fppp
fppp
rfwpppp
rfwppp
prfwpppp
– – – – – –
DEC opr8a
DECA
DECX
DEC oprx8,X
DEC ,X
DEC oprx8,SP
Decrement M ← (M) – $01
A ← (A) – $01
X ← (X) – $01
M ← (M) – $01
M ← (M) – $01
M ← (M) – $01
DIR
INH
INH
IX1
IX
SP1
3A
4A
5A
6A
7A
9E 6A
dd
ff
ff
5
1
1
5
4
6
rfwpp
p
p
rfwpp
rfwp
prfwpp
–– –
DIV Divide
A ← (H:A)÷(X); H ← Remainder INH 52 6fffffp – – – –
EOR #opr8i
EOR opr8a
EOR opr16a
EOR oprx16,X
EOR oprx8,X
EOR ,X
EOR oprx16,SP
EOR oprx8,SP
Exclusive OR Memory with Accumulator
A ← (A ⊕ M)
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A8
B8
C8
D8
E8
F8
9E D8
9E E8
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
pp
rpp
prpp
prpp
rpp
rfp
pprpp
prpp
0 – – –
Table 7-2. Instruction Set Summary (Sheet 4 of 9)
Source
Form
Operation
Address
Mode
Object Code
Cycles
Cyc-by-Cyc
Details
Affect
on CCR
VH I N Z C
Chapter 7 Central Processor Unit (S08CPUV2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
88 Freescale Semiconductor
INC opr8a
INCA
INCX
INC oprx8,X
INC ,X
INC oprx8,SP
Increment M ← (M) + $01
A ← (A) + $01
X ← (X) + $01
M ← (M) + $01
M ← (M) + $01
M ← (M) + $01
DIR
INH
INH
IX1
IX
SP1
3C
4C
5C
6C
7C
9E 6C
dd
ff
ff
5
1
1
5
4
6
rfwpp
p
p
rfwpp
rfwp
prfwpp
–– –
JMP opr8a
JMP opr16a
JMP oprx16,X
JMP oprx8,X
JMP ,X
Jump
PC ← Jump Address
DIR
EXT
IX2
IX1
IX
BC
CC
DC
EC
FC
dd
hh ll
ee ff
ff
3
4
4
3
3
ppp
pppp
pppp
ppp
ppp
– – – – – –
JSR opr8a
JSR opr16a
JSR oprx16,X
JSR oprx8,X
JSR ,X
Jump to Subroutine
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – $0001
Push (PCH); SP ← (SP) – $0001
PC ← Unconditional Address
DIR
EXT
IX2
IX1
IX
BD
CD
DD
ED
FD
dd
hh ll
ee ff
ff
5
6
6
5
5
ssppp
pssppp
pssppp
ssppp
ssppp
– – – – – –
LDA #opr8i
LDA opr8a
LDA opr16a
LDA oprx16,X
LDA oprx8,X
LDA ,X
LDA oprx16,SP
LDA oprx8,SP
Load Accumulator from Memory
A ← (M)
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A6
B6
C6
D6
E6
F6
9E D6
9E E6
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
pp
rpp
prpp
prpp
rpp
rfp
pprpp
prpp
0 – – –
LDHX #opr16i
LDHX opr8a
LDHX opr16a
LDHX ,X
LDHX oprx16,X
LDHX oprx8,X
LDHX oprx8,SP
Load Index Register (H:X)
H:X ← (M:M + $0001)
IMM
DIR
EXT
IX
IX2
IX1
SP1
45
55
32
9E AE
9E BE
9E CE
9E FE
jj kk
dd
hh ll
ee ff
ff
ff
3
4
5
5
6
5
5
ppp
rrpp
prrpp
prrfp
pprrpp
prrpp
prrpp
0 – – –
LDX #opr8i
LDX opr8a
LDX opr16a
LDX oprx16,X
LDX oprx8,X
LDX ,X
LDX oprx16,SP
LDX oprx8,SP
Load X (Index Register Low) from Memory
X ← (M)
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
AE
BE
CE
DE
EE
FE
9E DE
9E EE
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
pp
rpp
prpp
prpp
rpp
rfp
pprpp
prpp
0 – – –
LSL opr8a
LSLA
LSLX
LSL oprx8,X
LSL ,X
LSL oprx8,SP
Logical Shift Left
(Same as ASL)
DIR
INH
INH
IX1
IX
SP1
38
48
58
68
78
9E 68
dd
ff
ff
5
1
1
5
4
6
rfwpp
p
p
rfwpp
rfwp
prfwpp
––
LSR opr8a
LSRA
LSRX
LSR oprx8,X
LSR ,X
LSR oprx8,SP
Logical Shift Right DIR
INH
INH
IX1
IX
SP1
34
44
54
64
74
9E 64
dd
ff
ff
5
1
1
5
4
6
rfwpp
p
p
rfwpp
rfwp
prfwpp
–– 0
Table 7-2. Instruction Set Summary (Sheet 5 of 9)
Source
Form
Operation
Address
Mode
Object Code
Cycles
Cyc-by-Cyc
Details
Affect
on CCR
VH I N Z C
C
b0
b7
0
b0
b7
C0
Chapter 7 Central Processor Unit (S08CPUV2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 89
MOV opr8a,opr8a
MOV opr8a,X+
MOV #opr8i,opr8a
MOV ,X+,opr8a
Move
(M)destination ← (M)source
In IX+/DIR and DIR/IX+ Modes,
H:X ← (H:X) + $0001
DIR/DIR
DIR/IX+
IMM/DIR
IX+/DIR
4E
5E
6E
7E
dd dd
dd
ii dd
dd
5
5
4
5
rpwpp
rfwpp
pwpp
rfwpp
0 – – –
MUL Unsigned multiply
X:A ← (X) × (A) INH 42 5ffffp – 0– – – 0
NEG opr8a
NEGA
NEGX
NEG oprx8,X
NEG ,X
NEG oprx8,SP
Negate M ← – (M) = $00 – (M)
(Two’s Complement) A ← – (A) = $00 – (A)
X ← – (X) = $00 – (X)
M ← – (M) = $00 – (M)
M ← – (M) = $00 – (M)
M ← – (M) = $00 – (M)
DIR
INH
INH
IX1
IX
SP1
30
40
50
60
70
9E 60
dd
ff
ff
5
1
1
5
4
6
rfwpp
p
p
rfwpp
rfwp
prfwpp
––
NOP No Operation — Uses 1 Bus Cycle INH 9D 1p– – – – – –
NSA Nibble Swap Accumulator
A ← (A[3:0]:A[7:4]) INH 62 1p– – – – – –
ORA #opr8i
ORA opr8a
ORA opr16a
ORA oprx16,X
ORA oprx8,X
ORA ,X
ORA oprx16,SP
ORA oprx8,SP
Inclusive OR Accumulator and Memory
A ← (A) | (M)
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
AA
BA
CA
DA
EA
FA
9E DA
9E EA
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
pp
rpp
prpp
prpp
rpp
rfp
pprpp
prpp
0 – – –
PSHA Push Accumulator onto Stack
Push (A); SP ← (SP) – $0001 INH 87 2sp – – – – – –
PSHH Push H (Index Register High) onto Stack
Push (H); SP ← (SP) – $0001 INH 8B 2sp – – – – – –
PSHX Push X (Index Register Low) onto Stack
Push (X); SP ← (SP) – $0001 INH 89 2sp – – – – – –
PULA Pull Accumulator from Stack
SP ← (SP + $0001); Pull (A)INH 86 3ufp – – – – – –
PULH Pull H (Index Register High) from Stack
SP ← (SP + $0001); Pull (H)INH 8A 3ufp – – – – – –
PULX Pull X (Index Register Low) from Stack
SP ← (SP + $0001); Pull (X)INH 88 3ufp – – – – – –
ROL opr8a
ROLA
ROLX
ROL oprx8,X
ROL ,X
ROL oprx8,SP
Rotate Left through Carry DIR
INH
INH
IX1
IX
SP1
39
49
59
69
79
9E 69
dd
ff
ff
5
1
1
5
4
6
rfwpp
p
p
rfwpp
rfwp
prfwpp
––
ROR opr8a
RORA
RORX
ROR oprx8,X
ROR ,X
ROR oprx8,SP
Rotate Right through Carry DIR
INH
INH
IX1
IX
SP1
36
46
56
66
76
9E 66
dd
ff
ff
5
1
1
5
4
6
rfwpp
p
p
rfwpp
rfwp
prfwpp
––
Table 7-2. Instruction Set Summary (Sheet 6 of 9)
Source
Form
Operation
Address
Mode
Object Code
Cycles
Cyc-by-Cyc
Details
Affect
on CCR
VH I N Z C
C
b0
b7
b0
b7
C
Chapter 7 Central Processor Unit (S08CPUV2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
90 Freescale Semiconductor
RSP
Reset Stack Pointer (Low Byte)
SPL ← $FF
(High Byte Not Affected)
INH 9C 1p– – – – – –
RTI
Return from Interrupt
SP ← (SP) + $0001; Pull (CCR)
SP ← (SP) + $0001; Pull (A)
SP ← (SP) + $0001; Pull (X)
SP ← (SP) + $0001; Pull (PCH)
SP ← (SP) + $0001; Pull (PCL)
INH 80 9uuuuufppp
RTS
Return from Subroutine
SP ← SP + $0001; Pull (PCH)
SP ← SP + $0001; Pull (PCL)
INH 81 5ufppp – – – – – –
SBC #opr8i
SBC opr8a
SBC opr16a
SBC oprx16,X
SBC oprx8,X
SBC ,X
SBC oprx16,SP
SBC oprx8,SP
Subtract with Carry
A ← (A) – (M) – (C)
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A2
B2
C2
D2
E2
F2
9E D2
9E E2
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
pp
rpp
prpp
prpp
rpp
rfp
pprpp
prpp
––
SEC Set Carry Bit
(C ← 1) INH 99 1p– – – – – 1
SEI Set Interrupt Mask Bit
(I ← 1) INH 9B 1p– – 1 – – –
STA opr8a
STA opr16a
STA oprx16,X
STA oprx8,X
STA ,X
STA oprx16,SP
STA oprx8,SP
Store Accumulator in Memory
M ← (A)
DIR
EXT
IX2
IX1
IX
SP2
SP1
B7
C7
D7
E7
F7
9E D7
9E E7
dd
hh ll
ee ff
ff
ee ff
ff
3
4
4
3
2
5
4
wpp
pwpp
pwpp
wpp
wp
ppwpp
pwpp
0 – – –
STHX opr8a
STHX opr16a
STHX oprx8,SP
Store H:X (Index Reg.)
(M:M + $0001) ← (H:X)
DIR
EXT
SP1
35
96
9E FF
dd
hh ll
ff
4
5
5
wwpp
pwwpp
pwwpp
0 – – –
STOP
Enable Interrupts: Stop Processing
Refer to MCU Documentation
I bit ← 0; Stop Processing
INH 8E 2fp... – – 0 – – –
STX opr8a
STX opr16a
STX oprx16,X
STX oprx8,X
STX ,X
STX oprx16,SP
STX oprx8,SP
Store X (Low 8 Bits of Index Register)
in Memory
M ← (X)
DIR
EXT
IX2
IX1
IX
SP2
SP1
BF
CF
DF
EF
FF
9E DF
9E EF
dd
hh ll
ee ff
ff
ee ff
ff
3
4
4
3
2
5
4
wpp
pwpp
pwpp
wpp
wp
ppwpp
pwpp
0 – – –
Table 7-2. Instruction Set Summary (Sheet 7 of 9)
Source
Form
Operation
Address
Mode
Object Code
Cycles
Cyc-by-Cyc
Details
Affect
on CCR
VH I N Z C
Chapter 7 Central Processor Unit (S08CPUV2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 91
SUB #opr8i
SUB opr8a
SUB opr16a
SUB oprx16,X
SUB oprx8,X
SUB ,X
SUB oprx16,SP
SUB oprx8,SP
Subtract
A ← (A) – (M)
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
A0
B0
C0
D0
E0
F0
9E D0
9E E0
ii
dd
hh ll
ee ff
ff
ee ff
ff
2
3
4
4
3
3
5
4
pp
rpp
prpp
prpp
rpp
rfp
pprpp
prpp
––
SWI
Software Interrupt
PC ← (PC) + $0001
Push (PCL); SP ← (SP) – $0001
Push (PCH); SP ← (SP) – $0001
Push (X); SP ← (SP) – $0001
Push (A); SP ← (SP) – $0001
Push (CCR); SP ← (SP) – $0001
I ← 1;
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
INH 83 11 sssssvvfppp – – 1 – – –
TAP Transfer Accumulator to CCR
CCR ← (A) INH 84 1p
TAX
Transfer Accumulator to X (Index Register
Low)
X ← (A)
INH 97 1p– – – – – –
TPA Transfer CCR to Accumulator
A ← (CCR) INH 85 1p– – – – – –
TST opr8a
TSTA
TSTX
TST oprx8,X
TST ,X
TST oprx8,SP
Test for Negative or Zero (M) – $00
(A) – $00
(X) – $00
(M) – $00
(M) – $00
(M) – $00
DIR
INH
INH
IX1
IX
SP1
3D
4D
5D
6D
7D
9E 6D
dd
ff
ff
4
1
1
4
3
5
rfpp
p
p
rfpp
rfp
prfpp
0 – – –
TSX Transfer SP to Index Reg.
H:X ← (SP) + $0001 INH 95 2fp – – – – – –
TXA Transfer X (Index Reg. Low) to Accumulator
A ← (X) INH 9F 1p– – – – – –
Table 7-2. Instruction Set Summary (Sheet 8 of 9)
Source
Form
Operation
Address
Mode
Object Code
Cycles
Cyc-by-Cyc
Details
Affect
on CCR
VH I N Z C
Chapter 7 Central Processor Unit (S08CPUV2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
92 Freescale Semiconductor
TXS Transfer Index Reg. to SP
SP ← (H:X) – $0001 INH 94 2fp – – – – – –
WAIT Enable Interrupts; Wait for Interrupt
I bit ← 0; Halt CPU INH 8F 2+ fp... – – 0 – – –
Source Form: Everything in the source forms columns, except expressions in italic characters, is literal information which must appear in
the assembly source file exactly as shown. The initial 3- to 5-letter mnemonic and the characters (# , ( ) and +) are always a literal
characters.
nAny label or expression that evaluates to a single integer in the range 0-7.
opr8i Any label or expression that evaluates to an 8-bit immediate value.
opr16i Any label or expression that evaluates to a 16-bit immediate value.
opr8a Any label or expression that evaluates to an 8-bit direct-page address ($00xx).
opr16a Any label or expression that evaluates to a 16-bit address.
oprx8 Any label or expression that evaluates to an unsigned 8-bit value, used for indexed addressing.
oprx16 Any label or expression that evaluates to a 16-bit value, used for indexed addressing.
rel Any label or expression that refers to an address that is within –128 to +127 locations from the start of the next instruction.
Operation Symbols:
A Accumulator
CCR Condition code register
H Index register high byte
M Memory location
nAny bit
opr Operand (one or two bytes)
PC Program counter
PCH Program counter high byte
PCL Program counter low byte
rel Relative program counter offset byte
SP Stack pointer
SPL Stack pointer low byte
X Index register low byte
& Logical AND
| Logical OR
⊕Logical EXCLUSIVE OR
( ) Contents of
+Add
– Subtract, Negation (two’s complement)
×Multiply
÷Divide
# Immediate value
←Loaded with
: Concatenated with
Addressing Modes:
DIR Direct addressing mode
EXT Extended addressing mode
IMM Immediate addressing mode
INH Inherent addressing mode
IX Indexed, no offset addressing mode
IX1 Indexed, 8-bit offset addressing mode
IX2 Indexed, 16-bit offset addressing mode
IX+ Indexed, no offset, post increment addressing mode
IX1+ Indexed, 8-bit offset, post increment addressing mode
REL Relative addressing mode
SP1 Stack pointer, 8-bit offset addressing mode
SP2 Stack pointer 16-bit offset addressing mode
Cycle-by-Cycle Codes:
fFree cycle. This indicates a cycle where the CPU
does not require use of the system buses. An f
cycle is always one cycle of the system bus clock
and is always a read cycle.
pProgryam fetch; read from next consecutive
location in program memory
rRead 8-bit operand
s Push (write) one byte onto stack
uPop (read) one byte from stack
vRead vector from $FFxx (high byte first)
wWrite 8-bit operand
CCR Bits:
VOverflow bit
H Half-carry bit
I Interrupt mask
N Negative bit
Z Zero bit
C Carry/borrow bit
CCR Effects:
Set or cleared
– Not affected
U Undefined
Table 7-2. Instruction Set Summary (Sheet 9 of 9)
Source
Form
Operation
Address
Mode
Object Code
Cycles
Cyc-by-Cyc
Details
Affect
on CCR
VH I N Z C
Chapter 7 Central Processor Unit (S08CPUV2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 93
Table 7-3. Opcode Map (Sheet 1 of 2)
Bit-Manipulation Branch Read-Modify-Write Control Register/Memory
00 5
BRSET0
3DIR
10 5
BSET0
2DIR
20 3
BRA
2REL
30 5
NEG
2DIR
40 1
NEGA
1INH
50 1
NEGX
1INH
60 5
NEG
2IX1
70 4
NEG
1IX
80 9
RTI
1INH
90 3
BGE
2REL
A0 2
SUB
2IMM
B0 3
SUB
2DIR
C0 4
SUB
3 EXT
D0 4
SUB
3IX2
E0 3
SUB
2IX1
F0 3
SUB
1IX
01 5
BRCLR0
3DIR
11 5
BCLR0
2DIR
21 3
BRN
2REL
31 5
CBEQ
3DIR
41 4
CBEQA
3IMM
51 4
CBEQX
3IMM
61 5
CBEQ
3IX1+
71 5
CBEQ
2IX+
81 6
RTS
1INH
91 3
BLT
2REL
A1 2
CMP
2IMM
B1 3
CMP
2DIR
C1 4
CMP
3 EXT
D1 4
CMP
3IX2
E1 3
CMP
2IX1
F1 3
CMP
1IX
02 5
BRSET1
3DIR
12 5
BSET1
2DIR
22 3
BHI
2REL
32 5
LDHX
3EXT
42 5
MUL
1INH
52 6
DIV
1INH
62 1
NSA
1INH
72 1
DAA
1INH
82 5+
BGND
1INH
92 3
BGT
2REL
A2 2
SBC
2IMM
B2 3
SBC
2DIR
C2 4
SBC
3 EXT
D2 4
SBC
3IX2
E2 3
SBC
2IX1
F2 3
SBC
1IX
03 5
BRCLR1
3DIR
13 5
BCLR1
2DIR
23 3
BLS
2REL
33 5
COM
2DIR
43 1
COMA
1INH
53 1
COMX
1INH
63 5
COM
2IX1
73 4
COM
1IX
83 11
SWI
1INH
93 3
BLE
2REL
A3 2
CPX
2IMM
B3 3
CPX
2DIR
C3 4
CPX
3 EXT
D3 4
CPX
3IX2
E3 3
CPX
2IX1
F3 3
CPX
1IX
04 5
BRSET2
3DIR
14 5
BSET2
2DIR
24 3
BCC
2REL
34 5
LSR
2DIR
44 1
LSRA
1INH
54 1
LSRX
1INH
64 5
LSR
2IX1
74 4
LSR
1IX
84 1
TA P
1INH
94 2
TXS
1INH
A4 2
AND
2IMM
B4 3
AND
2DIR
C4 4
AND
3 EXT
D4 4
AND
3IX2
E4 3
AND
2IX1
F4 3
AND
1IX
05 5
BRCLR2
3DIR
15 5
BCLR2
2DIR
25 3
BCS
2REL
35 4
STHX
2DIR
45 3
LDHX
3IMM
55 4
LDHX
2DIR
65 3
CPHX
3IMM
75 5
CPHX
2DIR
85 1
TPA
1INH
95 2
TSX
1INH
A5 2
BIT
2IMM
B5 3
BIT
2DIR
C5 4
BIT
3 EXT
D5 4
BIT
3IX2
E5 3
BIT
2IX1
F5 3
BIT
1IX
06 5
BRSET3
3DIR
16 5
BSET3
2DIR
26 3
BNE
2REL
36 5
ROR
2DIR
46 1
RORA
1INH
56 1
RORX
1INH
66 5
ROR
2IX1
76 4
ROR
1IX
86 3
PULA
1INH
96 5
STHX
3EXT
A6 2
LDA
2IMM
B6 3
LDA
2DIR
C6 4
LDA
3 EXT
D6 4
LDA
3IX2
E6 3
LDA
2IX1
F6 3
LDA
1IX
07 5
BRCLR3
3DIR
17 5
BCLR3
2DIR
27 3
BEQ
2REL
37 5
ASR
2DIR
47 1
ASRA
1INH
57 1
ASRX
1INH
67 5
ASR
2IX1
77 4
ASR
1IX
87 2
PSHA
1INH
97 1
TA X
1INH
A7 2
AIS
2IMM
B7 3
STA
2DIR
C7 4
STA
3 EXT
D7 4
STA
3IX2
E7 3
STA
2IX1
F7 2
STA
1IX
08 5
BRSET4
3DIR
18 5
BSET4
2DIR
28 3
BHCC
2REL
38 5
LSL
2DIR
48 1
LSLA
1INH
58 1
LSLX
1INH
68 5
LSL
2IX1
78 4
LSL
1IX
88 3
PULX
1INH
98 1
CLC
1INH
A8 2
EOR
2IMM
B8 3
EOR
2DIR
C8 4
EOR
3 EXT
D8 4
EOR
3IX2
E8 3
EOR
2IX1
F8 3
EOR
1IX
09 5
BRCLR4
3DIR
19 5
BCLR4
2DIR
29 3
BHCS
2REL
39 5
ROL
2DIR
49 1
ROLA
1INH
59 1
ROLX
1INH
69 5
ROL
2IX1
79 4
ROL
1IX
89 2
PSHX
1INH
99 1
SEC
1INH
A9 2
ADC
2IMM
B9 3
ADC
2DIR
C9 4
ADC
3 EXT
D9 4
ADC
3IX2
E9 3
ADC
2IX1
F9 3
ADC
1IX
0A 5
BRSET5
3DIR
1A 5
BSET5
2DIR
2A 3
BPL
2REL
3A 5
DEC
2DIR
4A 1
DECA
1INH
5A 1
DECX
1INH
6A 5
DEC
2IX1
7A 4
DEC
1IX
8A 3
PULH
1INH
9A 1
CLI
1INH
AA 2
ORA
2IMM
BA 3
ORA
2DIR
CA 4
ORA
3 EXT
DA 4
ORA
3IX2
EA 3
ORA
2IX1
FA 3
ORA
1IX
0B 5
BRCLR5
3DIR
1B 5
BCLR5
2DIR
2B 3
BMI
2REL
3B 7
DBNZ
3DIR
4B 4
DBNZA
2INH
5B 4
DBNZX
2INH
6B 7
DBNZ
3IX1
7B 6
DBNZ
2IX
8B 2
PSHH
1INH
9B 1
SEI
1INH
AB 2
ADD
2IMM
BB 3
ADD
2DIR
CB 4
ADD
3 EXT
DB 4
ADD
3IX2
EB 3
ADD
2IX1
FB 3
ADD
1IX
0C 5
BRSET6
3DIR
1C 5
BSET6
2DIR
2C 3
BMC
2REL
3C 5
INC
2DIR
4C 1
INCA
1INH
5C 1
INCX
1INH
6C 5
INC
2IX1
7C 4
INC
1IX
8C 1
CLRH
1INH
9C 1
RSP
1INH
BC 3
JMP
2DIR
CC 4
JMP
3 EXT
DC 4
JMP
3IX2
EC 3
JMP
2IX1
FC 3
JMP
1IX
0D 5
BRCLR6
3DIR
1D 5
BCLR6
2DIR
2D 3
BMS
2REL
3D 4
TST
2DIR
4D 1
TSTA
1INH
5D 1
TSTX
1INH
6D 4
TST
2IX1
7D 3
TST
1IX
9D 1
NOP
1INH
AD 5
BSR
2REL
BD 5
JSR
2DIR
CD 6
JSR
3 EXT
DD 6
JSR
3IX2
ED 5
JSR
2IX1
FD 5
JSR
1IX
0E 5
BRSET7
3DIR
1E 5
BSET7
2DIR
2E 3
BIL
2REL
3E 6
CPHX
3EXT
4E 5
MOV
3DD
5E 5
MOV
2DIX+
6E 4
MOV
3IMD
7E 5
MOV
2IX+D
8E 2+
STOP
1INH
9E
Page 2 AE 2
LDX
2IMM
BE 3
LDX
2DIR
CE 4
LDX
3 EXT
DE 4
LDX
3IX2
EE 3
LDX
2IX1
FE 3
LDX
1IX
0F 5
BRCLR7
3DIR
1F 5
BCLR7
2DIR
2F 3
BIH
2REL
3F 5
CLR
2DIR
4F 1
CLRA
1INH
5F 1
CLRX
1INH
6F 5
CLR
2IX1
7F 4
CLR
1IX
8F 2+
WAIT
1INH
9F 1
TXA
1INH
AF 2
AIX
2IMM
BF 3
STX
2DIR
CF 4
STX
3 EXT
DF 4
STX
3IX2
EF 3
STX
2IX1
FF 2
STX
1IX
INH Inherent REL Relative SP1 Stack Pointer, 8-Bit Offset
IMM Immediate IX Indexed, No Offset SP2 Stack Pointer, 16-Bit Offset
DIR Direct IX1 Indexed, 8-Bit Offset IX+ Indexed, No Offset with
EXT Extended IX2 Indexed, 16-Bit Offset Post Increment
DD DIR to DIR IMD IMM to DIR IX1+ Indexed, 1-Byte Offset with
IX+D IX+ to DIR DIX+ DIR to IX+ Post Increment Opcode in
Hexadecimal
Number of Bytes
F0 3
SUB
1IX
HCS08 Cycles
Instruction Mnemonic
Addressing Mode
Chapter 7 Central Processor Unit (S08CPUV2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
94 Freescale Semiconductor
Bit-Manipulation Branch Read-Modify-Write Control Register/Memory
9E60 6
NEG
3SP1
9ED0 5
SUB
4SP2
9EE0 4
SUB
3SP1
9E61 6
CBEQ
4SP1
9ED1 5
CMP
4SP2
9EE1 4
CMP
3SP1
9ED2 5
SBC
4SP2
9EE2 4
SBC
3SP1
9E63 6
COM
3SP1
9ED3 5
CPX
4SP2
9EE3 4
CPX
3SP1
9EF3 6
CPHX
3SP1
9E64 6
LSR
3SP1
9ED4 5
AND
4SP2
9EE4 4
AND
3SP1
9ED5 5
BIT
4SP2
9EE5 4
BIT
3SP1
9E66 6
ROR
3SP1
9ED6 5
LDA
4SP2
9EE6 4
LDA
3SP1
9E67 6
ASR
3SP1
9ED7 5
STA
4SP2
9EE7 4
STA
3SP1
9E68 6
LSL
3SP1
9ED8 5
EOR
4SP2
9EE8 4
EOR
3SP1
9E69 6
ROL
3SP1
9ED9 5
ADC
4SP2
9EE9 4
ADC
3SP1
9E6A 6
DEC
3SP1
9EDA 5
ORA
4SP2
9EEA 4
ORA
3SP1
9E6B 8
DBNZ
4SP1
9EDB 5
ADD
4SP2
9EEB 4
ADD
3SP1
9E6C 6
INC
3SP1
9E6D 5
TST
3SP1
9EAE 5
LDHX
2IX
9EBE 6
LDHX
4IX2
9ECE 5
LDHX
3IX1
9EDE 5
LDX
4SP2
9EEE 4
LDX
3SP1
9EFE 5
LDHX
3SP1
9E6F 6
CLR
3SP1
9EDF 5
STX
4SP2
9EEF 4
STX
3SP1
9EFF 5
STHX
3SP1
INH Inherent REL Relative SP1 Stack Pointer, 8-Bit Offset
IMM Immediate IX Indexed, No Offset SP2 Stack Pointer, 16-Bit Offset
DIR Direct IX1 Indexed, 8-Bit Offset IX+ Indexed, No Offset with
EXT Extended IX2 Indexed, 16-Bit Offset Post Increment
DD DIR to DIR IMD IMM to DIR IX1+ Indexed, 1-Byte Offset with
IX+D IX+ to DIR DIX+ DIR to IX+ Post Increment
Note: All Sheet 2 Opcodes are Preceded by the Page 2 Prebyte (9E) Prebyte (9E) and Opcode in
Hexadecimal
Number of Bytes
9E60 6
NEG
3SP1
HCS08 Cycles
Instruction Mnemonic
Addressing Mode
Table 7-3. Opcode Map (Sheet 2 of 2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 95
Chapter 8
Analog-to-Digital Converter (ADC10V1)
8.1 Introduction
The 10-bit analog-to-digital converter (ADC) is a successive approximation ADC designed for operation
within an integrated microcontroller system-on-chip.
The ADC module design supports up to 28 separate analog inputs (AD0–AD27). Only four
(ADC1P0–ADC1P3) of the possible inputs are implemented on the MC9S08QD4 series MCU. These
inputs are selected by the ADCH bits.
Chapter 8 Analog-to-Digital Converter (ADC10V1)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
96 Freescale Semiconductor
Figure 8-1. MC9S08QD4 Series Block Diagram Highlighting ADC Block and Pins
8.1.1 Module Configurations
This section provides device-specific information for configuring the ADC on MC9S08QD4 series.
NOTES:
1Port pins are software configurable with pullup device if input port.
2Port pins are software configurable for output drive strength.
3Port pins are software configurable for output slew rate control.
4IRQ contains a software configurable (IRQPDD) pullup/pulldown device if PTA5 enabled as IRQ pin function (IRQPE = 1).
5RESET contains integrated pullup device if PTA5 enabled as reset pin function (RSTPE = 1).
6PTA5 does not contain a clamp diode to VDD and must not be driven above VDD. The voltage measured on this pin when
internal pullup is enabled may be as low as VDD – 0.7 V. The internal gates connected to this pin are pulled to VDD.
7PTA4 contains integrated pullup device if BKGD enabled (BKGDPE = 1).
8When pin functions as KBI (KBIPEn = 1) and associated pin is configured to enable the pullup device, KBEDGn can be used
to reconfigure the pullup as a pulldown device.
USER RAM
HCS08 CORE
CPU
BDC
2-CH 16-BIT TIMER/PWM
MODULE (TPM1)
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
RTI COP
IRQ LVD
VOLTAGE REGULATOR
PORT A
PTA5/TPM2CH0I/IRQ/RESET
PTA4/TPM2CH0O/BKGD/MS
PTA3/KBI1P3/TCLK2/ADC1P3
PTA2/KBI1P2/TCLK1/ADC1P2
PTA1/KBI1P1/TPM1CH1/ADC1P1
PTA0/KBI1P0/TPM1CH0/ADC1P0
4-BIT KEYBOARD
INTERRUPT MODULE (KBI)
256 / 128 BYTES
16 MHz INTERNAL CLOCK
SOURCE (ICS)
VSS
VDD
VSSA
VDDA
VREFL
VREFH
4
ANALOG-TO-DIGITAL
CONVERTER (ADC)
10-BIT
TPM1CH0
TPM1CH1
BKGD/MS
IRQ
4
1-CH 16-BIT TIMER/PWM
MODULE (TPM2)
TPM2CH0
USER FLASH
4096 / 2048 BYTES
TCLK2
TCLK1
Chapter 8 Analog-to-Digital Converter (ADC10V1)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 97
8.1.1.1 Channel Assignments
The ADC channel assignments for the MC9S08QD4 series devices are shown in Table 8-1. Reserved
channels convert to an unknown value.
8.1.1.2 Alternate Clock
The ADC is capable of performing conversions using the MCU bus clock, the bus clock divided by two,
or the local asynchronous clock (ADACK) within the module. The alternate clock, ALTCLK, input for the
MC9S08QD4 series MCU devices is not implemented.
8.1.1.3 Hardware Trigger
The ADC hardware trigger, ADHWT, is output from the real-time interrupt (RTI) counter. The RTI counter
can be clocked by either ICSERCLK or a nominal 32 kHz clock source within the RTI block.
The period of the RTI is determined by the input clock frequency and the RTIS bits. The RTI counter is a
free running counter that generates an overflow at the RTI rate determined by the RTIS bits. When the
ADC hardware trigger is enabled, a conversion is initiated upon a RTI counter overflow.
Table 8-1. ADC Channel Assignment
ADCH Channel Input Pin Control ADCH Channel Input Pin Control
00000 AD0 PTA0/ADC1P0 ADPC0 10000 AD16 VSS N/A
00001 AD1 PTA1/ADC1P1 ADPC1 10001 AD17 VSS N/A
00010 AD2 PTA2/ADC1P2 ADPC2 10010 AD18 VSS N/A
00011 AD3 PTA3/ADC1P3 ADPC3 10011 AD19 VSS N/A
00100 AD4 Vss N/A 10100 AD20 VSS N/A
00101 AD5 Vss N/A 10101 AD21 VSS N/A
00110 AD6 Vss N/A 10110 AD22 Reserved N/A
00111 AD7 Vss N/A 10111 AD23 Reserved N/A
01000 AD8 VSS N/A 11000 AD24 Reserved N/A
01001 AD9 VSS N/A 11001 AD25 Reserved N/A
01010 AD10 VSS N/A 11010 AD26 Temperature
Sensor1
1For information, see Section 8.1.1.5, “Temperature Sensor.”
N/A
01011 AD11 VSS N/A 11011 AD27 Internal Bandgap2
2Requires BGBE =1 in SPMSC1 see Section 5.8.8, “System Power Management Status and Control 1 Register (SPMSC1).”
For value of bandgap voltage reference see Appendix A.5, “DC Characteristics.”
N/A
01100 AD12 VSS N/A 11100 VREFH VDD N/A
01101 AD13 VSS N/A 11101 VREFH VDD N/A
01110 AD14 VSS N/A 11110 VREFL VSS N/A
01111 AD15 VSS N/A 11111 Module
Disabled
None N/A
Chapter 8 Analog-to-Digital Converter (ADC10V1)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
98 Freescale Semiconductor
The RTI can be configured to cause a hardware trigger in MCU run, wait, and stop3.
8.1.1.4 Analog Pin Enables
The ADC on MC9S08QD4 contains only one analog pin enable register, APCTL1.
8.1.1.5 Temperature Sensor
To use the on-chip temperature sensor, the user must perform the following:
• Configure ADC for long sample with a maximum of 1 MHz clock
• Convert the bandgap voltage reference channel (AD27)
— By converting the digital value of the bandgap voltage reference channel using the value of
VBG the user can determine VDD. For value of bandgap voltage, see Appendix A.5, “DC
Characteristics”.
• Convert the temperature sensor channel (AD26)
— By using the calculated value of VDD, convert the digital value of AD26 into a voltage, VTEMP
Equation 8-1 provides an approximate transfer function of the on-chip temperature sensor for VDD = 3.0V,
Temp = 25°C, using the ADC at fADCK = 1.0 MHz and configured for long sample.
TempC = 25 – ((VTEMP – 1.3894) / ( 0.0033)) Eqn. 8-1
0.0017 is the uncalibrated voltage versus temperature slope in V/°C. Uncalibrated accuracy of the
temperature sensor is approximately ±12°C, using Equation 8-1.
To improve accuracy the user must calibrate the bandgap voltage reference and temperature sensor.
Calibrating at 25°C will improve accuracy to ±4.5°C.
Calibration at 3 points, -40°C, 25°C and 105°C will improve accuracy to ±2.5°C. Once calibration has
been completed, the user will need to calculate the slope for both hot and cold. In application code, the
user would then calculate the temperature using Equation 8-1 as detailed above and then determine if the
temperature is above or below 25°C. Once determined if the temperature is above or below 25°C, the user
can recalculate the temperature using the hot or cold slope value obtained during calibration.
8.1.1.6 Low-Power Mode Operation
The ADC is capable of running in stop3 mode but requires LVDSE in SPMSC1 to be set.
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 99
8.1.2 Features
Features of the ADC module include:
• Linear successive approximation algorithm with 10 bits resolution.
• Up to 28 analog inputs.
• Output formatted in 10- or 8-bit right-justified format.
• Single or continuous conversion (automatic return to idle after single conversion).
• Configurable sample time and conversion speed/power.
• Conversion complete flag and interrupt.
• Input clock selectable from up to four sources.
• Operation in wait or stop3 modes for lower noise operation.
• Asynchronous clock source for lower noise operation.
• Selectable asynchronous hardware conversion trigger.
• Automatic compare with interrupt for less-than, or greater-than or equal-to, programmable value.
8.1.3 Block Diagram
Figure 8-2 provides a block diagram of the ADC module
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
100 Freescale Semiconductor
Figure 8-2. ADC Block Diagram
8.2 External Signal Description
The ADC module supports up to 28 separate analog inputs. It also requires four supply/reference/ground
connections.
Table 8-2. Signal Properties
Name Function
AD27–AD0 Analog Channel inputs
VREFH High reference voltage
VREFL Low reference voltage
VDDAD Analog power supply
VSSAD Analog ground
AD0
• • •
AD27
VREFH
VREFL
ADVIN
ADCH
Control Sequencer
initialize
sample
convert
transfer
abort
Clock
Divide
ADCK
÷2
Async
Clock Gen
Bus Clock
ALTCLK
ADICLK
ADIV
ADACK
ADCO
ADLSMP
ADLPC
MODE
complete
Data Registers
SAR Converter
Compare Value Registers
Compare
Value
Sum
AIEN
COCO
Interrupt
AIEN
COCO
ADTRG
1
2
1 2
MCU STOP
ADHWT
Logic
ACFGT
3
Compare true
3Compare true ADCCFG
ADCSC1
ADCSC2
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 101
8.2.1 Analog Power (VDDAD)
The ADC analog portion uses VDDAD as its power connection. In some packages, VDDAD is connected
internally to VDD. If externally available, connect the VDDAD pin to the same voltage potential as VDD.
External filtering may be necessary to ensure clean VDDAD for good results.
8.2.2 Analog Ground (VSSAD)
The ADC analog portion uses VSSAD as its ground connection. In some packages, VSSAD is connected
internally to VSS. If externally available, connect the VSSAD pin to the same voltage potential as VSS.
8.2.3 Voltage Reference High (VREFH)
VREFH is the high reference voltage for the converter. In some packages, VREFH is connected internally to
VDDAD. If externally available, VREFH may be connected to the same potential as VDDAD, or may be
driven by an external source that is between the minimum VDDAD spec and the VDDAD potential (VREFH
must never exceed VDDAD).
8.2.4 Voltage Reference Low (VREFL)
VREFL is the low reference voltage for the converter. In some packages, VREFL is connected internally to
VSSAD. If externally available, connect the VREFL pin to the same voltage potential as VSSAD.
8.2.5 Analog Channel Inputs (ADx)
The ADC module supports up to 28 separate analog inputs. An input is selected for conversion through
the ADCH channel select bits.
8.3 Register Definition
These memory mapped registers control and monitor operation of the ADC:
• Status and control register, ADCSC1
• Status and control register, ADCSC2
• Data result registers, ADCRH and ADCRL
• Compare value registers, ADCCVH and ADCCVL
• Configuration register, ADCCFG
• Pin enable registers, APCTL1, APCTL2, APCTL3
8.3.1 Status and Control Register 1 (ADCSC1)
This section describes the function of the ADC status and control register (ADCSC1). Writing ADCSC1
aborts the current conversion and initiates a new conversion (if the ADCH bits are equal to a value other
than all 1s).
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
102 Freescale Semiconductor
7654 3 210
RCOCO
AIEN ADCO ADCH
W
Reset:0001 1 111
= Unimplemented or Reserved
Figure 8-3. Status and Control Register (ADCSC1)
Table 8-3. ADCSC1 Register Field Descriptions
Field Description
7
COCO
Conversion Complete Flag — The COCO flag is a read-only bit which is set each time a conversion is
completed when the compare function is disabled (ACFE = 0). When the compare function is enabled (ACFE =
1) the COCO flag is set upon completion of a conversion only if the compare result is true. This bit is cleared
whenever ADCSC1 is written or whenever ADCRL is read.
0 Conversion not completed
1 Conversion completed
6
AIEN
Interrupt Enable — AIEN is used to enable conversion complete interrupts. When COCO becomes set while
AIEN is high, an interrupt is asserted.
0 Conversion complete interrupt disabled
1 Conversion complete interrupt enabled
5
ADCO
Continuous Conversion Enable — ADCO is used to enable continuous conversions.
0 One conversion following a write to the ADCSC1 when software triggered operation is selected, or one
conversion following assertion of ADHWT when hardware triggered operation is selected.
1 Continuous conversions initiated following a write to ADCSC1 when software triggered operation is selected.
Continuous conversions are initiated by an ADHWT event when hardware triggered operation is selected.
4:0
ADCH
Input Channel Select — The ADCH bits form a 5-bit field which is used to select one of the input channels. The
input channels are detailed in Figure 8-4.
The successive approximation converter subsystem is turned off when the channel select bits are all set to 1.
This feature allows for explicit disabling of the ADC and isolation of the input channel from all sources.
Terminating continuous conversions this way will prevent an additional, single conversion from being performed.
It is not necessary to set the channel select bits to all 1s to place the ADC in a low-power state when continuous
conversions are not enabled because the module automatically enters a low-power state when a conversion
completes.
Figure 8-4. Input Channel Select
ADCH Input Select ADCH Input Select
00000 AD0 10000 AD16
00001 AD1 10001 AD17
00010 AD2 10010 AD18
00011 AD3 10011 AD19
00100 AD4 10100 AD20
00101 AD5 10101 AD21
00110 AD6 10110 AD22
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 103
8.3.2 Status and Control Register 2 (ADCSC2)
The ADCSC2 register is used to control the compare function, conversion trigger and conversion active
of the ADC module.
Figure 8-5. Status and Control Register 2 (ADCSC2)
00111 AD7 10111 AD23
01000 AD8 11000 AD24
01001 AD9 11001 AD25
01010 AD10 11010 AD26
01011 AD11 11011 AD27
01100 AD12 11100 Reserved
01101 AD13 11101 VREFH
01110 AD14 11110 VREFL
01111 AD15 11111 Module disabled
7654 3 210
RADACT
ADTRG ACFE ACFGT
00
R1
1Bits 1 and 0 are reserved bits that must always be written to 0.
R1
W
Reset:0000 0 000
= Unimplemented or Reserved
Table 8-4. ADCSC2 Register Field Descriptions
Field Description
7
ADACT
Conversion Active — ADACT indicates that a conversion is in progress. ADACT is set when a conversion is
initiated and cleared when a conversion is completed or aborted.
0 Conversion not in progress
1 Conversion in progress
6
ADTRG
Conversion Trigger Select — ADTRG is used to select the type of trigger to be used for initiating a conversion.
Two types of trigger are selectable: software trigger and hardware trigger. When software trigger is selected, a
conversion is initiated following a write to ADCSC1. When hardware trigger is selected, a conversion is initiated
following the assertion of the ADHWT input.
0 Software trigger selected
1 Hardware trigger selected
Figure 8-4. Input Channel Select (continued)
ADCH Input Select ADCH Input Select
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
104 Freescale Semiconductor
8.3.3 Data Result High Register (ADCRH)
ADCRH contains the upper two bits of the result of a 10-bit conversion. When configured for 8-bit
conversions both ADR8 and ADR9 are equal to zero. ADCRH is updated each time a conversion
completes except when automatic compare is enabled and the compare condition is not met. In 10-bit
MODE, reading ADCRH prevents the ADC from transferring subsequent conversion results into the result
registers until ADCRL is read. If ADCRL is not read until after the next conversion is completed, then the
intermediate conversion result will be lost. In 8-bit mode there is no interlocking with ADCRL. In the case
that the MODE bits are changed, any data in ADCRH becomes invalid.
8.3.4 Data Result Low Register (ADCRL)
ADCRL contains the lower eight bits of the result of a 10-bit conversion, and all eight bits of an 8-bit
conversion. This register is updated each time a conversion completes except when automatic compare is
enabled and the compare condition is not met. In 10-bit mode, reading ADCRH prevents the ADC from
transferring subsequent conversion results into the result registers until ADCRL is read. If ADCRL is not
read until the after next conversion is completed, then the intermediate conversion results will be lost. In
8-bit mode, there is no interlocking with ADCRH. In the case that the MODE bits are changed, any data
in ADCRL becomes invalid.
5
ACFE
Compare Function Enable — ACFE is used to enable the compare function.
0 Compare function disabled
1 Compare function enabled
4
ACFGT
Compare Function Greater Than Enable — ACFGT is used to configure the compare function to trigger when
the result of the conversion of the input being monitored is greater than or equal to the compare value. The
compare function defaults to triggering when the result of the compare of the input being monitored is less than
the compare value.
0 Compare triggers when input is less than compare level
1 Compare triggers when input is greater than or equal to compare level
7 6543210
R 0 0 0 0 0 0 ADR9 ADR8
W
Reset: 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 8-6. Data Result High Register (ADCRH)
Table 8-4. ADCSC2 Register Field Descriptions (continued)
Field Description
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 105
8.3.5 Compare Value High Register (ADCCVH)
This register holds the upper two bits of the 10-bit compare value. These bits are compared to the upper
two bits of the result following a conversion in 10-bit mode when the compare function is enabled.In 8-bit
operation, ADCCVH is not used during compare.
8.3.6 Compare Value Low Register (ADCCVL)
This register holds the lower 8 bits of the 10-bit compare value, or all 8 bits of the 8-bit compare value.
Bits ADCV7:ADCV0 are compared to the lower 8 bits of the result following a conversion in either 10-bit
or 8-bit mode.
8.3.7 Configuration Register (ADCCFG)
ADCCFG is used to select the mode of operation, clock source, clock divide, and configure for low power
or long sample time.
7 6543210
R ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
W
Reset: 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 8-7. Data Result Low Register (ADCRL)
7654 3 210
R0 0 0 0
ADCV9 ADCV8
W
Reset:0000 0 000
= Unimplemented or Reserved
Figure 8-8. Compare Value High Register (ADCCVH)
7 6543210
R
ADCV7 ADCV6 ADCV5 ADCV4 ADCV3 ADCV2 ADCV1 ADCV0
W
Reset: 0 0 0 0 0 0 0 0
Figure 8-9. Compare Value Low Register(ADCCVL)
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
106 Freescale Semiconductor
7654 3 210
R
ADLPC ADIV ADLSMP MODE ADICLK
W
Reset:0000 0 000
Figure 8-10. Configuration Register (ADCCFG)
Table 8-5. ADCCFG Register Field Descriptions
Field Description
7
ADLPC
Low Power Configuration — ADLPC controls the speed and power configuration of the successive
approximation converter. This is used to optimize power consumption when higher sample rates are not required.
0 High speed configuration
1 Low power configuration: {FC31}The power is reduced at the expense of maximum clock speed.
6:5
ADIV
Clock Divide Select — ADIV select the divide ratio used by the ADC to generate the internal clock ADCK.
Ta b l e 8 - 6 shows the available clock configurations.
4
ADLSMP
Long Sample Time Configuration — ADLSMP selects between long and short sample time. This adjusts the
sample period to allow higher impedance inputs to be accurately sampled or to maximize conversion speed for
lower impedance inputs. Longer sample times can also be used to lower overall power consumption when
continuous conversions are enabled if high conversion rates are not required.
0 Short sample time
1 Long sample time
3:2
MODE
Conversion Mode Selection — MODE bits are used to select between 10- or 8-bit operation. See Ta b l e 8 - 7 .
1:0
ADICLK
Input Clock Select — ADICLK bits select the input clock source to generate the internal clock ADCK. See
Ta b l e 8 - 8 .
Table 8-6. Clock Divide Select
ADIV Divide Ratio Clock Rate
00 1 Input clock
01 2 Input clock ÷ 2
10 4 Input clock ÷ 4
11 8 Input clock ÷ 8
Table 8-7. Conversion Modes
MODE Mode Description
00 8-bit conversion (N=8)
01 Reserved
10 10-bit conversion (N=10)
11 Reserved
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 107
8.3.8 Pin Control 1 Register (APCTL1)
The pin control registers are used to disable the I/O port control of MCU pins used as analog inputs.
APCTL1 is used to control the pins associated with channels 0–7 of the ADC module.
Table 8-8. Input Clock Select
ADICLK Selected Clock Source
00 Bus clock
01 Bus clock divided by 2
10 Alternate clock (ALTCLK)
11 Asynchronous clock (ADACK)
7654 3 210
R
ADPC7 ADPC6 ADPC5 ADPC4 ADPC3 ADPC2 ADPC1 ADPC0
W
Reset:0000 0 000
Figure 8-11. Pin Control 1 Register (APCTL1)
Table 8-9. APCTL1 Register Field Descriptions
Field Description
7
ADPC7
ADC Pin Control 7 — ADPC7 is used to control the pin associated with channel AD7.
0 AD7 pin I/O control enabled
1 AD7 pin I/O control disabled
6
ADPC6
ADC Pin Control 6 — ADPC6 is used to control the pin associated with channel AD6.
0 AD6 pin I/O control enabled
1 AD6 pin I/O control disabled
5
ADPC5
ADC Pin Control 5 — ADPC5 is used to control the pin associated with channel AD5.
0 AD5 pin I/O control enabled
1 AD5 pin I/O control disabled
4
ADPC4
ADC Pin Control 4 — ADPC4 is used to control the pin associated with channel AD4.
0 AD4 pin I/O control enabled
1 AD4 pin I/O control disabled
3
ADPC3
ADC Pin Control 3 — ADPC3 is used to control the pin associated with channel AD3.
0 AD3 pin I/O control enabled
1 AD3 pin I/O control disabled
2
ADPC2
ADC Pin Control 2 — ADPC2 is used to control the pin associated with channel AD2.
0 AD2 pin I/O control enabled
1 AD2 pin I/O control disabled
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
108 Freescale Semiconductor
8.3.9 Pin Control 2 Register (APCTL2)
APCTL2 is used to control channels 8–15 of the ADC module.
1
ADPC1
ADC Pin Control 1 — ADPC1 is used to control the pin associated with channel AD1.
0 AD1 pin I/O control enabled
1 AD1 pin I/O control disabled
0
ADPC0
ADC Pin Control 0 — ADPC0 is used to control the pin associated with channel AD0.
0 AD0 pin I/O control enabled
1 AD0 pin I/O control disabled
7654 3 210
R
ADPC15 ADPC14 ADPC13 ADPC12 ADPC11 ADPC10 ADPC9 ADPC8
W
Reset:0000 0 000
Figure 8-12. Pin Control 2 Register (APCTL2)
Table 8-10. APCTL2 Register Field Descriptions
Field Description
7
ADPC15
ADC Pin Control 15 — ADPC15 is used to control the pin associated with channel AD15.
0 AD15 pin I/O control enabled
1 AD15 pin I/O control disabled
6
ADPC14
ADC Pin Control 14 — ADPC14 is used to control the pin associated with channel AD14.
0 AD14 pin I/O control enabled
1 AD14 pin I/O control disabled
5
ADPC13
ADC Pin Control 13 — ADPC13 is used to control the pin associated with channel AD13.
0 AD13 pin I/O control enabled
1 AD13 pin I/O control disabled
4
ADPC12
ADC Pin Control 12 — ADPC12 is used to control the pin associated with channel AD12.
0 AD12 pin I/O control enabled
1 AD12 pin I/O control disabled
3
ADPC11
ADC Pin Control 11 — ADPC11 is used to control the pin associated with channel AD11.
0 AD11 pin I/O control enabled
1 AD11 pin I/O control disabled
2
ADPC10
ADC Pin Control 10 — ADPC10 is used to control the pin associated with channel AD10.
0 AD10 pin I/O control enabled
1 AD10 pin I/O control disabled
Table 8-9. APCTL1 Register Field Descriptions (continued)
Field Description
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 109
8.3.10 Pin Control 3 Register (APCTL3)
APCTL3 is used to control channels 16–23 of the ADC module.
1
ADPC9
ADC Pin Control 9 — ADPC9 is used to control the pin associated with channel AD9.
0 AD9 pin I/O control enabled
1 AD9 pin I/O control disabled
0
ADPC8
ADC Pin Control 8 — ADPC8 is used to control the pin associated with channel AD8.
0 AD8 pin I/O control enabled
1 AD8 pin I/O control disabled
7654 3 210
R
ADPC23 ADPC22 ADPC21 ADPC20 ADPC19 ADPC18 ADPC17 ADPC16
W
Reset:0000 0 000
Figure 8-13. Pin Control 3 Register (APCTL3)
Table 8-11. APCTL3 Register Field Descriptions
Field Description
7
ADPC23
ADC Pin Control 23 — ADPC23 is used to control the pin associated with channel AD23.
0 AD23 pin I/O control enabled
1 AD23 pin I/O control disabled
6
ADPC22
ADC Pin Control 22 — ADPC22 is used to control the pin associated with channel AD22.
0 AD22 pin I/O control enabled
1 AD22 pin I/O control disabled
5
ADPC21
ADC Pin Control 21 — ADPC21 is used to control the pin associated with channel AD21.
0 AD21 pin I/O control enabled
1 AD21 pin I/O control disabled
4
ADPC20
ADC Pin Control 20 — ADPC20 is used to control the pin associated with channel AD20.
0 AD20 pin I/O control enabled
1 AD20 pin I/O control disabled
3
ADPC19
ADC Pin Control 19 — ADPC19 is used to control the pin associated with channel AD19.
0 AD19 pin I/O control enabled
1 AD19 pin I/O control disabled
2
ADPC18
ADC Pin Control 18 — ADPC18 is used to control the pin associated with channel AD18.
0 AD18 pin I/O control enabled
1 AD18 pin I/O control disabled
Table 8-10. APCTL2 Register Field Descriptions (continued)
Field Description
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
110 Freescale Semiconductor
8.4 Functional Description
The ADC module is disabled during reset or when the ADCH bits are all high. The module is idle when a
conversion has completed and another conversion has not been initiated. When idle, the module is in its
lowest power state.
The ADC can perform an analog-to-digital conversion on any of the software selectable channels. The
selected channel voltage is converted by a successive approximation algorithm into an 11-bit digital result.
In 8-bit mode, the selected channel voltage is converted by a successive approximation algorithm into a
9-bit digital result.
When the conversion is completed, the result is placed in the data registers (ADCRH and ADCRL).In
10-bit mode, the result is rounded to 10 bits and placed in ADCRH and ADCRL. In 8-bit mode, the result
is rounded to 8 bits and placed in ADCRL. The conversion complete flag (COCO) is then set and an
interrupt is generated if the conversion complete interrupt has been enabled (AIEN = 1).
The ADC module has the capability of automatically comparing the result of a conversion with the
contents of its compare registers. The compare function is enabled by setting the ACFE bit and operates
in conjunction with any of the conversion modes and configurations.
8.4.1 Clock Select and Divide Control
One of four clock sources can be selected as the clock source for the ADC module. This clock source is
then divided by a configurable value to generate the input clock to the converter (ADCK). The clock is
selected from one of the following sources by means of the ADICLK bits.
• The bus clock, which is equal to the frequency at which software is executed. This is the default
selection following reset.
• The bus clock divided by 2. For higher bus clock rates, this allows a maximum divide by 16 of the
bus clock.
• ALTCLK, as defined for this MCU (See module section introduction).
• The asynchronous clock (ADACK) – This clock is generated from a clock source within the ADC
module. When selected as the clock source this clock remains active while the MCU is in wait or
stop3 mode and allows conversions in these modes for lower noise operation.
Whichever clock is selected, its frequency must fall within the specified frequency range for ADCK. If the
available clocks are too slow, the ADC will not perform according to specifications. If the available clocks
1
ADPC17
ADC Pin Control 17 — ADPC17 is used to control the pin associated with channel AD17.
0 AD17 pin I/O control enabled
1 AD17 pin I/O control disabled
0
ADPC16
ADC Pin Control 16 — ADPC16 is used to control the pin associated with channel AD16.
0 AD16 pin I/O control enabled
1 AD16 pin I/O control disabled
Table 8-11. APCTL3 Register Field Descriptions (continued)
Field Description
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 111
are too fast, then the clock must be divided to the appropriate frequency. This divider is specified by the
ADIV bits and can be divide-by 1, 2, 4, or 8.
8.4.2 Input Select and Pin Control
The pin control registers (APCTL3, APCTL2, and APCTL1) are used to disable the I/O port control of the
pins used as analog inputs.When a pin control register bit is set, the following conditions are forced for the
associated MCU pin:
• The output buffer is forced to its high impedance state.
• The input buffer is disabled. A read of the I/O port returns a zero for any pin with its input buffer
disabled.
• The pullup is disabled.
8.4.3 Hardware Trigger
The ADC module has a selectable asynchronous hardware conversion trigger, ADHWT, that is enabled
when the ADTRG bit is set. This source is not available on all MCUs. Consult the module introduction for
information on the ADHWT source specific to this MCU.
When ADHWT source is available and hardware trigger is enabled (ADTRG=1), a conversion is initiated
on the rising edge of ADHWT. If a conversion is in progress when a rising edge occurs, the rising edge is
ignored. In continuous convert configuration, only the initial rising edge to launch continuous conversions
is observed. The hardware trigger function operates in conjunction with any of the conversion modes and
configurations.
8.4.4 Conversion Control
Conversions can be performed in either 10-bit mode or 8-bit mode as determined by the MODE bits.
Conversions can be initiated by either a software or hardware trigger. In addition, the ADC module can be
configured for low power operation, long sample time, continuous conversion, and automatic compare of
the conversion result to a software determined compare value.
8.4.4.1 Initiating Conversions
A conversion is initiated:
• Following a write to ADCSC1 (with ADCH bits not all 1s) if software triggered operation is
selected.
• Following a hardware trigger (ADHWT) event if hardware triggered operation is selected.
• Following the transfer of the result to the data registers when continuous conversion is enabled.
If continuous conversions are enabled a new conversion is automatically initiated after the completion of
the current conversion. In software triggered operation, continuous conversions begin after ADCSC1 is
written and continue until aborted. In hardware triggered operation, continuous conversions begin after a
hardware trigger event and continue until aborted.
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
112 Freescale Semiconductor
8.4.4.2 Completing Conversions
A conversion is completed when the result of the conversion is transferred into the data result registers,
ADCRH and ADCRL. This is indicated by the setting of COCO. An interrupt is generated if AIEN is high
at the time that COCO is set.
A blocking mechanism prevents a new result from overwriting previous data in ADCRH and ADCRL if
the previous data is in the process of being read while in 10-bit MODE (the ADCRH register has been read
but the ADCRL register has not). When blocking is active, the data transfer is blocked, COCO is not set,
and the new result is lost. In the case of single conversions with the compare function enabled and the
compare condition false, blocking has no effect and ADC operation is terminated. In all other cases of
operation, when a data transfer is blocked, another conversion is initiated regardless of the state of ADCO
(single or continuous conversions enabled).
If single conversions are enabled, the blocking mechanism could result in several discarded conversions
and excess power consumption. To avoid this issue, the data registers must not be read after initiating a
single conversion until the conversion completes.
8.4.4.3 Aborting Conversions
Any conversion in progress will be aborted when:
• A write to ADCSC1 occurs (the current conversion will be aborted and a new conversion will be
initiated, if ADCH are not all 1s).
• A write to ADCSC2, ADCCFG, ADCCVH, or ADCCVL occurs. This indicates a mode of
operation change has occurred and the current conversion is therefore invalid.
• The MCU is reset.
• The MCU enters stop mode with ADACK not enabled.
When a conversion is aborted, the contents of the data registers, ADCRH and ADCRL, are not altered but
continue to be the values transferred after the completion of the last successful conversion. In the case that
the conversion was aborted by a reset, ADCRH and ADCRL return to their reset states.
8.4.4.4 Power Control
The ADC module remains in its idle state until a conversion is initiated. If ADACK is selected as the
conversion clock source, the ADACK clock generator is also enabled.
Power consumption when active can be reduced by setting ADLPC. This results in a lower maximum
value for fADCK (see the electrical specifications).
8.4.4.5 Total Conversion Time
The total conversion time depends on the sample time (as determined by ADLSMP), the MCU bus
frequency, the conversion mode (8-bit or 10-bit), and the frequency of the conversion clock (fADCK). After
the module becomes active, sampling of the input begins. ADLSMP is used to select between short and
long sample times.When sampling is complete, the converter is isolated from the input channel and a
successive approximation algorithm is performed to determine the digital value of the analog signal. The
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 113
result of the conversion is transferred to ADCRH and ADCRL upon completion of the conversion
algorithm.
If the bus frequency is less than the fADCK frequency, precise sample time for continuous conversions
cannot be guaranteed when short sample is enabled (ADLSMP=0). If the bus frequency is less than 1/11th
of the fADCK frequency, precise sample time for continuous conversions cannot be guaranteed when long
sample is enabled (ADLSMP=1).
The maximum total conversion time for different conditions is summarized in Table 8-12.
The maximum total conversion time is determined by the clock source chosen and the divide ratio selected.
The clock source is selectable by the ADICLK bits, and the divide ratio is specified by the ADIV bits. For
example, in 10-bit mode, with the bus clock selected as the input clock source, the input clock divide-by-1
ratio selected, and a bus frequency of 8 MHz, then the conversion time for a single conversion is:
NOTE
The ADCK frequency must be between fADCK minimum and fADCK
maximum to meet ADC specifications.
Table 8-12. Total Conversion Time vs. Control Conditions
Conversion Type ADICLK ADLSMP Max Total Conversion Time
Single or first continuous 8-bit 0x, 10 0 20 ADCK cycles + 5 bus clock cycles
Single or first continuous 10-bit 0x, 10 0 23 ADCK cycles + 5 bus clock cycles
Single or first continuous 8-bit 0x, 10 1 40 ADCK cycles + 5 bus clock cycles
Single or first continuous 10-bit 0x, 10 1 43 ADCK cycles + 5 bus clock cycles
Single or first continuous 8-bit 11 0 5 μs + 20 ADCK + 5 bus clock cycles
Single or first continuous 10-bit 11 0 5 μs + 23 ADCK + 5 bus clock cycles
Single or first continuous 8-bit 11 1 5 μs + 40 ADCK + 5 bus clock cycles
Single or first continuous 10-bit 11 1 5 μs + 43 ADCK + 5 bus clock cycles
Subsequent continuous 8-bit;
fBUS > fADCK
xx 0 17 ADCK cycles
Subsequent continuous 10-bit;
fBUS > fADCK
xx 0 20 ADCK cycles
Subsequent continuous 8-bit;
fBUS > fADCK/11
xx 1 37 ADCK cycles
Subsequent continuous 10-bit;
fBUS > fADCK/11
xx 1 40 ADCK cycles
23 ADCK
cyc
Conversion time =
8 MHz/1
Number of bus cycles = 3.5 μs x 8 MHz = 28 cycles
5 bus cyc
8 MHz
+
= 3.5 μs
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
114 Freescale Semiconductor
8.4.5 Automatic Compare Function
The compare function can be configured to check for either an upper limit or lower limit. After the input
is sampled and converted, the result is added to the two’s complement of the compare value (ADCCVH
and ADCCVL). When comparing to an upper limit (ACFGT = 1), if the result is greater-than or equal-to
the compare value, COCO is set. When comparing to a lower limit (ACFGT = 0), if the result is less than
the compare value, COCO is set. The value generated by the addition of the conversion result and the two’s
complement of the compare value is transferred to ADCRH and ADCRL.
Upon completion of a conversion while the compare function is enabled, if the compare condition is not
true, COCO is not set and no data is transferred to the result registers. An ADC interrupt is generated upon
the setting of COCO if the ADC interrupt is enabled (AIEN = 1).
NOTE
The compare function can be used to monitor the voltage on a channel while
the MCU is in either wait or stop3 mode. The ADC interrupt will wake the
MCU when the compare condition is met.
8.4.6 MCU Wait Mode Operation
The WAIT instruction puts the MCU in a lower power-consumption standby mode from which recovery
is very fast because the clock sources remain active. If a conversion is in progress when the MCU enters
wait mode, it continues until completion. Conversions can be initiated while the MCU is in wait mode by
means of the hardware trigger or if continuous conversions are enabled.
The bus clock, bus clock divided by two, and ADACK are available as conversion clock sources while in
wait mode. The use of ALTCLK as the conversion clock source in wait is dependent on the definition of
ALTCLK for this MCU. Consult the module introduction for information on ALTCLK specific to this
MCU.
A conversion complete event sets the COCO and generates an ADC interrupt to wake the MCU from wait
mode if the ADC interrupt is enabled (AIEN = 1).
8.4.7 MCU Stop3 Mode Operation
The STOP instruction is used to put the MCU in a low power-consumption standby mode during which
most or all clock sources on the MCU are disabled.
8.4.7.1 Stop3 Mode With ADACK Disabled
If the asynchronous clock, ADACK, is not selected as the conversion clock, executing a STOP instruction
aborts the current conversion and places the ADC in its idle state. The contents of ADCRH and ADCRL
are unaffected by stop3 mode.After exiting from stop3 mode, a software or hardware trigger is required to
resume conversions.
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 115
8.4.7.2 Stop3 Mode With ADACK Enabled
If ADACK is selected as the conversion clock, the ADC continues operation during stop3 mode. For
guaranteed ADC operation, the MCU’s voltage regulator must remain active during stop3 mode. Consult
the module introduction for configuration information for this MCU.
If a conversion is in progress when the MCU enters stop3 mode, it continues until completion. Conversions
can be initiated while the MCU is in stop3 mode by means of the hardware trigger or if continuous
conversions are enabled.
A conversion complete event sets the COCO and generates an ADC interrupt to wake the MCU from stop3
mode if the ADC interrupt is enabled (AIEN = 1).
NOTE
It is possible for the ADC module to wake the system from low power stop
and cause the MCU to begin consuming run-level currents without
generating a system level interrupt. To prevent this scenario, software must
ensure that the data transfer blocking mechanism (discussed in
Section 8.4.4.2, “Completing Conversions,”) is cleared when entering stop3
and continuing ADC conversions.
8.4.8 MCU Stop1 and Stop2 Mode Operation
The ADC module is automatically disabled when the MCU enters either stop1 or stop2 mode. All module
registers contain their reset values following exit from stop1 or stop2. Therefore the module must be
re-enabled and re-configured following exit from stop1 or stop2.
8.5 Initialization Information
This section gives an example which provides some basic direction on how a user would initialize and
configure the ADC module. The user has the flexibility of choosing between configuring the module for
8-bit or 10-bit resolution, single or continuous conversion, and a polled or interrupt approach, among many
other options. Refer to Table 8-6, Table 8-7, and Table 8-8 for information used in this example.
NOTE
Hexadecimal values designated by a preceding 0x, binary values designated
by a preceding %, and decimal values have no preceding character.
8.5.1 ADC Module Initialization Example
8.5.1.1 Initialization Sequence
Before the ADC module can be used to complete conversions, an initialization procedure must be
performed. A typical sequence is as follows:
1. Update the configuration register (ADCCFG) to select the input clock source and the divide ratio
used to generate the internal clock, ADCK. This register is also used for selecting sample time and
low-power configuration.
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
116 Freescale Semiconductor
2. Update status and control register 2 (ADCSC2) to select the conversion trigger (hardware or
software) and compare function options, if enabled.
3. Update status and control register 1 (ADCSC1) to select whether conversions will be continuous
or completed only once, and to enable or disable conversion complete interrupts. The input channel
on which conversions will be performed is also selected here.
8.5.1.2 Pseudo — Code Example
In this example, the ADC module will be set up with interrupts enabled to perform a single 10-bit
conversion at low power with a long sample time on input channel 1, where the internal ADCK clock will
be derived from the bus clock divided by 1.
ADCCFG = 0x98 (%10011000)
Bit 7 ADLPC 1 Configures for low power (lowers maximum clock speed)
Bit 6:5 ADIV 00 Sets the ADCK to the input clock ÷ 1
Bit 4 ADLSMP 1 Configures for long sample time
Bit 3:2 MODE 10 Sets mode at 10-bit conversions
Bit 1:0 ADICLK 00 Selects bus clock as input clock source
ADCSC2 = 0x00 (%00000000)
Bit 7 ADACT 0 Flag indicates if a conversion is in progress
Bit 6 ADTRG 0 Software trigger selected
Bit 5 ACFE 0 Compare function disabled
Bit 4 ACFGT 0 Not used in this example
Bit 3:2 00 Unimplemented or reserved, always reads zero
Bit 1:0 00 Reserved for Freescale’s internal use; always write zero
ADCSC1 = 0x41 (%01000001)
Bit 7 COCO 0 Read-only flag which is set when a conversion completes
Bit 6 AIEN 1 Conversion complete interrupt enabled
Bit 5 ADCO 0 One conversion only (continuous conversions disabled)
Bit 4:0 ADCH 00001 Input channel 1 selected as ADC input channel
ADCRH/L = 0xxx
Holds results of conversion. Read high byte (ADCRH) before low byte (ADCRL) so that conversion
data cannot be overwritten with data from the next conversion.
ADCCVH/L = 0xxx
Holds compare value when compare function enabled
APCTL1=0x02
AD1 pin I/O control disabled. All other AD pins remain general purpose I/O pins
APCTL2=0x00
All other AD pins remain general purpose I/O pins
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 117
Figure 8-14. Initialization Flowchart for Example
8.6 Application Information
This section contains information for using the ADC module in applications. The ADC has been designed
to be integrated into a microcontroller for use in embedded control applications requiring an A/D
converter.
8.6.1 External Pins and Routing
The following sections discuss the external pins associated with the ADC module and how they must be
used for best results.
8.6.1.1 Analog Supply Pins
The ADC module has analog power and ground supplies (VDDAD and VSSAD) which are available as
separate pins on some devices. On other devices, VSSAD is shared on the same pin as the MCU digital VSS,
and on others, both VSSAD and VDDAD are shared with the MCU digital supply pins. In these cases, there
are separate pads for the analog supplies which are bonded to the same pin as the corresponding digital
supply so that some degree of isolation between the supplies is maintained.
When available on a separate pin, both VDDAD and VSSAD must be connected to the same voltage potential
as their corresponding MCU digital supply (VDD and VSS) and must be routed carefully for maximum
noise immunity and bypass capacitors placed as near as possible to the package.
YES
NO
RESET
INITIALIZE ADC
ADCCFG = $98
ADCSC1 = $41
ADCSC2 = $00
CHECK
COCO=1?
READ ADCRH
THEN ADCRL TO
CLEAR COCO BIT
CONTINUE
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
118 Freescale Semiconductor
In cases where separate power supplies are used for analog and digital power, the ground connection
between these supplies must be at the VSSAD pin. This must be the only ground connection between these
supplies if possible. The VSSAD pin makes a good single point ground location.
8.6.1.2 Analog Reference Pins
In addition to the analog supplies, the ADC module has connections for two reference voltage inputs. The
high reference is VREFH, which may be shared on the same pin as VDDAD on some devices. The low
reference is VREFL, which may be shared on the same pin as VSSAD on some devices.
When available on a separate pin, VREFH may be connected to the same potential as VDDAD, or may be
driven by an external source that is between the minimum VDDAD spec and the VDDAD potential (VREFH
must never exceed VDDAD). When available on a separate pin, VREFL must be connected to the same
voltage potential as VSSAD. Both VREFH and VREFL must be routed carefully for maximum noise
immunity and bypass capacitors placed as near as possible to the package.
AC current in the form of current spikes required to supply charge to the capacitor array at each successive
approximation step is drawn through the VREFH and VREFL loop. The best external component to meet this
current demand is a 0.1 μF capacitor with good high frequency characteristics. This capacitor is connected
between VREFH and VREFL and must be placed as near as possible to the package pins. Resistance in the
path is not recommended because the current will cause a voltage drop which could result in conversion
errors. Inductance in this path must be minimum (parasitic only).
8.6.1.3 Analog Input Pins
The external analog inputs are typically shared with digital I/O pins on MCU devices. The pin I/O control
is disabled by setting the appropriate control bit in one of the pin control registers. Conversions can be
performed on inputs without the associated pin control register bit set. It is recommended that the pin
control register bit always be set when using a pin as an analog input. This avoids problems with contention
because the output buffer will be in its high impedance state and the pullup is disabled. Also, the input
buffer draws dc current when its input is not at either VDD or VSS. Setting the pin control register bits for
all pins used as analog inputs must be done to achieve lowest operating current.
Empirical data shows that capacitors on the analog inputs improve performance in the presence of noise
or when the source impedance is high. Use of 0.01 μF capacitors with good high-frequency characteristics
is sufficient. These capacitors are not necessary in all cases, but when used they must be placed as near as
possible to the package pins and be referenced to VSSA.
For proper conversion, the input voltage must fall between VREFH and VREFL. If the input is equal to or
exceeds VREFH, the converter circuit converts the signal to $3FF (full scale 10-bit representation) or $FF
(full scale 8-bit representation). If the input is equal to or less than VREFL, the converter circuit converts it
to $000. Input voltages between VREFH and VREFL are straight-line linear conversions. There will be a
brief current associated with VREFL when the sampling capacitor is charging. The input is sampled for
3.5 cycles of the ADCK source when ADLSMP is low, or 23.5 cycles when ADLSMP is high.
For minimal loss of accuracy due to current injection, pins adjacent to the analog input pins must not be
transitioning during conversions.
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 119
8.6.2 Sources of Error
Several sources of error exist for A/D conversions. These are discussed in the following sections.
8.6.2.1 Sampling Error
For proper conversions, the input must be sampled long enough to achieve the proper accuracy. Given the
maximum input resistance of approximately 7kΩ and input capacitance of approximately 5.5 pF, sampling
to within 1/4LSB (at 10-bit resolution) can be achieved within the minimum sample window (3.5 cycles @
8 MHz maximum ADCK frequency) provided the resistance of the external analog source (RAS) is kept
below 5 kΩ.
Higher source resistances or higher-accuracy sampling is possible by setting ADLSMP (to increase the
sample window to 23.5 cycles) or decreasing ADCK frequency to increase sample time.
8.6.2.2 Pin Leakage Error
Leakage on the I/O pins can cause conversion error if the external analog source resistance (RAS) is high.
If this error cannot be tolerated by the application, keep RAS lower than VDDAD /(2
N*ILEAK) for less than
1/4LSB leakage error (N = 8 in 8-bit mode or 10 in 10-bit mode).
8.6.2.3 Noise-Induced Errors
System noise which occurs during the sample or conversion process can affect the accuracy of the
conversion. The ADC accuracy numbers are guaranteed as specified only if the following conditions are
met:
• There is a 0.1 μF low-ESR capacitor from VREFH to VREFL.
• There is a 0.1 μF low-ESR capacitor from VDDAD to VSSAD.
• If inductive isolation is used from the primary supply, an additional 1 μF capacitor is placed from
VDDAD to VSSAD.
•V
SSAD (and VREFL, if connected) is connected to VSS at a quiet point in the ground plane.
• Operate the MCU in wait or stop3 mode before initiating (hardware triggered conversions) or
immediately after initiating (hardware or software triggered conversions) the ADC conversion.
— For software triggered conversions, immediately follow the write to the ADCSC1 with a WAIT
instruction or STOP instruction.
— For stop3 mode operation, select ADACK as the clock source. Operation in stop3 reduces VDD
noise but increases effective conversion time due to stop recovery.
• There is no I/O switching, input or output, on the MCU during the conversion.
There are some situations where external system activity causes radiated or conducted noise emissions or
excessive VDD noise is coupled into the ADC. In these situations, or when the MCU cannot be placed in
wait or stop3 or I/O activity cannot be halted, these recommended actions may reduce the effect of noise
on the accuracy:
• Place a 0.01 μF capacitor (CAS) on the selected input channel to VREFL or VSSAD (this will
improve noise issues but will affect sample rate based on the external analog source resistance).
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
120 Freescale Semiconductor
• Average the result by converting the analog input many times in succession and dividing the sum
of the results. Four samples are required to eliminate the effect of a 1LSB, one-time error.
• Reduce the effect of synchronous noise by operating off the asynchronous clock (ADACK) and
averaging. Noise that is synchronous to ADCK cannot be averaged out.
8.6.2.4 Code Width and Quantization Error
The ADC quantizes the ideal straight-line transfer function into 1024 steps (in 10-bit mode). Each step
ideally has the same height (1 code) and width. The width is defined as the delta between the transition
points to one code and the next. The ideal code width for an N bit converter (in this case N can be 8 or 10),
defined as 1LSB, is:
1LSB = (VREFH - VREFL) / 2NEqn. 8-2
There is an inherent quantization error due to the digitization of the result. For 8-bit or 10-bit conversions
the code will transition when the voltage is at the midpoint between the points where the straight line
transfer function is exactly represented by the actual transfer function. Therefore, the quantization error
will be ± 1/2LSB in 8- or 10-bit mode. As a consequence, however, the code width of the first ($000)
conversion is only 1/2LSB and the code width of the last ($FF or $3FF) is 1.5LSB.
8.6.2.5 Linearity Errors
The ADC may also exhibit non-linearity of several forms. Every effort has been made to reduce these
errors but the system must be aware of them because they affect overall accuracy. These errors are:
• Zero-scale error (EZS) (sometimes called offset) — This error is defined as the difference between
the actual code width of the first conversion and the ideal code width (1/2LSB). Note, if the first
conversion is $001, then the difference between the actual $001 code width and its ideal (1LSB) is
used.
• Full-scale error (EFS) — This error is defined as the difference between the actual code width of
the last conversion and the ideal code width (1.5LSB). Note, if the last conversion is $3FE, then the
difference between the actual $3FE code width and its ideal (1LSB) is used.
• Differential non-linearity (DNL) — This error is defined as the worst-case difference between the
actual code width and the ideal code width for all conversions.
• Integral non-linearity (INL) — This error is defined as the highest-value the (absolute value of the)
running sum of DNL achieves. More simply, this is the worst-case difference of the actual
transition voltage to a given code and its corresponding ideal transition voltage, for all codes.
• Total unadjusted error (TUE) — This error is defined as the difference between the actual transfer
function and the ideal straight-line transfer function, and therefore includes all forms of error.
8.6.2.6 Code Jitter, Non-Monotonicity and Missing Codes
Analog-to-digital converters are susceptible to three special forms of error. These are code jitter,
non-monotonicity, and missing codes.
Code jitter is when, at certain points, a given input voltage converts to one of two values when sampled
repeatedly. Ideally, when the input voltage is infinitesimally smaller than the transition voltage, the
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 121
converter yields the lower code (and vice-versa). However, even very small amounts of system noise can
cause the converter to be indeterminate (between two codes) for a range of input voltages around the
transition voltage. This range is normally around ±1/2 LSB and will increase with noise. This error may be
reduced by repeatedly sampling the input and averaging the result. Additionally the techniques discussed
in Section 8.6.2.3, “Noise-Induced Errors,” will reduce this error.
Non-monotonicity is defined as when, except for code jitter, the converter converts to a lower code for a
higher input voltage. Missing codes are those values which are never converted for any input value.
In 8-bit or 10-bit mode, the ADC is guaranteed to be monotonic and to have no missing codes.
Analog-to-Digital Converter (S08ADC10V1)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
122 Freescale Semiconductor
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 123
Chapter 9
Internal Clock Source (S08ICSV1)
9.1 Introduction
The internal clock source (ICS) module provides clock source choices for the MCU. The module contains
a frequency-locked loop (FLL) as a clock source that is controllable by an internal reference clock. The
module can provide this FLL clock or the internal reference clock as a source for the MCU system clock,
ICSOUT.
Whichever clock source is chosen, ICSOUT is passed through a bus clock divider (BDIV) which allows a
lower final output clock frequency to be derived. ICSOUT is two times the bus frequency.
Figure 9-1 Shows the MC9S08QD4 series with the ICS module highlighted.
9.1.1 ICS Configuration Information
Bit-1 and bit-2 of ICS control register 1 (ICSC1) always read as 1.
Chapter 9 Internal Clock Source (S08ICSV1)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
124 Freescale Semiconductor
Figure 9-1. MC9S08QD4 Series Block Diagram Highlighting ICS Block
NOTES:
1Port pins are software configurable with pullup device if input port.
2Port pins are software configurable for output drive strength.
3Port pins are software configurable for output slew rate control.
4IRQ contains a software configurable (IRQPDD) pullup/pulldown device if PTA5 enabled as IRQ pin function (IRQPE = 1).
5RESET contains integrated pullup device if PTA5 enabled as reset pin function (RSTPE = 1).
6PTA5 does not contain a clamp diode to VDD and must not be driven above VDD. The voltage measured on this pin when
internal pullup is enabled may be as low as VDD – 0.7 V. The internal gates connected to this pin are pulled to VDD.
7PTA4 contains integrated pullup device if BKGD enabled (BKGDPE = 1).
8When pin functions as KBI (KBIPEn = 1) and associated pin is configured to enable the pullup device, KBEDGn can be used
to reconfigure the pullup as a pulldown device.
USER RAM
HCS08 CORE
CPU
BDC
2-CH 16-BIT TIMER/PWM
MODULE (TPM1)
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
RTI COP
IRQ LVD
VOLTAGE REGULATOR
PORT A
PTA5/TPM2CH0I/IRQ/RESET
PTA4/TPM2CH0O/BKGD/MS
PTA3/KBI1P3/TCLK2/ADC1P3
PTA2/KBI1P2/TCLK1/ADC1P2
PTA1/KBI1P1/TPM1CH1/ADC1P1
PTA0/KBI1P0/TPM1CH0/ADC1P0
4-BIT KEYBOARD
INTERRUPT MODULE (KBI)
256 / 128 BYTES
16 MHz INTERNAL CLOCK
SOURCE (ICS)
VSS
VDD
VSSA
VDDA
VREFL
VREFH
4
ANALOG-TO-DIGITAL
CONVERTER (ADC)
10-BIT
TPM1CH0
TPM1CH1
BKGD/MS
IRQ
4
1-CH 16-BIT TIMER/PWM
MODULE (TPM2)
TPM2CH0
USER FLASH
4096 / 2048 BYTES
TCLK2
TCLK1
Internal Clock Source (S08ICSV1)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 125
9.1.2 Features
Key features of the ICS module are:
• Frequency-locked loop (FLL) is trimmable for accuracy
— 0.2% resolution using internal 32 kHz reference
— 2% deviation over voltage and temperature using internal 32 kHz reference
• Internal or external reference clocks up to 5 MHz can be used to control the FLL
— 3 bit select for reference divider is provided
• Internal reference clock has 9 trim bits available
• Internal or external reference clocks can be selected as the clock source for the MCU
• Whichever clock is selected as the source can be divided down
— 2 bit select for clock divider is provided
– Allowable dividers are: 1, 2, 4, 8
– BDC clock is provided as a constant divide by 2 of the DCO output
• Control signals for a low power oscillator as the external reference clock are provided
— HGO, RANGE, EREFS, ERCLKEN, EREFSTEN
• FLL engaged internal mode is automatically selected out of reset
9.1.3 Modes of Operation
There are seven modes of operation for the ICS: FEI, FEE, FBI, FBILP, FBE, FBELP, and stop.
9.1.3.1 FLL Engaged Internal (FEI)
In FLL engaged internal mode, which is the default mode, the ICS supplies a clock derived from the FLL
which is controlled by the internal reference clock. The BDC clock is supplied from the FLL.
9.1.3.2 FLL Engaged External (FEE)
In FLL engaged external mode, the ICS supplies a clock derived from the FLL which is controlled by an
external reference clock. The BDC clock is supplied from the FLL.
9.1.3.3 FLL Bypassed Internal (FBI)
In FLL bypassed internal mode, the FLL is enabled and controlled by the internal reference clock, but is
bypassed. The ICS supplies a clock derived from the internal reference clock. The BDC clock is supplied
from the FLL.
9.1.3.4 FLL Bypassed Internal Low Power (FBILP)
In FLL bypassed internal low power mode, the FLL is disabled and bypassed, and the ICS supplies a clock
derived from the internal reference clock. The BDC clock is not available.
Internal Clock Source (S08ICSV1)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
126 Freescale Semiconductor
9.1.3.5 FLL Bypassed External (FBE)
In FLL bypassed external mode, the FLL is enabled and controlled by an external reference clock, but is
bypassed. The ICS supplies a clock derived from the external reference clock. The external reference clock
can be an external crystal/resonator supplied by an OSC controlled by the ICS, or it can be another external
clock source. The BDC clock is supplied from the FLL.
9.1.3.6 FLL Bypassed External Low Power (FBELP)
In FLL bypassed external low power mode, the FLL is disabled and bypassed, and the ICS supplies a clock
derived from the external reference clock. The external reference clock can be an external crystal/resonator
supplied by an OSC controlled by the ICS, or it can be another external clock source. The BDC clock is
not available.
9.1.3.7 Stop (STOP)
In stop mode the FLL is disabled and the internal or external reference clocks can be selected to be enabled
or disabled. The BDC clock is not available and the ICS does not provide an MCU clock source.
9.1.4 Block Diagram
Figure 9-2 is the ICS block diagram.
Figure 9-2. Internal Clock Source (ICS) Block Diagram
DCO
Filter
RDIV
TRIM
/ 2
9
External Reference
IREFS
Clock Source
Block
CLKS
n=0-7
/ 2n
n=0-3
/ 2n
Internal
Reference
Clock
BDIV
9ICSLCLK
ICSOUT
ICSIRCLK
EREFS
RANGE
EREFSTEN
HGO
Optional
IREFSTEN
ICSERCLK
Internal Clock Source Block
LP
ICSFFCLK
ERCLKEN
IRCLKEN
DCOOUT
FLL
RDIV_CLK
Internal Clock Source (S08ICSV1)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 127
9.2 External Signal Description
There are no ICS signals that connect off chip.
9.3 Register Definition
9.3.1 ICS Control Register 1 (ICSC1)
7 6543210
R
CLKS RDIV IREFS IRCLKEN IREFSTEN
W
Reset: 0 0 0 0 0 1 0 0
Figure 9-3. ICS Control Register 1 (ICSC1)
Table 9-1. ICS Control Register 1 Field Descriptions
Field Description
7:6
CLKS
Clock Source Select — Selects the clock source that controls the bus frequency. The actual bus frequency
depends on the value of the BDIV bits.
00 Output of FLL is selected.
01 Internal reference clock is selected.
10 External reference clock is selected.
11 Reserved, defaults to 00.
5:3
RDIV
Reference Divider — Selects the amount to divide down the FLL reference clock selected by the IREFS bits.
Resulting frequency must be in the range 31.25 kHz to 39.0625 kHz.
000 Encoding 0 — Divides reference clock by 1 (reset default)
001 Encoding 1 — Divides reference clock by 2
010 Encoding 2 — Divides reference clock by 4
011 Encoding 3 — Divides reference clock by 8
100 Encoding 4 — Divides reference clock by 16
101 Encoding 5 — Divides reference clock by 32
110 Encoding 6 — Divides reference clock by 64
111 Encoding 7 — Divides reference clock by 128
2
IREFS
Internal Reference Select — The IREFS bit selects the reference clock source for the FLL.
1 Internal reference clock selected
0 External reference clock selected
1
IRCLKEN
Internal Reference Clock Enable — The IRCLKEN bit enables the internal reference clock for use as
ICSIRCLK.
1 ICSIRCLK active
0 ICSIRCLK inactive
0
IREFSTEN
Internal Reference Stop Enable — The IREFSTEN bit controls whether or not the internal reference clock
remains enabled when the ICS enters stop mode.
1 Internal reference clock stays enabled in stop if IRCLKEN is set or if ICS is in FEI, FBI, or FBILP mode before
entering stop
0 Internal reference clock is disabled in stop
Internal Clock Source (S08ICSV1)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
128 Freescale Semiconductor
9.3.2 ICS Control Register 2 (ICSC2)
7 6543210
R
BDIV RANGE HGO LP EREFS ERCLKEN EREFSTEN
W
Reset:0 1000000
Figure 9-4. ICS Control Register 2 (ICSC2)
Table 9-2. ICS Control Register 2 Field Descriptions
Field Description
7:6
BDIV
Bus Frequency Divider — Selects the amount to divide down the clock source selected by the CLKS bits. This
controls the bus frequency.
00 Encoding 0 — Divides selected clock by 1
01 Encoding 1 — Divides selected clock by 2 (reset default)
10 Encoding 2 — Divides selected clock by 4
11 Encoding 3 — Divides selected clock by 8
5
RANGE
Frequency Range Select — Selects the frequency range for the external oscillator.
1 High frequency range selected for the external oscillator
0 Low frequency range selected for the external oscillator
4
HGO
High Gain Oscillator Select — The HGO bit controls the external oscillator mode of operation.
1 Configure external oscillator for high gain operation
0 Configure external oscillator for low power operation
3
LP
Low Power Select — The LP bit controls whether the FLL is disabled in FLL bypassed modes.
1 FLL is disabled in bypass modes unless BDM is active
0 FLL is not disabled in bypass mode
2
EREFS
External Reference Select — The EREFS bit selects the source for the external reference clock.
1 Oscillator requested
0 External Clock Source requested
1
ERCLKEN
External Reference Enable — The ERCLKEN bit enables the external reference clock for use as ICSERCLK.
1ICSERCLK active
0 ICSERCLK inactive
0
EREFSTEN
External Reference Stop Enable — The EREFSTEN bit controls whether or not the external reference clock
remains enabled when the ICS enters stop mode.
1 External reference clock stays enabled in stop if ERCLKEN is set or if ICS is in FEE, FBE, or FBELP mode
before entering stop
0 External reference clock is disabled in stop
Internal Clock Source (S08ICSV1)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 129
9.3.3 ICS Trim Register (ICSTRM)
9.3.4 ICS Status and Control (ICSSC)
7 6543210
R
TRIM
W
POR: 1 0 0 0 0 0 0 0
Reset:U UUUUUUU
Figure 9-5. ICS Trim Register (ICSTRM)
Table 9-3. ICS Trim Register Field Descriptions
Field Description
7:0
TRIM
ICS Trim Setting — The TRIM bits control the internal reference clock frequency by controlling the internal
reference clock period. The bits’ effect are binary weighted (i.e., bit 1 will adjust twice as much as bit 0).
Increasing the binary value in TRIM will increase the period, and decreasing the value will decrease the period.
An additional fine trim bit is available in ICSSC as the FTRIM bit.
7 6543210
R 0 0 0 0 CLKST OSCINIT
FTRIM
W
POR:
Reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
U
Figure 9-6. ICS Status and Control Register (ICSSC)
Table 9-4. ICS Status and Control Register Field Descriptions
Field Description
7:4 Reserved, must be cleared.
3:2
CLKST
Clock Mode Status — The CLKST bits indicate the current clock mode. The CLKST bits don’t update
immediately after a write to the CLKS bits due to internal synchronization between clock domains.
00 Output of FLL is selected.
01 FLL Bypassed, Internal reference clock is selected.
10 FLL Bypassed, External reference clock is selected.
11 Reserved.
1OSC Initialization — If the external reference clock is selected by ERCLKEN or by the ICS being in FEE, FBE,
or FBELP mode, and if EREFS is set, then this bit is set after the initialization cycles of the external oscillator
clock have completed. This bit is cleared only when either ERCLKEN or EREFS are cleared.
0ICS Fine Trim — The FTRIM bit controls the smallest adjustment of the internal reference clock frequency.
Setting FTRIM will increase the period and clearing FTRIM will decrease the period by the smallest amount
possible.
Internal Clock Source (S08ICSV1)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
130 Freescale Semiconductor
9.4 Functional Description
9.4.1 Operational Modes
Figure 9-7. Clock Switching Modes
The seven states of the ICS are shown as a state diagram and are described below. The arrows indicate the
allowed movements between the states.
9.4.1.1 FLL Engaged Internal (FEI)
FLL engaged internal (FEI) is the default mode of operation and is entered when all the following
conditions occur:
• CLKS bits are written to 00
• IREFS bit is written to 1
• RDIV bits are written to divide trimmed reference clock to be within the range of 31.25 kHz to
39.0625 kHz.
In FLL engaged internal mode, the ICSOUT clock is derived from the FLL clock, which is controlled by
the internal reference clock. The FLL loop will lock the frequency to 512 times the filter frequency, as
selected by the RDIV bits. The ICSLCLK is available for BDC communications, and the internal reference
clock is enabled.
FLL Bypassed
Internal Low
Power(FBILP)
IREFS=1
CLKS=00
Entered from any state
when MCU enters stop
FLL Engaged
Internal (FEI)
FLL Bypassed
Internal (FBI)
FLL Bypassed
External (FBE)
FLL Engaged
External (FEE)
FLL Bypassed
External Low
Power(FBELP)
IREFS=0
CLKS=00
IREFS=0
CLKS=10
BDM Enabled
or LP =0
Returns to state that was active
before MCU entered stop, unless
reset occurs while in stop.
IREFS=0
CLKS=10
BDM Disabled
and LP=1
IREFS=1
CLKS=01
BDM Enabled
or LP=0
IREFS=1
CLKS=01
BDM Disabled
and LP=1
Stop
Internal Clock Source (S08ICSV1)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 131
9.4.1.2 FLL Engaged External (FEE)
The FLL engaged external (FEE) mode is entered when all the following conditions occur:
• CLKS bits are written to 00
• IREFS bit is written to 0
• RDIV bits are written to divide reference clock to be within the range of 31.25 kHz to 39.0625 kHz
In FLL engaged external mode, the ICSOUT clock is derived from the FLL clock which is controlled by
the external reference clock.The FLL loop will lock the frequency to 512 times the filter frequency, as
selected by the RDIV bits. The ICSLCLK is available for BDC communications, and the external
reference clock is enabled.
9.4.1.3 FLL Bypassed Internal (FBI)
The FLL bypassed internal (FBI) mode is entered when all the following conditions occur:
• CLKS bits are written to 01
• IREFS bit is written to 1.
• BDM mode is active or LP bit is written to 0
In FLL bypassed internal mode, the ICSOUT clock is derived from the internal reference clock. The FLL
clock is controlled by the internal reference clock, and the FLL loop will lock the FLL frequency to 512
times the Filter frequency, as selected by the RDIV bits. The ICSLCLK will be available for BDC
communications, and the internal reference clock is enabled.
9.4.1.4 FLL Bypassed Internal Low Power (FBILP)
The FLL bypassed internal low power (FBILP) mode is entered when all the following conditions occur:
• CLKS bits are written to 01
• IREFS bit is written to 1.
• BDM mode is not active and LP bit is written to 1
In FLL bypassed internal low power mode, the ICSOUT clock is derived from the internal reference clock
and the FLL is disabled. The ICSLCLK will be not be available for BDC communications, and the internal
reference clock is enabled.
9.4.1.5 FLL Bypassed External (FBE)
The FLL bypassed external (FBE) mode is entered when all the following conditions occur:
• CLKS bits are written to 10.
• IREFS bit is written to 0.
• BDM mode is active or LP bit is written to 0.
In FLL bypassed external mode, the ICSOUT clock is derived from the external reference clock. The FLL
clock is controlled by the external reference clock, and the FLL loop will lock the FLL frequency to 512
Internal Clock Source (S08ICSV1)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
132 Freescale Semiconductor
times the filter frequency, as selected by the RDIV bits, so that the ICSLCLK will be available for BDC
communications, and the external reference clock is enabled.
9.4.1.6 FLL Bypassed External Low Power (FBELP)
The FLL bypassed external low power (FBELP) mode is entered when all the following conditions occur:
• CLKS bits are written to 10.
• IREFS bit is written to 0.
• BDM mode is not active and LP bit is written to 1.
In FLL bypassed external low power mode, the ICSOUT clock is derived from the external reference clock
and the FLL is disabled. The ICSLCLK will be not be available for BDC communications. The external
reference clock is enabled.
9.4.1.7 Stop
Stop mode is entered whenever the MCU enters a STOP state. In this mode, all ICS clock signals are static
except in the following cases:
ICSIRCLK will be active in stop mode when all the following conditions occur:
• IRCLKEN bit is written to 1
• IREFSTEN bit is written to 1
ICSERCLK will be active in stop mode when all the following conditions occur:
• ERCLKEN bit is written to 1
• EREFSTEN bit is written to 1
9.4.2 Mode Switching
When switching between FLL engaged internal (FEI) and FLL engaged external (FEE) modes the IREFS
bit can be changed at anytime, but the RDIV bits must be changed simultaneously so that the resulting
frequency stays in the range of 31.25 kHz to 39.0625 kHz. After a change in the IREFS value the FLL will
begin locking again after a few full cycles of the resulting divided reference frequency.
The CLKS bits can also be changed at anytime, but the RDIV bits must be changed simultaneously so that
the resulting frequency stays in the range of 31.25 kHz to 39.0625 kHz. The actual switch to the newly
selected clock will not occur until after a few full cycles of the new clock. If the newly selected clock is
not available, the previous clock will remain selected.
9.4.3 Bus Frequency Divider
The BDIV bits can be changed at anytime and the actual switch to the new frequency will occur
immediately.
Internal Clock Source (S08ICSV1)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 133
9.4.4 Low Power Bit Usage
The low power bit (LP) is provided to allow the FLL to be disabled and thus conserve power when it is
not being used. However, in some applications it may be desirable to enable the FLL and allow it to lock
for maximum accuracy before switching to an FLL engaged mode. Do this by writing the LP bit to 0.
9.4.5 Internal Reference Clock
When IRCLKEN is set the internal reference clock signal will be presented as ICSIRCLK, which can be
used as an additional clock source. The ICSIRCLK frequency can be re-targeted by trimming the period
of the internal reference clock. This can be done by writing a new value to the TRIM bits in the ICSTRM
register. Writing a larger value will slow down the ICSIRCLK frequency, and writing a smaller value to
the ICSTRM register will speed up the ICSIRCLK frequency. The TRIM bits will effect the ICSOUT
frequency if the ICS is in FLL engaged internal (FEI), FLL bypassed internal (FBI), or FLL bypassed
internal low power (FBILP) mode. The TRIM and FTRIM value will not be affected by a reset.
Until ICSIRCLK is trimmed, programming low reference divider (RDIV) factors may result in ICSOUT
frequencies that exceed the maximum chip-level frequency and violate the chip-level clock timing
specifications (see the Device Overview chapter).
If IREFSTEN is set and the IRCLKEN bit is written to 1, the internal reference clock will keep running
during stop mode in order to provide a fast recovery upon exiting stop.
All MCU devices are factory programmed with a trim value in a reserved memory location. This value can
be copied to the ICSTRM register during reset initialization. The factory trim value does not include the
FTRIM bit. For finer precision, the user can trim the internal oscillator in the application and set the
FTRIM bit accordingly.
9.4.6 Optional External Reference Clock
The ICS module can support an external reference clock with frequencies between 31.25 kHz to 5 MHz
in all modes. When the ERCLKEN is set, the external reference clock signal will be presented as
ICSERCLK, which can be used as an additional clock source. When IREFS = 1, the external reference
clock will not be used by the FLL and will only be used as ICSERCLK. In these modes, the frequency can
be equal to the maximum frequency the chip-level timing specifications will support (see the Device
Overview chapter).
If EREFSTEN is set and the ERCLKEN bit is written to 1, the external reference clock will keep running
during stop mode in order to provide a fast recovery upon exiting stop.
Internal Clock Source (S08ICSV1)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
134 Freescale Semiconductor
9.4.7 Fixed Frequency Clock
The ICS presents the divided FLL reference clock as ICSFFCLK for use as an additional clock source for
peripheral modules. The ICS provides an output signal (ICSFFE) which indicates when the ICS is
providing ICSOUT frequencies four times or greater than the divided FLL reference clock (ICSFFCLK).
In FLL engaged mode (FEI and FEE) this is always true and ICSFFE is always high. In ICS bypass modes,
ICSFFE will get asserted for the following combinations of BDIV and RDIV values:
• BDIV=00 (divide by 1), RDIV ≥ 010
• BDIV=01 (divide by 2), RDIV ≥ 011
• BDIV=10 (divide by 4), RDIV ≥ 100
• BDIV=11 (divide by 8), RDIV ≥ 101
9.5 Module Initialization
This section describes how to initialize and configure the ICS module. The following sections contain two
initialization examples.
9.5.1 ICS Module Initialization Sequence
The ICS comes out of POR configured for FEI mode with the BDIV set for divide-by 2. The internal
reference will stabilize in tIRST microseconds before the FLL can acquire lock. As soon as the internal
reference is stable, the FLL will acquire lock in tAcquire milliseconds.
Upon POR, the internal reference will require trimming to guarantee an accurate clock. Freescale
recommends using FLASH location 0xFFAE for storing the fine trim bit, FTRIM in the ICSSC register,
and 0xFFAF for storing the 8-bit trim value for the ICSTRM register. The MCU will not automatically
copy the values in these FLASH locations to the respective registers. Therefore, user code must copy these
values from FLASH to the registers.
NOTE
The BDIV value must not be changed to divide-by 1 without first trimming
the internal reference. Failure to do so could result in the MCU running out
of specification.
9.5.1.1 Initialization Sequence, Internal Clock Mode to External Clock Mode
To change from FEI or FBI clock modes to FEE or FBE clock modes, follow this procedure:
1. Enable the external clock source by setting the appropriate bits in ICSC2.
— If FBE will be the selected mode, also set the LP bit at this time to minimize power
consumption.
2. If necessary, wait for the external clock source to stabilize. Typical crystal startup times are given
in Electrical Characteristics appendix. If EREFS is set in step 1, then the OSCINIT bit will set as
soon as the oscillator has completed the initialization cycles.
3. Write to ICSC1 to select the clock mode.
Internal Clock Source (S08ICSV1)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 135
— If entering FEE, set the reference divider and clear the IREFS bit to switch to the external
reference.
— The internal reference can optionally be kept running by setting the IRCLKEN bit. This is
useful if the application will switch back and forth between internal clock and external clock
modes. For minimum power consumption, leave the internal reference disabled while in an
external clock mode.
4. The CLKST bits can be monitored to determine when the mode switch has completed. If FEE was
selected, the bus clock will be stable in tAcquire milliseconds. The CLKST bits will not change when
switching from FEI to FEE.
9.5.1.2 Initialization Sequence, External Clock Mode to Internal Clock Mode
To change from FEE or FBE clock modes to FEI or FBI clock modes, follow this procedure:
1. If saved, copy the TRIM and FTRIM values from FLASH to the ICSTRM and ICSSC registers.
This needs to be done only once after POR.
2. Enable the internal clock reference by selecting FBI (CLKS = 0:1) or selecting FEI (CLKS = 0:0,
RDIV = 0:0:0, and IREFS = 1) in ICSC1.
3. Wait for the internal clock reference to stabilize. The typical startup time is given in the Electrical
Characteristics appendix.
4. Write to ICSC2 to disable the external clock.
— The external reference can optionally be kept running by setting the ERCLKEN bit. This is
useful if the application will switch back and forth between internal clock and external clock
modes. For minimum power consumption, leave the external reference disabled while in an
internal clock mode.
— If FBI will be the selected mode, also set the LP bit at this time to minimize power
consumption.
NOTE
The internal reference must be enabled and running before disabling the
external clock. Therefore it is imperative to execute steps 2 and 3 before
step 4.
5. The CLKST bits in the ICSSC register can be monitored to determine when the mode switch has
completed. The CLKST bits will not change when switching from FEE to FEI. If FEI was selected,
the bus clock will be stable in tAcquire milliseconds.
Internal Clock Source (S08ICSV1)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
136 Freescale Semiconductor
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 137
Chapter 10
Keyboard Interrupt (S08KBIV2)
10.1 Introduction
The keyboard interrupt KBI module provides up to eight independently enabled external interrupt sources.
Only four (KBI1P0–KBI1P3) of the possible interrupts are implemented on the MC9S08QD4 series MCU.
These inputs are selected by the KBIPE bits.
Figure 10-1 Shows the MC9S08QD4 series with the KBI module and pins highlighted.
Chapter 10 Keyboard Interrupt (S08KBIV2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
138 Freescale Semiconductor
Figure 10-1. MC9S08QD4 Series Block Diagram Highlighting KBI Block and Pins
NOTES:
1Port pins are software configurable with pullup device if input port.
2Port pins are software configurable for output drive strength.
3Port pins are software configurable for output slew rate control.
4IRQ contains a software configurable (IRQPDD) pullup/pulldown device if PTA5 enabled as IRQ pin function (IRQPE = 1).
5RESET contains integrated pullup device if PTA5 enabled as reset pin function (RSTPE = 1).
6PTA5 does not contain a clamp diode to VDD and must not be driven above VDD. The voltage measured on this pin when
internal pullup is enabled may be as low as VDD – 0.7 V. The internal gates connected to this pin are pulled to VDD.
7PTA4 contains integrated pullup device if BKGD enabled (BKGDPE = 1).
8When pin functions as KBI (KBIPEn = 1) and associated pin is configured to enable the pullup device, KBEDGn can be used
to reconfigure the pullup as a pulldown device.
USER RAM
HCS08 CORE
CPU
BDC
2-CH 16-BIT TIMER/PWM
MODULE (TPM1)
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
RTI COP
IRQ LVD
VOLTAGE REGULATOR
PORT A
PTA5/TPM2CH0I/IRQ/RESET
PTA4/TPM2CH0O/BKGD/MS
PTA3/KBI1P3/TCLK2/ADC1P3
PTA2/KBI1P2/TCLK1/ADC1P2
PTA1/KBI1P1/TPM1CH1/ADC1P1
PTA0/KBI1P0/TPM1CH0/ADC1P0
4-BIT KEYBOARD
INTERRUPT MODULE (KBI)
256 / 128 BYTES
16 MHz INTERNAL CLOCK
SOURCE (ICS)
VSS
VDD
VSSA
VDDA
VREFL
VREFH
4
ANALOG-TO-DIGITAL
CONVERTER (ADC)
10-BIT
TPM1CH0
TPM1CH1
BKGD/MS
IRQ
4
1-CH 16-BIT TIMER/PWM
MODULE (TPM2)
TPM2CH0
USER FLASH
4096 / 2048 BYTES
TCLK2
TCLK1
Keyboard Interrupts (S08KBIV2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 139
10.1.1 Features
The KBI features include:
• Up to eight keyboard interrupt pins with individual pin enable bits.
• Each keyboard interrupt pin is programmable as falling edge (or rising edge) only, or both falling
edge and low level (or both rising edge and high level) interrupt sensitivity.
• One software enabled keyboard interrupt.
• Exit from low-power modes.
10.1.2 Modes of Operation
This section defines the KBI operation in wait, stop, and background debug modes.
10.1.2.1 KBI in Wait Mode
The KBI continues to operate in wait mode if enabled before executing the WAIT instruction. Therefore,
an enabled KBI pin (KBPEx = 1) can be used to bring the MCU out of wait mode if the KBI interrupt is
enabled (KBIE = 1).
10.1.2.2 KBI in Stop Modes
The KBI operates asynchronously in stop3 mode if enabled before executing the STOP instruction.
Therefore, an enabled KBI pin (KBPEx = 1) can be used to bring the MCU out of stop3 mode if the KBI
interrupt is enabled (KBIE = 1).
During either stop1 or stop2 mode, the KBI is disabled. In some systems, the pins associated with the KBI
may be sources of wakeup from stop1 or stop2, see the stop modes section in the Modes of Operation
chapter. Upon wake-up from stop1 or stop2 mode, the KBI module will be in the reset state.
10.1.2.3 KBI in Active Background Mode
When the microcontroller is in active background mode, the KBI will continue to operate normally.
10.1.3 Block Diagram
The block diagram for the keyboard interrupt module is shown Figure 10-2.
Keyboard Interrupts (S08KBIV2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
140 Freescale Semiconductor
Figure 10-2. KBI Block Diagram
10.2 External Signal Description
The KBI input pins can be used to detect either falling edges, or both falling edge and low level interrupt
requests. The KBI input pins can also be used to detect either rising edges, or both rising edge and high
level interrupt requests.
The signal properties of KBI are shown in Table 10-1.
10.3 Register Definition
The KBI includes three registers:
• An 8-bit pin status and control register.
• An 8-bit pin enable register.
• An 8-bit edge select register.
Refer to the direct-page register summary in the Memory chapter for the absolute address assignments for
all KBI registers. This section refers to registers and control bits only by their names.
Some MCUs may have more than one KBI, so register names include placeholder characters to identify
which KBI is being referenced.
10.3.1 KBI Status and Control Register (KBISC)
KBISC contains the status flag and control bits, which are used to configure the KBI.
Table 10-1. Signal Properties
Signal Function I/O
KBIPn Keyboard interrupt pins I
DQ
CK
CLR
V
DD
KBMOD
KBIE
KEYBOARD
INTERRUPT FF
KBACK
RESET
SYNCHRONIZER
KBF
STOP BYPASS
STOP
BUSCLK
KBIPEn
0
1
S
KBEDGn
KBIPE0
0
1
S
KBEDG0
KBIP0
KBIPn
KBI
INTERRU
PT
Keyboard Interrupts (S08KBIV2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 141
10.3.2 KBI Pin Enable Register (KBIPE)
KBIPE contains the pin enable control bits.
10.3.3 KBI Edge Select Register (KBIES)
KBIES contains the edge select control bits.
76543210
R 0 0 0 0 KBF 0
KBIE KBMOD
WKBACK
Reset:00000000
= Unimplemented
Figure 10-3. KBI Status and Control Register
Table 10-2. KBISC Register Field Descriptions
Field Description
7:4 Unused register bits, always read 0.
3
KBF
Keyboard Interrupt Flag — KBF indicates when a keyboard interrupt is detected. Writes have no effect on KBF.
0 No keyboard interrupt detected.
1 Keyboard interrupt detected.
2
KBACK
Keyboard Acknowledge — Writing a 1 to KBACK is part of the flag clearing mechanism. KBACK always reads
as 0.
1
KBIE
Keyboard Interrupt Enable — KBIE determines whether a keyboard interrupt is requested.
0 Keyboard interrupt request not enabled.
1 Keyboard interrupt request enabled.
0
KBMOD
Keyboard Detection Mode — KBMOD (along with the KBEDG bits) controls the detection mode of the keyboard
interrupt pins.0Keyboard detects edges only.
1 Keyboard detects both edges and levels.
76543210
R
KBIPE7 KBIPE6 KBIPE5 KBIPE4 KBIPE3 KBIPE2 KBIPE1 KBIPE0
W
Reset:00000000
Figure 10-4. KBI Pin Enable Register
Table 10-3. KBIPE Register Field Descriptions
Field Description
7:0
KBIPEn
Keyboard Pin Enables — Each of the KBIPEn bits enable the corresponding keyboard interrupt pin.
0 Pin not enabled as keyboard interrupt.
1 Pin enabled as keyboard interrupt.
Keyboard Interrupts (S08KBIV2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
142 Freescale Semiconductor
10.4 Functional Description
This on-chip peripheral module is called a keyboard interrupt (KBI) module because originally it was
designed to simplify the connection and use of row-column matrices of keyboard switches. However, these
inputs are also useful as extra external interrupt inputs and as an external means of waking the MCU from
stop or wait low-power modes.
The KBI module allows up to eight pins to act as additional interrupt sources. Writing to the KBIPEn bits
in the keyboard interrupt pin enable register (KBIPE) independently enables or disables each KBI pin.
Each KBI pin can be configured as edge sensitive or edge and level sensitive based on the KBMOD bit in
the keyboard interrupt status and control register (KBISC). Edge sensitive can be software programmed to
be either falling or rising; the level can be either low or high. The polarity of the edge or edge and level
sensitivity is selected using the KBEDGn bits in the keyboard interrupt edge select register (KBIES).
10.4.1 Edge Only Sensitivity
Synchronous logic is used to detect edges. A falling edge is detected when an enabled keyboard interrupt
(KBIPEn=1) input signal is seen as a logic 1 (the deasserted level) during one bus cycle and then a logic 0
(the asserted level) during the next cycle. A rising edge is detected when the input signal is seen as a logic
0 (the deasserted level) during one bus cycle and then a logic 1 (the asserted level) during the next
cycle.Before the first edge is detected, all enabled keyboard interrupt input signals must be at the
deasserted logic levels. After any edge is detected, all enabled keyboard interrupt input signals must return
to the deasserted level before any new edge can be detected.
A valid edge on an enabled KBI pin will set KBF in KBISC. If KBIE in KBISC is set, an interrupt request
will be presented to the CPU. Clearing of KBF is accomplished by writing a 1 to KBACK in KBISC.
10.4.2 Edge and Level Sensitivity
A valid edge or level on an enabled KBI pin will set KBF in KBISC. If KBIE in KBISC is set, an interrupt
request will be presented to the CPU. Clearing of KBF is accomplished by writing a 1 to KBACK in
76543210
R
KBEDG7 KBEDG6 KBEDG5 KBEDG4 KBEDG3 KBEDG2 KBEDG1 KBEDG0
W
Reset:00000000
Figure 10-5. KBI Edge Select Register
Table 10-4. KBIES Register Field Descriptions
Field Description
7:0
KBEDGn
Keyboard Edge Selects — Each of the KBEDGn bits selects the falling edge/low level or rising edge/high level
function of the corresponding pin).
0 Falling edge/low level.
1 Rising edge/high level.
Keyboard Interrupts (S08KBIV2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 143
KBISC provided all enabled keyboard inputs are at their deasserted levels. KBF will remain set if any
enabled KBI pin is asserted while attempting to clear by writing a 1 to KBACK.
10.4.3 KBI Pullup/Pulldown Resistors
The KBI pins can be configured to use an internal pullup/pulldown resistor using the associated I/O port
pullup enable register. If an internal resistor is enabled, the KBIES register is used to select whether the
resistor is a pullup (KBEDGn = 0) or a pulldown (KBEDGn = 1).
10.4.4 KBI Initialization
When a keyboard interrupt pin is first enabled it is possible to get a false keyboard interrupt flag. To
prevent a false interrupt request during keyboard initialization, the user must do the following:
1. Mask keyboard interrupts by clearing KBIE in KBISC.
2. Enable the KBI polarity by setting the appropriate KBEDGn bits in KBIES.
3. If using internal pullup/pulldown device, configure the associated pullup enable bits in PTxPE.
4. Enable the KBI pins by setting the appropriate KBIPEn bits in KBIPE.
5. Write to KBACK in KBISC to clear any false interrupts.
6. Set KBIE in KBISC to enable interrupts.
Keyboard Interrupts (S08KBIV2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
144 Freescale Semiconductor
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 145
Chapter 11
Timer/Pulse-Width Modulator (S08TPMV2)
11.1 Introduction
Figure 11-1 shows the MC9S08QD4 series block diagram with the TPM module and pins highlighted.
11.1.1 TPM2 Configuration Information
The TPM2 module consist of a single channel, TPM2CH0, that is multiplexed with input pin PTA4 and
output pin PTA5. When TPM2 is configured for input capture, the TPM2CH0 will connect to the PTA5
(TPM2CH0I). When TPM2 is configured for output compare, the TPM2CH0 will connect to the PTA4
(TPM2CH0O). When TPM2 is disabled, PTA4 and PTA5 function as standard port pins.
11.1.2 TCLK1 and TCLK2 Configuration Information
The TCLK1 and TCLK2 are the external clock source inputs for TPM1 and TPM2 respectively.
Chapter 11 Timer/Pulse-Width Modulator (S08TPMV2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
146 Freescale Semiconductor
Figure 11-1. MC9S08QD4 Series Block Diagram Highlighting TPM Block and Pins
NOTES:
1Port pins are software configurable with pullup device if input port.
2Port pins are software configurable for output drive strength.
3Port pins are software configurable for output slew rate control.
4IRQ contains a software configurable (IRQPDD) pullup/pulldown device if PTA5 enabled as IRQ pin function (IRQPE = 1).
5RESET contains integrated pullup device if PTA5 enabled as reset pin function (RSTPE = 1).
6PTA5 does not contain a clamp diode to VDD and must not be driven above VDD. The voltage measured on this pin when
internal pullup is enabled may be as low as VDD – 0.7 V. The internal gates connected to this pin are pulled to VDD.
7PTA4 contains integrated pullup device if BKGD enabled (BKGDPE = 1).
8When pin functions as KBI (KBIPEn = 1) and associated pin is configured to enable the pullup device, KBEDGn can be used
to reconfigure the pullup as a pulldown device.
USER RAM
HCS08 CORE
CPU
BDC
2-CH 16-BIT TIMER/PWM
MODULE (TPM1)
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
RTI COP
IRQ LVD
VOLTAGE REGULATOR
PORT A
PTA5/TPM2CH0I/IRQ/RESET
PTA4/TPM2CH0O/BKGD/MS
PTA3/KBI1P3/TCLK2/ADC1P3
PTA2/KBI1P2/TCLK1/ADC1P2
PTA1/KBI1P1/TPM1CH1/ADC1P1
PTA0/KBI1P0/TPM1CH0/ADC1P0
4-BIT KEYBOARD
INTERRUPT MODULE (KBI)
256 / 128 BYTES
16 MHz INTERNAL CLOCK
SOURCE (ICS)
VSS
VDD
VSSA
VDDA
VREFL
VREFH
4
ANALOG-TO-DIGITAL
CONVERTER (ADC)
10-BIT
TPM1CH0
TPM1CH1
BKGD/MS
IRQ
4
1-CH 16-BIT TIMER/PWM
MODULE (TPM2)
TPM2CH0
USER FLASH
4096 / 2048 BYTES
TCLK2
TCLK1
Timer/Pulse-Width Modulator (S08TPMV2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 147
11.1.3 Features
The TPM has the following features:
• Each TPM may be configured for buffered, center-aligned pulse-width modulation (CPWM) on all
channels
• Clock sources independently selectable per TPM (multiple TPMs device)
• Selectable clock sources (device dependent): bus clock, fixed system clock, external pin
• Clock prescaler taps for divide by 1, 2, 4, 8, 16, 32, 64, or 128
• 16-bit free-running or up/down (CPWM) count operation
• 16-bit modulus register to control counter range
• Timer system enable
• One interrupt per channel plus a terminal count interrupt for each TPM module (multiple TPMs
device)
• Channel features:
— Each channel may be input capture, output compare, or buffered edge-aligned PWM
— Rising-edge, falling-edge, or any-edge input capture trigger
— Set, clear, or toggle output compare action
— Selectable polarity on PWM outputs
11.1.4 Block Diagram
Figure 11-2 shows the structure of a TPM. Some MCUs include more than one TPM, with various
numbers of channels.
Timer/Pulse-Width Modulator (S08TPMV2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
148 Freescale Semiconductor
Figure 11-2. TPM Block Diagram
The central component of the TPM is the 16-bit counter that can operate as a free-running counter, a
modulo counter, or an up-/down-counter when the TPM is configured for center-aligned PWM. The TPM
counter (when operating in normal up-counting mode) provides the timing reference for the input capture,
output compare, and edge-aligned PWM functions. The timer counter modulo registers,
TPMxMODH:TPMxMODL, control the modulo value of the counter. (The values 0x0000 or 0xFFFF
effectively make the counter free running.) Software can read the counter value at any time without
affecting the counting sequence. Any write to either byte of the TPMxCNT counter resets the counter
regardless of the data value written.
PRESCALE AND SELECT
16-BIT COMPARATOR
MAIN 16-BIT COUNTER
16-BIT COMPARATOR
16-BIT LATCH
PORT
16-BIT COMPARATOR
16-BIT LATCH
CHANNEL 0
CHANNEL 1
INTERNAL BUS
LOGIC
INTERRUPT
PORT
LOGIC
16-BIT COMPARATOR
16-BIT LATCH
CHANNEL n PORT
LOGIC
COUNTER RESET
DIVIDE BY
CLOCK SOURCE
OFF, BUS, XCLK, EXT
BUSCLK
XCLK
SELECT
SYNC
INTERRUPT
INTERRUPT
INTERRUPT
1, 2, 4, 8, 16, 32, 64, or 128
LOGIC
LOGIC
LOGIC
LOGIC
CLKSA
CLKSB PS2 PS1 PS0
CPWMS
TOIE
TOF
ELS0A
CH0F
ELS0B
ELS1B ELS1A
ELSnB ELSnA
CH1F
CHnF
CH0IE
CH1IE
CHnIE
MS1B
MS0B
MSnB
MS0A
MS1A
MSnA
. . .
. . .
. . .
TPMxMODH:TPMxMO
TPMxC0VH:TPMxC0VL
TPMxC1VH:TPMxC1VL
TPMxCnVH:TPMxCnVL
TPMxCHn
TPMxCH1
TPMxCH0
TPMxCLK
Timer/Pulse-Width Modulator (S08TPMV2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 149
All TPM channels are programmable independently as input capture, output compare, or buffered
edge-aligned PWM channels.
11.2 External Signal Description
When any pin associated with the timer is configured as a timer input, a passive pullup can be enabled.
After reset, the TPM modules are disabled and all pins default to general-purpose inputs with the passive
pullups disabled.
11.2.1 External TPM Clock Sources
When control bits CLKSB:CLKSA in the timer status and control register are set to 1:1, the prescaler and
consequently the 16-bit counter for TPMx are driven by an external clock source, TPMxCLK, connected
to an I/O pin. A synchronizer is needed between the external clock and the rest of the TPM. This
synchronizer is clocked by the bus clock so the frequency of the external source must be less than one-half
the frequency of the bus rate clock. The upper frequency limit for this external clock source is specified to
be one-fourth the bus frequency to conservatively accommodate duty cycle and phase-locked loop (PLL)
or frequency-locked loop (FLL) frequency jitter effects.
On some devices the external clock input is shared with one of the TPM channels. When a TPM channel
is shared as the external clock input, the associated TPM channel cannot use the pin. (The channel can still
be used in output compare mode as a software timer.) Also, if one of the TPM channels is used as the
external clock input, the corresponding ELSnB:ELSnA control bits must be set to 0:0 so the channel is not
trying to use the same pin.
11.2.2 TPMxCHn — TPMx Channel n I/O Pins
Each TPM channel is associated with an I/O pin on the MCU. The function of this pin depends on the
configuration of the channel. In some cases, no pin function is needed so the pin reverts to being controlled
by general-purpose I/O controls. When a timer has control of a port pin, the port data and data direction
registers do not affect the related pin(s). See the Pins and Connections chapter for additional information
about shared pin functions.
11.3 Register Definition
The TPM includes:
• An 8-bit status and control register (TPMxSC)
• A 16-bit counter (TPMxCNTH:TPMxCNTL)
• A 16-bit modulo register (TPMxMODH:TPMxMODL)
Each timer channel has:
• An 8-bit status and control register (TPMxCnSC)
• A 16-bit channel value register (TPMxCnVH:TPMxCnVL)
Refer to the direct-page register summary in the Memory chapter of this data sheet for the absolute address
assignments for all TPM registers. This section refers to registers and control bits only by their names. A
Timer/Pulse-Width Modulator (S08TPMV2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
150 Freescale Semiconductor
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
11.3.1 Timer Status and Control Register (TPMxSC)
TPMxSC contains the overflow status flag and control bits that are used to configure the interrupt enable,
TPM configuration, clock source, and prescale divisor. These controls relate to all channels within this
timer module.
76543210
RTOF
TOIE CPWMS CLKSB CLKSA PS2 PS1 PS0
W
Reset00000000
= Unimplemented or Reserved
Figure 11-3. Timer Status and Control Register (TPMxSC)
Table 11-1. TPMxSC Register Field Descriptions
Field Description
7
TOF
Timer Overflow Flag — This flag is set when the TPM counter changes to 0x0000 after reaching the modulo
value programmed in the TPM counter modulo registers. When the TPM is configured for CPWM, TOF is set after
the counter has reached the value in the modulo register, at the transition to the next lower count value. Clear
TOF by reading the TPM status and control register when TOF is set and then writing a 0 to TOF. If another TPM
overflow occurs before the clearing sequence is complete, the sequence is reset so TOF would remain set after
the clear sequence was completed for the earlier TOF. Reset clears TOF. Writing a 1 to TOF has no effect.
0 TPM counter has not reached modulo value or overflow
1 TPM counter has overflowed
6
TOIE
Timer Overflow Interrupt Enable — This read/write bit enables TPM overflow interrupts. If TOIE is set, an
interrupt is generated when TOF equals 1. Reset clears TOIE.
0 TOF interrupts inhibited (use software polling)
1 TOF interrupts enabled
5
CPWMS
Center-Aligned PWM Select — This read/write bit selects CPWM operating mode. Reset clears this bit so the
TPM operates in up-counting mode for input capture, output compare, and edge-aligned PWM functions. Setting
CPWMS reconfigures the TPM to operate in up-/down-counting mode for CPWM functions. Reset clears
CPWMS.
0 All TPMx channels operate as input capture, output compare, or edge-aligned PWM mode as selected by the
MSnB:MSnA control bits in each channel’s status and control register
1 All TPMx channels operate in center-aligned PWM mode
4:3
CLKS[B:A]
Clock Source Select — As shown in Table 11-2, this 2-bit field is used to disable the TPM system or select one
of three clock sources to drive the counter prescaler. The external source and the XCLK are synchronized to the
bus clock by an on-chip synchronization circuit.
2:0
PS[2:0]
Prescale Divisor Select — This 3-bit field selects one of eight divisors for the TPM clock input as shown in
Ta b le 1 1 - 3 . This prescaler is located after any clock source synchronization or clock source selection, so it affects
whatever clock source is selected to drive the TPM system.
Timer/Pulse-Width Modulator (S08TPMV2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 151
11.3.2 Timer Counter Registers (TPMxCNTH:TPMxCNTL)
The two read-only TPM counter registers contain the high and low bytes of the value in the TPM counter.
Reading either byte (TPMxCNTH or TPMxCNTL) latches the contents of both bytes into a buffer where
they remain latched until the other byte is read. This allows coherent 16-bit reads in either order. The
coherency mechanism is automatically restarted by an MCU reset, a write of any value to TPMxCNTH or
TPMxCNTL, or any write to the timer status/control register (TPMxSC).
Reset clears the TPM counter registers.
Table 11-2. TPM Clock Source Selection
CLKSB:CLKSA TPM Clock Source to Prescaler Input
0:0 No clock selected (TPMx disabled)
0:1 Bus rate clock (BUSCLK)
1:0 Fixed system clock (XCLK)
1:1 External source (TPMxCLK)1,2
1The maximum frequency that is allowed as an external clock is one-fourth of the bus
frequency.
2If the external clock input is shared with channel n and is selected as the TPM clock source,
the corresponding ELSnB:ELSnA control bits must be set to 0:0 so channel n does not try to
use the same pin for a conflicting function.
Table 11-3. Prescale Divisor Selection
PS2:PS1:PS0 TPM Clock Source Divided-By
0:0:0 1
0:0:1 2
0:1:0 4
0:1:1 8
1:0:0 16
1:0:1 32
1:1:0 64
1:1:1 128
76543210
R Bit 15 14 13 12 11 10 9 Bit 8
W Any write to TPMxCNTH clears the 16-bit counter.
Reset00000000
Figure 11-4. Timer Counter Register High (TPMxCNTH)
Timer/Pulse-Width Modulator (S08TPMV2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
152 Freescale Semiconductor
When background mode is active, the timer counter and the coherency mechanism are frozen such that the
buffer latches remain in the state they were in when the background mode became active even if one or
both bytes of the counter are read while background mode is active.
11.3.3 Timer Counter Modulo Registers (TPMxMODH:TPMxMODL)
The read/write TPM modulo registers contain the modulo value for the TPM counter. After the TPM
counter reaches the modulo value, the TPM counter resumes counting from 0x0000 at the next clock
(CPWMS = 0) or starts counting down (CPWMS = 1), and the overflow flag (TOF) becomes set. Writing
to TPMxMODH or TPMxMODL inhibits TOF and overflow interrupts until the other byte is written.
Reset sets the TPM counter modulo registers to 0x0000, which results in a free-running timer counter
(modulo disabled).
It is good practice to wait for an overflow interrupt so both bytes of the modulo register can be written well
before a new overflow. An alternative approach is to reset the TPM counter before writing to the TPM
modulo registers to avoid confusion about when the first counter overflow will occur.
76543210
RBit 7654321Bit 0
W Any write to TPMxCNTL clears the 16-bit counter.
Reset00000000
Figure 11-5. Timer Counter Register Low (TPMxCNTL)
76543210
R
Bit 15 14 13 12 11 10 9 Bit 8
W
Reset00000000
Figure 11-6. Timer Counter Modulo Register High (TPMxMODH)
76543210
R
Bit 7654321Bit 0
W
Reset00000000
Figure 11-7. Timer Counter Modulo Register Low (TPMxMODL)
Timer/Pulse-Width Modulator (S08TPMV2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 153
11.3.4 Timer Channel n Status and Control Register (TPMxCnSC)
TPMxCnSC contains the channel interrupt status flag and control bits that are used to configure the
interrupt enable, channel configuration, and pin function.
76543210
R
CHnF CHnIE MSnB MSnA ELSnB ELSnA
00
W
Reset00000000
= Unimplemented or Reserved
Figure 11-8. Timer Channel n Status and Control Register (TPMxCnSC)
Table 11-4. TPMxCnSC Register Field Descriptions
Field Description
7
CHnF
Channel n Flag — When channel n is configured for input capture, this flag bit is set when an active edge occurs
on the channel n pin. When channel n is an output compare or edge-aligned PWM channel, CHnF is set when
the value in the TPM counter registers matches the value in the TPM channel n value registers. This flag is
seldom used with center-aligned PWMs because it is set every time the counter matches the channel value
register, which correspond to both edges of the active duty cycle period.
A corresponding interrupt is requested when CHnF is set and interrupts are enabled (CHnIE = 1). Clear CHnF
by reading TPMxCnSC while CHnF is set and then writing a 0 to CHnF. If another interrupt request occurs before
the clearing sequence is complete, the sequence is reset so CHnF would remain set after the clear sequence
was completed for the earlier CHnF. This is done so a CHnF interrupt request cannot be lost by clearing a
previous CHnF. Reset clears CHnF. Writing a 1 to CHnF has no effect.
0 No input capture or output compare event occurred on channel n
1 Input capture or output compare event occurred on channel n
6
CHnIE
Channel n Interrupt Enable — This read/write bit enables interrupts from channel n. Reset clears CHnIE.
0 Channel n interrupt requests disabled (use software polling)
1 Channel n interrupt requests enabled
5
MSnB
Mode Select B for TPM Channel n — When CPWMS = 0, MSnB = 1 configures TPM channel n for
edge-aligned PWM mode. For a summary of channel mode and setup controls, refer to Table 11-5.
4
MSnA
Mode Select A for TPM Channel n — When CPWMS = 0 and MSnB = 0, MSnA configures TPM channel n for
input capture mode or output compare mode. Refer to Ta b le 1 1 - 5 for a summary of channel mode and setup
controls.
3:2
ELSn[B:A]
Edge/Level Select Bits — Depending on the operating mode for the timer channel as set by
CPWMS:MSnB:MSnA and shown in Ta bl e 1 1 - 5 , these bits select the polarity of the input edge that triggers an
input capture event, select the level that will be driven in response to an output compare match, or select the
polarity of the PWM output.
Setting ELSnB:ELSnA to 0:0 configures the related timer pin as a general-purpose I/O pin unrelated to any timer
channel functions. This function is typically used to temporarily disable an input capture channel or to make the
timer pin available as a general-purpose I/O pin when the associated timer channel is set up as a software timer
that does not require the use of a pin.
Timer/Pulse-Width Modulator (S08TPMV2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
154 Freescale Semiconductor
If the associated port pin is not stable for at least two bus clock cycles before changing to input capture
mode, it is possible to get an unexpected indication of an edge trigger. Typically, a program would clear
status flags after changing channel configuration bits and before enabling channel interrupts or using the
status flags to avoid any unexpected behavior.
11.3.5 Timer Channel Value Registers (TPMxCnVH:TPMxCnVL)
These read/write registers contain the captured TPM counter value of the input capture function or the
output compare value for the output compare or PWM functions. The channel value registers are cleared
by reset.
In input capture mode, reading either byte (TPMxCnVH or TPMxCnVL) latches the contents of both bytes
into a buffer where they remain latched until the other byte is read. This latching mechanism also resets
(becomes unlatched) when the TPMxCnSC register is written.
Table 11-5. Mode, Edge, and Level Selection
CPWMS MSnB:MSnA ELSnB:ELSnA Mode Configuration
X XX 00 Pin not used for TPM channel; use as an external clock for the TPM or
revert to general-purpose I/O
0 00 01 Input capture Capture on rising edge only
10 Capture on falling edge only
11 Capture on rising or falling edge
01 00 Output
compare
Software compare only
01 Toggle output on compare
10 Clear output on compare
11 Set output on compare
1X 10 Edge-aligned
PWM
High-true pulses (clear output on compare)
X1 Low-true pulses (set output on compare)
1 XX 10 Center-aligned
PWM
High-true pulses (clear output on compare-up)
X1 Low-true pulses (set output on compare-up)
76543210
R
Bit 15 14 13 12 11 10 9 Bit 8
W
Reset00000000
Figure 11-9. Timer Channel Value Register High (TPMxCnVH)
76543210
R
Bit 7654321Bit 0
W
Reset00000000
Figure 11-10. Timer Channel Value Register Low (TPMxCnVL)
Timer/Pulse-Width Modulator (S08TPMV2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 155
In output compare or PWM modes, writing to either byte (TPMxCnVH or TPMxCnVL) latches the value
into a buffer. When both bytes have been written, they are transferred as a coherent 16-bit value into the
timer channel value registers. This latching mechanism may be manually reset by writing to the
TPMxCnSC register.
This latching mechanism allows coherent 16-bit writes in either order, which is friendly to various
compiler implementations.
11.4 Functional Description
All TPM functions are associated with a main 16-bit counter that allows flexible selection of the clock
source and prescale divisor. A 16-bit modulo register also is associated with the main 16-bit counter in the
TPM. Each TPM channel is optionally associated with an MCU pin and a maskable interrupt function.
The TPM has center-aligned PWM capabilities controlled by the CPWMS control bit in TPMxSC. When
CPWMS is set to 1, timer counter TPMxCNT changes to an up-/down-counter and all channels in the
associated TPM act as center-aligned PWM channels. When CPWMS = 0, each channel can
independently be configured to operate in input capture, output compare, or buffered edge-aligned PWM
mode.
The following sections describe the main 16-bit counter and each of the timer operating modes (input
capture, output compare, edge-aligned PWM, and center-aligned PWM). Because details of pin operation
and interrupt activity depend on the operating mode, these topics are covered in the associated mode
sections.
11.4.1 Counter
All timer functions are based on the main 16-bit counter (TPMxCNTH:TPMxCNTL). This section
discusses selection of the clock source, up-counting vs. up-/down-counting, end-of-count overflow, and
manual counter reset.
After any MCU reset, CLKSB:CLKSA = 0:0 so no clock source is selected and the TPM is inactive.
Normally, CLKSB:CLKSA would be set to 0:1 so the bus clock drives the timer counter. The clock source
for the TPM can be selected to be off, the bus clock (BUSCLK), the fixed system clock (XCLK), or an
external input. The maximum frequency allowed for the external clock option is one-fourth the bus rate.
Refer to Section 11.3.1, “Timer Status and Control Register (TPMxSC)” and Table 11-2 for more
information about clock source selection.
When the microcontroller is in active background mode, the TPM temporarily suspends all counting until
the microcontroller returns to normal user operating mode. During stop mode, all TPM clocks are stopped;
therefore, the TPM is effectively disabled until clocks resume. During wait mode, the TPM continues to
operate normally.
The main 16-bit counter has two counting modes. When center-aligned PWM is selected (CPWMS = 1),
the counter operates in up-/down-counting mode. Otherwise, the counter operates as a simple up-counter.
As an up-counter, the main 16-bit counter counts from 0x0000 through its terminal count and then
continues with 0x0000. The terminal count is 0xFFFF or a modulus value in TPMxMODH:TPMxMODL.
Timer/Pulse-Width Modulator (S08TPMV2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
156 Freescale Semiconductor
When center-aligned PWM operation is specified, the counter counts upward from 0x0000 through its
terminal count and then counts downward to 0x0000 where it returns to up-counting. Both 0x0000 and the
terminal count value (value in TPMxMODH:TPMxMODL) are normal length counts (one timer clock
period long).
An interrupt flag and enable are associated with the main 16-bit counter. The timer overflow flag (TOF) is
a software-accessible indication that the timer counter has overflowed. The enable signal selects between
software polling (TOIE = 0) where no hardware interrupt is generated, or interrupt-driven operation
(TOIE = 1) where a static hardware interrupt is automatically generated whenever the TOF flag is 1.
The conditions that cause TOF to become set depend on the counting mode (up or up/down). In
up-counting mode, the main 16-bit counter counts from 0x0000 through 0xFFFF and overflows to 0x0000
on the next counting clock. TOF becomes set at the transition from 0xFFFF to 0x0000. When a modulus
limit is set, TOF becomes set at the transition from the value set in the modulus register to 0x0000. When
the main 16-bit counter is operating in up-/down-counting mode, the TOF flag gets set as the counter
changes direction at the transition from the value set in the modulus register and the next lower count
value. This corresponds to the end of a PWM period. (The 0x0000 count value corresponds to the center
of a period.)
Because the HCS08 MCU is an 8-bit architecture, a coherency mechanism is built into the timer counter
for read operations. Whenever either byte of the counter is read (TPMxCNTH or TPMxCNTL), both bytes
are captured into a buffer so when the other byte is read, the value will represent the other byte of the count
at the time the first byte was read. The counter continues to count normally, but no new value can be read
from either byte until both bytes of the old count have been read.
The main timer counter can be reset manually at any time by writing any value to either byte of the timer
count TPMxCNTH or TPMxCNTL. Resetting the counter in this manner also resets the coherency
mechanism in case only one byte of the counter was read before resetting the count.
11.4.2 Channel Mode Selection
Provided CPWMS = 0 (center-aligned PWM operation is not specified), the MSnB and MSnA control bits
in the channel n status and control registers determine the basic mode of operation for the corresponding
channel. Choices include input capture, output compare, and buffered edge-aligned PWM.
11.4.2.1 Input Capture Mode
With the input capture function, the TPM can capture the time at which an external event occurs. When an
active edge occurs on the pin of an input capture channel, the TPM latches the contents of the TPM counter
into the channel value registers (TPMxCnVH:TPMxCnVL). Rising edges, falling edges, or any edge may
be chosen as the active edge that triggers an input capture.
When either byte of the 16-bit capture register is read, both bytes are latched into a buffer to support
coherent 16-bit accesses regardless of order. The coherency sequence can be manually reset by writing to
the channel status/control register (TPMxCnSC).
An input capture event sets a flag bit (CHnF) that can optionally generate a CPU interrupt request.
Timer/Pulse-Width Modulator (S08TPMV2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 157
11.4.2.2 Output Compare Mode
With the output compare function, the TPM can generate timed pulses with programmable position,
polarity, duration, and frequency. When the counter reaches the value in the channel value registers of an
output compare channel, the TPM can set, clear, or toggle the channel pin.
In output compare mode, values are transferred to the corresponding timer channel value registers only
after both 8-bit bytes of a 16-bit register have been written. This coherency sequence can be manually reset
by writing to the channel status/control register (TPMxCnSC).
An output compare event sets a flag bit (CHnF) that can optionally generate a CPU interrupt request.
11.4.2.3 Edge-Aligned PWM Mode
This type of PWM output uses the normal up-counting mode of the timer counter (CPWMS = 0) and can
be used when other channels in the same TPM are configured for input capture or output compare
functions. The period of this PWM signal is determined by the setting in the modulus register
(TPMxMODH:TPMxMODL). The duty cycle is determined by the setting in the timer channel value
register (TPMxCnVH:TPMxCnVL). The polarity of this PWM signal is determined by the setting in the
ELSnA control bit. Duty cycle cases of 0 percent and 100 percent are possible.
As Figure 11-11 shows, the output compare value in the TPM channel registers determines the pulse width
(duty cycle) of the PWM signal. The time between the modulus overflow and the output compare is the
pulse width. If ELSnA = 0, the counter overflow forces the PWM signal high and the output compare
forces the PWM signal low. If ELSnA = 1, the counter overflow forces the PWM signal low and the output
compare forces the PWM signal high.
Figure 11-11. PWM Period and Pulse Width (ELSnA = 0)
When the channel value register is set to 0x0000, the duty cycle is 0 percent. By setting the timer channel
value register (TPMxCnVH:TPMxCnVL) to a value greater than the modulus setting, 100% duty cycle
can be achieved. This implies that the modulus setting must be less than 0xFFFF to get 100% duty cycle.
Because the HCS08 is a family of 8-bit MCUs, the settings in the timer channel registers are buffered to
ensure coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to either register,
TPMxCnVH or TPMxCnVL, write to buffer registers. In edge-PWM mode, values are transferred to the
corresponding timer channel registers only after both 8-bit bytes of a 16-bit register have been written and
the value in the TPMxCNTH:TPMxCNTL counter is 0x0000. (The new duty cycle does not take effect
until the next full period.)
PERIOD
PULSE
WIDTH
OVERFLOW OVERFLOW OVERFLOW
OUTPUT
COMPARE OUTPUT
COMPARE
OUTPUT
COMPARE
TPMxC
Timer/Pulse-Width Modulator (S08TPMV2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
158 Freescale Semiconductor
11.4.3 Center-Aligned PWM Mode
This type of PWM output uses the up-/down-counting mode of the timer counter (CPWMS = 1). The
output compare value in TPMxCnVH:TPMxCnVL determines the pulse width (duty cycle) of the PWM
signal and the period is determined by the value in TPMxMODH:TPMxMODL.
TPMxMODH:TPMxMODL must be kept in the range of 0x0001 to 0x7FFF because values outside this
range can produce ambiguous results. ELSnA will determine the polarity of the CPWM output.
pulse width = 2 x (TPMxCnVH:TPMxCnVL) Eqn. 11-1
period = 2 x (TPMxMODH:TPMxMODL);
for TPMxMODH:TPMxMODL = 0x0001–0x7FFF Eqn. 11-2
If the channel value register TPMxCnVH:TPMxCnVL is zero or negative (bit 15 set), the duty cycle will
be 0%. If TPMxCnVH:TPMxCnVL is a positive value (bit 15 clear) and is greater than the (nonzero)
modulus setting, the duty cycle will be 100% because the duty cycle compare will never occur. This
implies the usable range of periods set by the modulus register is 0x0001 through 0x7FFE (0x7FFF if
generation of 100% duty cycle is not necessary). This is not a significant limitation because the resulting
period is much longer than required for normal applications.
TPMxMODH:TPMxMODL = 0x0000 is a special case that must not be used with center-aligned PWM
mode. When CPWMS = 0, this case corresponds to the counter running free from 0x0000 through 0xFFFF,
but when CPWMS = 1 the counter needs a valid match to the modulus register somewhere other than at
0x0000 in order to change directions from up-counting to down-counting.
Figure 11-12 shows the output compare value in the TPM channel registers (multiplied by 2), which
determines the pulse width (duty cycle) of the CPWM signal. If ELSnA = 0, the compare match while
counting up forces the CPWM output signal low and a compare match while counting down forces the
output high. The counter counts up until it reaches the modulo setting in TPMxMODH:TPMxMODL, then
counts down until it reaches zero. This sets the period equal to two times TPMxMODH:TPMxMODL.
Figure 11-12. CPWM Period and Pulse Width (ELSnA = 0)
Center-aligned PWM outputs typically produce less noise than edge-aligned PWMs because fewer I/O pin
transitions are lined up at the same system clock edge. This type of PWM is also required for some types
of motor drives.
Because the HCS08 is a family of 8-bit MCUs, the settings in the timer channel registers are buffered to
ensure coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to any of the registers,
TPMxMODH, TPMxMODL, TPMxCnVH, and TPMxCnVL, actually write to buffer registers. Values are
PERIOD
PULSE WIDTH
COUNT =
COUNT = 0
OUTPUT
COMPARE
(COUNT UP)
OUTPUT
COMPARE
(COUNT DOWN)
COUNT =
TPMxMODH:TPMx
TPM1C
TPMxMODH:TPMx
2 x
2 x
Timer/Pulse-Width Modulator (S08TPMV2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 159
transferred to the corresponding timer channel registers only after both 8-bit bytes of a 16-bit register have
been written and the timer counter overflows (reverses direction from up-counting to down-counting at the
end of the terminal count in the modulus register). This TPMxCNT overflow requirement only applies to
PWM channels, not output compares.
Optionally, when TPMxCNTH:TPMxCNTL = TPMxMODH:TPMxMODL, the TPM can generate a TOF
interrupt at the end of this count. The user can choose to reload any number of the PWM buffers, and they
will all update simultaneously at the start of a new period.
Writing to TPMxSC cancels any values written to TPMxMODH and/or TPMxMODL and resets the
coherency mechanism for the modulo registers. Writing to TPMxCnSC cancels any values written to the
channel value registers and resets the coherency mechanism for TPMxCnVH:TPMxCnVL.
11.5 TPM Interrupts
The TPM generates an optional interrupt for the main counter overflow and an interrupt for each channel.
The meaning of channel interrupts depends on the mode of operation for each channel. If the channel is
configured for input capture, the interrupt flag is set each time the selected input capture edge is
recognized. If the channel is configured for output compare or PWM modes, the interrupt flag is set each
time the main timer counter matches the value in the 16-bit channel value register. See the Resets,
Interrupts, and System Configuration chapter for absolute interrupt vector addresses, priority, and local
interrupt mask control bits.
For each interrupt source in the TPM, a flag bit is set on recognition of the interrupt condition such as timer
overflow, channel input capture, or output compare events. This flag may be read (polled) by software to
verify that the action has occurred, or an associated enable bit (TOIE or CHnIE) can be set to enable
hardware interrupt generation. While the interrupt enable bit is set, a static interrupt will be generated
whenever the associated interrupt flag equals 1. It is the responsibility of user software to perform a
sequence of steps to clear the interrupt flag before returning from the interrupt service routine.
11.5.1 Clearing Timer Interrupt Flags
TPM interrupt flags are cleared by a 2-step process that includes a read of the flag bit while it is set (1)
followed by a write of 0 to the bit. If a new event is detected between these two steps, the sequence is reset
and the interrupt flag remains set after the second step to avoid the possibility of missing the new event.
11.5.2 Timer Overflow Interrupt Description
The conditions that cause TOF to become set depend on the counting mode (up or up/down). In
up-counting mode, the 16-bit timer counter counts from 0x0000 through 0xFFFF and overflows to 0x0000
on the next counting clock. TOF becomes set at the transition from 0xFFFF to 0x0000. When a modulus
limit is set, TOF becomes set at the transition from the value set in the modulus register to 0x0000. When
the counter is operating in up-/down-counting mode, the TOF flag gets set as the counter changes direction
at the transition from the value set in the modulus register and the next lower count value. This corresponds
to the end of a PWM period. (The 0x0000 count value corresponds to the center of a period.)
Timer/Pulse-Width Modulator (S08TPMV2)
MC9S08QD4 Series MCU Data Sheet, Rev. 5
160 Freescale Semiconductor
11.5.3 Channel Event Interrupt Description
The meaning of channel interrupts depends on the current mode of the channel (input capture, output
compare, edge-aligned PWM, or center-aligned PWM).
When a channel is configured as an input capture channel, the ELSnB:ELSnA control bits select rising
edges, falling edges, any edge, or no edge (off) as the edge that triggers an input capture event. When the
selected edge is detected, the interrupt flag is set. The flag is cleared by the 2-step sequence described in
Section 11.5.1, “Clearing Timer Interrupt Flags.”
When a channel is configured as an output compare channel, the interrupt flag is set each time the main
timer counter matches the 16-bit value in the channel value register. The flag is cleared by the 2-step
sequence described in Section 11.5.1, “Clearing Timer Interrupt Flags.”
11.5.4 PWM End-of-Duty-Cycle Events
For channels that are configured for PWM operation, there are two possibilities:
• When the channel is configured for edge-aligned PWM, the channel flag is set when the timer
counter matches the channel value register that marks the end of the active duty cycle period.
• When the channel is configured for center-aligned PWM, the timer count matches the channel
value register twice during each PWM cycle. In this CPWM case, the channel flag is set at the start
and at the end of the active duty cycle, which are the times when the timer counter matches the
channel value register.
The flag is cleared by the 2-step sequence described in Section 11.5.1, “Clearing Timer Interrupt Flags.”
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 161
Chapter 12
Development Support
12.1 Introduction
Development support systems in the HCS08 include the background debug controller (BDC). The BDC
provides a single-wire debug interface to the target MCU that provides a convenient interface for
programming the on-chip flash and other nonvolatile memories. The BDC is also the primary debug
interface for development and allows non-intrusive access to memory data and traditional debug features
such as CPU register modify, breakpoints, and single instruction trace commands.
In the HCS08 Family, address and data bus signals are not available on external pins (not even in test
modes). Debug is done through commands fed into the target MCU via the single-wire background debug
interface. The debug module provides a means to selectively trigger and capture bus information so an
external development system can reconstruct what happened inside the MCU on a cycle-by-cycle basis
without having external access to the address and data signals.
12.1.1 Forcing Active Background
The method for forcing active background mode depends on the specific HCS08 derivative. For the
MC9S08QD4 series, you can force active background mode by holding the BKGD pin low as the MCU
exits the reset condition independent of what caused the reset. If no debug pod is connected to the BKGD
pin, the MCU will always reset into normal operating mode.
12.1.2 Module Configuration
The alternative BDC clock source for MC9S08QD4 series is the ICGCLK. See Chapter 9, “Internal Clock
Source (S08ICSV1),” for more information about ICGCLK and how to select clock sources.
Development Support
MC9S08QD4 Series MCU Data Sheet, Rev. 5
162 Freescale Semiconductor
12.1.3 Features
Features of the BDC module include:
• Single pin for mode selection and background communications
• BDC registers are not located in the memory map
• SYNC command to determine target communications rate
• Non-intrusive commands for memory access
• Active background mode commands for CPU register access
• GO and TRACE1 commands
• BACKGROUND command can wake CPU from stop or wait modes
• One hardware address breakpoint built into BDC
• Oscillator runs in stop mode, if BDC enabled
• COP watchdog disabled while in active background mode
12.2 Background Debug Controller (BDC)
All MCUs in the HCS08 Family contain a single-wire background debug interface that supports in-circuit
programming of on-chip nonvolatile memory and sophisticated non-intrusive debug capabilities. Unlike
debug interfaces on earlier 8-bit MCUs, this system does not interfere with normal application resources.
It does not use any user memory or locations in the memory map and does not share any on-chip
peripherals.
BDC commands are divided into two groups:
• Active background mode commands require that the target MCU is in active background mode (the
user program is not running). Active background mode commands allow the CPU registers to be
read or written, and allow the user to trace one user instruction at a time, or GO to the user program
from active background mode.
• Non-intrusive commands can be executed at any time even while the user’s program is running.
Non-intrusive commands allow a user to read or write MCU memory locations or access status and
control registers within the background debug controller.
Typically, a relatively simple interface pod is used to translate commands from a host computer into
commands for the custom serial interface to the single-wire background debug system. Depending on the
development tool vendor, this interface pod may use a standard RS-232 serial port, a parallel printer port,
or some other type of communications such as a universal serial bus (USB) to communicate between the
host PC and the pod. The pod typically connects to the target system with ground, the BKGD pin, RESET,
and sometimes VDD. An open-drain connection to reset allows the host to force a target system reset,
which is useful to regain control of a lost target system or to control startup of a target system before the
on-chip nonvolatile memory has been programmed. Sometimes VDD can be used to allow the pod to use
power from the target system to avoid the need for a separate power supply. However, if the pod is powered
separately, it can be connected to a running target system without forcing a target system reset or otherwise
disturbing the running application program.
Development Support
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 163
Figure 12-1. BDM Tool Connector
12.2.1 BKGD Pin Description
BKGD is the single-wire background debug interface pin. The primary function of this pin is for
bidirectional serial communication of active background mode commands and data. During reset, this pin
is used to select between starting in active background mode or starting the user’s application program.
This pin is also used to request a timed sync response pulse to allow a host development tool to determine
the correct clock frequency for background debug serial communications.
BDC serial communications use a custom serial protocol first introduced on the M68HC12 Family of
microcontrollers. This protocol assumes the host knows the communication clock rate that is determined
by the target BDC clock rate. All communication is initiated and controlled by the host that drives a
high-to-low edge to signal the beginning of each bit time. Commands and data are sent most significant
bit first (MSB first). For a detailed description of the communications protocol, refer to Section 12.2.2,
“Communication Details.”
If a host is attempting to communicate with a target MCU that has an unknown BDC clock rate, a SYNC
command may be sent to the target MCU to request a timed sync response signal from which the host can
determine the correct communication speed.
BKGD is a pseudo-open-drain pin and there is an on-chip pullup so no external pullup resistor is required.
Unlike typical open-drain pins, the external RC time constant on this pin, which is influenced by external
capacitance, plays almost no role in signal rise time. The custom protocol provides for brief, actively
driven speedup pulses to force rapid rise times on this pin without risking harmful drive level conflicts.
Refer to Section 12.2.2, “Communication Details,” for more detail.
When no debugger pod is connected to the 6-pin BDM interface connector, the internal pullup on BKGD
chooses normal operating mode. When a debug pod is connected to BKGD it is possible to force the MCU
into active background mode after reset. The specific conditions for forcing active background depend
upon the HCS08 derivative (refer to the introduction to this Development Support section). It is not
necessary to reset the target MCU to communicate with it through the background debug interface.
12.2.2 Communication Details
The BDC serial interface requires the external controller to generate a falling edge on the BKGD pin to
indicate the start of each bit time. The external controller provides this falling edge whether data is
transmitted or received.
BKGD is a pseudo-open-drain pin that can be driven either by an external controller or by the MCU. Data
is transferred MSB first at 16 BDC clock cycles per bit (nominal speed). The interface times out if
512 BDC clock cycles occur between falling edges from the host. Any BDC command that was in progress
2
4
6NO CONNECT 5
NO CONNECT 3
1
RESET
BKGD GND
VDD
Development Support
MC9S08QD4 Series MCU Data Sheet, Rev. 5
164 Freescale Semiconductor
when this timeout occurs is aborted without affecting the memory or operating mode of the target MCU
system.
The custom serial protocol requires the debug pod to know the target BDC communication clock speed.
The clock switch (CLKSW) control bit in the BDC status and control register allows the user to select the
BDC clock source. The BDC clock source can either be the bus or the alternate BDC clock source.
The BKGD pin can receive a high or low level or transmit a high or low level. The following diagrams
show timing for each of these cases. Interface timing is synchronous to clocks in the target BDC, but
asynchronous to the external host. The internal BDC clock signal is shown for reference in counting
cycles.
Figure 12-2 shows an external host transmitting a logic 1 or 0 to the BKGD pin of a target HCS08 MCU.
The host is asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated falling edge
to where the target perceives the beginning of the bit time. Ten target BDC clock cycles later, the target
senses the bit level on the BKGD pin. Typically, the host actively drives the pseudo-open-drain BKGD pin
during host-to-target transmissions to speed up rising edges. Because the target does not drive the BKGD
pin during the host-to-target transmission period, there is no need to treat the line as an open-drain signal
during this period.
Figure 12-2. BDC Host-to-Target Serial Bit Timing
Figure 12-3 shows the host receiving a logic 1 from the target HCS08 MCU. Because the host is
asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on
BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long
enough for the target to recognize it (at least two target BDC cycles). The host must release the low drive
before the target MCU drives a brief active-high speedup pulse seven cycles after the perceived start of the
bit time. The host must sample the bit level about 10 cycles after it started the bit time.
EARLIEST START
TARGET SENSES BIT LEVEL
10 CYCLES
SYNCHRONIZATION
UNCERTAINTY
BDC CLOCK
(TARGET MCU)
HOST
TRANSMIT 1
HOST
TRANSMIT 0
PERCEIVED START
OF BIT TIME
OF NEXT BIT
Development Support
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 165
Figure 12-3. BDC Target-to-Host Serial Bit Timing (Logic 1)
Figure 12-4 shows the host receiving a logic 0 from the target HCS08 MCU. Because the host is
asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on
BKGD to the start of the bit time as perceived by the target MCU. The host initiates the bit time but the
target HCS08 finishes it. Because the target wants the host to receive a logic 0, it drives the BKGD pin low
for 13 BDC clock cycles, then briefly drives it high to speed up the rising edge. The host samples the bit
level about 10 cycles after starting the bit time.
HOST SAMPLES BKGD PIN
10 CYCLES
BDC CLOCK
(TARGET MCU)
HOST DRIVE
TO BKGD PIN
TARGET MCU
SPEEDUP PULSE
PERCEIVED START
OF BIT TIME
HIGH-IMPEDANCE
HIGH-IMPEDANCE HIGH-IMPEDANCE
BKGD PIN
R-C RISE
10 CYCLES
EARLIEST START
OF NEXT BIT
Development Support
MC9S08QD4 Series MCU Data Sheet, Rev. 5
166 Freescale Semiconductor
Figure 12-4. BDM Target-to-Host Serial Bit Timing (Logic 0)
12.2.3 BDC Commands
BDC commands are sent serially from a host computer to the BKGD pin of the target HCS08 MCU. All
commands and data are sent MSB-first using a custom BDC communications protocol. Active background
mode commands require that the target MCU is currently in the active background mode while
non-intrusive commands may be issued at any time whether the target MCU is in active background mode
or running a user application program.
Table 12-1 shows all HCS08 BDC commands, a shorthand description of their coding structure, and the
meaning of each command.
Coding Structure Nomenclature
This nomenclature is used in Table 12-1 to describe the coding structure of the BDC commands.
10 CYCLES
BDC CLOCK
(TARGET MCU)
HOST DRIVE
TO BKGD PIN
TARGET MCU
DRIVE AND
PERCEIVED START
OF BIT TIME
HIGH-IMPEDANCE
BKGD PIN
10 CYCLES
SPEED-UP PULSE
SPEEDUP
PULSE
EARLIEST START
OF NEXT BIT
HOST SAMPLES BKGD PIN
Development Support
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 167
Commands begin with an 8-bit hexadecimal command code in the host-to-target
direction (most significant bit first)
/ = separates parts of the command
d = delay 16 target BDC clock cycles
AAAA = a 16-bit address in the host-to-target direction
RD = 8 bits of read data in the target-to-host direction
WD = 8 bits of write data in the host-to-target direction
RD16 = 16 bits of read data in the target-to-host direction
WD16 = 16 bits of write data in the host-to-target direction
SS = the contents of BDCSCR in the target-to-host direction (STATUS)
CC = 8 bits of write data for BDCSCR in the host-to-target direction (CONTROL)
RBKP = 16 bits of read data in the target-to-host direction (from BDCBKPT breakpoint
register)
WBKP = 16 bits of write data in the host-to-target direction (for BDCBKPT breakpoint register)
Development Support
MC9S08QD4 Series MCU Data Sheet, Rev. 5
168 Freescale Semiconductor
Table 12-1. BDC Command Summary
Command
Mnemonic
Active BDM/
Non-intrusive
Coding
Structure Description
SYNC Non-intrusive n/a1
1The SYNC command is a special operation that does not have a command code.
Request a timed reference pulse to determine
target BDC communication speed
ACK_ENABLE Non-intrusive D5/d Enable acknowledge protocol. Refer to
Freescale document order no. HCS08RMv1/D.
ACK_DISABLE Non-intrusive D6/d Disable acknowledge protocol. Refer to
Freescale document order no. HCS08RMv1/D.
BACKGROUND Non-intrusive 90/d Enter active background mode if enabled
(ignore if ENBDM bit equals 0)
READ_STATUS Non-intrusive E4/SS Read BDC status from BDCSCR
WRITE_CONTROL Non-intrusive C4/CC Write BDC controls in BDCSCR
READ_BYTE Non-intrusive E0/AAAA/d/RD Read a byte from target memory
READ_BYTE_WS Non-intrusive E1/AAAA/d/SS/RD Read a byte and report status
READ_LAST Non-intrusive E8/SS/RD Re-read byte from address just read and report
status
WRITE_BYTE Non-intrusive C0/AAAA/WD/d Write a byte to target memory
WRITE_BYTE_WS Non-intrusive C1/AAAA/WD/d/SS Write a byte and report status
READ_BKPT Non-intrusive E2/RBKP Read BDCBKPT breakpoint register
WRITE_BKPT Non-intrusive C2/WBKP Write BDCBKPT breakpoint register
GO Active BDM 08/d Go to execute the user application program
starting at the address currently in the PC
TRACE1 Active BDM 10/d Trace 1 user instruction at the address in the
PC, then return to active background mode
TAGGO Active BDM 18/d Same as GO but enable external tagging
(HCS08 devices have no external tagging pin)
READ_A Active BDM 68/d/RD Read accumulator (A)
READ_CCR Active BDM 69/d/RD Read condition code register (CCR)
READ_PC Active BDM 6B/d/RD16 Read program counter (PC)
READ_HX Active BDM 6C/d/RD16 Read H and X register pair (H:X)
READ_SP Active BDM 6F/d/RD16 Read stack pointer (SP)
READ_NEXT Active BDM 70/d/RD Increment H:X by one then read memory byte
located at H:X
READ_NEXT_WS Active BDM 71/d/SS/RD Increment H:X by one then read memory byte
located at H:X. Report status and data.
WRITE_A Active BDM 48/WD/d Write accumulator (A)
WRITE_CCR Active BDM 49/WD/d Write condition code register (CCR)
WRITE_PC Active BDM 4B/WD16/d Write program counter (PC)
WRITE_HX Active BDM 4C/WD16/d Write H and X register pair (H:X)
WRITE_SP Active BDM 4F/WD16/d Write stack pointer (SP)
WRITE_NEXT Active BDM 50/WD/d Increment H:X by one, then write memory byte
located at H:X
WRITE_NEXT_WS Active BDM 51/WD/d/SS Increment H:X by one, then write memory byte
located at H:X. Also report status.
Development Support
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 169
The SYNC command is unlike other BDC commands because the host does not necessarily know the
correct communications speed to use for BDC communications until after it has analyzed the response to
the SYNC command.
To issue a SYNC command, the host:
• Drives the BKGD pin low for at least 128 cycles of the slowest possible BDC clock (The slowest
clock is normally the reference oscillator/64 or the self-clocked rate/64.)
• Drives BKGD high for a brief speedup pulse to get a fast rise time (This speedup pulse is typically
one cycle of the fastest clock in the system.)
• Removes all drive to the BKGD pin so it reverts to high impedance
• Monitors the BKGD pin for the sync response pulse
The target, upon detecting the SYNC request from the host (which is a much longer low time than would
ever occur during normal BDC communications):
• Waits for BKGD to return to a logic high
• Delays 16 cycles to allow the host to stop driving the high speedup pulse
• Drives BKGD low for 128 BDC clock cycles
• Drives a 1-cycle high speedup pulse to force a fast rise time on BKGD
• Removes all drive to the BKGD pin so it reverts to high impedance
The host measures the low time of this 128-cycle sync response pulse and determines the correct speed for
subsequent BDC communications. Typically, the host can determine the correct communication speed
within a few percent of the actual target speed and the communication protocol can easily tolerate speed
errors of several percent.
12.2.4 BDC Hardware Breakpoint
The BDC includes one relatively simple hardware breakpoint that compares the CPU address bus to a
16-bit match value in the BDCBKPT register. This breakpoint can generate a forced breakpoint or a tagged
breakpoint. A forced breakpoint causes the CPU to enter active background mode at the first instruction
boundary following any access to the breakpoint address. The tagged breakpoint causes the instruction
opcode at the breakpoint address to be tagged so that the CPU will enter active background mode rather
than executing that instruction if and when it reaches the end of the instruction queue. This implies that
tagged breakpoints can only be placed at the address of an instruction opcode while forced breakpoints can
be set at any address.
The breakpoint enable (BKPTEN) control bit in the BDC status and control register (BDCSCR) is used to
enable the breakpoint logic (BKPTEN = 1). When BKPTEN = 0, its default value after reset, the
breakpoint logic is disabled and no BDC breakpoints are requested regardless of the values in other BDC
breakpoint registers and control bits. The force/tag select (FTS) control bit in BDCSCR is used to select
forced (FTS = 1) or tagged (FTS = 0) type breakpoints.
12.3 Register Definition
This section contains the descriptions of the BDC registers and control bits.
Development Support
MC9S08QD4 Series MCU Data Sheet, Rev. 5
170 Freescale Semiconductor
This section refers to registers and control bits only by their names. A Freescale-provided equate or header
file is used to translate these names into the appropriate absolute addresses.
12.3.1 BDC Registers and Control Bits
The BDC has two registers:
• The BDC status and control register (BDCSCR) is an 8-bit register containing control and status
bits for the background debug controller.
• The BDC breakpoint match register (BDCBKPT) holds a 16-bit breakpoint match address.
These registers are accessed with dedicated serial BDC commands and are not located in the memory
space of the target MCU (so they do not have addresses and cannot be accessed by user programs).
Some of the bits in the BDCSCR have write limitations; otherwise, these registers may be read or written
at any time. For example, the ENBDM control bit may not be written while the MCU is in active
background mode. (This prevents the ambiguous condition of the control bit forbidding active background
mode while the MCU is already in active background mode.) Also, the four status bits (BDMACT, WS,
WSF, and DVF) are read-only status indicators and can never be written by the WRITE_CONTROL serial
BDC command. The clock switch (CLKSW) control bit may be read or written at any time.
Development Support
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 171
12.3.1.1 BDC Status and Control Register (BDCSCR)
This register can be read or written by serial BDC commands (READ_STATUS and WRITE_CONTROL)
but is not accessible to user programs because it is not located in the normal memory map of the MCU.
76543210
R
ENBDM
BDMACT
BKPTEN FTS CLKSW
WS WSF DVF
W
Normal
Reset
00000000
Reset in
Active BDM:
11001000
= Unimplemented or Reserved
Figure 12-5. BDC Status and Control Register (BDCSCR)
Table 12-2. BDCSCR Register Field Descriptions
Field Description
7
ENBDM
Enable BDM (Permit Active Background Mode) — Typically, this bit is written to 1 by the debug host shortly
after the beginning of a debug session or whenever the debug host resets the target and remains 1 until a normal
reset clears it.
0 BDM cannot be made active (non-intrusive commands still allowed)
1 BDM can be made active to allow active background mode commands
6
BDMACT
Background Mode Active Status — This is a read-only status bit.
0 BDM not active (user application program running)
1 BDM active and waiting for serial commands
5
BKPTEN
BDC Breakpoint Enable — If this bit is clear, the BDC breakpoint is disabled and the FTS (force tag select)
control bit and BDCBKPT match register are ignored.
0 BDC breakpoint disabled
1 BDC breakpoint enabled
4
FTS
Force/Tag Select — When FTS = 1, a breakpoint is requested whenever the CPU address bus matches the
BDCBKPT match register. When FTS = 0, a match between the CPU address bus and the BDCBKPT register
causes the fetched opcode to be tagged. If this tagged opcode ever reaches the end of the instruction queue,
the CPU enters active background mode rather than executing the tagged opcode.
0 Tag opcode at breakpoint address and enter active background mode if CPU attempts to execute that
instruction
1 Breakpoint match forces active background mode at next instruction boundary (address need not be an
opcode)
3
CLKSW
Select Source for BDC Communications Clock — CLKSW defaults to 0, which selects the alternate BDC clock
source.
0 Alternate BDC clock source
1 MCU bus clock
Development Support
MC9S08QD4 Series MCU Data Sheet, Rev. 5
172 Freescale Semiconductor
12.3.1.2 BDC Breakpoint Match Register (BDCBKPT)
This 16-bit register holds the address for the hardware breakpoint in the BDC. The BKPTEN and FTS
control bits in BDCSCR are used to enable and configure the breakpoint logic. Dedicated serial BDC
commands (READ_BKPT and WRITE_BKPT) are used to read and write the BDCBKPT register but is
not accessible to user programs because it is not located in the normal memory map of the MCU.
Breakpoints are normally set while the target MCU is in active background mode before running the user
application program. For additional information about setup and use of the hardware breakpoint logic in
the BDC, refer to Section 12.2.4, “BDC Hardware Breakpoint.”
12.3.2 System Background Debug Force Reset Register (SBDFR)
This register contains a single write-only control bit. A serial background mode command such as
WRITE_BYTE must be used to write to SBDFR. Attempts to write this register from a user program are
ignored. Reads always return 0x00.
2
WS
Wait or Stop Status — When the target CPU is in wait or stop mode, most BDC commands cannot function.
However, the BACKGROUND command can be used to force the target CPU out of wait or stop and into active
background mode where all BDC commands work. Whenever the host forces the target MCU into active
background mode, the host must issue a READ_STATUS command to check that BDMACT = 1 before
attempting other BDC commands.
0 Target CPU is running user application code or in active background mode (was not in wait or stop mode when
background became active)
1 Target CPU is in wait or stop mode, or a BACKGROUND command was used to change from wait or stop to
active background mode
1
WSF
Wait or Stop Failure Status — This status bit is set if a memory access command failed due to the target CPU
executing a wait or stop instruction at or about the same time. The usual recovery strategy is to issue a
BACKGROUND command to get out of wait or stop mode into active background mode, repeat the command
that failed, then return to the user program. (Typically, the host would restore CPU registers and stack values and
re-execute the wait or stop instruction.)
0 Memory access did not conflict with a wait or stop instruction
1 Memory access command failed because the CPU entered wait or stop mode
0
DVF
Data Valid Failure Status — This status bit is not used in the MC9S08QD4 series because it does not have any
slow access memory.
0 Memory access did not conflict with a slow memory access
1 Memory access command failed because CPU was not finished with a slow memory access
Table 12-2. BDCSCR Register Field Descriptions (continued)
Field Description
Development Support
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 173
Figure 12-6. System Background Debug Force Reset Register (SBDFR)
76543210
R00000000
WBDFR1
1BDFR is writable only through serial background mode debug commands, not from user programs.
Reset00000000
= Unimplemented or Reserved
Table 12-3. SBDFR Register Field Description
Field Description
0
BDFR
Background Debug Force Reset — A serial active background mode command such as WRITE_BYTE allows
an external debug host to force a target system reset. Writing 1 to this bit forces an MCU reset. This bit cannot
be written from a user program.
Development Support
MC9S08QD4 Series MCU Data Sheet, Rev. 5
174 Freescale Semiconductor
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 175
Appendix A
Electrical Characteristics
A.1 Introduction
This chapter contains electrical and timing specifications.
A.2 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not
guaranteed. Stress beyond the limits specified in Table A-1 may affect device reliability or cause
permanent damage to the device. For functional operating conditions, refer to the remaining tables in this
section.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable
pull-up resistor associated with the pin is enabled.
Table A-1. Absolute Maximum Ratings
Rating Symbol Value Unit
Supply voltage VDD –0.3 to +5.8 V
Maximum current into VDD IDD 120 mA
Digital input voltage VIn –0.3 to VDD +0.3 V
Instantaneous maximum current
Single pin limit (applies to all port pins)1, 2, 3
1 Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
2All functional non-supply pins are internally clamped to VSS and VDD.
3Power supply must maintain regulation within operating VDD range during instantaneous and
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than
IDD, the injection current may flow out of VDD and could result in external power supply going
out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low (which would reduce overall power
consumption).
ID±25 mA
Storage temperature range Tstg –55 to 150 °C
Appendix A Electrical Characteristics
MC9S08QD4 Series MCU Data Sheet, Rev. 5
176 Freescale Semiconductor
A.3 Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package
thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in
on-chip logic and voltage regulator circuits and it is user-determined rather than being controlled by the
MCU design. In order to take PI/O into account in power calculations, determine the difference between
actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of
unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very
small.
The average chip-junction temperature (TJ) in °C can be obtained from:
TJ = TA + (PD × θJA)Eqn. A-1
where:
TA = Ambient temperature, °C
θJA = Package thermal resistance, junction-to-ambient, °C/W
PD = Pint + PI/O
Pint = IDD × VDD, Watts — chip internal power
PI/O = Power dissipation on input and output pins — user determined
For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ
(if PI/O is neglected) is:
PD = K ÷ (TJ + 273°C) Eqn. A-2
Solving Equation A-1 and Equation A-2 for K gives:
K = PD × (TA + 273°C) + θJA × (PD)2Eqn. A-3
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring
PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by
solving Equation A-1 and Equation A-2 iteratively for any value of TA.
Table A-2. Thermal Characteristics
Rating Symbol Value Unit
Operating temperature range
(packaged)
TATL to TH
–40 to 125
°C
Thermal resistance (single-layer board)
8-pin PDIP
8-pin NB SOIC
θJA 113
150
°C/W
Thermal resistance (four-layer board)
8-pin PDIP
8-pin NB SOIC
θJA 72
87
°C/W
Appendix A Electrical Characteristics
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 177
A.4 ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early
CMOS circuits, normal handling precautions must be used to avoid exposure to static discharge.
Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels
of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the human body
model (HBM), the machine model (MM) and the charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
A.5 DC Characteristics
This section includes information about power supply requirements and I/O pin characteristics.
Table A-3. ESD and Latch-up Test Conditions
Model Description Symbol Value Unit
Human
Body
Series resistance R1 1500 Ω
Storage capacitance C 100 pF
Number of pulses per pin — 3
Machine Series resistance R1 0 Ω
Storage capacitance C 200 pF
Number of pulses per pin — 3
Latch-up Minimum input voltage limit – 2.5 V
Maximum input voltage limit 7.5 V
Table A-4. ESD and Latch-Up Protection Characteristics
No. Rating1
1Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.
Symbol Min Max Unit
1 Human body model (HBM) VHBM ± 2000 — V
2 Machine model (MM) VMM ± 200 — V
3 Charge device model (CDM) VCDM ± 500 — V
4Latch-up current at TA = 85°CI
LAT ± 100 — mA
Appendix A Electrical Characteristics
MC9S08QD4 Series MCU Data Sheet, Rev. 5
178 Freescale Semiconductor
Table A-5. DC Characteristics (Temperature Range = –40 to 125°C Ambient)
Parameter Symbol Min Typical Max Unit
Supply voltage (run, wait, and stop modes.) VDD 2.7 5.5 V
POR re-arm voltage1VPOR 0.9 1.4 2.0 V
Minimum RAM retention supply voltage applied to VDD VRAM VPOR2, 3 —V
Low-voltage detection threshold — high range
(Consumer and Industrial MC9S08QDx)
VDD falling
VDD rising)
VLVDH
4.2
4.3
4.3
4.4
4.4
4.5
V
V
Low-voltage detection threshold — high range
(Automotive S9S08QDx)
(VDD falling)
–40°C to 0°C
0 to 125°C
(VDD rising)
–40°C to 0°C
0 to 125°C
4.175
4.2
4.275
4.3
4.3
4.4
4.3
4.4
4.4
4.5
4.4
4.5
V
Low-voltage detection threshold — low range
(VDD falling)
(VDD rising) VLVDL
2.48
2.54
2.56
2.62
2.64
2.7
V
V
Low-voltage warning threshold — high range
(Consumer and Industrial MC9S08QDx)
(VDD falling)
(VDD rising)
VLVWH
4.2
4.3
4.3
4.4
4.4
4.5
V
V
Low-voltage warning threshold — high range
(Automotive S9S08QDx)
(VDD falling)
–40°C to 0°C
0 to 125°C
(VDD rising)
–40°C to 0°C
0 to 125°C
4.175
4.2
4.275
4.3
4.3
4.4
4.3
4.4
4.4
4.5
4.4
4.5
V
Low-voltage warning threshold — low range
(VDD falling)
(VDD rising) VLV W L
2.48
2.54
2.56
2.62
2.64
2.7
V
V
Low-voltage inhibit reset/recover hysteresis
5V
3V Vhys
—
—
100
60
—
—
mV
mV
Bandgap Voltage Reference
(Consumer and Industrial MC9S08QDx)
Factory trimmed at VDD = 3.0V, Temp = 25°C
VBG
1.19 1.20 1.21 V
Bandgap Voltage Reference (S9S08QDx)
Factory trimmed at VDD = 3.0V, Temp = 25°C
–40°C to 125°C
1.18 1.20 1.215 V
Input high voltage (2.7 V ≤ VDD ≤ 5.5 V) (all digital inputs) VIH 0.7 × VDD —V
Input low voltage (2.7 V ≤ VDD ≤ 5.5 V) (all digital inputs) VIL —0.3 × VDD V
Input hysteresis (all digital inputs) Vhys 0.06 × VDD —V
Input leakage current (Per pin)
VIn = VDD or VSS, all input only pins |IIn| — 0.025 1.0 μA
Appendix A Electrical Characteristics
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 179
High impedance (off-state) leakage current (per pin)
VIn = VDD or VSS, all input/output |IOZ| — 0.025 1.0 μA
Internal pullup resistors4RPU 17.5 52.5 kΩ
Internal pulldown resistor (IRQ) RPD 17.5 52.5 kΩ
Output high voltage — Low Drive (PTxDSn = 0)
5 V, ILoad = –2 mA
3 V, ILoad = –0.6 mA
5 V, ILoad = –0.4 mA
3 V, ILoad = –0.24 mA
VOH
VDD – 1.5
VDD – 1.5
VDD – 0.8
VDD – 0.8
—
—
—
—
—
—
—
—
V
Output high voltage — High Drive (PTxDSn = 1)
5 V, ILoad = –10 mA
3 V, ILoad = –3 mA
5 V, ILoad = –2 mA
3 V, ILoad = –0.4 mA
VDD – 1.5
VDD – 1.5
VDD – 0.8
VDD – 0.8
—
—
—
—
—
—
—
—
Maximum total IOH for all port pins
5V
3V |IOHT|—
—
—
—
100
60 mA
Output low voltage — Low Drive (PTxDSn = 0)
5 V, ILoad = 2 mA
3 V, ILoad = 0.6 mA
5 V, ILoad = 0.4 mA
3 V, ILoad = 0.24 mA
VOL
—
—
—
—
—
—
—
—
1.5
1.5
0.8
0.8 V
Output low voltage — High Drive (PTxDSn = 1)
5 V, ILoad = 10 mA
3 V, ILoad = 3 mA
5 V, ILoad = 2 mA
3 V, ILoad = 0.4 mA
—
—
—
—
—
—
—
—
1.5
1.5
0.8
0.8
Maximum total IOL for all port pins
5V
3V IOLT
—
—
—
—
100
60 mA
DC injection current2, 5, 6, 7
Single pin limit
VIN > VDD
VIN < VSS
Total MCU limit, includes sum of all stressed pins
VIN > VDD
VIN < VSS
IIC
0
0
0
0
—
2
–0.2
12
–1.2
mA
Input capacitance (all non-supply pins) CIn —7pF
1Maximum is highest voltage that POR is guaranteed.
2RAM will retain data down to POR voltage. RAM data not guaranteed to be valid following a POR.
3This parameter is characterized and not tested on each device.
4Measurement condition for pull resistors: VIn = VSS for pullup and VIn = VDD for pulldown.
5All functional non-supply pins are internally clamped to VSS and VDD.
6Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.
Table A-5. DC Characteristics (continued)(Temperature Range = –40 to 125°C Ambient)
Parameter Symbol Min Typical Max Unit
Appendix A Electrical Characteristics
MC9S08QD4 Series MCU Data Sheet, Rev. 5
180 Freescale Semiconductor
Figure A-1. Typical Low-Side Driver (Sink) Characteristics
Low Drive (PTxDSn = 0), VDD = 5.0V, VOL vs. IOL
Figure A-2. Typical Low-Side Driver (Sink) Characteristics
Low Drive (PTxDSn = 0), VDD = 3.0 V, VOL vs. IOL
7Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result
in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if
clock rate is very low (which would reduce overall power consumption).
14
12
10
8
6
4
2
0
00.4 0.8 1.2 1.6 22.4
2.8
V
OL
/V
I
OL
/mA
–40
0
25
85
125
Typical Low-side Driver (LDS) Characteristics,
V
DD
= 5.0 V, PORTA
105
–40
25
85
105
–1.61.211.4
0.8
0.60.4
0.20
V
OL
/V
0
1
2
3
4
5
6
I
OL
/mA
Typical Low-side Driver (LDS) Characteristics,
V
DD
= 3.0 V, PORTA
0
125
Appendix A Electrical Characteristics
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 181
Figure A-3. Typical Low-Side Driver (Sink) Characteristics
High Drive (PTxDSn = 1), VDD = 5.0 V, VOL vs. IOL
Figure A-4. Typical Low-Side Driver (Sink) Characteristics
High Drive (PTxDSn = 1), VDD = 3.0 V, VOL vs. IOL
2.82.4
2
1.6
1.20.8
0.4
0
0
V
OL
/V
I
OL
/mA
5
10
15
20
25
30
35
40
Typical Low-side Driver (HDS) Characteristics,
V
DD
= 5.0 V, PORTA
105
–40
0
25
85
125
–40
25
85
105
0
1.61.41.2
1
0.8
0.6
0.4
0.2
0
2
V
OL
/V
4
0
6
8
10
12
14
Typical Low-side Driver (HDS) Characteristics,
V
DD
= 3.0 V, PORTA
I
OL
/mA
125
Appendix A Electrical Characteristics
MC9S08QD4 Series MCU Data Sheet, Rev. 5
182 Freescale Semiconductor
Figure A-5. Typical High-Side Driver (Source) Characteristics
Low Drive (PTxDSn = 0), VDD = 5.0 V, VOH vs. IOH
Figure A-6. Typical High-Side Driver (Source) Characteristics
Low Drive (PTxDSn = 0), VDD = 3.0 V, VOH vs. IOH
–40
25
85
105
0
5.2
4.8
4.44
3.6
3.2
2.8
2.4
0
I
OH
/mA
–1
–2
–3
–4
–5
–6
–7
–8
V
OH
/V
Typical High-side Driver (LDS) Characteristics,
V
DD
= 5.0 V, PORTA
125
–40
25
85
105
0
3
2.8
2.6
2.4
2.2
21.8
1.6
–3
–2.5
–2
–1.5
–1
–0.5
0
Typical High-side Driver (LDS) Characteristics,
V
DD
= 3.0 V, PORTA
V
OH
/V
I
OH
/mA
125
Appendix A Electrical Characteristics
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 183
Figure A-7. Typical High-Side Driver (Source) Characteristics
High Drive (PTxDSn = 1), VDD = 5.0 V, VOH vs. IOH
Figure A-8. Typical High-Side Driver (Source) Characteristics
High Drive (PTxDSn = 1), VDD = 3.0 V, VOH vs. IOH
–30
–25
–20
–15
–10
–5
0
I
OH
/mA
2.4 2.8 3.2 3.6 44.4 4.8 5.2
V
OH
/V
Typical High-side Driver (HDS) Characteristics,
V
DD
= 5.0 V, PORTA
105
–40
0
25
85
125
V
OH
/V
32.8
2.6
2.422.2
1.6 1.8
–12
–10
–8
–6
–4
–2
0
I
OH
/mA
Typical High-side Driver (HDS) Characteristics,
V
DD
= 3.0 V, PORTA
105
–40
0
25
85
125
Appendix A Electrical Characteristics
MC9S08QD4 Series MCU Data Sheet, Rev. 5
184 Freescale Semiconductor
A.6 Supply Current Characteristics
This section includes information about power supply current in various operating modes
Table A-6. Supply Current Characteristics
Parameter Symbol VDD (V) Typical1
1Typicals are measured at 25°C.
Max2
2Values given here are preliminary estimates prior to completing characterization.
Unit
Run supply current3 measured at
(CPU clock = 2 MHz, fBus = 1 MHz) RIDD
5 0.95 1.54 mA
30.90 1.5
Run supply current5 measured at
(CPU clock = 16 MHz, fBus = 8 MHz) RIDD
53.5 5
6 mA
33.4 5
Wait mode supply current7 measured at
(CPU clock = 16 MHz, fBus = 8 MHz) WIDD
51.55 2.2mA
31.50 2.2
Stop2 mode supply current
(Consumer and Industrial MC9S08QDx)
–40 to 85°C
–40 to 125°C
–40 to 85°C
–40 to 125°C
S2IDD
50.80 7.58
20 4
μA
3 0.80 7.08
15
μA
Stop2 mode supply current
(Automotive S9S08QDx)
–40 to 85°C
–40 to 125°C
–40 to 85°C
–40 to 125°C
50.80 7.59
25 4
μA
3 0.80 7.08
20
μA
Stop3 mode supply current
(Consumer and Industrial MC9S08QDx)
–40 to 85° C
–40 to 125°C
–40 to 85° C
–40 to 125°C
S3IDD s
50.90 8.08
254
μA
3 0.90 7.18
20
μA
Stop3 mode supply current
(Automotive S9S08QDx)
–40 to 85° C
–40 to 125°C
–40 to 85° C
–40 to 125°C
50.90 8.08
304
μA
3 0.90 7.18
25
μA
RTI adder to stop2 or stop310, 25°C5400 nA
3350 nA
LVD adder to stop3 (LVDE = LVDSE = 1) 5110 μA
390 μA
Adder to stop3 for oscillator enabled (IREFSTEN = 1) 575 μA
365 μA
Appendix A Electrical Characteristics
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 185
Figure A-9. Typical Run IDD vs. Bus Freq. (FEI) (ADC off)
3All modules except ADC active, and does not include any dc loads on port pins
4Every unit tested to this parameter. All other values in the Max column are guaranteed by characterization.
5All modules except ADC active, and does not include any dc loads on port pins
6Every unit tested to this parameter. All other values in the Max column are guaranteed by characterization.
7Most customers are expected to find that the auto-wakeup from a stop mode can be used instead of the higher current wait
mode.
8This parameter is characterized and not tested on each device.
9This parameter is characterized and not tested on each device.
10 Most customers are expected to find that auto-wakeup from stop2 or stop3 can be used instead of the higher current wait
mode. Wait mode typical is 560 μA at 3 V with fBus = 1 MHz.
R
IDD
/mA
10
8
6
4
02
0.00
0.50
1.00
1.50
4.00
3.50
3.00
2.50
2.00
Bus/MHz
Typical R
IDD
(V
DD
=5.0 V, ADC off) vs. Bus Freq.
105
–40
0
25
85
125
Appendix A Electrical Characteristics
MC9S08QD4 Series MCU Data Sheet, Rev. 5
186 Freescale Semiconductor
A.7 Internal Clock Source Characteristics
Table A-7. Internal Clock Source Specifications
Characteristic Symbol Min Typ1
1Data in Typical column was characterized at 3.0 V and 3.0 V, 25°C or is typical recommended value.
Max Unit
Average internal reference frequency - untrimmed fint_ut 25 31.25 41.66 kHz
Average internal reference frequency - trimmed fint_t — 31.25 — kHz
DCO output frequency range - untrimmed fdco_ut 12.8 16 21.33 MHz
DCO output frequency range - trimmed fdco_t —16—MHz
Resolution of trimmed DCO output frequency at fixed voltage and
temperature (Consumer and Industrial MC9S08QDx)2
2Characterized, but not tested.
Δfdco_res_t
——± 0.2
%fdco
Resolution of trimmed DCO output frequency at fixed voltage and
temperature (Automotive S9S08QDx)2
–40°C to 0°C
0 to 125°C
——
± 0.3
± 0.2
Total deviation of trimmed DCO output frequency over voltage and
temperature 3
Consumer and Industrial MC9S08QDx
Automotive S9S08QDx
Δfdco_t ——
± 2
± 3
%fdco
FLL acquisition time 3,3
3This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing
from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference,
this specification assumes it is already running.
tacquire 1ms
Long term Jitter of DCO output clock (averaged over 2 ms interval) 4
4Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBUS.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for
a given interval.
CJitter ——0.6
%fdco
Appendix A Electrical Characteristics
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 187
Figure A-10. Typical Deviation of DCO Output vs. Temperature
Figure A-11. Typical Deviation of DCO Output vs. Operating Voltage
–40 –20 0 20 40 60 80 100 120 140
0.60%
0.50%
0.40%
0.30%
0.20%
0.10%
0.00%
–0.10%
–0.20%
–0.30%
–0.40%
Tem p. / C
Deviation of DCO Output from Trimmed Frequency
(8 MHz, 5.5 V)
Deviation
0.70%
0.80%
0.20%
0.15%
0.10%
0.05%
0.00%
–0.05%
–0.10%
–0.15%
–0.20%
32.5 3.5 4
V
DD
/ V
55.56
Deviation
4.5
Deviation of DCO Output from Trimmed Frequency
(8 MHz, 25
°
C)
Appendix A Electrical Characteristics
MC9S08QD4 Series MCU Data Sheet, Rev. 5
188 Freescale Semiconductor
A.8 AC Characteristics
This section describes AC timing characteristics for each peripheral system.
A.8.1 Control Timing
Figure A-12. Reset Timing
Table A-8. Control Timing
Parameter Symbol Min Typical1
1Data in Typical column was characterized at 3.0 V, 25°C.
Max Unit
Bus frequency (tcyc = 1/fBus)f
Bus 1—8MHz
Real-time interrupt internal oscillator period tRTI 700 —1300 μs
External reset pulse width2
2This is the shortest pulse that is guaranteed to be recognized.
textrst 100 — — ns
IRQ pulse width
Asynchronous path2
Synchronous path3
3This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
tILIH, tIHIL 100
1.5 tcyc
——
ns
KBIPx pulse width
Asynchronous path2
Synchronous path3tILIH, tIHIL 100
1.5 tcyc
——ns
Port rise and fall time (load = 50 pF)4
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
4Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40°C to 125°C.
tRise, tFall
—
—
3
30
—
—
ns
BKGD/MS setup time after issuing background debug force
reset to enter user or BDM modes
tMSSU 500 — — ns
BKGD/MS hold time after issuing background debug force
reset to enter user or BDM modes 5
5To enter BDM mode following a POR, BKGD/MS must be held low during the power-up and for a hold time of tMSH after VDD
rises above VLVD.
tMSH 100 — — μs
textrst
RESET PIN
Appendix A Electrical Characteristics
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 189
Figure A-13. IRQ/KBIPx Timing
A.8.2 Timer/PWM (TPM) Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that
can be used as the optional external source to the timer counter. These synchronizers operate from the
current bus rate clock.
Figure A-14. Timer External Clock
Figure A-15. Timer Input Capture Pulse
Table A-9. TPM/MTIM Input Timing
Function Symbol Min Max Unit
External clock frequency fTCLK dc fBus/4 MHz
External clock period tTCLK 4—t
cyc
External clock high time tclkh 1.5 — tcyc
External clock low time tclkl 1.5 — tcyc
Input capture pulse width tICPW 1.5 — tcyc
tIHIL
IRQ/KBIPx
tILIH
IRQ/KBIPx
tText
tclkh
tclkl
TCLK
tICPW
TPMCHn
tICPW
TPMCHn
Appendix A Electrical Characteristics
MC9S08QD4 Series MCU Data Sheet, Rev. 5
190 Freescale Semiconductor
A.9 ADC Characteristics
Table A-10. ADC Characteristics
Characteristic Conditions Symb Min Typ1Max Unit Comment
Supply Current
ADLPC = 1
ADLSMP = 1
ADCO = 1
VDDAD < 3.6 V (3.0 V Typ)
IDDAD
— 110 —
μA
Over
temperature
(Typ 25°C)
VDDAD < 5.5 V (5.0 V Typ) — 130 —
Supply Current
ADLPC = 1
ADLSMP = 0
ADCO = 1
VDDAD < 3.6 V (3.0 V Typ)
IDDAD
— 200 —
μA
VDDAD < 5.5 V (5.0 V Typ) — 220 —
Supply Current
ADLPC = 0
ADLSMP = 1
ADCO = 1
VDDAD < 3.6 V (3.0 V Typ)
IDDAD
— 320 —
μA
VDDAD < 5.5 V (5.0 V Typ) — 360 —
Supply Current
ADLPC = 0
ADLSMP = 0
ADCO = 1
VDDAD < 3.6V (3.0 V Typ)
IDDAD
— 580 —
μA
VDDAD < 5.5V (5.0 V Typ) — 660 —
Supply Current Stop, Reset, Module Off IDDAD — <1 100 nA
Ref Voltage High VREFH 2.7 VDDAD VDDAD V
Ref Voltage Low VREFL VSSAD VSSAD VSSAD V
ADC Conversion
Clock
High Speed (ADLPC = 0) fADCK
0.4 — 8.0 MHz tADCK =
1/fADCK
Low Power (ADLPC = 1) 0.4 — 4.0
ADC Asynchronous
Clock Source
High Speed (ADLPC = 0) fADACK
2.5 4 6.6 MHz tADACK =
1/fADACK
Low Power (ADLPC = 1) 1.25 2 3.3
Conversion Time Short Sample (ADLSMP = 0)
tADC
20 20 23 tADCK
cycles
Add 2 to 5
tBus =1/fBus
cycles
Long Sample (ADLSMP = 1) 40 40 43
Sample Time Short Sample (ADLSMP = 0) tADS
444
tADCK
cycles
Long Sample (ADLSMP = 1) 24 24 24
Input Voltage VADIN VREFL —V
REFH V
Input Capacitance CADIN — 7 10 pF Not Tested
Input Impedance RADIN —515kΩNot Tested
Analog Source
Impedance RAS ——10
(2) kΩExternal to
MCU
Ideal Resolution
(1LSB)
10 bit mode RES 2.637 4.883 5.371 mV VREFH/2N
8 bit mode 10.547 19.53 21.48
Total Unadjusted
Error
10 bit mode ETUE
0±1.5 ±3.5 LSB Includes
quantization
8 bit mode 0 ±0.7 ±1.0
Differential
Non-Linearity
10 bit mode DNL 0±0.5 ±1.0 LSB
8 bit mode 0 ±0.3 ±0.5
Monotonicity and no-missing-codes guaranteed
Integral
Non-Linearity
10 bit mode INL 0±0.5 ±1.0 LSB
8 bit mode 0 ±0.3 ±0.5
Appendix A Electrical Characteristics
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 191
A.10 Flash Specifications
This section provides details about program/erase times and program-erase endurance for the flash
memory.
Program and erase operations do not require any special power sources other than the normal VDD supply.
For more detailed information about program/erase operations, see the Memory section.
Zero-Scale Error 10 bit mode EZS
0±1.5 ±3.1 LSB VADIN = VSSA
8 bit mode 0 ±0.5 ±0.7
Full-Scale Error 10 bit mode EFS
0±1.0 ±1.5 LSB VADIN = VDDA
8 bit mode 0 ±0.5 ±0.5
Quantization Error 10 bit mode EQ——±0.5 LSB 8 bit mode is
not truncated
1Typical values assume VDDAD = 5.0 V, Temp = 25°C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2At 4 MHz, for maximum frequency, use proportionally lower source impedance.
Table A-11. Flash Characteristics
Characteristic Symbol Min Typical Max Unit
Supply voltage for program/erase
–40°C to 125°CV
prog/erase 2.7 5.5 V
Supply voltage for read operation VRead 2.7 5.5 V
Internal FCLK frequency1
1 The frequency of this clock is controlled by a software setting.
fFCLK 150 200 kHz
Internal FCLK period (1/FCLK) tFcyc 56.67μs
Byte program time (random location)(2) tprog 9t
Fcyc
Byte program time (burst mode)(2) tBurst 4t
Fcyc
Page erase time2
2These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for
calculating approximate time to program and erase.
tPage 4000 tFcyc
Mass erase time(2) tMass 20,000 tFcyc
Program/erase endurance3
TL to TH = –40°C to + 125°C
T = 25°C
3Typical endurance for flash was evaluated for this product family on the 9S12Dx64. For additional information on how
Freescale defines typical endurance, please refer to Engineering Bulletin EB619/D, Typical Endurance for Nonvolatile Memory.
10,000 —
100,000
—
—
cycles
Data retention4
4Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated
to 25°C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer
to Engineering Bulletin EB618/D, Typical Data Retention for Nonvolatile Memory.
tD_ret 15 100 — years
Table A-10. ADC Characteristics (continued)
Characteristic Conditions Symb Min Typ1Max Unit Comment
Appendix A Electrical Characteristics
MC9S08QD4 Series MCU Data Sheet, Rev. 5
192 Freescale Semiconductor
MC9S08QD4 Series MCU Data Sheet, Rev. 5
Freescale Semiconductor 193
Appendix B
Ordering Information and Mechanical Drawings
B.1 Ordering Information
This section contains ordering numbers for the devices.
B.1.1 Device Numbering Scheme
• Numbering Scheme for Consumer and Industrial Products
Figure 12-7. Numbering Scheme for Consumer and Industrial Products
• Numbering Scheme for Automotive Products
Figure B-1. Numbering Scheme for Automotive Products
Table B-1. Device Numbering System
Device Number1
1See Tabl e 1 -2 for a complete description of modules included on each device.
Memory Available Packages Qualification
Flash RAM Type Type
MC9S08QD4
MC9S08QD2
4 KB
2 KB
256 B
128 B
8 PDIP
8 NB SOIC
Consumer and Industrial
S9S08QD4
S9S08QD2
4 KB
2 KB
256 B
128 B 8 NB SOIC Automotive
MC
Temperature range
Family
Memory
Status
Core (V = –40°C to +105°C)
(9 = Flash-based)
9S08QD XX
(MC = Fully Qualified)
X
Package designator (see Table B- 2 )
4
Approximate memory size (in Kbytes)
(C = –40°C to +85°C)
(M = –40°C to +125°C)
S
Temperature range
Family
Memory
Status
Core (V = –40°C to +105°C)
(9 = Flash-based)
9S08QD XX
(S = Fully Qualified)
X
Package designator (see Table B- 2 )
4
Approximate memory size (in Kbytes)
(C = –40°C to +85°C)
(M = –40°C to +125°C)
XX
Fab and Maskset Indicator Suffix
Appendix B Ordering Information and Mechanical Drawings
MC9S08QD4 Series MCU Data Sheet, Rev. 5
194 Freescale Semiconductor
B.2 Mechanical Drawings
The following pages are mechanical specifications for the package options. See Table B-2 for the
document number of each package type.
Table B-2. Package Information
Pin Count Type Designator Document No.
8 PDIP PC 98ASB42420B
8 NB SOIC SC 98ASB42564B
MC9S08QD4
Rev. 5, 11/2008
How to Reach Us:
Home Page:
www.freescale.com
Web Support:
http://www.freescale.com/support
USA/Europe or Locations Not Listed:
Freescale Semiconductor, Inc.
Technical Information Center, EL516
2100 East Elliot Road
Tempe, Arizona 85284
1-800-521-6274 or +1-480-768-2130
www.freescale.com/support
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
www.freescale.com/support
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,
Tokyo 153-0064
Japan
0120 191014 or +81 3 5437 9125
support.japan@freescale.com
Asia/Pacific:
Freescale Semiconductor China Ltd.
Exchange Building 23F
No. 118 Jianguo Road
Chaoyang District
Beijing 100022
China
+86 10 5879 8000
support.asia@freescale.com
For Literature Requests Only:
Freescale Semiconductor Literature Distribution Center
P.O. Box 5405
Denver, Colorado 80217
1-800-441-2447 or +1-303-675-2140
Fax: +1-303-675-2150
LDCForFreescaleSemiconductor@hibbertgroup.com
Information in this document is provided solely to enable system and software
implementers to use Freescale Semiconductor products. There are no express or
implied copyright licenses granted hereunder to design or fabricate any integrated
circuits or integrated circuits based on the information in this document.
Freescale Semiconductor reserves the right to make changes without further notice to
any products herein. Freescale Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale Semiconductor assume any liability arising out of the application or use of any
product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters that may be
provided in Freescale Semiconductor data sheets and/or specifications can and do vary
in different applications and actual performance may vary over time. All operating
parameters, including “Typicals”, must be validated for each customer application by
customer’s technical experts. Freescale Semiconductor does not convey any license
under its patent rights nor the rights of others. Freescale Semiconductor products are
not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Freescale Semiconductor product
could create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Freescale
Semiconductor was negligent regarding the design or manufacture of the part.
RoHS-compliant and/or Pb-free versions of Freescale products have the functionality
and electrical characteristics as their non-RoHS-compliant and/or non-Pb-free
counterparts. For further information, see http://www.freescale.com or contact your
Freescale sales representative.
For information on Freescale’s Environmental Products program, go to
http://www.freescale.com/epp.
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
All other product or service names are the property of their respective owners.
© Freescale Semiconductor, Inc. 2006-2008. All rights reserved.
