General Description
The DS4830 provides a complete optical control, calibra-
tion, and monitor solution based on a low-power, 16-bit,
microcontroller core, providing program and RAM data
memory. I/O resources include a fast/accurate analog-to-
digital converter (ADC), fast comparators with an inter-
nal comparison digital-to-analog converter (DAC), 12-bit
DACs, 12-bit PWMs, internal and external temperature
sensors, fast sample/hold, I2C slave host interface, and a
multiprotocol serial master/slave interface.
Direct connection of diode-connected transistors, used
as remote temperature sensors, is supported as well as
expansion to additional external digital temperature sen-
sor ICs using the on-chip master I2C interface. An inde-
pendent slave I2C interface facilitates communication to
a host microprocessor in addition to password-protected
in-system reprogramming of the on-chip flash.
Firmware development is supported by third-party highly
versatile C-compilers and development software that
programs flash and performs in-circuit debug through the
integrated JTAG interface and associated hardware.
Applications
●PON Diplexers and Triplexers: GPON, 10GEPON,
XPON OLT, ONU
●Optical Transceivers: XFP, SFP, SFP+, QSFP, 40G,
100G
Features
●16-Bit Low-Power Microcontroller
●36 kWords Total Program Memory
• 32 kWords Flash Program Memory
• 4 kWords ROM Program Memory
●1 kWords Data RAM
●8 DAC Channels
• 12-Bit Buffered Voltage DACs
• Internal or External Reference
●10 PWM Channels
• Boost/Buck DC-DC Control with Support for
7-Bit to 12-Bit Resolution and 1MHz Switching
Frequency
• Supports 4-Channel TECC H-Bridge Control
●8-Bit Fast Comparator with 16-Input Mux
• 1.6μs per Comparison
●13-Bit A/D Converter with 26-Input Mux (27ksps)
●Temperature Measurement Analog Front-End
• Internal Temperature Sensor, ±3°C
• 0.0625°C Resolution
• Supports Two External Temperature Sensors
• Differential Rail-Rail Inputs
●31 GPIO Pins
●Maskable Interrupt Sources
●Internal 20MHz Oscillator, CPU Core Frequency
10MHz
• 4% Accurate from 0°C to +50°C
●Up to 133MHz External Clock for PWM and Timers
●Slave Communication Interface: SPI or 400kHz
I2C-Compatible 2-Wire
●Master Communication Interface: SPI, 400kHz
I2C-Compatible, or Maxim 3-Wire Laser Driver
●I2C and JTAG Bootloader
●Two 16-Bit Timers
●2.97V to 3.63V Operating Voltage Range
●Brownout Monitor
●JTAG Port with In-System Debug and Programming
●Low Power Consumption (16mA) with All Analog
Active
Ordering Information appears at end of data sheet.
Typical Application Circuit appears at end of data sheet.
19-5934; Rev 3; 1/17
DS4830 Optical Microcontroller
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be
simultaneously available through various sales channels. For information about device errata, go to: www.maximintegrated.com/errata.
VDD to GND .......................................................-0.3V to +3.97V
SCL, SDA, RST .................................................. -0.3V to +3.63V
All Other Pins to GND
except REG18 and REG285 ...............-0.3V to (VDD + 0.5V)*
Continuous Sink Current .................... 20mA per pin, 50mA total
Continuous Source Current ................ 20mA per pin, 50mA total
Operating Temperature Range ........................... -40°C to +85°C
Storage Temperature Range ............................ -55°C to +125°C
Lead Temperature (soldering, 10s) ................................. +300°C
Soldering Temperature (reflow) ....................................... +260°C
*Subject to not exceeding +3.97V.
(VDD = 2.97V to 3.63V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = 3.3V, TA = +25°C.)
(TA = -40°C to +85°C, unless otherwise noted.)
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
DC Electrical Characteristics
Recommended Operating Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VDD Operating Voltage VDD (Note 1) 2.97 3.63 V
Input Logic-High VIH 0.7 x VDD VDD + 0.3 V
Input Logic-Low VIL -0.3 0.3 x VDD V
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package Information
40TQFN
Package Code T4055+2
Outline Number 21-0140
Land Pattern Number 90-0016
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Current
ICPU
CPU mode, all analog disabled
(Notes 2, 3) 4.8
mA
IFASTCOMP 2
ISAMPLEHOLDS Both sample/hold 1.5
IADC 2.8
IDACS Per channel (Note 4) 0.6
Brownout Voltage VBO Monitors VDD (Note 1) 2.7 V
Brownout Hysteresis VBOH Monitors VDD (Note 1) 0.07 V
1.8V Regulator Initial Voltage VREG18 (Note 1) 1.71 1.8 1.89 V
2.85V Regulator Initial Voltage VREG285 (Note 1) 2.8 2.85 2.9 V
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(VDD = 2.97V to 3.63V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = 3.3V, TA = +25°C.)
DC Electrical Characteristics (continued)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Clock Frequencies
fOSC-
PERIPHERAL
TA = +25°C (Note 5) 20 MHz
fMOSC-CORE TA = +25°C (Note 5) 10
Clock Error fERR TA = -40°C to +85°C ±8 %
External Clock Input fXCLK 20 133 MHz
Voltage Range: GP[15:0],
SHEN, DACPW[7:0], REFINA,
REFINB
VRANGE (Note 1) -0.3 VDD +
0.3 V
Output Logic-Low: SCL, SDA,
MDIO, MDI, MCL, MCS,
REFINA, REFINB, All GPIO
Pins
VOL1 IOL = 4mA (Note 1) 0.4 V
Output Logic-High: SDA, MDIO,
MDI, MCL, MCS, REFINA,
REFINB, All GPIO Pins Not
Open Drain
VOH1 IOH = -4mA (Note 1) VDD -
0.5 V
Pullup Current: MDIO, MDI,
MCL, MCS, All GPIO Pins IPU1 VPIN = 0V 26 55 78 µA
GPIO Drive Strength, Extra
Strong Outputs: GP0, GP1,
MCS, PW8, PW9
RHISt 9 27.6
Ω
RLOSt 8 25.2
GPIO Drive Strength, Strong
Outputs: MDI, DACPW3,
DACPW6
RHIA 17 32.4
Ω
RLOA 12 26.4
GPIO Drive Strength, Excluding
Strong GPIO Outputs
RHIB 27 57 Ω
RLOB 31 63
DAC
DAC Resolution DACR12 Bits
DAC Internal Reference
Accuracy DACREFACC 2.5V internal reference -1.25 +1.25 %
DAC Internal Reference Power-
Up Speed tDACPUP 99% settled 10 µs
Reference Input Full-Scale
Range (REFINA, REFINB) REFFS 1 2.5 V
DAC Operating Current IDACS Per channel See the DC Electrical
Characteristics
DAC Integral Nonlinearity DACINL 12-bit at 2.5V reference 12 LSB
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(VDD = 2.97V to 3.63V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = 3.3V, TA = +25°C.)
DC Electrical Characteristics (continued)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DAC Differential Nonlinearity DACDNL 12-bit at 2.5V reference, guaranteed
by design, not production tested 1 LSB
DAC Offset VOFFSET-DAC At code “0” 0 18 mV
DAC Source Load Regulation IDAC-SOURCE 0 to full-scale output 8.6 mV/mA
DAC Sink Capability and Sink
Load Regulation
RDAC-SINK
0 to 0.5V output, limited by output
buffer impedance 500 Ω
IDAC-SINK 0.5V to full-scale output 11.5 mV/mA
DAC Settling Time tDAC
Output load capacitance between
33pF and 270pF, from 10% to 90% 10 µs
FAST COMPARATOR/QUICK TRIPS
Fast Comparator Resolution FCR8 Bits
Fast Comparator Internal
Reference Accuracy FCREFACC -1.25 +1.25 %
Fast Comparator Operating
Current IFASTCOMP
See the DC Electrical
Characteristics
Fast Comparator Full Scale VFS-COMP 2.38 2.42 2.48 V
Fast Comparator Integral
Nonlinearity INL Differential mode, 2.2nF capacitor at
input, tested at worst-case positions ±2 LSB
Fast Comparator Differential
Nonlinearity DNL Differential mode, 2.2nF capacitor at
input, guaranteed by design 1 LSB
Fast Comparator Offset VOFFSET-COMP 2 LSB
Fast Comparator Input
Resistance RIN-COMP (Note 6) 15 MΩ
Fast Comparator Input
Capacitance CIN-COMP 4 pF
Fast Comparator Sample Rate fCOMP 625 ksps
ADC
ADC Resolution ADCRDefault or slow ADC clock setting 13 Bits
ADC Internal Reference
Accuracy ADCREFACC -0.85 +0.85 %
ADC Operating Current IADC
See the DC Electrical
Characteristics
ADC Full-Scale 1 VFS-ADC1 1.2 V
ADC Full-Scale 2 VFS-ADC2 0.6 V
ADC Full-Scale 3 VFS-ADC3 2.4 V
ADC Full-Scale 4 VFS-ADC4 4.8 V
ADC Integral Nonlinearity ADCINL Computed using end points best t:
13-bit, +25°C, VDD = 3.3V, VFS-ADC3
10 LSB
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(VDD = 2.97V to 3.63V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = 3.3V, TA = +25°C.)
DC Electrical Characteristics (continued)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
ADC Differential Nonlinearity ADCDNL VFS = 1.2V ±0.5 LSB
ADC Sample-Sample Deviation ADC full-scale set to VFS-ADC3 5 LSB
ADC Offset VOFFSET-ADC 13-bit, VFS = 1.2V -8 +1 +8 LSB
GP[15:0] Input Resistance RIN-ADC 15 MΩ
ADC Sample Rate fSAMPLE (Note 7) 8 ksps
ADC Temperature Conversion
Time tTEMP 4.2 ms
Internal Temperature
Measurement Error TINTERR (Note 8) ±2 °C
Remote Temperature
Measurement Error
(DS4830 Error Only)
TREMERR (Note 8) ±2 °C
SAMPLE/HOLD
Sample/Hold Input Range VSHP ADC-SHN[1:0] = GND 0 1 V
Sample/Hold Capacitance CSH ADC-SHP[1:0] to ADC-SHN[1:0] 5 pF
Sample Input Leakage ISHLKG
ADC-SHP[1:0] and ADC-SHN[1:0]
connected to GND 1.2 µA
Sample Time ts
ADC-SHP[1:0] and ADC-SHN[1:0]
connected to 50Ω voltage source 300 ns
Sample Conversion Complete th
Time from valid sample to ADC data
available 320 µs
Sample Offset VSH-OFF Measured at 10mV -10 -1.6 +7 mV
Sample Error ERRSH
VADC-SHP to VADC-SHN = 300mV,
ts = 300ns, driven with 50Ω voltage
source
-4 +4 %
Sample Discharge Strength RDIS
ADC-SHP[1:0] or ADC-SHN[1:0] to
GND 900 Ω
FLASH MEMORY
Flash Erase Time tME Mass erase 22.9 24.14 25.35 ms
tPE Page erase 22.9 24.14 25.35
Flash Programming Time per
Word tPROG (Note 9) 69 74 79 µs
Flash Programming
Temperature TFLASH -40 +85 °C
Flash Endurance nFLASH TA = +50°C, guaranteed by design 20,000 Write
Cycles
Data Retention tRET TA = +50°C, guaranteed by design 100 Years
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(VDD = 2.97V to 3.63V, TA = -40°C to +85°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
I2C-COMPATIBLE INTERFACE (See Figure 1)
SCL/MSCL Clock Frequency fSCL Timeout not enabled 400 kHz
SCL Bootloader Clock Frequency fSCL:BOOT 100 kHz
Bus Free Time Between a STOP
and START Condition tBUF 1.3 µs
Hold Time (Repeated)
START Condition tHD:STA (Note 10) 0.6 µs
Low Period of SCL/MSCL Clock tLOW 1.3 µs
High Period of SCL/MSCL Clock tHIGH 0.6 µs
Setup Time for a (Repeated)
START Condition tSU:STA 0.6 µs
Data Hold Time (Note 11) tHD:DAT
Receive 0 ns
Transmit 300
Data Setup Time tSU:DAT (Note 12) 100 ns
SCL/MSCL, SDA/MSDA
Capacitive Loading CB(Note 12) 400 pF
Rise Time of Both SDA and
SCL Signals tR(Note 12) 20 + 0.1CB300 ns
Fall Time of Both SDA and
SCL Signals tF(Note 12) 20 + 0.1CB300 ns
Setup Time for STOP Condition tSU:STO 0.6 µs
Spike Pulse Width That Can Be
Suppressed by Input Filter tSP (Note 13) 50 ns
SCL/MSCL and SDA/MSDA Input
Capacitance CBIN 5 pF
SMBus Timeout tSMBUS 30 ms
3-WIRE DIGITAL INTERFACE (See Figure 2)
MCL Clock Frequency fSCLOUT 1000 kHz
MCL Duty Cycle t3WDC 50 %
MDIO Setup Time tDS 100 ns
MDIO Hold Time tDH 100 ns
MCS Pulse-Width Low tCSW 500 ns
MCS Leading Time Before the
First MCL Edge tL500 ns
MCS Trailing Time After the Last
MCL Edge tT500 ns
MDIO, MCL Load CB3W Total bus capacitance on one line 10 pF
AC Electrical Characteristics
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(VDD = 2.97V to 3.63V, TA = -40°C to +85°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SPI DIGITAL INTERFACE (See Figure 3 and Figure 4)
SPI Master Operating Frequency 1/tMSPICK fSYS/2 MHz
SPI Slave Operating Frequency 1/tSSPICK fSYS/4 MHz
SPI I/O Rise/Fall Time tSPI_RF CL = 15pF, pullup = 560Ω 25 ns
MSPICK Output Pulse-Width
High/Low tMCH, tMCL
tMSPICK/2 - tSPI_
RF
ns
MSPIDO Output Hold After
MSPICK Sample Edge tMOH
tMSPICK/2 - tSPI_
RF
ns
MSPIDO Output Valid to MSPICK
Sample Edge
(MSPIDO Setup)
tMOV
tMSPICK/2 - tSPI_
RF
ns
MSPIDI Input Valid to MSPICK
Sample Edge (MSPIDI Setup) tMIS 2tSPI_RF ns
MSPIDI Input to MSPICK
Sample Edge Rise/Fall Hold tMIH 0 ns
MSPICK Inactive to MSPIDO
Inactive tMLH
tMSPICK/2 - tSPI_
RF
ns
SSPICK Input Pulse-Width High/
Low tSCH, tSCL tSSPICK/2 ns
SSPICS Active to First Shift Edge tSSE tSPI_RF ns
SSPIDI Input to SSPICK Sample
Edge Rise/Fall Setup tSIS tSPI_RF ns
SSPIDI Input from SSPICK
Sample Edge Transition Hold tSIH tSPI_RF ns
SSPIDO Output Valid After
SSPICK Shift Edge Transition tSOV 2tSPI_RF ns
SSPICS Inactive tSSH
tSSPICK +
tSPI_RF
ns
SSPICK Inactive to SSPICS
Rising tSD tSPI_RF ns
SSPIDO Output Disabled After
SSPICS Edge Rise tSLH
2tSSPICK +
2tSPI_RF
ns
AC Electrical Characteristics (continued)
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Note 1: All voltages are referenced to GND. Currents entering the IC are specified as positive, and currents exiting the IC are
specified as negative.
Note 2: Maximum current assuming 100% CPU duty cycle.
Note 3: This value does not include current in GPIO, SCL, SDA, MDIO, MDI, MCL, REFINA, and REFINB.
Note 4: Using internal reference.
Note 5: There is one internal oscillator. The oscillator (peripheral clock) goes through a 2:1 divider to create the core clock.
Note 6: Guaranteed by design.
Note 7: ADC conversions are delayed up to 1.6µs if the fast comparator is sampling the selected ADC channel. This can cause a
slight decrease in the ADC sampling rate.
Note 8: Temperature readings average 64 times.
Note 9: Programming time does not include overhead associated with the utility ROM interface.
Note 10: fSCL must meet the minimum clock low time plus the rise/fall times.
Note 11: This device internally provides a hold time of at least 75ns for the SDA signal (referred to the VIH:MIN of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
Note 12: CB—Total capacitance of one bus line in pF.
Note 13: Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant.
(VDD = 2.97V to 3.63V, TA = -40°C to +85°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
JTAG DIGITAL INTERFACE (See Figure 5)
JTAG Logic Reference VREF VDD/2 V
TCK High Time tTH 0.5 µs
TCK Low Time tTL 0.5 µs
TCK Low to TDO Output tTLQ 0.125 µs
TMS, TDI Input Setup to TCK
High tDVTH 0.25 µs
TMS, TDI Input Hold After TCK
High tTHDX 0.25 µs
AC Electrical Characteristics (continued)
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Figure 1. I2C Timing Diagram
Figure 2. 3-Wire Timing Diagram
Timing Diagrams
SCL/
MSCL
NOTE: TIMING IS REFERENCED TO VILMAX AND VIHMIN.
SDA/
MSDA
STOP START REPEATED
START
tBUF
tHD:STA
tHD:DAT tSU:DAT
tSU:STO
tHD:STA
tSP
tSU:STA
tHIGH
tR
tF
tLOW
MCS
MCL
MDIO
MCS
MCL
MCS
1 2 3 4 5 6 7 8
A6
9 10 11 12 13 14 150
1 2 3 4 5 6 7 8 9 10 11 12 13 14 150
A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
WRITE MODE
READ MODE
A0
A6 A5 A4 A3 A2 A1 A0
tL
tL
tDS
tDH
tDS
tDH
tT
tT
R/W
R/W
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Figure 3. SPI Master Communications Timing Diagram
Figure 4. SPI Slave Communications Timing Diagram
Timing Diagrams (continued)
MSPICS
(SAS = 0)
MSPICK
CKPOL/CKPHA
MSPICK
CKPOL/CKPHA
1/0
0/1
1/1
0/0
1/0
0/1
1/1
0/0
MSPIDO
MSPIDI
LSB
LSB
SHIFT SAMPLE SHIFT SAMPLE
tMSPICK
tMCH
tMOH
tMIS
tMOV
tSPI_RF
tMLH
tMIH
tMCL
MSB MSB-1
MSB MSB-1
SHIFT SAMPLE SHIFT SAMPLE
SSPICS
(SAS = 1)
SSPIDI
SSPIDO
tSSE
tSSPICK
tSCH tSCL
tSIS
tSOV tSLH
tSSH
tSD
tSPI_RF
tSIH
MSB MSB-1
MSB MSB-1
LSB
LSB
SSPICK
CKPOL/CKPHA
SSPICK
CKPOL/CKPHA
1/0
0/1
1/1
0/0
1/0
0/1
1/1
0/0
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Figure 5. JTAG Timing Diagram
Timing Diagrams (continued)
TCK
TMS/TDI
TDO
VREF
tTH
tTLQ
tTL
tTHDX
tDVTH
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(TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics
DAC INL (LSB)
DS4830 toc01
SETTING (DEC)
DAC INL (LSB)
400035002500 30001000 1500 2000500
-4
-3
-2
-1
0
1
2
3
4
5
-5
0
ADC INL (LSB)
DS4830 toc03
INPUT VOLTAGE (V)
ADC INL (LSB)
2.01.51.00.5
-8
-3
2
7
12
-13
0
DAC DNL (LSB)
DS4830 toc02
SETTING (DEC)
DAC DNL (LSB)
400035002500 30001000 1500 2000500
-0.9
-0.8
-0.6
-0.4
-0.2
0
0.2
-0.7
-0.5
-0.3
-0.1
0.1
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
-1.0
0
ADC DNL (LSB)
DS4830 toc04
INPUT VOLTAGE (V)
ADC DNL (LSB)
2.01.51.00.5
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1.0
-1.0
0 2.5
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Pin Description
Pin Conguration
TQFN
(5mm x 5mm)
TOP VIEW
35
36
34
33
12
11
13
SCL
GP0
REG285
GP1
VDD
14
RST
MCS
MDI
MDIO
VDD
PW9
PW8
SHEN
GP15
1 2
DACPW2
4 5 6 7
27282930 26 24 23 22
DACPW3
DACPW4
GP11
GP10
REG18
GP9
SDA
MCL
3
25
37
DACPW5 GP8
38
39
40
DACPW6
REFINB
DACPW7
GP7
GP6
GP5
EP
+
DACPW1
32
15
GP12
DACPW0
31
16
17
18
19
20 GP13
GP2
GP3
GP4 GP14
8 9 10
21
REFINA
DS4830
PIN NAME INPUT
STRUCTURE(S)
OUTPUT
STRUCTURE
POWER-ON
STATE
SELECTABLE FUNCTIONS
(FIRST COLUMN IS DEFAULT FUNCTION) PORT
1RST Digital Open Drain High
Impedance RST — — — —
2 SCL Digital Open Drain High
Impedance
I2C Slave
Clock SCL
SPI
SSPICK — — —
3 SDA Digital Open Drain High
Impedance
I2C Slave
Data SDA
SPI
SSPIDI — — —
4 GP0 ADC/Digital Input Push-Pull,
Extra Strong 55µA Pullup ADC-S0 ADC-
D0P PW0 — P2.0
5 REG285 VREG None 2.85V Only function is for bypass capacitor for
2.85V internal regulator —
6 GP1 ADC/Digital Input Push-Pull,
Extra Strong 55µA Pullup ADC-S1 ADC-
D0N PW1 — P2.1
7 VDD
Voltage Supply, ADC
Input None VDD ADC-VDD — — — —
8 GP2 SH Input, ADC Input None High
Impedance ADC-S2 ADC-
SHP0
ADC-
D1P — —
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Pin Description (continued)
PIN NAME INPUT
STRUCTURE(S)
OUTPUT
STRUCTURE
POWER-ON
STATE
SELECTABLE FUNCTIONS
(FIRST COLUMN IS DEFAULT FUNCTION) PORT
9 GP3 SH input, ADC Input None High
Impedance ADC-S3 ADC-
SHN0
ADC-
D1N — —
10 GP4 ADC/Digital Input Push-Pull 55µA Pullup JTAG TCK ADC-S4 ADC-
D2P — P6.0
11 GP5 ADC/Digital Input Push-Pull 55µA Pullup JTAG TDI ADC-S5 ADC-
D2N — P6.1
12 GP6 ADC/Digital Input Push-Pull 55µA Pullup ADC-S6 ADC-
D3P PW2 SPI
SSPIDO P2.2
13 GP7 ADC/Digital Input Push-Pull 55µA Pullup ADC-S7 ADC-
D3N PW3 SPI
SSPICS P2.3
14 GP8
ADC/Digital I/P,
External Temp A+ I/P
(ADC-TEXT_A)
Push-Pull 55µA Pullup ADC-S8 ADC-
D4P — — P2.4
15 GP9
ADC/Digital I/P,
External Temp A- I/P
(ADC-TEXT_A)
Push-Pull 55µA Pullup ADC-S9 ADC-
D4N — — P2.5
16 REG18 VREG None 1.8V Pin for 1.8V regulator bypass capacitor —
17 GP10
ADC/Digital I/P,
External Temp A+ I/P
(ADC-TEXT_B)
Push-Pull 55µA Pullup JTAG TMS ADC-
S10
ADC-
D5P — P6.2
18 GP11
ADC/Digital I/P,
External Temp A+ I/P
(ADC-TEXT_B)
Push-Pull 55µA Pullup JTAG TDO ADC-
S11
ADC-
D5N — P6.3
19 GP12 SH Input, ADC/Digital
Input Push-Pull 55µA Pullup ADC-S12 ADC-
SHP1
ADC-
D6P — P0.0
20 GP13 SH Input, ADC/Digital
Input Push-Pull 55µA Pullup ADC-S13 ADC-
SHN1
ADC-
D6N — P0.1
21 GP14 ADC/Digital Input Push-Pull 55µA Pullup ADC-S14 ADC-
D7P SHEN1 — P0.2
22 GP15 ADC/Digital Input Push-Pull 55µA Pullup ADC-S15 ADC-
D7N — — P0.3
23 SHEN Digital Push-Pull 55µA Pullup SHEN0 — — — P6.4
24 MDIO Digital Push-Pull 55µA Pullup 3-Wire Data
MDIO
I2C
MSDA
SPI
MSPIDO
PW4 P1.0
25 MDI Digital Push-Pull,
Strong 55µA Pullup — — SPI
MSPIDI PW5 P1.3
26 MCL Digital Push-Pull 55µA Pullup 3-Wire Clock
MCL
I2C
MSCL
SPI
MSPICK PW6 P1.1
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Pin Description (continued)
PIN NAME INPUT
STRUCTURE(S)
OUTPUT
STRUCTURE
POWER-ON
STATE
SELECTABLE FUNCTIONS
(FIRST COLUMN IS DEFAULT FUNCTION) PORT
27 MCS Digital Push-Pull,
Extra Strong 55µA Pullup 3-Wire Chip
Select MCS —SPI
MSPICS PW7 P1.2
28 VDD Voltage Supply None VDD ADC-VDD — — — —
29 PW9 Digital Push-Pull,
Extra Strong 55µA Pullup PW9 — — — P0.7
30 PW8 Digital Push-Pull,
Extra Strong 55µA Pullup PW8 — — — P0.6
31 REFINA Reference, ADC/Digital
Input (ADC_REFA) Push-Pull 55µA Pullup ADC-
REFINA — — — P2.6
32 DACPW0 Digital Push-Pull 55µA Pullup
DAC0, FS
= REFINA
or Internal
Reference
PW0 — — P0.4
33 DACPW1 Digital Push-Pull 55µA Pullup
DAC1, FS
= REFINA
or Internal
Reference
PW1 — — P0.5
34 DACPW2 Digital Push-Pull 55µA Pullup
DAC2, FS
= REFINA
or Internal
Reference
PW2 CLKIN — P6.5
35 DACPW3 Digital Push-Pull,
Strong 55µA Pullup
DAC3, FS
= REFINA
or Internal
Reference
PW3 — — P1.5
36 DACPW4 Digital Push-Pull 55µA Pullup
DAC4, FS
= REFINB
or Internal
Reference
PW4 — — P1.6
37 DACPW5 Digital Push-Pull 55µA Pullup
DAC5, FS
= REFINB
or Internal
Reference
PW5 — — P1.7
38 DACPW6 Digital Push-Pull,
Strong 55µA Pullup
DAC6, FS
= REFINB
or Internal
Reference
PW6 — — P6.6
39 REFINB Reference, ADC/
Digital Input Push-Pull 55µA Pullup ADC-
REFINB — — — P1.4
DS4830 Optical Microcontroller
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Note: Bypass VDD, REG285, and REG18 each with a 1µF X5R and 10nF capacitors to ground. All input-only pins and open-drain
outputs are high impedance after VDD exceeds VBO and prior to code execution. Pins configured as GPIO have a weak internal pul-
lup. See the Selectable Functions table for more information.
Pin Description (continued)
PIN NAME INPUT
STRUCTURE(S)
OUTPUT
STRUCTURE
POWER-ON
STATE
SELECTABLE FUNCTIONS
(FIRST COLUMN IS DEFAULT FUNCTION) PORT
40 DACPW7 Digital Push-Pull 55µA Pullup
DAC7, FS
= REFINB
or Internal
Reference
PW7 — — P2.7
— EP Exposed Pad
(Connect to GND) — GND — — — — —
Selectable Functions
FUNCTION NAME DESCRIPTION
ADC-D[7:0][P/N] Differential Inputs to ADC. Also used for external temperature sensors.
ADC-REFIN[A/B] REFINA and REFINB Monitor Inputs to ADC
ADC-S[15:0] Single-Ended Inputs to ADC
ADC-SH[P/N][1:0] Sample/Hold Inputs 1 and 0
ADC-VDD VDD Monitor Input to ADC
DAC[7:0] Voltage DAC Outputs
MCL, MCS, MDIO Maxim Proprietary 3-Wire Interface, MCL (Clock), MCS (Chip Select), MDIO (Data). Used to control
the MAX3798 family of high-speed laser drivers.
MSCL, MSDA I2C Master Interface: MSCL (I2C Master Slave), MSDA (I2C Master Data)
MSPICK, MSPICS, MSPIDI,
MSPIDO
SPI Master Interface: MSPICK (Clock), MSPICS (Active-Low Chip Select), MSPIDI (Data In),
MSPIDO (Data Out)
P0.n, P1.n, P2.n, P6.n General-Purpose Inputs/Outputs. Can also function as interrupts.
PW[9:0] PWM Outputs
RST Used by JTAG and as Active-Low Reset for Device
SCL, SDA I2C Slave Interface: SCL (I2C Slave Clock), SDA (I2C Slave Data). These also function as a
password-protected programming interface.
SHEN[1:0] Sample/Hold Enable Inputs. Can also function as interrupts.
SSPICK, SSPICS, SSPIDI,
SSPIDO
SPI Slave Interface: SSPICK (Clock), SSPICS (Active-Low Chip Select), SSPIDI (Data In),
SSPIDO (Data Out). In SPI slave mode, the I2C slave interface is disabled.
TCK, TDI, TDO, TMS JTAG Interface Pins. Also includes RST.
DS4830 Optical Microcontroller
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Block Diagram
CLOCK CONTROL,
WATCHDOG TIMER, AND
POWER MONITOR
CKCN
WDCN
IC
IC IP
LOOP COUNTERS
DATA POINTERS
DPC
4K x 16 UTILITY ROM
FFFFh
8FFFh
8000h
7FFFh
0000h
PROGRAM
MEMORY SPACE
LC[n]
AP
APC
PSF
10MHz CPU CLOCK
IMR
IIR
INTERRUPT
LOGIC
ADDRESS
GENERATION
DP[0], DP[1],
FP = (BP+OFFS)
32K x 16 USER
PROGRAM MEMORY
ACCUMULATORS
(16)
BOOLEAN
VARIABLE
MANIPULATION
INSTRUCTION
DECODE
(src, dst TRANSPORT
DETERMINATION)
4K x 16 UTILITY ROM
FFFFh
8FFFh
8000h
03FFh
0000h
DATA
MEMORY SPACE
1K x 16 SRAM
SP
STACK MEMORY
16 x 16
MASTER:
I2C
SPI
3-WIRE
MDI
MDIO
MCL
MCS
SLAVE:
I2C
SPI
SCL
SDA
SSPIDO
SSPICS
SHEN[1:0]
GP[15:0]
CLKIN
REFIN[A/B]
PW[9:0]
DACPW[7:0]
16-BIT TIMERS
x 2
20MHz
OSC
/2 CORE
CLOCK
MEMORY MANAGEMENT
UNIT (MMU)
RST
13-BIT ADC
8-BIT COMP D-PWM x 10
VDD
ADC-D[7:0][P/N]
PWM[9:0]
ADC-S[15:0]
INTERNAL TEMP
REFIN[A/B]
DAC[7:0]
12-BIT
DAC x 8 VREF
UP TO 31
PORT PINS GPIO
DS4830
CS
x2DISCH
ADC-SHP[1:0]
ADC-SHN[1:0]
SAMPLE/HOLD
DS4830 Optical Microcontroller
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Detailed Description
The following is an introduction to the primary features
of the DS4830 optical microcontroller. More detailed
descriptions of the device features can be found in the
DS4830 User’s Guide.
Microcontroller Core Architecture
The device employs a low-power, low-cost, high-perfor-
mance, 16-bit RISC microcontroller with on-chip flash
memory. It is structured on an advanced, 16 accumula-
tor- based, 16-bit RISC architecture. Fetch and execution
operations are completed in one cycle without pipelining,
since the instruction contains both the op code and data.
The highly efficient core is supported by 16 accumulators
and a 16-level hardware stack, enabling fast subroutine
calling and task switching. Data can be quickly and
efficiently manipulated with three internal data pointers.
Multiple data pointers allow more than one function to
access data memory without having to save and restore
data pointers each time. The data pointers can auto-
matically increment or decrement following an operation,
eliminating the need for software intervention.
Module Information
Top-level instruction decoding is extremely simple and
based on transfers to and from registers. The registers
are organized into functional modules, which are in turn
divided into the system register and peripheral register
groups.
Peripherals and other features are accessed through
peripheral registers. These registers reside in modules 0
to 5. The following provides information about the specific
module in which each peripheral resides:
●Module 0: Timer 1, GPIO Ports 0, 1, and 2
●Module 1: I2C Master, GPIO Port 6, SPI Slave, SVM
●Module 2: I2C Slave, Analog-to-Digital Converter
(ADC), Sample/Hold, Temperature, 3-Wire Master
●Module 3: Timer 2, MAC-Related Registers
●Module 4: Digital-to-Analog Converter (DAC)
●Module 5: Quick Trips, SPI Master, PWM
Instruction Set
The instruction set is composed of fixed-length, 16-bit
instructions that operate on registers and memory loca-
tions. The instruction set is highly orthogonal, allowing
arithmetic and logical operations to use any register along
with the accumulator. Special-function registers control
the peripherals and are subdivided into register modules.
Memory Organization
The device incorporates several memory areas:
●32 kWords of flash memory for application program
storage
●1 kWords of SRAM for storage of temporary variables
●4 kWords of utility ROM contain a debugger and pro-
gram loader
●16-level stack memory for storage of program return
addresses and general-purpose use
The memory is implemented with separate address spac-
es for program memory, data memory, and register space.
ROM, application code, and data memory can be placed
into a single contiguous memory map. The device allows
data memory to be mapped into program space, permit-
ting code execution from data memory. In addition, pro-
gram memory can be mapped into data space, permitting
code constants to be accessed as data memory. Figure 6
shows the DS4830’s memory map when executing from
program memory space. Refer to the DS4830 User’s
Guide for memory map information when executing from
data or ROM space.
The incorporation of flash memory allows field upgrade of
the firmware. Flash memory can be password protected
with a 16-word key, denying access to program memory
by unauthorized individuals.
Utility ROM
The utility ROM is a 4 kWord block of internal ROM
memory that defaults to a starting address of 8000h. The
utility ROM consists of subroutines that can be called from
application software, which includes the following:
●In-system programming (bootstrap loader) over JTAG
or I2C-compatible interfaces
●In-circuit debug routines
●Internal self-test routines
●Callable routines for in-application flash programming
Following any reset, execution begins in the utility ROM.
The ROM software determines whether the program
execution should immediately jump to location 0000h,
the start of application code, or to one of the special
routines mentioned. Routines within the utility ROM are
firmware-accessible and can be called as subroutines by
the application software. More information on the utility
ROM contents is contained in the DS4830 User’s Guide.
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Password
Some applications require protection against unauthor-
ized viewing of program code memory. For these applica-
tions, access to in-system programming, in-application
programming, or in-circuit debugging functions is prohib-
ited until a password has been supplied. The password is
defined as the 16 words of physical program memory at
addresses 0010h–001Fh.
A single password lock (PWL) bit is implemented in
the device. When the PWL is set to 1 (power-on-reset
default) and the contents of the memory at addresses
0010h–001Fh are any value other than all FFh or 00h, the
password is required to access the utility ROM, including
in-circuit debug and in-system programming routines that
allow reading or writing of internal memory. When PWL is
cleared to 0, these utilities are fully accessible without the
password. The password is automatically set to all ones
following a mass erase.
Detailed information regarding the password can be
found in the DS4830 User’s Guide.
Stack Memory
A 16-bit, 16-level internal stack provides storage for pro-
gram return addresses. The stack is used automatically
by the processor when the CALL, RET, and RETI instruc-
tions are executed and interrupts serviced. The stack can
also be used explicitly to store and retrieve data by using
the PUSH, POP, and POPI instructions.
On reset, the stack pointer, SP, initializes to the top of the
stack (0Fh). The CALL, PUSH, and interrupt-vectoring
operations increment SP, then store a value at the location
pointed to by SP. The RET, RETI, POP, and POPI opera-
tions retrieve the value at SP and then decrement SP.
Figure 6. Memory Map When Program is Executing from Flash Memory
SYSTEM
REGISTERS
PERIPHERAL
REGISTERS
DP
16 x 16
STACK
M5
M4
M3
M2
M1
M0
5h
0Fh
00h
4h
3h
2h
1h
0h
FFFFh FFFFh FFFFh
8FFFh9FFFh8FFFh
7FFFh
0000h 0000h 0000h
4K x 16
UTILITY ROM
8K x 8
UTILITY ROM
4K x 16
UTILITY ROM
2K x 8
SRAM DATA
1K x 16
SRAM DATA
32K x 16
USER PROGRAM
MEMORY
8000h 8000h 8000h
07FFh 03FFh
DPC
SP
IP
PFX
A
AP
Fh
00h 0Fh
00h 1Fh
Eh
Dh
Ch
Bh
9h
8h
PROGRAM
MEMORY SPACE
DATA MEMORY
(BYTE MODE)
DATA MEMORY
(WORD MODE)
001Fh
0010h
PASSWORD
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Programming
The microcontroller’s flash memory can be programmed
by one of two methods: in-system programming or in
application programming. These provide great flexibility in
system design as well as reduce the life-cycle cost of the
embedded system. Programming can be password pro-
tected to prevent unauthorized access to code memory.
In-System Programming
An internal bootstrap loader allows the device to be pro-
grammed over the JTAG or I2C compatible interfaces.
As a result, system software can be upgraded in-system,
eliminating the need for a costly hardware retrofit when
software updates are required.
The programming source select (PSS) bits in the ICDF
register determine which interface is used for boot load-
ing operation. The device supports JTAG and I2C as an
interface corresponding to the 00 and 01 bits of PSS,
respectively. See Figure 7.
In-Application Programming
The in-application programming feature allows the micro-
controller to modify its own flash program memory. This
allows on-the-fly software updates in mission-critical
applications that cannot afford downtime. Alternatively, it
allows the application to develop custom loader software
that can operate under the control of the application soft-
ware. The utility ROM contains firmware-accessible flash
programming functions that erase and program flash
memory. These functions are described in detail in the
DS4830 User’s Guide.
Figure 7. In-System Programming
DS4830 RESET INITIATED BY
POR, I2C SELF-RESET, OR
RST PIN.
RESET DEVICE.
BEGIN BOOT ROM CODE
EXECUTION AT 8000h.
WAIT FOR 320 SYSTEM
CYCLES (32µs). RESET I2C.
SET PWL BIT.
SET ROD BIT.
BOOTLOADER
SET PSS[1:0] = 01
ROM CODE ENABLES
SLAVE I2C INTERFACE:
ADDRESS IS 36h.
IS JTAG_SPE BIT SET?
NO
YES
SET USING JTAG PROGRAMMER,
FOLLOWED BY RESET OF DEVICE.
WAITS FOR EXIT LOADER
COMMAND FROM HOST
SET BY WRITING F0h TO I2C SLAVE
34h.
JUMP TO USER CODE
(FLASH) AT 0000h.
IS I2C_SPE BIT SET?
NO
YES
DS4830 Optical Microcontroller
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Register Set
Sets of registers control most device functions. These
registers provide a working space for memory operations
as well as configuring and addressing peripheral registers
on the device. Registers are divided into two major types:
system registers (special-purpose registers, or SPRs) and
peripheral registers (special-function registers, or SFRs).
The common register set, also known as the system
registers, includes the ALU, accumulator registers, data
pointers, interrupt vectors and control, and stack pointer.
The peripheral registers define additional functionality,
and the functionality is broken up into discrete modules.
Both the system registers and the peripheral registers are
described in detail in the DS4830 User’s Guide.
System Timing
The device generates its 10MHz instruction clock (MOSC)
internally. On power-up, the oscillator’s output (which can-
not be accessed externally) is disabled until VDD rises
above VBO. Once this threshold is reached, the output
is enabled after approximately 1ms, clocking the device.
See Figure 8.
System Reset
The device features several sources that can be used to
reset the DS4830.
Power-On Reset
An internal power-on-reset (POR) circuit is used to
enhance system reliability. This circuit forces the device to
perform a POR whenever a rising voltage on VDD climbs
above VBO. When this happens the following events
occur:
●All registers and circuits enter their reset state.
●The POR flag (WDCN.7) is set to indicate the source
of the reset.
●Code execution begins at location 8000h when the
reset condition is released.
Brownout Detect/Reset
The device features a brownout detect/reset function.
Whenever the power monitor detects a brownout condi-
tion (when VDD < VBO), it immediately issues a reset and
stays in that state as long as VDD remains below VBO.
Once VDD voltage rises above VBO, the device waits
for tSU:MOSC before returning to normal operation, also
referred to as CPU state. If a brownout occurs during
tSU:MOSC, the device again goes back to the brownout
state. Otherwise, it enters into CPU state. In CPU state,
the brownout detector is also enabled.
On power-up, the device always enters brownout state
first and then follows the above sequence. The reset
issued by brownout is the same as POR. Any action
performed after POR also happens on brownout reset.
All the registers that are cleared on POR are also cleared
on brownout reset.
Figure 8. System Timing
tSU:MOSC = ~1ms
CORE
CLOCK
VDD
VBO
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Watchdog Timer Reset
The watchdog timer provides a mechanism to reset the
processor in the case of undesirable code execution. The
watchdog timer is a hardware timer designed to be peri-
odically reset by the application software. If the software
operates correctly, the timer is reset before it reaches its
maximum count. However, if undesirable code execution
prevents a reset of the watchdog timer, the timer reaches
its maximum count and resets the processor.
The watchdog timer is controlled through two bits in the
WDCN register (WDCN[5:4]: WD[1:0]). Its timeout period
can be set to one of the four programmable intervals
ranging from 212 to 221 system clock (MOSC) periods
(0.409ms to 0.210s). The watchdog interrupt occurs at the
end of this timeout period, which is 512 MOSC clock peri-
ods, or approximately 50µs, before the reset. The reset
generated by the watchdog timer lasts for four system
clock cycles, which is 0.4µs. Software can determine if a
reset is caused by a watchdog timeout by checking the
watchdog timer reset flag (WTRF) in the WDCN register.
Execution resumes at location 8000h following a watch-
dog timer reset.
External Reset
Asserting RST low causes the device to enter the reset
state. The external reset function is described in the
DS4830 User’s Guide. Execution resumes at location
8000h after RST is released. The DAC and PWM outputs
are unchanged during execution of external reset.
Internal System Reset
The host can issue an I2C command (BBh) to reset the
communicating device. This reset has the same effect as
the external reset as far as the reset values of all registers
are concerned. Also, an internal system reset can occur
when the in-system programming is done (ROD = 1). The
DAC and PWM outputs are unchanged during execution
of an internal reset.
Further details are available in the DS4830 User’s Guide.
Programmable Timer
The device features two general-purpose programmable
timers. Various timing loops can be implemented using the
timers. Each general-purpose timer uses three SFRs. GTCN
is the general control register, GTV is the timer value regis-
ter, and GTC is the timer compare register.The timer can
be used in two modes: free-running mode and compare
mode with interrupts. Both are described in detail in the
DS4830 User’s Guide.
The functionality of the timers can be accessed through
three SFRs for each of the general-purpose timers. The
timer SFRs are accessed in module 0 and module 3.
Detailed information regarding the timer block can be
found in the DS4830 User’s Guide.
Hardware Multiplier
The hardware multiplier (multiply-accumulate, or MAC
module) is a very powerful tool, especially for applica-
tions that require heavy calculations. This multiplier
can execute the multiply or multiply-negate, or multiply-
accumulate or multiply-subtract operation for signed or
unsigned operands. The MAC module uses eight SFRs,
mapped as register 0h–05h and 08h–09h in module M3.
System Interrupts
Multiple interrupt sources are available to respond to
internal and external events. The microcontroller archi-
tecture uses a single interrupt vector (IV) and single inter-
rupt-service routine (ISR) design. For maximum flexibility,
interrupts can be enabled globally, individually, or by mod-
ule. When an interrupt condition occurs, its individual flag
is set, even if the interrupt source is disabled at the local,
module, or global level. Interrupt flags must be cleared
within the firmware-interrupt routine to avoid repeated
interrupts from the same source. Application software
must ensure a delay between the write to the flag and the
RETI instruction to allow time for the interrupt hardware
to remove the internal interrupt condition. Asynchronous
interrupt flags require a one-instruction delay and syn-
chronous interrupt flags require a two-instruction delay.
When an enabled interrupt is detected, execution jumps
to a user-programmable interrupt vector location. The IV
register defaults to 0000h on reset or power-up, so if it is
not changed to a different address, application firmware
must determine whether a jump to 0000h came from a
RST or interrupt source.
Once control has been transferred to the ISR, the inter-
rupt identification register (IIR) can be used to determine
if a system register or peripheral register was the source
of the interrupt. In addition to IIR, MIIR registers are
implemented to indicate which particular function under
a peripheral module has caused the interrupt. The device
contains six peripheral modules, M0 to M5. An MIIR reg-
ister is implemented in modules M1 and M2. The MIIRs
are 16-bit read-only registers and all of them default to
all zeros on system reset. Once the module that causes
the interrupt is singled out, it can then be interrogated
for the specific interrupt source and software can take
DS4830 Optical Microcontroller
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22
appropriate action. Interrupts are evaluated by application
code allowing the definition of a unique interrupt priority
scheme for each application. Interrupt sources are availa-
ble from the watchdog timer, the ADC (including sample/
holds), fast comparators, the programmable timer, SVM,
the I2C-compatible master and slave interface, 3-wire,
master and slave SPI, and all GPIO pins.
I/O Port
The device allows for most inputs and outputs to func-
tion as general-purpose input and/or output pins. There
are four ports: P0, P1, P2, and P6. Note that there is no
port corresponding to P6.7. The 7th bit of port 6 is non-
functional in all SFRs. Each pin is multiplexed with at least
one special function, such as interrupts, I/O pins, or JTAG
pins, etc.
The GPIO pins have Schmitt trigger receivers and full
CMOS output drivers and can support alternate functions.
The ports can be accessed through SFRs (PO[0,1,2,6],
PI[0,1,2,6], PD[0,1,2,6], EIE[0,1,2,6], EIF[0,1,2,6], and
EIES[0,1,2,6]) in modules 0 and 1, and each pin can be
individually configured. The pin is either high impedance
or a weak pullup when defined as an input, dependent on
the state of the corresponding bit in the output register. In
addition, each pin can function as external interrupt with
individual enable, flag and active edge selection, when
programmed as input.
The I/O port SFRs are accessed in module 0 and 1.
Detailed information regarding the GPIO block can be
found in the DS4830 User’s Guide.
DAC Outputs
The device provides eight 12-bit DAC outputs with multi-
ple reference options. An internal 2.5V reference is pro-
vided. There are also two selectable external references.
REFINA can be selected as the full-scale reference for
DAC0 to DAC3. REFINB can be selected as the full-scale
reference for DAC4 to DAC7. The DAC outputs are volt-
age buffered. Each DAC can be individually disabled and
put into a low-power power-down mode using DACCFG.
An external reset does not affect the DAC outputs.
If a DAC output is used during the lifetime of the DS4830,
the DAC must always be enabled to guarantee meeting
the INL and offset specifications. If a pin is used for a
DAC, it should be used only for the DAC function. The
pin’s function should not be switched between DAC and
PWM or switched between DAC and GPIO.
The DAC SFRs are accessed in module 4. Detailed
information regarding the DAC block can be found in the
DS4830 User’s Guide.
PWM Outputs
The device provides 10 independently configurable PWM
outputs. The PWM outputs are configured using three
SFRs: PWMCN, PWMDATA, and PWNSYNC. Using
PWMCN and PWMDATA, individual PWM channels can
be programmed for unique duty cycles (DCYCn), config-
urations (PWMCFGn), and delays (PWMDLYn), where n
represents the PWM channel number.
The PWM clock can be obtained from the core clock,
peripheral clock, or an external clock, depending on
CLK_SEL bits programmed in individual PWMCFGn reg-
isters. The PWMCFGn register also enables/disables the
corresponding PWM output and selects the PWM polarity.
The user can set the duty cycle and the frequency of each
PWM output individually by configuring the corresponding
DCYCn register and the PWMCFGn register.
The device allows 4-slot or 32-slot pulse spreading
options for each PWM channel. The PWM outputs can be
configured to be output on an alternate location using the
configuration register. PWMDLY is a 12-bit register used
for providing starting delay on different PWM channels,
and can be used to create multiphase PWM operation.
Different channels can be synchronized using the
PWMSYNC register. Doing so effectively brings the chan-
nels in phase by restarting the channels that are to be
synchronized. An external reset does not affect the PWM
outputs.
The PWM SFRs are accessed in module 5. Detailed
information regarding the PWM block can be found in the
DS4830 User’s Guide.
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Analog-to-Digital Converter
and Sample/Hold
The analog-to-digital converter (ADC) controller is the
digital interface block between the CPU and the ADC. It
provides all the necessary controls to the ADC and the
CPU interface. The ADC uses a set of SFRs for configur-
ing the ADC in desired mode of operation.
The device contains a 13-bit ADC with an input mux
(Figure 9). The mux selects the ADC input from 16 sin-
gle-ended or eight differential inputs. Additionally, the
channels can be configured to convert internal and external
temperature, VDD, internal reference, or REFINA/B. Two
channels can be programmed to be sample/hold inputs.
The internal channel is used exclusively to measure the
die temperature. The SFR registers control the ADC.
ADC
When used in voltage input mode, the voltage applied on
the corresponding channel (differential or single-ended)
is converted to a digital readout. The ADC can be set
up to continuously poll selected input channels (continu-
ous-sequence mode) or run a short burst of conversions
and enter a shutdown mode to conserve power (single-
sequence mode).
In voltage mode there are four full-scale values that can
be programmed. These values can be trimmed by mod-
ifying the associated gain registers (ADCG1, ADCG2,
ADCG3, ADCG4). By default these are set to 1.2V, 0.6V,
2.4V, and 4.8V full scale.
The ADCCLK is derived from the system clock with divi-
sion ratio defined by the ADC control register. An A/D
conversion takes 15 ADCCLK cycles to complete with
additional four core clocks used for data processing.
Internally every channel is converted twice and the aver-
age of two conversions is written to the data buffer. This
gives each conversion result in (30 x ADC Clock Period
+ 800ns). ADC sampling rate is approximately 40ksps
for the fastest ADC clock (core clock/8). In applications
where extending the acquisition time is desired, the sam-
ple can be acquired over a prolonged period determined
by the ADC control register.
Each ADC channel can have its own configuration, such
as differential mode select, data alignment select, acqui-
sition extension enable, and ADC gain select, etc. The
ADC also has 24 (0 to 23) 16-bit data buffers for conver-
sion result storage. The ADC data available interrupt flag
(ADDAI) can be configured to trigger an interrupt following
a predetermined number of samples. Once set, ADDAI
can be cleared by software or at the start of a conversion
process.
Sample/Hold
Pin combinations GP2-GP3 and GP12-GP13 can be used
for sample/hold conversions if enabled in the SHCN regis-
ter. These two can be independently enabled or disabled
by writing a 1 or 0 to their corresponding bit locations in
SHCN register. A data buffer location is reserved for each
channel. When a particular channel is enabled, a sample
of the input voltage is taken when a signal is issued on
the SHEN pin, converted and stored in the corresponding
data buffer.
The two sample/hold channels can sample simultaneous-
ly on the same SHEN signal or different SHEN signals
depending on the SH_DUAL bit in the SHCN SFR.
The sample/hold data available interrupt flag (SHnDAI)
can be configured to trigger an interrupt following sam-
ple completion. Once set, SHnDAI can be cleared by
software.
Each sample/hold circuit consists of a sampling capaci-
tor, charge injection nulling switches, and a buffer. Also
included is a discharge circuit used to discharge parasitic
capacitance on the input node and the sample capacitor
before sampling begins. The negative input pins can be
used to reduce ground offsets and noise.
Figure 9. ADC Block Diagram
ADC-S[15:0]
ADC-D[7:0][P/N]
ADC-SHP[1:0]
ADC-SHN[1:0]
ADC-REFIN[A/B]
ADC-VDD
ADC-VREF_2.5V
ADC-TEXT_A(+/-)
ADC-TEXT_B(+/-)
ADC-TINT
MUX
ADCONV
(START CONVERSATION)
ADCCFG
PGA
ADGAIN
13-BIT ADC
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Temperature Measurement
The device provides an internal temperature sensor for
die temperature monitoring and two external remote
temperature-sensing channels. In external temperature
mode, current is forced into an external diode that is con-
nected between user-specified channel pins (GP8-GP9
or GP10-GP11). The diode temperature is obtained by
measuring the diode voltages at multiple bias currents.
These temperature channels can be enabled inde-
pendently by setting the appropriate bit locations in the
TEMPCN register. Whenever a temperature conversion
is complete, the corresponding flag (INTDAI for internal
conversion, EX0DAI and EX1DAI for external conversion)
is set. These can be configured to cause an interrupt, and
can be cleared by software. The temperature measure-
ment resolution is 0.0625°C.
The device can use all the three modes explained above
simultaneously by using a time-slicing mechanism per-
formed by the internal controller. The ADC-related SFRs
are accessed in module 1 and module 2. For details about
this and the three blocks, refer to the ADC section of the
DS4830 User’s Guide.
Fast Comparator/Quick Trips
The device supports 8-bit quick-trip comparison function-
ality. The quick trips are required to continuously monitor
user-defined channels in a round-robin sequence.
The quick- trip controller allows the user control of the list
of channels to monitor. Each mode has a corresponding
choice of list of channels for the round robin.
In any mode of quick-trip operation, the quick trip (analog)
performs two comparisons on any selected channel.
1) Comparison with a high-threshold value.
2) Comparison with a low-threshold value.
Any comparison above the high-threshold value or below
the low-threshold value causes a bit to set in the cor-
responding register. This bit can be used to trigger an
interrupt. The threshold values are stored in 32 inter-
nal register (16 for low-threshold settings and 16 for
high-threshold settings). The quick-trip controller provides
the appropriate sequence of clock and threshold values
for the quick trips. Because the quick trips and the ADC
use the same input pins, the controller ensures that no
collision takes place.
The quick-trip-related SFRs are accessed in module
5. Refer to the quick trip section of the DS4830 User’s
Guidefor more information.
I2C-Compatible Interface Modules
The device provides two independent I2C-compatible
interfaces: one is a master and the other is a slave.
I2C-Compatible Master Interface
The device features an internal I2C-compatible master
interface for communication with a wide variety of external
I2C devices. The I2C-compatible master bus is a bidirec-
tional bus using two bus lines: the serial-data line (MSDA)
and the serial-clock line (MSCL). For the I2C-compatible
master, the device has ownership of the I2C bus and
drives the clock and generates the START and STOP
signals. This allows the device to send data to a slave or
receive data from a slave.
When the I2C-compatible master interface is disabled,
MSDA and MSCL can be used as GPIO pins P1.0 and
P1.1, respectively, and accessed through PO1/PI1/PD1.
I2C-Compatible Slave Interface
The device also features an internal I2C-compatible slave
interface for communication with a host. Furthermore,
the device can be in-system programmed (bootloaded)
through the I2C-compatible slave interface. The two inter-
face signals used by the I2C slave interface are SCL and
SDA. For the I2C-compatible slave interface, the device
relies on an externally generated clock to drive SCL and
responds to data and commands only when requested by
the I2C master device. The I2C-compatible slave interface
is open drain and requires external pullup resistors.
SMBus Timeout
Both the I2C-compatible master and slave interfaces can
work in SMBus-compatible mode for communication with
other SMBus devices. To achieve this, a 30ms timer has
been implemented on the I2C-compatible slave interface
to make the interface SMBus compatible. The purpose of
this timer is to issue a timeout interrupt and thus the firm-
ware can reset the I2C-compatible slave interface when
the SCL is held low for longer than 30ms. The timer only
starts when none of the following conditions is true:
1) The I2C-compatible slave interface is in the idle state
and there is no communications on the bus.
2) The I2C-compatible slave interface is not working in
SMBus-compatible mode.
3) The SCL logic level is high.
4) The I2C-compatible slave interface is disabled.
When a timeout occurs, the timeout bit is set and an inter-
rupt is generated, if enabled.
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The I2C master-related SFRs are accessed in module 1.
The I2C slave-related SFRs are accessed in module 2.
Details can be found in the I2C section of the DS4830
User’s Guide.
Serial Peripheral Interface Module
The device supports master and slave SPI interfaces.
The SPI provides an independent serial communication
channel to communicate synchronously with peripheral
devices in a multiple master or multiple slave system. The
interface allows access to a four-wire, full-duplex serial
bus, and can be operated in either master mode or slave
mode. Collision detection is provided when two or more
masters attempt a data transfer at the same time. The
maximum data rate of the SPI is 1/4 the system reference
clock frequency for slave mode and 1/2 the system clock
frequency for master mode.
The four interface signals used by the SPI are as follows:
●Master In-Slave Out. This signal is an output from a
slave device, SSPIDO, and an input to the master
device, MSPIDI. It is used to serially transfer data
from the slave to the master. Data is transferred most
significant bit (MSB) first. The slave device places this
pin in an input state with a weak pullup when it is not
selected.
●Master Out-Slave In. This signal is an output from a
master device, MSPIDO, and an input to the slave
devices, SSPIDI. It is used to serially transfer data
from the master to the slave. Data is transferred MSB
first.
●SPI Clock. This serial clock is an output from the mas-
ter device, MSPICK, and an input to the slave devices,
SSPICK. It is used to synchronize the transfer of data
between the master and the slave on the data bus.
●Active-Low Slave Select. The slave-select signal is
an input to enable the SPI module in slave mode,
SSPICS, by a master device. The SPI module sup-
ports configuration of an active SSPICS state through
the slave-active select. Normally, this signal has no
function in master mode and its port pin can be used
as a general-purpose I/O. However, the SSEL can
optionally be used as a mode fault detection in master
mode.
SPI Master Interface
The master mode is used when the device’s SPI controls
the data transmission rates and data format. The SPI is
placed in master mode by setting the master mode bit
(MSTM). Only an SPI master device can initiate a data
transfer. Writing a data character to the SPI data buffer
(SPIB), when in master mode, starts a data transfer. The
SPI master immediately shifts out the data serially on
MSPIDO, MSB first, while providing the serial clock on the
MSPICK output. New data is simultaneously gated in on
MSPIDI into the least significant bit (LSB) of the shift reg-
ister. At the end of a transfer, the received data is loaded
into the data buffer for reading, and the SPI transfer com-
plete flag (SPIC) is set. If SPIC is set, an interrupt request
is generated to the interrupt handler, if enabled.
SPI Slave Interface
Slave mode is used when the SPI is controlled by another
peripheral device. The SPI is in slave mode when an
internal bit (MSTM) is cleared to logic 0. In slave mode the
SPI is dependent on the SSPICK sourced from the master
to control the data transfer. The SSPICK input frequency
should not be greater than the system clock frequency of
the slave device divided by 4. The SPI master transfers
data to a slave on SSPIDI, MSB first, and the selected
slave device simultaneously transfers the contents of
its shift register to the master on SSPIDO, also MSB
first. Data received from the master replaces data in the
slave’s shift register at the completion of a transfer. Just
like in the master mode, received data is loaded into the
read buffer, and the SPI transfer complete flag is set at the
end of the transfer. The setting of the transfer complete
flag can cause an interrupt if enabled.
The SPI master-related SFRs are accessed in module 5.
The SPI slave-related SFRs are accessed in module 1.
Details can be found in the SPI section of the DS4830
User’s Guide.
3-Wire Interface Module
The DS4830 controls devices like the MAX3798/MAX3799
over a proprietary 3-wire interface. The DS4830 acts as the
3-wire master, initiating communication with and generat-
ing the clock for the MAX3798/MAX3799. It is a 3-pin inter-
face consisting of MDIO (a bidirectional data line), an MCL
clock signal, and a MCS chip-select output (active high).
The 3-wire master-related SFRs are accessed in module
2. Detailed information regarding the 3-wire interface
block can be found in the DS4830 User’s Guide.
DS4830 Optical Microcontroller
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In-Circuit Debug
Embedded debugging capability is available through the
JTAG-compatible test access port (TAP). Embedded
debug hardware and embedded ROM firmware provide
in-circuit debugging capability to the user application,
eliminating the need for an expensive in-circuit emulator.
Figure 10 shows a block diagram of the in-circuit debug-
ger. The in-circuit debug features include the following:
●A hardware debug engine
●A set of registers able to set breakpoints on register,
code, or data accesses (ICDA, ICDB, ICDC, ICDD,
ICDF, ICDT0, and ICDT1)
●A set of debug service routines stored in the utility ROM
The embedded hardware debug engine is an independent
hardware block in the microcontroller. The debug engine
can monitor internal activities and interact with selected
internal registers while the CPU is executing user code.
Collectively, the hardware and software features allow two
basic modes of in-circuit debugging:
●Background mode allows the host to configure and set
up the in-circuit debugger while the CPU continues to
execute the application software at full speed. Debug
mode can be invoked from background mode.
●Debug mode allows the debug engine to take control
of the CPU, providing read/write access to internal
registers and memory, and single-step trace operation.
Applications Information
Power-Supply Decoupling
To achieve the best results when using the DS4830,
decouple the VDD power supply with a 0.1µF capacitor.
Use a high-quality, ceramic, surface-mount capacitor
if possible. Surface-mount components minimize lead
inductance, which improves performance, and ceram-
ic capacitors tend to have adequate high-frequency
response for decoupling applications. Decouple the
REG285 and REG18 pins using 1µF X5R and 10nF
capacitors (one each/per output). Note: Do not use
either of these pins for external circuitry.
Additional Documentation
Designers must have three documents to fully use all
the features of this device. This data sheet contains pin
descriptions, feature overviews, and electrical specifica-
tions. Errata sheets contain deviations from published
specifications. User guides offer detailed information
about device features and operation. The following docu-
ments can be downloaded from www.maximintegrated.
com/DS4830.
●This DS4830 data sheet, which contains electrical/timing
specifications, package information, and pin descriptions.
●The DS4830 revision-specific errata sheet, if applicable.
●The DS4830 User’s Guide, which contains detailed
information and programming guidelines for core features
and peripherals.
Development and Technical Support
Maxim and third-party suppliers provide a variety of high-
ly versatile, affordably priced development tools for this
microcontroller, including the following:
●Compilers (C and assembly)
●In-circuit debugger
●Integrated Development Environments (IDEs)
●Serial-to-JTAG converters for programming and debugging
●USB-to-JTAG converters for programming and debugging
A partial list of development tool vendors can be found at
www.maximintegrated.com/MAXQ_tools.
Email mixedsignal.apps@maximintegrated.com for
technical support.
Figure 10. In-Circuit Debugger
TAP
CONTROLLER
CPU
DEBUG
ENGINE
DEBUG
SERVICE
ROUTINES
(UTILITY ROM)
CONTROL
BREAKPOINT
ADDRESS
DATA
DS4830
TMS
TCK
TDI
TDO
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Typical Application Circuit
VCCT VSEL
R1
TOUTA
25Ω
25ΩTOUTC
VOUT
SDA
SCL
CSEL
SDA
SCL
CSEL
13-BIT ADC
SLAVE
I2C
BIAS
MONITOR
MD
DFB
MAX3948 DS4830 MODE_DEF1 (SCL)
MODE_DEF2 (SDA)
VCCT VSEL
R2
TOUTA
25Ω
25ΩTOUTC
VOUT
SDA
SCL
CSEL
MD
DFB
MAX3948
VCCT VSEL
R3
TOUTA
25Ω
25ΩTOUTC
VOUT
SDA
SCL
CSEL
MD
DFB
MAX3948
VCCT VSEL
TOUTA
25Ω
25ΩTOUTC
VOUT
SDA
SCL
CSEL
MD
DFB
MAX3948
VCC (+3.3V)
RSSI
MONITOR
DS4830 Optical Microcontroller
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+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*EP = Exposed pad.
Ordering Information
PART TEMP RANGE PIN-PACKAGE
DS4830T+T -40°C to +85°C 40 TQFN-EP*
DS4830 Optical Microcontroller
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Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 6/11 Initial release —
1 10/11
Corrected the lead temperature from +260°C to +300°C in the Absolute Maximum
Ratings section; added explanation to the DAC Outputs section about the DAC
operation to achieve desired INL levels
2, 22
2 6/13
Style edits, rephrasing, edits to all Electrical Characteristics tables, values updated,
Typical Operating Characteristics added, Block Diagram updated, and updated
Figures 6, 7, 8
1–8, 12, 13,
15–27
3 1/17 Updated Package Information table 2
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
DS4830 Optical Microcontroller
© 2017 Maxim Integrated Products, Inc.
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30
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.