TC6321
2017 Microchip Technology Inc. DS20005724A-page 1
Features
Integrated Gate-to-Source Resistor
Integrated Gate-to-Source Zener Diode
Low Threshold
Low On-Resistance
Low Input Capacitance
Fast Switching Speeds
Free from Secondary Breakdown
Low Input and Output Leakage
Independent, Electrically Isolated N- and
P-Channels
8-Lead Very Thin Plastic Dual Flat, No Lead,
6x5mmVDFN Package
Applications
High-Voltage Pulser
•Amplifiers
•Buffers
Piezoelectric Transducer Drivers
General-Purpose Line Drivers
Logic-Level Interfaces
Package Types
Description
The TC6321 consists of high-voltage, low-threshold
N-channel and P-channel MOSFETs in an 8-Lead
VDFN package. Both MOSFETs have integrated
gate-to-source resistors and gate-to-source
Zener diode clamps, which are desired for high-voltage
pulser applications.
The TC6321 is a complimentary, high-speed,
high-voltage, gate-clamped N- and P-channel
MOSFET pair, which utilizes an advanced vertical
DMOS structure and the well-proven silicon-gate
manufacturing process. This combination produces a
device with the power-handling capabilities of bipolar
transistors and with the high-input impedance and
positive temperature coefficient inherent in MOS
devices. Characteristic of all MOS structures, this
device is free from thermal runaway and thermally-
induced secondary breakdown.
Vertical DMOS FETs are ideally suited to a wide range
of switching and amplifying applications where very low
threshold voltage, high breakdown voltage, high input
impedance, low input capacitance and fast switching
speeds are desired.
TC6321
6x5 VDFN*
* Includes Dual Exposed Thermal Pads (EP);
see Table 3-1.
DN
DN
DP
DP
SN
GN
SP
GP 3
4
2
1
5
6
7
8
N- and P-Channel Enhancement-Mode MOSFET Pa ir
TC6321
DS20005724A-page 2 2017 Microchip Technology Inc.
Typical Application Circuit
Functional Block Diagram
+100V
TC6321
-100V
VDD VH
VSS VL
OE
INA
INB
10 nF
10 nF
MD12XX, MD17XX,
MD18XX
N-Channel
P-Channel
DN
DN
DP
DP
SN
GN
GP
SP
2017 Microchip Technology Inc. DS20005724A-page 3
TC6321
1.0 ELECTRICAL CHARAC TERISTICS
Absolute Maximum Ratings †
Drain-to-Source Voltage..........................................................................................................................................BVDSX
Drain-to-Gate Voltage ............................................................................................................................................ BVDGX
Operating and Storage Temperature.......................................................................................................-55°C to +175°C
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not intended. Exposure to maximum rating conditions for
extended periods may affect device reliability.
N-CHANNEL DC AND AC ELECTRICAL CHARACTE RISTICS
Unless otherwise noted, TA=T
J= +25°C.
Parameters Sym. Min. Typ. Max. Units Conditions
DC Parameters (Note 1)
Drain-to-Source Breakdown
Voltage BVDSS 200 V VGS = 0V, ID = 2.0 mA
Gate Threshold Voltage VGS(th) 1.0 2.0 V VGS =V
DS, ID = 1.0 mA
Change in VGS(th) with
Temperature VGS(th) –4.5 mV/ºC VGS =V
DS, ID = 1.0 mA
(Note 2)
Gate-to-Source Shunt Resistor RGS 10 50 kIGS = 100 μA
Gate-to-Source Zener Voltage VZGS 13.2 25 V IGS = 2 mA
Zero Gate Voltage Drain
Current IDSS
10.0 μAV
DS = 200V
VGS = 0V
——1.0mAV
DS = 200V, VGS = 0V
TJ = +125°C (Note 2)
On-State Drain Current ID(ON)
1.0 A VGS =4.5V, V
DS = 25V
2.0 VGS = 10V, VDS = 25V
Static Drain-to-Source On-State
Resistance RDS(ON)
——8.0 VGS = 4.5V, ID=150mA
——7.0 V
GS = 10V, ID= 1.0A
Change in RDS(ON) with
Temperature RDS(ON) ——1.0%/ºC
VGS = 4.5V, ID=150mA
(Note 2)
AC Parameters (Note 2)
Forward Transconductance GFS 400 mmho VGS = 25V, ID= 500 mA
Input Capacitance CISS ——110
pF
VGS = 0V
VDS = 25V
f = 1.0 MHz
Common Source Output
Capacitance COSS ——60
Reverse Transfer Capacitance CRSS ——23
Turn-On Delay Time td(ON) ——10
ns
VGS = 10V
VDS = 25V
ID = 1.0A
RGEN = 25
Rise Time tr——15
Turn-Off Delay Time td(OFF) ——20
Fall Time tf——15
Note 1: Unless otherwise stated, all DC parameters are 100% tested at +25°C. Pulse test: 300 µs pulse, 2% duty
cycle.
2: Specification is obtained by characterization and is not 100% tested.
TC6321
DS20005724A-page 4 2017 Microchip Technology Inc.
Diode Parameters
Diode Forward Voltage Drop VSD ——1.8 V
VGS= 0V, ISD= 500 mA
(Note 1)
Reverse Recovery Time trr —100— ns
VGS = 0V, ISD = 500 mA
diF/dt = 25 A/µ (Note 2)
P-CHANNEL DC AND AC ELECTRICAL CHARACTERISTICS
Unless otherwise noted, TA = TJ = +25°C.
Parameter Sym. Min. Typ. Max. Unit Condition
DC Parameters (Note 1)
Drain-to-Source Breakdown
Voltage BVDSS –200 V VGS= 0V, ID= –2.0 mA
Gate Threshold Voltage VGS(th) –1.0 –2.4 V VGS =V
DS, ID = –1.0 mA
Change in VGS(th) with
Temperature VGS(th) ——4.5mV/ºC
VGS =V
DS, ID = –1.0 mA
(Note 2)
Gate-to-Source Shunt Resistor RGS 10 50 kIGS = 100 μA
Gate-to-Source Zener Voltage VZGS 13.2 25 V IGS = –2 mA
Zero Gate Voltage Drain
Current IDSS
–10.0 μAV
DS = 200V, VGS = 0V
–1.0 mA VDS = 200V, VGS = 0V
TJ= +125°C, (Note 2)
On-State Drain Current ID(ON)
–1.0 AVGS = –4.5V, VDS = –25V
–2.0 VGS = –10V, VDS = –25V
Static Drain-to-Source On-State
Resistance RDS(ON)
——10 VGS = –4.5V, ID = –150 mA
——8.0 V
GS = –10V, ID = –1.0A
Change in RDS(ON) with
Temperature RDS(ON) ——1.0%/°C
VGS = –25V, ID = –200 mA
(Note 2)
AC Parameters (Note 2)
Forward Transconductance GFS 400 mmho VGS = –25V, ID = –500 mA
Input Capacitance CISS ——200
pF VGS = 0V
VDS = –25V
f = 1.0 MHz
Common Source Output
Capacitance COSS ——55
Reverse Transfer Capacitance CRSS ——30
Turn-On Delay Time td(ON) ——10
ns
VGS = –10V
VDS = –25V
ID = –1.0A
RGEN = 25
Rise Time tr——15
Turn-Off Delay Time td(OFF) ——20
Fall Time tf——15
Note 1: Unless otherwise stated, all DC parameters are 100% tested at +25°C. Pulse test: 300 µs pulse, 2% duty
cycle.
2: Specification is obtained by characterization and is not 100% tested.
N-CHANNEL DC AND AC ELECTRICAL CHARACTERISTICS (CONTINUED)
Unless otherwise noted, TA=T
J= +25°C.
Parameters Sym. Min. Typ. Max. Units Conditions
Note 1: Unless otherwise stated, all DC parameters are 100% tested at +25°C. Pulse test: 300 µs pulse, 2% duty
cycle.
2: Specification is obtained by characterization and is not 100% tested.
2017 Microchip Technology Inc. DS20005724A-page 5
TC6321
Diode Parameters
Diode Forward Voltage Drop VSD –1.8 V VGS= 0V, ISD= –500 mA
(Note 1)
Reverse Recovery Time trr —100— ns
VGS = 0V, ISD = –500 mA
diF/dt = -25 A/µs (Note 2)
TEMPERATURE SPECIFICATIONS
Parameters Sym. Min. Typ. Max. Units Conditions
Temperature Ranges
Operating Temperature TJ–40 +150 °C
Storage Temperature TA–55 +175 °C
Thermal Package Resistances
Thermal Resistance,
6x5 mm VDFN-8LD
JC 1.43 °C/W
JA —34.4— °C/W
P-CHANNEL DC AND AC ELECTRICAL CHARACTERISTICS (CONT INUED)
Unless otherwise noted, TA = TJ = +25°C.
Parameter Sym. Min. Typ. Max. Unit Condition
Note 1: Unless otherwise stated, all DC parameters are 100% tested at +25°C. Pulse test: 300 µs pulse, 2% duty
cycle.
2: Specification is obtained by characterization and is not 100% tested.
TC6321
DS20005724A-page 6 2017 Microchip Technology Inc.
NOTES:
2017 Microchip Technology Inc. DS20005724A-page 7
TC6321
2.0 TYPICAL PERFORMANCE CURV ES
Note: Unless otherwise indicated, TA = TJ = 25°C.
FIGURE 2-1: N-Channel ID vs. VDS
(Output Characteristics).
FIGURE 2-2: N-Channel On-Resistance
vs. Temperature.
FIGURE 2-3: N-Channel ID vs. VGS.
FIGURE 2-4: P-Ch ann el ID vs. VDS
(Output Characteristics).
FIGURE 2-5: P-Channel On-Re si s tance
vs. Temperature.
FIGURE 2-6: P-Chann el I D vs. VGS.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
0 50 100 150 200
ID(A)
VDS (V)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
-55 -25 0 25 50 75 100 125 150 175
RDS(ON) (normalized)
Temperature (°C)
VGS = 4.5V, ID= 150 mA
VGS = 10V, ID = 1A
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
012345678910
I
D
(A)
V
GS
(V)
Temp. = 25 C
VDS = +25V
-3.50
-3.00
-2.50
-2.00
-1.50
-1.00
-0.50
0.00
-200-150-100-500
I
D
(A)
V
DS
(V)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
-55 -25 0 25 50 75 100 125 150 175
R
DS(ON)
(normalized)
Temperature (°C)
VGS = -4.5V, ID = -150 mA
VGS = -10V, ID= -1A
-3.5
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
-10-9-8-7-6-5-4-3-2-10
ID(A)
VGS (V)
Temp. = 25&
VDS = -25V
TC6321
DS20005724A-page 8 2017 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = TJ = 25°C.
FIGURE 2-7: N-Channel On-Resistance
vs. Drain Current.
FIGURE 2-8: N-Channel Capacitance vs.
Drain-to-Source Voltage.
FIGURE 2-9: N-Channel VGS(th) vs.
Temperature.
FIGURE 2-10: P- Ch ann el On -Re si s tance
vs. Drain Current.
FIGURE 2-11: P-Chann el Capacitance vs.
Drain-to-Source Voltage.
FIGURE 2-12: P-Ch ann el VGS(th) vs.
Temperature.
0
2
4
6
8
10
12
14
16
18
20
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50
RDS(ON) ()
ID(A)
VGS = 4.5V
VGS = 10V
0
50
100
150
200
250
300
350
0 10203040
Capacitance (pF)
V
DS
(V)
CISS
COSS
CRSS
f= 1 MHz
0.60
0.70
0.80
0.90
1.00
1.10
1.20
-55-250 255075100125150175
V
GS(th)
(normalized)
Temperature (°C)
0
2
4
6
8
10
12
14
16
18
20
-3.50-3.25-3.00-2.75-2.50-2.25-2.00-1.75-1.50-1.25-1.00-0.75-0.50-0.250.00
R
DS(ON)
()
I
D
(A)
VGS = -4.5V
VGS = -10V
0
50
100
150
200
250
300
350
-40-30-20-100
Capacitance (pF)
V
DS
(V)
CISS
COSS
CRSS
f= 1MHz
0.60
0.70
0.80
0.90
1.00
1.10
1.20
-55-250 255075100125150175
V
GS(th)
(normalized)
Temperature (°C)
2017 Microchip Technology Inc. DS20005724A-page 9
TC6321
Note: Unless otherwise indicated, TA = TJ = 25°C.
FIGURE 2-13: N-Channel BVDSS vs.
Temperature. FIGURE 2-14: P-Chann el BV DSS vs.
Temperature.
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
-55-250 255075100125150175
BV
DSS
(normalized)
Temperature (°C)
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
-55-250 255075100125150175
BV
DSS
(normalized)
Temperature (°C)
TC6321
DS20005724A-page 10 2017 Microchip Technology Inc.
NOTES:
2017 Microchip Technology Inc. DS20005724A-page 11
TC6321
3.0 PIN DESCRIPTION
The descriptions of the pins are listed in Table 3- 1.
TABLE 3-1: PIN FUNCTION TABLE
TC6321
6x5 VDFN Name Description
1 SN Source N-Channel
2 GN Gate N-Channel
3 GP Gate P-Channel
4 SP Source P-Channel
5, 6 DP Drain P-Channel
7,8 DN Drain N-Channel
9 EP Dual Exposed Thermal Pads
TC6321
DS20005724A-page 12 2017 Microchip Technology Inc.
NOTES:
2017 Microchip Technology Inc. DS20005724A-page 13
TC6321
4.0 FUNCTIONAL DESCRIPTION
4.1 N-Channel Switching Waveforms
and Test Circuit
Figure 4-1 shows the N-channel switching waveforms
and test circuit.
FIGURE 4-1: N-Channel Switching Waveforms and Test Circuit.
4.2 P-Channel Switching Waveforms
and Test Circuit
Figure 4-2 shows the P-channel switching waveforms
and test circuit.
FIGURE 4-2: P-Channel Switching Waveforms and Test Circuit.
t(ON)
td(ON) tr
10%
90%
10%
90%
90%
10%
t(OFF)
tf
td(OFF)
0 V
10 V
Input
Output
VDD
0 V
VDD
Output
Input
RGEN
RL
VSOURCE TC6321
t
(ON)
t
d(ON)
t
r
10%
90%
10%
90%
90%
10%
t
(OFF)
t
f
t
d(OFF)
-10 V
0 V
Input
Output
0 V
V
SS
TC6321
DS20005724A-page 14 2017 Microchip Technology Inc.
NOTES:
2017 Microchip Technology Inc. DS20005724A-page 15
TC6321
5.0 APPLICATION INFORMATION
The TC6321 N- and P-MOSFET pair is designed for a
wide range of switching and amplifying applications
where high-voltage, high-current drive and fast
switching speeds are required, especially for medical
ultrasound applications.
A typical application pairs the TC6321 with any of
MD12xx, MD17xx, or MD18xx ultrasound family
MOSFET Drivers in order to form a high-speed and
high-voltage (+/–100V 2.5A) pulser circuit. Figure 5-1
illustrates the application circuit digram for a two level
pulser.
FIGURE 5-1: TC6321 - Application Circuit Diagram.
+100V
TC6321
-100V
VDD VH
VSS VL
OE
INA
INB
10 nF
10 nF
MD12XX, MD17XX,
MD18XX
TC6321
DS20005724A-page 16 2017 Microchip Technology Inc.
NOTES:
2017 Microchip Technology Inc. DS20005724A-page 17
TC6321
6.0 PACKAGING INFORMATION
6.1 Package Marking Information
8-Lead VDFN (6 x 5 mm) Example
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
TC6321
V/9U
1640
256
3
e
TC6321
DS20005724A-page 18 2017 Microchip Technology Inc.
B
A
0.10 C
0.10 C
(DATUM B)
(DATUM A)
C
SEATING
PLANE
NOTE 1
2X
TOP VIEW
SIDE VIEW
BOTTOM VIEW
NOTE 1
12
N
0.10 C A B
0.10 C A B
0.10 C
0.08 C
Microchip Technology Drawing C04-413A Sheet 1 of 2
2X
8X
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
8-Lead Very Thin Plastic Dual Flat, No Lead (9U) - 6x5 mm Body [VDFN]
With Dual Exposed Pads
D
E
A
A3
A1
2X D2
2X E2
4X (K1)
4X (K2)
2X
2X
8X b
0.10 C A B
0.05 C
8X L
e
2
12
N
e
(K3)
(K4)
D
4
E
4
2017 Microchip Technology Inc. DS20005724A-page 19
TC6321
Microchip Technology Drawing C04-413A Sheet 2 of 2
Number of Terminals
Overall Height
Terminal Width
Overall Width
Terminal Length
Exposed Pad Width (X2)
Terminal Thickness
Pitch
Standoff
Units
Dimension Limits
A1
A
b
E2
A3
e
L
E
N
1.27 BSC
0.20 REF
3.15
0.55
0.35
0.80
0.00
0.40
0.60
3.25
0.85
0.02
5.00 BSC
MILLIMETERS
MIN NOM
8
3.35
0.65
0.45
0.90
0.05
MAX
K4 0.60 REF
REF: Reference Dimension, usually without tolerance, for information purposes only.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
1.
2.
3.
Notes:
Pin 1 visual index feature may vary, but must be located within the hatched area.
Package is saw singulated
Dimensioning and tolerancing per ASME Y14.5M
Exposed Pad to Exposed Pad
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Overall Length
Exposed Pad Length (X2)
D
D2 2.25
6.00 BSC
2.35 2.45
8-Lead Very Thin Plastic Dual Flat, No Lead (9U) - 6x5 mm Body [VDFN]
With Dual Exposed Pads
Molded Package Edge to Exposed Pad K3 0.35 REF
Terminal to Exposed Pad (X4) K2 0.20 REF
Terminal to Exposed Pad (X4) K1 0.35 REF
TC6321
DS20005724A-page 20 2017 Microchip Technology Inc.
2017 Microchip Technology Inc. DS20005724A-page 21
TC6321
APPENDIX A: REVISION HISTORY
Revision A (March 2017)
Original Release of this Document.
TC6321
DS20005724A-page 22 2017 Microchip Technology Inc.
NOTES:
2017 Microchip Technology Inc. DS20005724A-page 23
TC6321
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X/
Temperature
XX
Package
Device: TC6321T: N- and P-Channel Enhancement-Mode
MOSFET Pair, Tape and Reel
Temperature: V = -55°C to +175°C (Various temperature levels) (1)
Package Type: 9U = Very Thin Plastic Dual Flat, No Lead, VDFN,
8-Lead, 6x5 mm Body, with Dual Exposed Pads
Examples:
a) TC6321T-E/MQ: Tape and Reel,
Various temperature levels,
8-LD VDFN package
Note 1: Shipment of these devices may require an
end-use/end-user certificate per SPI-43508.
TC6321
DS20005724A-page 24 2017 Microchip Technology Inc.
NOTES:
2017 Microchip Technology Inc. DS20005724A-page 25
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory,
CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ,
KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST
Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo,
CodeGuard, CryptoAuthentication, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
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ZENA are trademarks of Microchip Technology Incorporated in the
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SQTP is a service mark of Microchip Technology Incorporated in
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Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
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Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2017, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-1396-7
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
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Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPI C® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS20005724A-page 26 2017 Microchip Technology Inc.
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Worldwide Sales and Service
11/07/16