1. General description
The 74LVC373A consists of eight D-type transparent latches, featuring separate D-type
inputs fo r each latch and 3-st ate true output s for bus- oriented applica tions. A latch enable
input (pin LE) and an output enable input (pin OE) are common to all internal latches.
When pin LE is HIGH, data at the D-inputs (pins D0 to D7) enters the latches. In this
condition, the latches are transparent, that is, a latch output will change each time its
corresponding D-input changes. When pin LE is LOW, the latches store the information
that was present at the D-inputs one set-up time preceding the HIGH-to-LOW transition of
pin LE.
When pin OE is LOW , the co ntents of the eight latches are available at the Q-outpu ts (pins
Q0 to Q7). When pin OE is HIGH, the outputs go to the high-impedance OFF-state.
Operation of input pin OE does not affect the state of the latches.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices as translators in
mixed 3.3 V and 5 V applications.
The 74LVC373A is functionally identical to the 74LVC573A, but has a different pin
arrangement.
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
High-impedance outputs when VCC = 0 V
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B ex ce ed s 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from 40 C to +85 C and 40 C to +125 C
74LVC373A
Octal D-type transparent latch with 5 V tolerant
inputs/outputs; 3-state
Rev. 3 — 22 November 2012 Product data sheet
74LVC373A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 22 November 2012 2 of 19
NXP Semiconductors 74LVC373A
Octal D-type trans parent latch with 5 V tolerant inputs/outputs; 3-state
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Type number Package
Temperatu re range Name Description Version
74LVC373AD 40 Cto+125C SO20 plastic small outline package; 20 leads; body width 7.5
mm SOT163-1
74LVC373ADB 40 Cto+125C SSOP20 plastic shrink small outline package; 20 leads;
body width 5.3 mm SOT339-1
74LVC373APW 40 Cto+125C TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm SOT360-1
74LVC373ABQ 40 Cto+125C DHVQFN20 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 20 terminals; body
2.5 4.5 0.85 mm
SOT764-1
Fig 1. Logic symbol Fig 2. IEC logic symbol
mna881
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
LE
11 1
18
17
14
13
8
7
4
3
19
16
15
12
9
6
5
2
OE
mna880
19
16
15
12
9
6
5
1EN
11 C1
1D 2
18
17
14
13
8
7
4
3
74LVC373A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 22 November 2012 3 of 19
NXP Semiconductors 74LVC373A
Octal D-type trans parent latch with 5 V tolerant inputs/outputs; 3-state
Fig 3. Functional diagram Fig 4. Logic diagram for one latch
mna882
3-STATE
OUTPUTS
LATCH
1 to 8
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7 19
16
15
12
9
6
5
2
D0
D1
D2
D3
D4
D5
D6
D7
LE
OE
18
11
1
17
14
13
8
7
4
3
Q
LE
D
LE
LE
LE
mna189
Fig 5. Logic diagra m
mna883
Q4
D4
D
LE
Q
Q3
D3
D
LE
Q
Q2
D2
D
LE
Q
Q1
D1
D
LELELE
Q
Q0
D0
DQ
LE
OE
LE LE LE LE
Q5
D5
D
LE
Q
LE
Q6
D6
D
LE
Q
LE
Q7
D7
D
LE
Q
LE
74LVC373A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 22 November 2012 4 of 19
NXP Semiconductors 74LVC373A
Octal D-type trans parent latch with 5 V tolerant inputs/outputs; 3-state
5. Pinning information
5.1 Pinning
5.2 Pin description
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 6. Pin configuration for SO20 and (T)SSOP20 Fig 7. Pin configuration for DHVQFN20
373A
OE V
CC
Q0 Q7
D0 D7
D1 D6
Q1 Q6
Q2 Q5
D2 D5
D3 D4
Q3 Q4
GND LE
001aad090
1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19
001aad089
373A
Transparent top view
Q4
D3
Q3
D4
D2 D5
Q2 Q5
Q1 Q6
D1 D6
D0 D7
Q0 Q7
GND
LE
OE
VCC
912
8 13
7 14
6 15
GND(1)
5 16
4 17
3 18
2 19
10
11
1
20
terminal 1
index area
Table 2. Pin description
Symbol Pin Description
OE 1 output enable input (active LOW)
LE 11 latch enable input (active HIGH)
D[0:7] 3, 4, 7, 8, 13, 14, 17, 18 data input
Q[0:7] 2, 5, 6, 9, 12, 15, 16, 19 latch output
GND 10 ground (0 V)
VCC 20 supply voltage
74LVC373A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 22 November 2012 5 of 19
NXP Semiconductors 74LVC373A
Octal D-type trans parent latch with 5 V tolerant inputs/outputs; 3-state
6. Functional description
[1] H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition
Z = High-impedance OFF-state
7. Limiting values
[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.
[2] The output voltage ratings may be exceeded if the output current ratings are observed.
[3] For SO20 packages: above 70 C the value of Ptot derates linearly with 8 mW/K.
For (T)SSOP20 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60 C the value of Ptot derates linearly with 4.5 mW/K.
Table 3. Functional table[1]
Operating modes Input Internal latch Output
OE LE Dn Qn
Enable and read register
(transparent mode) LHLLL
LHHHH
Latch and read register L L l L L
LLhHH
Latch register and disable
outputs HLl LZ
HLhHZ
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +6.5 V
IIK input clampi n g cu rre nt VI < 0 50 - mA
VIinput voltage [1] 0.5 +6.5 V
IOK output clamping current VO > VCC or VO < 0 - 50 mA
VOoutput voltage HIGH or LOW-state [2] 0.5 VCC + 0.5 V
3-state [2] 0.5 +6.5 V
IOoutput current VO = 0 V to VCC -50 mA
ICC supply cur ren t - 100 m A
IGND ground current 100 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb = 40 C to +125 C[3] -500 mW
74LVC373A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 22 November 2012 6 of 19
NXP Semiconductors 74LVC373A
Octal D-type trans parent latch with 5 V tolerant inputs/outputs; 3-state
8. Recommended operating conditions
9. Static characteristics
Table 5. Recommended operating con ditions
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage 1.65 - 3.6 V
functional 1.2 - - V
VIinput voltage 0 - 5.5 V
VOoutput voltage HIGH or LOW-state 0 - VCC V
3-state 0 - 5.5 V
Tamb ambient temperature in free air 40 - +125 C
t/V input transition rise and fall rate VCC = 1.65 V to 2.7 V 0 - 20 ns/V
VCC = 2.7 V to 3.6 V 0 - 10 ns/V
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
VIH HIGH-level
input voltage VCC = 1.2 V 1.08 - - 1.08 - V
VCC = 1.65 V to 1.95 V 0.65 VCC - - 0.65 VCC -V
VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V
VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V
VIL LOW-level
input voltage VCC = 1.2 V - - 0.12 - 0.12 V
VCC = 1.65 V to 1.95 V - - 0.35 VCC -0.35 VCC V
VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V
VOH HIGH-level
output
voltage
VI=V
IH or VIL
IO=100 A;
VCC =1.65Vto3.6V VCC 0.2 - - VCC 0.3 - V
IO=4mA; V
CC = 1.65 V 1.2 - - 1.05 - V
IO=8mA; V
CC = 2.3 V 1.8 - - 1.65 - V
IO=12 mA; VCC = 2.7 V 2.2 - - 2.05 - V
IO=18 mA; VCC = 3.0 V 2.4 - - 2.25 - V
IO=24 mA; VCC = 3.0 V 2.2 - - 2.0 - V
VOL LOW-level
output
voltage
VI=V
IH or VIL
IO= 100 A;
VCC = 1.65 V to 3.6 V - - 0.2 - 0.3 V
IO=4mA; V
CC = 1.65 V - - 0.45 - 0.65 V
IO=8mA; V
CC = 2.3 V - - 0.6 - 0.8 V
IO=12mA; V
CC = 2.7 V - - 0.4 - 0.6 V
IO=24mA; V
CC = 3.0 V - - 0.55 - 0.8 V
IIinput leakage
current VCC = 3.6 V; VI=5.5VorGND - 0.1 5-20 A
74LVC373A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 22 November 2012 7 of 19
NXP Semiconductors 74LVC373A
Octal D-type trans parent latch with 5 V tolerant inputs/outputs; 3-state
[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb =25C.
10. Dynamic characteristics
IOZ OFF-state
output
current
VI=V
IH or VIL; VCC = 3.6 V;
VO=5.5VorGND; -0.1 5-20 A
IOFF power-off
leakage
supply
VCC = 0 V; VIor VO= 5.5 V - 0.1 10 - 20 A
ICC supply
current VCC = 3.6 V; VI=V
CC or GND;
IO=0A -0.110 - 40A
ICC additional
supply
current
per input pin; VCC = 2.7 V to 3.6
V; VI=V
CC 0.6 V; IO=0A - 5 500 - 5000 A
CIinput
capacitance VCC = 0 V to 3.6 V;
VI=GNDtoV
CC
-5.0- - -pF
Table 6. Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 12.
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
tpd propagation delay Dn to Qn; see Figure 8 [2]
VCC = 1.2 V - 14 - - - ns
VCC = 1.65 V to 1.95 V 1.5 6.5 15.8 1.5 18.2 ns
VCC = 2.3 V to 2.7 V 1.0 3.4 8.2 1.0 9.4 ns
VCC = 2.7 V 1.5 3.4 7.8 1.5 10.0 ns
VCC = 3.0 V to 3.6 V 1.5 2.9 6.8 1.5 8.5 ns
LE to Qn; see Figure 9 [2]
VCC = 1.2 V - 16 - - - ns
VCC = 1.65 V to 1.95 V 2.2 7.3 16.8 2.2 19.3 ns
VCC = 2.3 V to 2.7 V 1.5 3.9 8.6 1.5 10.0 ns
VCC = 2.7 V 1.5 3.5 8.2 1.5 10.5 ns
VCC = 3.0 V to 3.6 V 1.5 3.3 7.2 1.5 9.0 ns
ten enable time OE to Qn; see Figure 10 [2]
VCC = 1.2 V - 17 - - - ns
VCC = 1.65 V to 1.95 V 1.5 6.8 17.6 1.5 20.3 ns
VCC = 2.3 V to 2.7 V 1.5 3.8 9.7 1.5 11.2 ns
VCC = 2.7 V 1.5 3.8 8.7 1.5 11.0 ns
VCC = 3.0 V to 3.6 V 1.5 3.1 7.7 1.5 10.0 ns
74LVC373A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 22 November 2012 8 of 19
NXP Semiconductors 74LVC373A
Octal D-type trans parent latch with 5 V tolerant inputs/outputs; 3-state
[1] Typical values are measured at Tamb =25C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.
[2] tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
[4] CPD is used to determine the dynamic power dissipation (PDin W).
PD=C
PD VCC2fiN+(CLVCC2fo) where:
fi= input frequency in MHz; fo= output frequency in MHz
CL= output load capacitance in pF
VCC = supply voltage in Volts
N = number of inputs switching
(CLVCC2fo) = sum of the outputs
tdis disable time OE to Qn; see Figure 10 [2]
VCC = 1.2 V - 8.0 - - - ns
VCC = 1.65 V to 1.95 V 2.3 4.3 10.3 2.3 11.9 ns
VCC = 2.3 V to 2.7 V 1.0 2.4 5.8 1.0 6.8 ns
VCC = 2.7 V 1.5 3.2 7.1 1.5 9.0 ns
VCC = 3.0 V to 3.6 V 1.5 3.0 6.1 1.5 8.0 ns
tWpulse width LE HIGH; see Figure 9
VCC = 1.65 V to 1.95 V 5.0 - - 5.0 - ns
VCC = 2.3 V to 2.7 V 4.0 - - 4.0 - ns
VCC = 2.7 V 3.0 - - 3.0 - ns
VCC = 3.0 V to 3.6 V 3.0 1.5 - 3.0 - ns
tsu set-up time Dn to LE; see Figure 11
VCC = 1.65 V to 1.95 V 4.0 - - 4.0 - ns
VCC = 2.3 V to 2.7 V 3.0 - - 3.0 - ns
VCC = 2.7 V 2.0 - - 2.0 - ns
VCC = 3.0 V to 3.6 V 2.0 0.0 - 2.0 - ns
thhold time Dn to LE; see Figure 11
VCC = 1.65 V to 1.95 V 3.0 - - 3.0 - ns
VCC = 2.3 V to 2.7 V 2.0 - - 2.0 - ns
VCC = 2.7 V 1.5 - - 1.5 - ns
VCC = 3.0 V to 3.6 V 1.5 0.3 - 1.5 - ns
tsk(0) output skew time VCC = 3.0 V to 3.6 V [3] - - 1.0 - 1.5 ns
CPD power dissipation
capacitance per latch; VI = GND to VCC [4]
VCC = 1.65 V to 1.95 V - 16.6 - - pF
VCC = 2.3 V to 2.7 V - 19.2 - - pF
VCC = 3.0 V to 3.6 V - 21.6 - - pF
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 12.
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
74LVC373A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 22 November 2012 9 of 19
NXP Semiconductors 74LVC373A
Octal D-type trans parent latch with 5 V tolerant inputs/outputs; 3-state
11. AC waveforms
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8. Input (Dn) to output (Qn) propagation delays
mna884
Dn input
Qn output
t
PHL
t
PLH
GND
V
I
V
M
V
M
V
OH
V
OL
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 9. Latch Enable input (LE) pulse width, the latch enable inp ut to ou tput (Qn) propagation dela y s
74LVC373A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 22 November 2012 10 of 19
NXP Semiconductors 74LVC373A
Octal D-type trans parent latch with 5 V tolerant inputs/outputs; 3-state
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 10. 3-state enable and disable times
mna886
tPLZ
tPHZ
output
disabled output
enabled
VY
VX
output
enabled
Qn output
LOW-to-OFF
OFF-to-LOW
Qn output
HIGH-to-OFF
OFF-to-HIGH
OE input
VOL
VOH
VCC
VI
VM
GND
GND
tPZL
tPZH
VM
VM
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 11. Data set-up and hold times for the Dn input to the LE input
mna887
th
tsu
th
tsu
VM
VM
VI
GND
VI
GND
LE input
Dn input
Table 8. Measurement points
Supply voltage Input Output
VCC VIVMVMVXVY
1.2 V VCC 0.5 VCC 0.5 VCC VOL + 0.15 V VOH 0.15 V
1.65 V to 1.95 V VCC 0.5 VCC 0.5 VCC VOL + 0.15 V VOH 0.15 V
2.3 V to 2.7 V VCC 0.5 VCC 0.5 VCC VOL + 0.15 V VOH 0.15 V
2.7 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH 0.3 V
3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH 0.3 V
74LVC373A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 22 November 2012 11 of 19
NXP Semiconductors 74LVC373A
Octal D-type trans parent latch with 5 V tolerant inputs/outputs; 3-state
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 12. Test circuit for measuring switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aae331
V
EXT
V
CC
V
I
V
O
DUT
CL
RT
RL
RL
G
Table 9. Test data
Supply voltage Input Load VEXT
VItr, tfCLRLtPLH, tPHL tPLZ, tPZL tPHZ, tPZH
1.2 V VCC 2 ns 30 pF 1 kopen 2 VCC GND
1.65 V to 1.95 V VCC 2 ns 30 pF 1 kopen 2 VCC GND
2.3 V to 2.7 V VCC 2 ns 30 pF 500 open 2 VCC GND
2.7V 2.7V 2.5 ns 50 pF 500 open 2 VCC GND
3.0Vto3.6V 2.7V 2.5 ns 50 pF 500 open 2 VCC GND
74LVC373A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 22 November 2012 12 of 19
NXP Semiconductors 74LVC373A
Octal D-type trans parent latch with 5 V tolerant inputs/outputs; 3-state
12. Package outline
Fig 13. Package outline SOT163-1 (SO20)
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZ
ywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
2.65 0.3
0.1 2.45
2.25 0.49
0.36 0.32
0.23 13.0
12.6 7.6
7.4 1.27 10.65
10.00 1.1
1.0 0.9
0.4 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.1
0.4
SOT163-1
10
20
wM
bp
detail X
Z
e
11
1
D
y
0.25
075E04 MS-013
pin 1 index
0.1 0.012
0.004 0.096
0.089 0.019
0.014 0.013
0.009 0.51
0.49 0.30
0.29 0.05
1.4
0.055
0.419
0.394 0.043
0.039 0.035
0.016
0.01
0.25
0.01 0.004
0.043
0.016
0.01
0 5 10 mm
scale
X
θ
A
A1
A2
HE
Lp
Q
E
c
L
vMA
(A )
3
A
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
99-12-27
03-02-19
74LVC373A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 22 November 2012 13 of 19
NXP Semiconductors 74LVC373A
Octal D-type trans parent latch with 5 V tolerant inputs/outputs; 3-state
Fig 14. Package outline SOT339-1 (SSOP20)
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQ(1)
Zywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.38
0.25 0.20
0.09 7.4
7.0 5.4
5.2 0.65 7.9
7.6 0.9
0.7 0.9
0.5 8
0
o
o
0.131.25 0.2 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
1.03
0.63
SOT339-1 MO-150 99-12-27
03-02-19
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
110
20 11
y
0.25
pin 1 index
0 2.5 5 mm
scale
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1
A
max.
2
74LVC373A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 22 November 2012 14 of 19
NXP Semiconductors 74LVC373A
Octal D-type trans parent latch with 5 V tolerant inputs/outputs; 3-state
Fig 15. Package outline SOT360-1 (TSSOP20)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 6.6
6.4 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.5
0.2 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT360-1 MO-153 99-12-27
03-02-19
wM
bp
D
Z
e
0.25
110
20 11
pin 1 index
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
A
max.
1.1
74LVC373A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 22 November 2012 15 of 19
NXP Semiconductors 74LVC373A
Octal D-type trans parent latch with 5 V tolerant inputs/outputs; 3-state
Fig 16. Package outline SOT764-1 (DHVQFN20)
terminal 1
index area
0.51
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 4.6
4.4
Dh
3.15
2.85
y1
2.6
2.4 1.15
0.85
e1
3.5
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT764-1 MO-241 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT764-1
DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
20 terminals; body 2.5 x 4.5 x 0.85 mm
A(1)
max.
AA1c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
29
19 12
11
10
1
20
X
D
E
C
BA
terminal 1
index area
AC
CB
vM
wM
E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)
02-10-17
03-01-27
74LVC373A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 22 November 2012 16 of 19
NXP Semiconductors 74LVC373A
Octal D-type trans parent latch with 5 V tolerant inputs/outputs; 3-state
13. Abbreviations
14. Revision history
Table 10. Abbreviations
Acronym Description
CDM Charged Device Model
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74LVC373A v.3 20121122 Product data sheet - 74LVC373A v.2
Modifications: •The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
•Legal texts have been adapted to the new company name where appropriate.
•Table 4, Table 5, Table 6, Table 7, Table 8 and Table 9: values added for lower voltage ranges.
74LVC373A v.2 20030519 Product specification - 74LVC373A v.1
74LVC373A v.1 19980729 Product specification - -
74LVC373A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 22 November 2012 17 of 19
NXP Semiconductors 74LVC373A
Octal D-type trans parent latch with 5 V tolerant inputs/outputs; 3-state
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device (s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond tho se described in the
Product data sheet.
15.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconduct ors’ aggregate and cumulati ve liability toward s
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, lif e-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by cust omer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product develop ment.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
74LVC373A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 22 November 2012 18 of 19
NXP Semiconductors 74LVC373A
Octal D-type trans parent latch with 5 V tolerant inputs/outputs; 3-state
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for aut omo tive use. It is neither qua lif ied nor test ed
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in au tomotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from custome r design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a docume nt is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74LVC373A
Octal D-type trans parent latch with 5 V tolerant inputs/outputs; 3-state
© NXP B.V. 2012. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of rele ase: 22 November 2012
Document identifier : 7 4LV C3 73 A
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Functional description . . . . . . . . . . . . . . . . . . . 5
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 Recommended operating conditions. . . . . . . . 6
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
11 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 9
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
16 Contact information. . . . . . . . . . . . . . . . . . . . . 18
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19