ZL50235/GDC - Zarlink Semiconductor, Inc.

Features

• In dep endent m ult ipl e c hannel s of echo

c anc ell ati o n; from 16 channels o f 64ms t o 8

channe ls of 128ms with th e ability to mix

c han ne ls at 128ms o r 64 ms i n an y co m bi na ti on

• Independent Power Down mode for each group of

2 chann els f o r power manag em en t

• Ful ly com pli an t to ITU -T G.1 65, G.1 68 (200 0) and

(2 00 2) specifi ca ti ons

• Pas sed AT&T voic e q uali ty testing for ca rri er

gr ad e echo c an cel lers.

• Compatible to ST-BUS and G CI interfa ces with

2Mb/s serial PCM data

• PCM c oding, µ/A-Law I TU -T G.711 or si g n

magnitude

• Per c hannel F ax / Mo de m G.164 2 100 Hz or G.165

2100Hz phase reversal Tone Disable

• Per c han nel ech o ca nceller para me t ers control

• Tra nsparen t dat a transfe r an d m ut e

• Fast re conve rge nce on ec h o path changes

• Ful ly progra m ma bl e converg en ce spee ds

• Pat e nt ed Ad vance d N on-Line ar Proce sso r wit h

high quality subjective performance

• Protection against narrow band signal divergence

and instability in high echo environments

• 0 dB to -12 dB l eve l adju s ters (3 dB steps) at a ll

signal ports

• Offset nulling of all PCM chan nels

• 10 MH z o r 20 M H z m aster clo ck o peration

• 3.3 V IO pads and 1. 8 V L ogi c cor e operation wi th

5-Volt tole rant inputs

• IEEE-114 9.1 (JTAG) Test Access P ort

• ZL50232 , ZL5 0233, Z L5 0234 and ZL5 02 35 h ave

same pi no ut s in b ot h L QF P a nd LBGA packages

Applications

• Vo ice over IP ne twork ga teway s

• Voice o ver ATM, Frame Rela y

• T1/ E1 / J1 m ult ichannel e cho ca nce l lati on

• Wir eless base stations

• Echo Canceller po ol s

• DCME, satellite and multiplexer system

Ma r ch 2003

Ordering Information

ZL50235/QCC 100-Pin LQFP

ZL50235/GDC 208-Ball LBGA

-40°C to +85°C

ZL50235

16 Channel Voice Echo Canceller

Data Sheet

Figure 1 - ZL50235 Device O verview

RESET

Rout

Sout

DS CS R/W A10-A0 DTA D7-D0

DD1 (3.3V)

TDI TDO TCK TRSTTMS

Rin

IRQ

C4i

F0i

MCLK

ODE

Sin

Fsel

Test PortMicroprocessor Interface

Timing

Unit

Serial

Parallel

Serial

PLL Note:

R e fe r to Fi gure 4

for Echo Canceller

block diagram

DD2 (1.8V)

Echo Canceller Pool

Group 0

ECA/ECB

Group 4

ECA/ECB

Group 1

ECA/ECB

Group 5

ECA/ECB

Group 2

ECA/ECB

Group 6

ECA/ECB

Group 3

ECA/ECB

Group 7

ECA/ECB

ZL50235 Data Sheet

2Zarlink Semiconductor Inc.

Description

The ZL50235 Voice Echo Cancel ler implement s a cost eff ectiv e s oluti on for telephon y voic e-band echo canc ellat ion

conforming to ITU-T G.168 requirements. The Z L50235 arc hit ecture cont ains 8 g roups o f two echo cancel lers (ECA

and ECB) which can be configured to provide two channels of 64 milliseconds or one channel of 128 milliseconds

echo cancellation. This provides 16 channels of 64 milliseconds to 8 channels of 128 milliseconds echo

cancellation or any combination of the two configurations. The ZL50235 supports ITU-T G.165 and G.164 tone

disable requi rem ents.

Figure 2 - 100 Pin LQFP

1711972523211935 13151

VSS

R/W

DTA

2 4 6 8 10 12 14 16 18 20 22 24

51525354555657585960616263646566676869707172737475

100

VDD1

VDD2

VSS

A10

VSS

VDD2

VDD1

VSS

PLLVSS2

ODE

Sout

Rout

Sin

VSS

C4ib

Foib

Rin

VDD2

Mclk

fsel

PLLVSS1

PLLVDD

VDD1

TMS

TDI

TDO

TCK

VSS

TRSTB

RESETB

IRQB

ZL50235QC

(100 pin LQFP)

VDD1 = 3.3V VDD2 = 1.8V

VDD1

VSS

IC0

Data Sheet ZL50235

3Zarlink Semiconductor Inc.

Figure 3 - 208 B all LBG A

12345678910111213

- A1 cor ner is identified by meta llized mark ings.

14 15 16

VDD2

c4i

F0i Rin SinRout ODE

Sout

MCLK

Fsel

TMSTDI

TCK

RESET IRQ DS CSR/W DTA

D0 D1 D2 D4 D5 D6 D7

A10

ZL50235GD

VDD1

IC0

PLLVSS PLLVDD

IC0 IC0 IC0

IC0 IC0

IC0

IC0 IC0

IC0

IC0 VDD1

VSS

TDO TRST

NC NC

NC NC NC

VSS

VSS VSS

VSS

VSS VSS

VSS VSS VSS VSS

VSS

VSS VSS VSS VSS

VSS

VSS VSS

VSS

VSS VSS VSS VSS

VSS

VSS VSS VSS VSS

VSS

VSS VSS

VSS

VSS VSS VSS

VSS

VDD1

VDD1 VDD1

VDD1

VDD1 VDD1

VDD1

VDD1 VDD1

VDD1

VDD1 VDD1

VDD1

VDD1 VDD1

VDD1

VDD2

VDD2 VDD2

VDD2

VDD2 VDD2

VSS

VSS VSS VSS VSS

VDD1

ZL50235 Data Sheet

4Zarlink Semiconductor Inc.

Pin Description

Name

PIN #

Description

208-Ball LBGA 100 PIN

LQFP

VSS A1, A3,A7,A11, A13,

A15, A16, B2, B6, B8,

B12, B14, B15, B16, C3,

C5, C7, C9, C11, C12,

C13, C14, C16, D4, D8,

D10, D12, D13, E3, E4,

E1 4 , F13 , G 3 , G 4 , G 7 ,

G8, G9, G10, H7, H8,

H9, H10, H13, H14, J7,

J 8 , J9, J10, K7 , K8 , K 9 ,

K10, K13, K14, L3, L4,

M13, M14, M15, N3, N4,

N5, N7, N9, N11, N13,

P2, P3, P5, P7, P9, P11,

P13, P14, R2, R14,

R15, R16, T1, T3, T7,

T10, T14, T16

5, 18, 32,

42, 56, 69 ,

81, 98

Ground.

VDD1 A5, A9, B10, C4, C8,

B4, C10, D3, D5, D7,

D9, D11, D14, E13, F3,

F4, F14, H3, H4, J13,

J14, L13, L14, M3, M4,

N6, N8, N10, N14, N15,

P4, P6, P8, P10, P15,

R4, R6, R8, R10, R12,

T5, T12

27, 48, 77 ,

100 Positi ve Power Suppl y VDD1. Nominally 3.3 Volt .

VDD2 C6, D6, J3, J4, N12,

P12, G13, G14 14, 37, 64 ,

91 Positive Power Supply VDD2. Nomin ally 1.8 Vo lts

IC0 E15, F15, A1 2, A10, A6,

A2, B1, B3, C1, C2, D2,

E2, J2, K2, R1

7, 41, 43,

65, 66, 67 ,

68, 70, 71 ,

72, 86, 87 ,

88, 93, 94

Internal Connection. These pins must be connected to VSS for

normal operation.

NC A14, C15, D1, D15, E1,

F1, G1, G15, H1, H15,

J1 , J 15 , K1 ,

K15,L1,L15,F2,L2

24, 25, 26 ,

44, 45, 46 ,

47, 49, 51 ,

52, 53, 54 ,

55, 73, 74 ,

75, 76, 78 ,

79, 80, 82 ,

83, 84, 85 ,

89, 99, 50

No connection. These pins must be lef t open for normal

operation.

IRQ R9 9 Inter rupt Re quest (Open Drain Output). This output goes low

when an interrupt occ urs in any channel. IRQ returns high when

all the int errupts have been read fr om the Int errupt FIFO

Data Sheet ZL50235

5Zarlink Semiconductor Inc.

DS R11 10 Data S trobe (Input). This active low i nput works in conj unction

with CS to enable the re ad and wri te operatio ns.

CS R13 11 Chip Select (Input). This active low input is used by a

microprocessor to activat e the microprocessor port.

R/W R5 12 Read/Write (Input). This input cont rols the direction of th e data

bus lines (D7-D0) during a mic roprocessor access.

DTA R7 13 Data Transfer Acknowl edgment (Open Drain Output). T h is

activ e low output indicates that a data bus transfer is completed.

A pull-up resistor (1K typical) is required at this output.

D0..D7 T2,T4,T6,T8,T9,T11,

T13,T15 15, 16, 17,

19, 20, 21,

22, 23

Data Bus D0 - D7 (Bidire cti onal). These pins form the 8-bit

bidirectional data bus of the microprocessor port.

A0..A10 P16,N16,M16,L16,K16,

J16,H16,G16,F16,E16,

D16

28, 29, 30,

31, 33, 34,

35, 36, 38,

39, 40

Address A0 to A10 (Input). These inputs provide the A10 - A0

address lines to the internal re gisters.

ODE B13 57 O utput Drive Enable (Input). This input pin is logically AND’d

with the O DE bit-6 of the Main Control Reg ist er. Whe n both ODE

bit and ODE input pin ar e high, the Rout and Sout ST- BUS

outputs are enabled.

When the ODE bit is low or the ODE input pin i s low, the Rout

and Sout ST-B US outputs are hi gh impedance.

Sout A8 58 Send PCM Signal Outp ut (Output). Port 1 TDM data output

streams. Sout pi n output s se rial TDM data st rea ms at 2.048 Mb/s

with 16 channe ls per str eam .

Rout B9 59 Receive PCM Signal Output (Output). Port 2 TDM data output

streams. Rout pi n ou tput s seri al TDM d ata st ream s at 2. 048 Mb/s

with 16 channe ls per str eam .

Sin B11 60 Send PCM Signal Input (Inpu t) . Por t 2 TDM data input streams.

Sin pin receives serial TDM data streams at 2. 048 Mb /s wi th 16

channels per stream.

Rin B7 61 Recei ve PCM Signal I nput (I nput). Port 1 TD M da t a i n pu t

streams. Rin pin rece ives ser ial TDM dat a streams at 2. 048 Mb/s

with 16 channe ls per str eam .

F0i B5 62 Frame Pulse (Input). This input accepts and automatically

identifies fram e synchronization signals formatted according to

ST-BUS or GCI inte rf ace specification s.

C4i A4 63 Serial Clock (Input). 4.096 MHz serial clock for shifting dat a

in/out on the serial streams (Rin, Sin , Rout, Sout).

MCLK G2 90 Master Clock (Input). Nominal 10M Hz or 20MHz Master Clock

input. May be connected to an asynchronous (re lative to frame

signal) clock source.

Pin Description (continued)

Name

PIN #

Description

208-Ball LBGA 100 PIN

LQFP

ZL50235 Data Sheet

6Zarlink Semiconductor Inc.

1. 0 Devi ce Overvie w

The ZL50235 architecture contains 16 echo cancellers divided into 8 groups. Each group has two echo cancellers,

Echo Canceller A and Echo Canceller B. Each group can be configured in Normal, Extended Delay or Back-to-

Back configurations. In Normal configuration, a group of echo cancellers provides two channels of 64ms echo

cancellation, which run independently on different channels. In Extended Delay configuration, a group of echo

cancellers achieves 128ms of echo cancellation by cascading the two echo cancellers (A & B). In Back-to-Back

configuration, the two echo cancellers from the same group are positioned to cancel echo coming from both

directions in a single channel, providing full-duplex 64ms echo cancellation.

Fsel H2 92 Frequency select (Input). This input selects the Master Clock

frequency ope rat ion. When Fsel pin i s low, nomina l 20 MHz

Master Clock input must be applied. When Fsel pin i s high,

nominal 10 MHz Master Clock input must be applied.

PLLVss1

PLLVss2 K3 97, 95 PLL Ground. Must be connected to VSS

PLLVDD K4 96 PLL Power Supply. Must be connected to VDD2 = 1.8V

TMS M2 1 Test Mode Select (3.3V Input). JTAG signal that control s the

state transitions of the TAP controller. This pi n is pul led high by

an internal pull- up when not driven.

TDI M1 2 Test Serial Data In (3.3V Input). JTAG serial test instructions

and data are shifted in on this pi n. This pin is pull ed high by an

internal pull- up when not driven.

TDO N1 3 Test Serial Data Out (Outpu t). JTAG seria l dat a is outpu t on thi s

pin on the fall ing edge of TCK. This pin is held i n high impedan ce

state when JTAG scan is not enab led.

TCK P1 4 Test Clock (3.3V In put) . Pr ovid e s th e clo ck t o the J TAG t e st

logic.

TRST N2 6 Test Reset (3.3V Inpu t). Asynchronously init ializes the JTAG

TAP contr oller by p utt ing it in the Test-Logic-Reset state. This pi n

should be pulsed low on power-up or held low, to ensure that the

ZL50235 is in the normal functional mode. This pin is pulled by

an inte rnal pull-down when not driven.

RESET R3 8 Devi ce Reset (Schmitt Trigger Input). An active low resets the

device and puts the ZL50235 into a low-power st and-by mode.

When the RESET pin is r e t urn ed to log ic high an d a c l ock is

applied to the MCLK p in, the device will automatica lly execute

initialization routines, which preset all the Control and Sta tus

Regi s t ers to their d efault power -up value s.

Pin Description (continued)

Name

PIN #

Description

208-Ball LBGA 100 PIN

LQFP

Data Sheet ZL50235

7Zarlink Semiconductor Inc.

Each echo canceller contains the following main elements (see Figure 4).

• Adaptive Fi lt er f o r est im at ing the ec ho chan ne l

• Subtracto r for ca nc el li ng the echo

• Double-Tal k d etector for disa bl ing the fil ter ada ptat ion durin g period s of d ou bl e-tal k

• Pat h Ch ange d etector fo r fast re converg en ce on maj o r ech o path changes

• Instability Detector to combat instability in very low ERL env ironments

• Patented Advanced Non-Linear Processor for suppression of residual echo, with comfort noise injection

• Di sab l e Tone Detecto rs f or det e cti ng val id disab le t o nes at se nd and r ece i ve pa th i np uts

• Nar ro w- B an d D et e ct or for pre venting A daptive Fi lt er d i vergence f ro m n ar row-band sig nal s

• Offset Null filte rs for remov ing the D C compo nent in PCM ch annels

• 0 to -12dB level adju sters at all signal ports

• Parallel controller interfa ce compatible with Motorola mic rocontro llers

• PCM enco de r/ dec oder co mpa ti ble w i th µ/A-Law ITU-T G.711 or Sign-Magnitude coding

Each echo canceller in the ZL50235 has four functional states: Mute, Bypass, Disable Adaptation and Enable

Adaptation. These are explained in the section entitl ed Echo Canceller Functional States.

Figure 4 - Functional Block Diagram

1. 1 Adap tive Fi l ter

The adaptive filt er adapts t o the e cho path and generates an estimate of the echo signal. This echo e sti m ate is then

subtracted from Sin. For each group of echo cancellers, the adaptive filter is a 1024 tap FIR adaptive filter which is

divided into two sections. Each section contains 512 taps providing 64ms of echo estimation. In Normal

configuration, the fir st section i s dedicated to channel A and the second sect ion to channel B. In Exten ded Delay

configuration, both sections are cascaded to provide 128ms of echo estimation in channel A. In Back-to Back

configuration, the first section is used in the receive direction and the second section is used in the transmit

direction for the same channel.

Non-Linear

Processor

Offset

Null Linear/

/A-Law

Microprocessor

Interface

Double - Talk

Detector

Control

Narrow-Band

Detector

/A-Law/

Linear

Offset

Null

Echo Canc el ler (N), wh ere 0 < N < 15

Sout

Rin

Sin

Rout

Programmable Bypass

(channel N)

MuteR

MuteS

0 to -12dB

Level Adjust

Linear/

/A-Law 0 to -12dB

Lev el Adjust

0 to -12dB

Level Adjust

/A-Law/

Linear 0 to -12dB

L evel Adjust

Adaptive

Filter

Disable Tone

Detector

Disable Tone

Detector

Path Change

Instability

Detector

ZL50235 Data Sheet

8Zarlink Semiconductor Inc.

1.2 D ouble -Talk Detect or

Double-Talk is defined as those periods of time when signal energy is present in both directions simultaneously.

When this happens, it is necessary to disable the filter adaptation to prevent divergence of the Adaptive Filter

coefficients. Note that when double-talk is detected, the adaptation process is halted but the echo canceller

continues to cancel echo using the previous converged echo profile. A double-talk condition exists whenever the

relative signal level s of Rin (Lrin) and Sin (Lsin) meet the following condit ion:

Lsin > Lrin + 20log10(DTDT)

where DTDT is th e Double-Talk Detect ion Threshold. Lsin and Lrin are signal levels expressed in dBm0.

A different method is used when it is uncertain whether Sin consists of a low level double-talk signal or an echo

return. During these periods, the adaptation process is slowed down but it is not halted. The slow convergence

speed is set using the Slow sub-register in Control Register 4. During slow convergence, the adaptation speed is

reduced by a factor of 2Slow relative to normal convergence for non-zero values of Slow. If Slow equals zero,

adaptation is halted completely.

In the G.168 standard, the echo return loss is expected to be at least 6 dB. This implies that the Double-Talk

Detector Threshold (DTDT) should be set to 0.5 (-6 dB). However, in order to achieve additional guardband, the

DTDT is set inter nally to 0.5625 (- 5 dB).

In some applications the return loss can be higher or lower than 6 dB. The ZL50235 allows the user to change the

detection thr eshold to suit each application’ s need. This threshold can be set by writing the desired threshold value

into the DTDT register.

The DTDT regis ter is 16 bits wide. The regi ster value i n hexadecimal can be calculat ed wit h the follo wing equation:

DTDT(hex) = hex(DTDT(dec) * 32768)

where 0 < DTDT(dec) < 1

Examp le: For DTDT = 0.5625 (-5 dB), the

hexadecimal value becomes

hex(0.5625 * 32768) = 4800hex

1.3 Pa th Ch a nge De tect or

Integrated into the ZL50235 is a Path Change Detector. This permits fast reconvergence when a major change

occurs in the echo channel. Subtle changes in the echo channel are also tracked automatically once convergence

is achi eved, but at a much slower speed.

The Path Change Detector is activated by setting the PathDet bit in Control Register 3 to “1”. An optional path

clearing feature can be enabled by setting the PathClr bit in Control Register 3 to “1”. With path clearing turned on,

the existing echo channel estimate will also be cleared (i.e. the adaptive filter will be filled with zeroes) upon

detection of a major path chang e.

Data Sheet ZL50235

9Zarlink Semiconductor Inc.

1.4 Non-Linear Processor (NLP)

After echo cancellation, there is always a small amount of residual echo which may still be audible. The ZL50235

uses Zarlink’s patented Advanced NLP to remove residual echo signals which have a level lower than the

Adaptive Suppression Threshold (TSUP in G.168). This threshold depends upon the level of the Rin (Lrin)

reference signal as well as the programmed value of the Non-Linear Processor Threshold register (NLPTHR).

TSUP can be calculated by the following equation:

TSUP = Lrin + 20log10(NLPTHR)

where NLPTHR i s the Non-Linear Processor Threshold register value and Lrin is the relativ e power level expressed

in dBm0. The NLPTHR register is 16 bits wide. The register value in hexadecimal can be calculated with the

following equation:

NLPTHR(hex) = hex(NLPTHR(dec) * 3276 8)

where 0 < NLPTHR(dec) < 1

When the level of residual error signal falls below TSUP, the NLP is activated furth er at tenuating t he residual signal

by an additional 30 dB. To prevent a perceived decrease in background noise due to the activation of the NLP, a

spectrally-shaped comfort noise, equivalent in power level to the background noise, is injected. This keeps the

perceived noise l evel constant. Consequently, the user does not hear the activation and de-activat ion of the NLP.

The NLP processor can be disabled by setti ng the NLPDis bit to “1” in Contr ol Regi ster 2.

The comfort noise injector can be disabled by setting the INJDis bit to “1” in Control Register 1. It should be noted

that th e NLPTHR is valid and the comfort noise in jection is acti ve only when the NLP is enabled.

The patented Advanced NLP provides a number of new and improved features over the original NLP found in

previous generation devices. Differences between the Advanced NLP and the original NLP are summarized in

Table 1.

The NLPSel bit in Control Regi ster 3 select s which NLP is used. A “1” will select the Advanced NLP, “0” selects the

origi nal NLP. (See page 29 - Control Regis ter 3 bit descr iption)

The Advanced NLP uses a new noise ramping scheme to quickly and more accurately estimate the background

noise level. The noise ramping method of the original NLP can also be used. The InjCtrl bit in Control Register 3

selects the ramping sch eme .

Feat ure Regi s te r o r Bit(s) A dvanc ed

NLP Default

Value

Original NLP

Default Value

NLP Sele ct ion NLPS e l (Con trol Re gi ster 3) 1 0 (fea t ure

not sup ported)

Reject uncanceled echo as noise NLRun1 (Control Register 3) 1 0 (feature

not sup ported)

Reject double-talk as noise NLRun2 (Control Register 3) 1 0 (feature

not sup ported)

Noise level estimator ramping scheme InjCtrl (Control Regi ster 3) 1 0 (feature

not sup ported)

Noi se l e vel ra mp i ng r ate NLI nc (Nois e C ont ro l ) 5( hex ) C(h ex )

Noise level scaling Noise Scaling 16(hex) 74(hex)

Table 1 - Co m pari son of N LP Typ es

ZL50235 Data Sheet

10 Zarlink Semiconductor Inc.

The NLInc sub-register in Noise Control is used to set the ramping speed. When InjCtrl = 1 (such as with the

Advanced NLP), a lower value will give faster ramping. When InjCtrl = 0 (such as with the original NLP), a higher

value will give faster ramping. NLInc is a 4-bit value, so only values from 0 to F(hex) are valid.

The Noise Scaling register can be used to adjust the relative volume of the comfort noise. Lowering this value will

scale the inj ected noise level down, conversely, raisi ng the value will scale the co mfort noise up. Due to differ ences

in the noise estim ator operation, the Advanced NLP requires a different scaling value than th e ori ginal NLP.

IMPORTANT NOTE: NLInc and the Noise Scaling register have been pre-programmed with G.168 compliant

values. Changing these values may result in undesirable comfort noise performance!

The Advanced NLP also contains safeguards to prevent double-talk and uncanceled echo from being mistaken for

background noise. These features were not present in the original NLP. They can be disabled by setting the

NLRun1 and NLRun2 bits in Control Register 3 to “0”.

1.5 Disa b l e Ton e Detector

The G.165 recommendation defines the disable tone as having the following characteristics: 2100 Hz (±21Hz) sine

wave, a power level between -6 to -31 dBm0, and a phase reversal of 180 degrees (± 25 degrees) every

450 ms (±25 ms). If the disable tone is present for a minimum of one second with at least one phase reversal, the

Tone Detector will trigger.

The G.164 recommendation defines the disable tone as a 2100 Hz (+21 Hz) sine wave with a power level between

0 to -31 dBm0. If the disable tone is present for a minimum of 400 ms, with or without phase reversal, the Tone

Detector will trigger.

The ZL50235 has two Tone Detectors per channels (for a total of 32) in order to monitor the occurrence of a valid

disable tone on both R in and Sin. Upon detection of a disable tone, TD bit of the Status Register will indicate logic

high and an i nterrupt i s generated (i.e. IR Q pin low). Refer to Fig ure 5 and to the Interrupts sec t i on.

Figure 5 - Disable Tone Detection

Once a Tone Detector has been triggered, there is no longer a need for a valid disable tone (G.164 or G.165) to

maintain Tone Detector status (i.e. TD bit high). The Tone Detector status will only release (i.e. TD bit low) if the

signals Rin and Sin fall below -30 dBm0, in the frequency range of 390 Hz to 700 Hz, and below -34 dBm0, in the

frequency range of 700 Hz to 3400 Hz, for at least 400 ms. Whenever a Tone Detector releases, an interrupt is

generated (i. e. I R Q pin low).

The selection between G.165 and G.164 tone disable is controlled by the PHDis bit in Control Register 2 on a per

channel basis. When the PHDis bit is set to “1”, G.164 tone disable requirements are selected.

In response to a valid disable tone, the echo canceller must be switched from the Enable Adaptation state to the

Bypass state. This can be done in two ways, automatically or externally. In automatic mode, the Tone Detectors

internally control the switching between Enable Adaptation and Bypass states. The automatic mode is activated by

setting the AutoTD bit i n Control Register 2 to high. In ex ternal mode, an external controller is needed to s ervice t he

TD bit

Rin

Sin

Echo Ca nc e lle r A

Tone Detector

Tone Detector S tat us r eg

ECA

TD bit

Rin

Sin

Echo Ca nc e lle r B

Tone Detector

Tone Detector S tat us r eg

ECB

Data Sheet ZL50235

11Zarlink Semiconductor Inc.

interrupts and poll the TD bits in the Status Registers. Following the detection of a disable tone (TD bit high) on a

given channel, the external controller must switch the echo canceller from Enabl e Adaptation to Bypass sta te.

1.6 In stab ility De tector

In systems with very low echo channel return loss (ERL), there may be enough feedback in the loop to cause

stability prob lems in the ad aptive filte r. This instability can result i n variable p it ched ringing or oscillati on. Shou ld this

ringi ng occur, the Instability Detector will activat e and suppress the osci llati ons.

The Inst abilit y Detector is acti vated by setting the RingClr bi t i n Control Register 3 to “1”.

1.7 Narrow Band Signal Detector (NBSD)

Single or dual frequency tones (i.e. DTMF tones) present in the receive input (Rin) of the echo canceller for a

prolonged period of time may cause the Adaptive Filter to diverge. The Narrow Band Signal Detector (NBSD) is

designed to prevent this by detecting single or dual tones of arbitrary frequency, phase, and amplitude. When

narrow band si gnals are detected, adapt ation is halted but the echo canceller conti nues to cancel echo.

The NBSD will be active regardless of the Echo Canceller functional state. However the NBSD can be disabled by

setting the NBDis bit to “1” in Control Register 2.

1.8 Offs et Nu ll Filte r

Adaptive filters in general do not operate properly when a DC offset is present at any input. To remove the DC

compone nt, the ZL50235 incorporat es O ffset Null filters in both Rin and Sin input s.

The offset null fi lters can be dis abled by setti ng the HPFDis bit to “1” in Control Register 2.

1.9 Ad justable Leve l Pa ds

The ZL50235 provides adjustable level pads at Rin, Rout, Sin and Sout. This setup allows signal strength to be

adjusted both i nside and outside the echo path. Eac h signal level may be in dependent ly scaled with anywhere from

0 to -12 dB level, i n 3 dB steps. Level val ues are set using the Gains regi ster.

CAUTION: Gain adjustmen t can help interface the ZL50235 to a particular system in order to p rovi de opt imum echo

cancellation, but it can also degrade performance if not done carefully. Excessive loss may cause low signal levels

and slow convergence. Exer cise great care when adjusting these values.

The -12 dB PAD bit in Control Register 1 is still supported as a legacy feature. Setting this bit will provide 12 dB of

attenuation at Rin, and override the values in the Gains register.

1.10 ITU-T G.16 8 Comp lianc e

The ZL50235 has been certified G.168 (1997), (2000) and (2002) compliant in all 64 ms cancellation modes

(i.e. Normal and Back-to-Back configurations) by in-house testing with the DSPG ECT-1 echo canceller tester.

The ZL50235 has also been tested for G.168 compliance and all voice quality tests at AT&T Labs. The ZL50235

was classified as “carrier grade” echo canceller.

ZL50235 Data Sheet

12 Zarlink Semiconductor Inc.

2.0 Device Configuration

The ZL50235 architecture contains 16 echo cancellers divided into 8 groups. Each group has two echo cancellers

which can be individually controlled (Echo Canceller A (ECA) and Echo Canceller B (ECB)). They can be set in

three distinct configurations: Normal, Back-to-Back, and Extended Delay. See Figures 6, 7, and 8.

2.1 Normal Configuration

In Normal configuration, the two echo cancellers (Echo Canceller A and B) are positioned in parallel, as shown in

Figure 6, provi ding 64 milliseconds of ech o cancellati on in two channels simult aneousl y.

Figure 6 - Normal D evice Configuration (64ms)

2.2 Back-to-Back Configuration

In Back-to-Back configuration, the two echo cancellers from the same group are positioned to cancel echo coming

from both directions in a single channel providing full-duplex 64ms echo cancellation. See Figure 7. This

configuration uses onl y one tim eslot on PORT 1 and PORT2 and the second times lot normally associated with ECB

contains zero code. Back-to-Back configuration allows a no-glue interface for applications where bidirectional echo

cancellati on is required.

Figure 7 - B ack-to-Back Device Conf iguration (64ms)

Rin

Rout

Sout

Sin

echo

path A

echo

path B

channel A

ch annel A

channel B

ch annel B

ECA

ECB

Adaptive

Fi l ter (6 4m s)

Adaptive

Filt er (64 ms )

PORT1PORT2

ECA

Sin Sout

Rout Rin

ECB

echo echo

path path

Adaptive

Filt er ( 64m s )

Adaptive

Filt er ( 64ms )

PORT1PORT2

Data Sheet ZL50235

13Zarlink Semiconductor Inc.

Back-to-Back configuration is selected by writing a “1” into the BBM bit of Control Register 1 for both Echo

Canceller A and Echo Canceller B for a given group of echo canceller. Table 4 shows the 8 groups of 2 cancellers

that can be conf igured int o Back-to-Back.

Examples of Back-to-Back configuration include positioning one group of echo cancellers between a codec and a

transmission device or between two codecs for echo control on anal og trunks.

2.3 Extend ed D elay c onfig uratio n

In this configuration, the two echo cancellers from the same group are internally cascaded into one 128

milliseconds echo canceller. See Figure 8. This configuration uses only one timeslot on PORT1 and PORT2 and

the second timeslot normally associated with ECB contains quiet code.

Figure 8 - Extended Delay Configuration (128ms)

Extended Delay configuration is selected by writing a “1” into the ExtDl bit in Echo Canceller A, Control Register 1.

For a given group, only Echo Canceller A, Control Register 1, has the ExtDl bit. For Echo Canceller B Control

Table 4 shows the 8 groups of 2 cancell ers that can each be configured into 64ms or 128ms echo ta il capaci ty.

3.0 Echo C ancelle r Functional States

Each echo ca nceller has f our functional st ates: Mute, Bypass, Disabl e Adaptation and En a b le A d ap ta ti on .

3.1 Mute

In Normal and in Ext ended Delay configurati ons, writing a “1” into the MuteR bi t r eplaces Rin wit h quiet code which

is applied to both the Adaptive Filter and Rout. Writing a “1” into the MuteS bit replaces the Sout PCM data with

quiet code.

I n Ba c k- to -B a ck c o nfi guration, w ri ti n g a “ 1” in to t h e Mu t eR bit of Echo Canceller A, Control Register 2, causes

quiet code to be transmitted on Rout. Writing a “1” into the MuteS bit of Echo Canceller A, Control Register 2,

causes quiet code to be tr ansm itted on Sout.

LINEAR

16 bits

2’s

complement

SIGN/

MAGNITUDE

µ-Law

A-Law

CCI TT (G.711)

µ-Law A-Law

+Zero

(qu iet code) 0000hex 80hex FFhex D5hex

Tab le 2 - Quiet PC M Cod e Ass ign ment

channel A

ECA

Sin Sout

Rout Rin

echo

path A Adaptive Filter

(128 ms)

PORT1PORT2

ZL50235 Data Sheet

14 Zarlink Semiconductor Inc.

In Ext ended Delay and in Back-to-Back config urati ons, MuteR and Mute S bi ts of Echo Cance ller B must always be

“0”. Refer to Figure 4 and to Control Register 2 for bit description.

3.2 Bypass

The Bypass state directly transfers PCM codes from Rin to Rout and from Sin to Sout. When Bypass state is

selected, the Adaptive Filte r coeffici ents are reset to zero. Bypass state must be sele cted for at least one fr am e

(125 µs) in or der to properl y clear the fi lter.

3.3 Disa ble A da ptatio n

When t he Disable Adaptation state i s selected, the Adapti ve Filter coefficients are frozen at their cur rent value. The

adaptation process is halted, however, the echo canceller continues to cancel echo.

3.4 Enable Adaptation

In Enable Adaptation state, the Adaptive Filter coefficients are continually updated. This allows the echo canceller

to mod el t he echo return path characterist ics in order to cance l echo. This is the normal operati ng state.

The echo canceller functions are selected in Control Register 1 and Control Register 2 through four control bits:

MuteS, MuteR, Bypass and AdaptDis. Refer t o the Regi sters Description for details.

4.0 ZL5 0 235 Throughput Dela y

The throu ghput delay of the ZL50235 varies accordi ng to the d evice configurat ion. For all de vice configurations, Rin

to Rout has a delay of two frames and Si n to Sout has a dela y of three f rames. In Bypass state, the Rin to Rout and

Sin to Sout paths have a delay of two frames.

5.0 S er ial P CM I/O c ha nne ls

There are two sets of TDM I/O st reams, each with channels numb ered from 0 to 31. One set of input streams is for

Receive (Rin) channels, and the other set of input streams is for Send (Sin) channels. Likewise, one set of output

streams is for Rout PCM channe ls, and the other set i s for Sout channels. See Figure 9 for channel allocation.

The arrangement and connection of PCM channels to each echo canc ell er is a 2 port I/O configurat ion for each set

of PCM Send and Receive channels, as illustrated in Figure 9.

5.1 S e rial Data In terf ac e Ti min g

The ZL50235 provides ST-BUS and GCI interface timing. The Serial Interface clock frequency, C4i, is 4.096 MHz.

The input and output data rate of the ST-BUS and GCI bus is 2.048 Mb/s.

The 8 KHz input frame pulse can be in either ST-BUS or GCI format. The ZL50235 automatically detects the

presence of an input frame pulse and identifies it as either ST-BUS or GCI. In ST-BUS format, every second falling

edge of the C4i clock marks a bit boundary, and the data is clocked in on the rising edge of C4i, three quarters of

the way into the bit cell (See Figure 12). In GCI format, every second rising edge of the C4i clock marks the bit

boundary, and data i s clocked in on the sec ond fallin g edge of C4i , half the way into the bit cell (see Figure 13).

Data Sheet ZL50235

15Zarlink Semiconductor Inc.

Figure 9 - ST-BUS and GCI Interface Channel Assignment for 2Mb/s Data Streams

Base

Address + Echo Canceller A Base

Address + Echo Canceller B

Byte LS

Byte MS

Byte LS

Byte

- 00h Control Reg 1 - 20h Control Reg 1

- 01h Control Reg 2 - 21h Control Reg 2

- 02h Status Reg - 22h Status Reg

- 03h Reserved - 23h Reserved

- 04h Flat Delay Reg - 24h Flat Delay Reg

- 05h Reserved - 25h Reserved

- 06h De cay Step Size Reg - 26h Decay Step Size Reg

- 07h Decay S tep Number - 27h Decay St ep Num ber

- 08h Control Reg 3 - 28h Control Reg 3

- 09h Control Reg 4 - 29h Control Reg 4

- 0Ah Noise Scal ing - 2Ah Noise Scaling

- 0Bh Noise Control - 2Bh Noise Control

0Dh 0Ch Rin Peak Detect Reg 2Dh 2Ch Rin Peak Detect Reg

0Fh 0Eh Sin Peak Detect Reg 2Fh 2Eh Sin Peak Detect Reg

11h 10h Error Peak Detect Reg 31h 30h Error Peak Detect Reg

13h 12h Reserved 33h 32h Reserved

15h 14h DTDT Reg 35h 34h DTDT Reg

17h 16h Reserved 37h 36h Reserved

19h 18h NLPTHR 39h 38h NLPTHR

1Bh 1Ah St ep Size, MU 3Bh 3Ah S tep Size, MU

1Dh 1Ch Gains 3Dh 3Ch Gains

1Fh 1Eh Reserved 3Fh 3Eh Reserved

Table 3 - Me m ory Mapping of Per C ha nnel C on t rol and Status Regi s t ers

F0i

Rin/Sin

Rout/Sout

125 µsec

ST-BUS

F0i

GCI interface

Note: Refer to Figur e 12 and Fi gure 13 for tim ing details.

62.5

sec

123456789 1011121314150

Active Channels

Disabled Channels with Random Data

ZL50235 Data Sheet

16 Zarlink Semiconductor Inc.

6.0 Me m ory Ma ppe d Cont rol and Status reg iste rs

Inte rnal memo ry and register s are memory mappe d into the addr ess sp ace of the HOST interf ace. The int ernal dual

ported memory is mapped into segments on a “per channel” basis to monitor and control each individual echo

canceller and associated PCM channels. For example, in Normal configuration, echo canceller #5 makes use of

Echo Canceller B from group 2. It occupies the internal address space from 0A0hex to 0BFhex and interfaces to

PCM channe l #5 on all serial PCM I/O streams.

As illustrated in Table 3, the “per channel” registers provide independent control and status bits for each echo

canceller. Figure 10 shows the memory map of the control/status regist er bl ocks for all echo cancellers.

When Extended Delay or Back-to-Back configu rat ion is selected, Cont rol Regist er 1 of ECA and ECB and Cont rol

Table 4 is a list of the channels used for the 16 groups of echo cancellers when they are configured as Extended

Delay or Back-to-Back.

6.1 Normal Configuration

For a given group (group 0 to 7), 2 PCM I/O channels are used. For example, group 1 Echo Cancellers A and B,

channels 2 and 3 are active.

6.2 Exte n ded De lay Co nfigu ratio n

For a given group (group 0 to 7), only one PCM I/O channel is active (Echo Canceller A) and the other channel

carries quiet code. For example, group 2, Echo Canceller A (Channel 4) will be active and Echo Canceller B

(Channel 5) will carr y quiet code.

6.3 Back-to-Back Configuration

For a given group (group 0 to 7), only one PCM I/O channel is active (Echo Canceller A) and the other channel

carries quiet code. For example, group 5, Echo Canceller A (Channel 10) will be active and Echo Canceller B

(Channel 11) will carry quiet code.

Group Channels

00, 1

12, 3

24, 5

36, 7

48, 9

5 10, 11

6 12, 13

7 14, 15

Table 4 - Group and Chann el allocation

Data Sheet ZL50235

17Zarlink Semiconductor Inc.

Fig ure 10 - Memory Mapping

6.4 Power Up Sequence

On power up, the RESET pin must b e held low for 100 µs. Forcing the RESET pi n low will put the ZL50235 in power

down state. In this state, all internal clocks are halted, D<7:0>, Sout, Rout, DTA and IRQ pins are tristated. The 8

Main Contro l Regi sters, the Interrupt FIFO Regis ter and the Test Register are reset to zero.

When the RESET pin returns to logic high and a valid MCLK is applied, the user must wait 500 µs for the PLL to

lock. C4i and F0i can be active during this period. Once the PLL has locked, the user must power up the 8 groups

of echo cancellers individually, by writing a “1” into the PWUP bit in each group of echo canceller’s Main Control

For each group of echo cancellers, when the PWU P bit toggles from zero to one, echo cancellers A and B execute

their initialization routine. The initial ization routi ne sets the ir registers, Base Add ress+00 hex to Base Address+3Fhex,

to the def ault Reset Value and clea rs t he Adaptive Filter coefficients. Two f rames are necessary for the initialization

routi ne to execute properly.

Once the initi ali zation routine i s executed, the user can set the per channel Control Regist ers, Base Address+ 00hex

to Base Address+3Fhex, for the specific appl ication.

6 . 5 Po wer manage m ent

Each group of echo cancellers can be placed in Power Down mode by writing a “0” into the PWUP bit in their

respective Main Control Register. When a given group is in Power Down mode, the corresponding PCM data are

bypassed from Rin to Rout and from Sin to Sout with two frames delay. Refer to the Main Control Register section

for descr iption.

The typic al power consump ti on can be calculat ed with the followi ng equation:

PC = 9 * Nb_of_groups + 3.6, in mW

where 0 ≤ Nb_of_groups ≤ 8.

0000h -->

Channel 0, ECA Ctrl/Stat R egisters 001Fh

0020h -->

Channel 1, ECB Ctrl/Stat R egisters 003Fh

0040h -->

Channel 2, ECA Ctrl/Stat R egisters 005Fh

0060h -->

Channel 3, ECB Ctrl/Stat R egisters 007Fh

01C0h -->

Channel 14, ECA Ctrl/Stat Reg is te rs 01DFh

01E0h -- >

Channel 15, ECB Ctrl/Stat Reg is te rs 01FFh

0400h --> 040 7h

Main Contr ol Reg is ters <7:0>

Group 0

Echo

Cancellers

Registers

Groups 2 -- > 6

Echo Cancellers

Registers

Group 1

Echo

Cancellers

Registers

Group 7

Echo

Cancellers

Registers

0410h

Interrupt F IFO Register

0411h

Test Regi ster

0412h ---> FFFFh

Reserved Test Register

ZL50235 Data Sheet

18 Zarlink Semiconductor Inc.

6.6 Call Initialization

To ensure fast initial convergence on a new call, it is important to clear the Adaptive Filter. This is done by putting

the echo canceller in bypas s mode for at least one frame (125 µs) and then enabl ing adaptation.

Since the Narrow Band Det ector is “ON” regardless of the functional state of Ec ho Canceller it is recommended that

the Echo canceller s are reset befor e any call progress tones are applied.

6.7 Inter rupts

The ZL50235 provides an interrupt pin (IRQ) to indicate to the HOST processor when a G.164 or G.165 Tone

Disable is detected and released.

Although the ZL50235 may be configured to react automatically to tone disable status on any input PCM voice

channels, the user may want for the external HOST processor to respond to Tone Disable information in an

appropriate application-specific manner.

Each echo canceller will generate an interrupt when a Tone Disable occurs and will generate another interrupt

when a Tone Disable releases.

Upon receiving an IRQ, the HOST CPU should read the Interrupt FIFO Register. This register is a FIFO memory

containing the channel number of the echo canceller that has generated the interr upt.

All pending interrupts from any of the echo cancellers and their associated input channel number are stored in this

FIFO memory. The IRQ always returns high after a read access to the Interrupt FIFO Register. The IRQ pin will

toggle low for each pending interrupt.

After the HOST CPU has received the channel number of the interrupt source, the corresponding per channel

Status Register can be read from internal memory to determine the cause of the interrupt (see Table 3 for address

mapping of S tatus register). The TD bit indicates the presence of a Tone Disable.

The MIRQ bit 5 in the Main Control Register 0 masks interrupts from the ZL50235. To provide more flexibility, the

MTDBI (bit-4) and MTDAI (bit-3) bits in the Main Control Register<7:0> allow Tone Disable to be masked or

unmas ked from generating an inter rupt on a per channel ba sis. Refer to the Regi sters Description section.

Data Sheet ZL50235

19Zarlink Semiconductor Inc.

7.0 JTAG Support

The ZL50235 JTAG interface conforms to the Boundary-Scan standard IEEE1149.1. This standard specifies a

design-for-testability technique called Boundary-Scan test (BST). The operation of the Boundary Scan circuitry is

controlled by an Test Acces s Port (TAP) controller. JTAG i nputs a re 3.3 Volts compli ant only.

7. 1 Test Access P o r t (TAP)

The TAP provides access to many test functions of the ZL50235. It consists of four input pins and one output pin.

The following pins are fo und on the TAP.

• Test Clock Input (TCK )

The TCK provid es t h e cl o ck for the test log i c. The TCK does n ot int e r fere with a ny on-c hi p c lock and thus

re m ains i n de pende nt. The TCK permits sh i fting of t e st data into or out o f the B oundar y-S can re gist er cel ls

c onc urr e nt with the oper ati o n of t h e device an d w ith out inter fering w it h the on- ch ip logic.

• Test Mode Select Input (TMS )

The logic signa ls r ec ei ve d at th e TMS input ar e i nte r preted b y the TAP Cont roll e r to co nt rol th e t es t

operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to

VDD1 when it is not driven fro m an e xternal source .

• Test Data Inp ut (TDI)

Serial inpu t data applied to this port is fed either into the ins truction register or into a test data register,

depend ing o n t h e sequence pre viously a ppl ied to th e T MS i np ut. B oth r e gi ste r s are describ ed i n a

s ubs equ ent sec ti on. The r ece i ved i npu t data is sam pl e d a t the ri sing edge of T CK pu ls es. This p in i s

internally pulled to VDD1 w hen it is not driven from an e xt e r nal sourc e.

• Test Data Output (TDO)

Dependi ng on t h e se quenc e p revi o usl y a pplied to the T M S input, the cont en ts of eit h er the i nstr u cti on

falling edge of the TC K pulses. W hen n o data is shifted through the Bound ary Scan ce lls, the TDO driver is

s et to a high imp edanc e state.

• Test Reset (TRST)

This pin is used to reset the JTAG scan structure. This pin is in ternally pulled to VSS.

7. 2 Instruction Regi s ter

In accordance wit h the IEEE 1149.1 standard, the ZL50235 uses public instructions . The JTAG Interface cont ains a

3-bit instruction register. Instructions are serially loaded into the instruction register from the TDI when the TAP

Controller is in its shifted-IR state. Subsequently, the instructions are decoded to achieve two basic functions: to

select the test data reg ister that will oper ate while the inst ructi on is current , and to defin e t he serial t est dat a regist er

path, which is used to shift data between TDI and TDO during data register scanning.

7.3 Test Data Registers

As specified in IEEE 1149.1, the ZL50235 JTAG In terface contains t hree test data regist ers:

• Boundar y-S can reg ist er

The Boundary-S ca n r e gi ste r con si sts of a serie s of B ou ndary-S ca n cells arr a nged to form a scan path

ar ou nd t h e bo undar y of t h e ZL 50235 co re l og i c.

• Bypass Regi s t er

The Bypa ss re gi ster is a s in gle stage s hif t r egister tha t provide s a o ne- b i t path f ro m TDI to TD O .

• Device Id ent if ication registe r

The Device Identification reg ister provides acce ss to the following e ncoded info rmation:

devi c e version num ber, part n um ber an d m an ufacturer' s nam e.

ZL50235 Data Sheet

20 Zarlink Semiconductor Inc.

8. 0 Register Description

Echo Cancelle r A (ECA): Control Register 1

Power-up 00hex R/W Address: 00hex + Base Address

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset INJDis BBM PAD Bypass AdpDis 0 ExtDI

Functional Description of Register Bits

Reset When high, the power-up in it ializat ion is executed. This presets all regi ster bits inclu ding

this bit and clears the Adaptive Filter coefficients.

INJDis When hig h, th e noise inject ion process is disabled. When low noise i njection i s enabled.

BBM When high, the Back to Back configuration is enabled. When low, the Normal

confi gurati on is enabl ed. Note: Do n ot enable Exte nded-Del ay and BBM configurat ions at

the same ti m e. Always set both BBM bits of the two echo cancell ers (Control Re gister 1)

of the same group to the same logi c value to avoid conflic t.

PAD W hen high, 12d B of attenua tion i s i nsert ed into t he Rin to Rout path . When low , the Gains

Bypass When high, Sin data is by-p assed to Sout and Rin dat a is by-passed to Rout. The

Adaptive Filter coeffi cients are set to zero and the fil ter adaptation is stopped. When low,

output data on both Sout and Rout is a function of the echo canceller algorithm.

AdpDis When hig h, echo canceller adaptation is disabled. The Voice Processor cancels echo.

When low, the echo cancel ler dynam ically adapts to the echo path characteri stics.

0 Bits m arked as “1” or “0” are reserved bits and should be written as indicated.

ExtDl When high, Echo Cancel lers A and B of the same gr oup are inter nally cascaded into one

128ms ech o canceller. When low, Echo Cancellers A and B of the same group operate

independently.

Echo Cancelle r B (ECB): Control Register 1

Power-up 02hex R/W Address: 20hex + Base Address

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reset INJDis BBM PAD Bypass AdpDis 1 0

Functional Description of Register Bits

Reset When high, the power-up initialization is executed which preset s all register bits includi ng

this bit and clears the Adaptive Filter coefficients.

INJDis When hig h, th e noise inject ion process is disabled. When low, noise injec tion is enabl ed.