CIN
VIN SW
AGND
FB
PGOOD
VOUT
RFB1
RFB2
COUT
EN
SS/TRK VCC CVCC
CC1
COMP
RC1
VIN
LM20333
BOOT
GND
L
CBOOT
D1
(Optional)
SYNC
LM20333
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LM20333 36V, 3A Synchronous Buck Regulator with Frequency Synchronization
Check for Samples: LM20333
1FEATURES DESCRIPTION
The LM20333 is a full featured synchronous buck
2• 4.5V to 36V Input Voltage Range regulator capable of delivering up to 3A of load
• 3A Output Current, 5.2A Peak Current current. The current mode control loop is externally
• 130 mΩ/110 mΩIntegrated Power MOSFETs compensated with only two components, offering both
high performance and ease of use. The device is
• 94% Peak Efficiency with Synchronous optimized to work over the input voltage range of
Rectification 4.5V to 36V making it well suited for high voltage
• 1.5% Feedback Voltage Accuracy systems.
• Current Mode Control, Selectable The device features internal Over Voltage Protection
Compensation (OVP) and Over Current Protection (OCP) circuits for
• Oscillator Synchronization from 250kHz to increased system reliability. A precision Enable pin
1.5MHz and integrated UVLO allows the turn on of the device
to be tightly controlled and sequenced. Startup inrush
• Adjustable Output Voltage Down to 0.8V currents are limited by both an internally fixed and
• Compatible with Pre-biased Loads externally adjustable soft-start circuit. Fault detection
• Programmable Soft-start with External and supply sequencing are possible with the
Capacitor integrated power good (PGOOD) circuit.
• Precision Enable Pin with Hysteresis The LM20333 is designed to work well in multi-rail
• OVP, UVLO Inputs and PGOOD Output power supply architectures. The output voltage of the
device can be configured to track a higher voltage rail
• Internally Protected with Peak Current Limit, using the SS/TRK pin. If the output of the LM20333 is
Thermal Shutdown and Restart pre-biased at startup it will not sink current to pull the
• Accurate Current Limit Minimizes Inductor output low until the internal soft-start ramp exceeds
Size the voltage at the feedback pin.
• Non-linear Current Mode Slope Compensation The switching frequency of the LM20333 can be
• 20-Pin HTSSOP Exposed Pad Package synchronized to an external clock by use of the
SYNC pin. The SYNC pin is capable of synchronizing
APPLICATIONS to input signals ranging from 250 kHz to 1.5 MHz.
• Simple to Design, High Efficiency Point of The LM20333 is offered in an exposed pad 20-pin
Load Regulation from a 4.5V to 36V Bus HTSSOP package that can be soldered to the PCB,
eliminating the need for bulky heatsinks.
• High Performance DSPs, FPGAs, ASICs and
Microprocessors
• Communications Infrastructure, Automotive
Simplified Application Circuit
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2008–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
VIN
1
FB
SS/TRK
SW
VIN
GND AGND
SW
EN
VIN
PGOOD
COMP
EP
VCC
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SW
GND GND
SW
VIN
SYNC
BOOT
LM20333
SNVS558D –MAY 2008–REVISED APRIL 2013
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Connection Diagram
Figure 1. 20-Pin HTSSOP, Top View
See PWP0020A Package
PIN DESCRIPTIONS
Pin(s) Name Description Application Information
1 SS/TRK Soft-Start or Tracking control input An internal 4.5 µA current source charges an external capacitor to set
the soft-start rate. The PWM can track to an external voltage ramp with
a low impedance source. If left open, an internal 1 ms SS ramp is
activated.
2 FB Feedback input to the error amplifier This pin is connected to the inverting input of the internal
from the regulated output transconductance error amplifier. An 800 mV reference is internally
connected to the non-inverting input of the error amplifier.
3 PGOOD Power good output signal Open drain output indicating the output voltage is regulating within
tolerance. A pull-up resistor of 10 kΩto 100 kΩis recommended if this
function is used.
4 COMP Output of the internal error amplifier and The loop compensation network should be connected between the
input to the Pulse Width Modulator COMP pin and the AGND pin.
5,6,15,16 VIN Input supply voltage Nominal operating range: 4.5V to 36V.
7,8,13,14 SW Switch pin The drain terminal of the internal Synchronous Rectifier power
NMOSFET and the source terminal of the internal Control power
NMOSFET.
9,10,11 GND Ground Internal reference for the power MOSFETs.
12 AGND Analog ground Internal reference for the regulator control functions.
17 BOOT Boost input for bootstrap capacitor An internal diode from VCC to BOOT charges an external capacitor
required from SW to BOOT to power the Control MOSFET gate driver.
18 VCC Output of the high voltage linear VCC tracks VIN up to about 7.2V. Above VIN = 7.2V, VCC is regulated
regulator. The VCC voltage is regulated to approximately 5.5 Volts. A 0.1 µF to 1 µF ceramic decoupling
to approximately 5.5V. capacitor is required. The VCC pin is an output only.
19 EN Enable or UVLO input An external voltage divider can be used to set the line undervoltage
lockout threshold. If the EN pin is left unconnected, a 2 µA pull-up
current source pulls the EN pin high to enable the regulator.
20 SYNC Frequency synchronization input An external clock connected to this pin will set the switching frequency.
If left open the device will operate at approximately 200 kHz.
EP Exposed Exposed pad Exposed metal pad on the underside of the package with a weak
Pad electrical connection to GND. Connect this pad to the PC board ground
plane in order to improve heat dissipation.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings(1)(2)
VIN to GND -0.3V to +38V
BOOT to GND -0.3V to +43V
BOOT to SW -0.3V to +7V
SW to GND -0.5V to +38V
SW to GND (Transient) -1.5V (< 20 ns)
FB, EN, SS/TRK, COMP, SYNC, PGOOD to GND -0.3V to +6V
VCC to GND -0.3V to +8V
Storage Temperature -65°C to 150°C
ESD Rating
Human Body Model(3) 2kV
(1) Absolute Maximum Ratings indicate limits beyond witch damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test
conditions, see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) The human body model is a 100 pF capacitor discharged through a 1.5 kΩresistor to each pin.
Operating Ratings
VIN to GND +4.5V to +36V
Junction Temperature −40°C to + 125°C
Electrical Characteristics
Unless otherwise stated, the following conditions apply: VVIN = 12V. Limits in standard type are for TJ= 25°C only, limits in
bold face type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and maximum limits are
specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at
TJ= 25°C, and are provided for reference purposes only.
Symbol Parameter Conditions Min Typ Max Units
VFB Feedback Pin Voltage VVIN = 4.5V to 36V 0.788 0.8 0.812 V
RHSW-DS(ON) High-Side MOSFET On-Resistance ISW = 3A 130 225 mΩ
RLSW-DS(ON) Low-Side MOSFET On-Resistance ISW = 3A 110 190 mΩ
IQOperating Quiescent Current VVIN = 4.5V to 36V 2.3 3mA
ISD Shutdown Quiescent Current VEN = 0V 150 180 µA
VUVLO VIN Under Voltage Lockout Rising VVIN 44.25 4.5 V
VUVLO(HYS) VIN Under Voltage Lockout Hysteresis 350 450 mV
VVCC VCC Voltage IVCC = -5 mA, VEN = 5V 5.5 V
ISS Soft-Start Pin Source Current VSS = 0V 24.5 7µA
VTRKACC Soft-Start/Track Pin Accuracy VSS = 0.4V -10 515 mV
IBOOT BOOT Diode Leakage VBOOT = 4V 10 nA
VF-BOOT BOOT Diode Forward Voltage IBOOT = -100 mA 0.9 1.1 V
Powergood
VFB(OVP) Over Voltage Protection Rising Threshold VFB(OVP) / VFB 107 110 112 %
VFB(OVP-HYS) Over Voltage Protection Hysteresis ΔVFB(OVP) / VFB 23%
VFB(PG) PGOOD Threshold, VOUT Rising VFB(PG) / VFB 93 95 97 %
VFB(PG-HYS) PGOOD Hysteresis ΔVFB(PG) / VFB 23%
TPGOOD PGOOD Delay 20 µs
IPGOOD(SNK) PGOOD Low Sink Current VPGOOD = 0.5V 0.6 1 mA
IPGOOD(SRC) PGOOD High Leakage Current VPGOOD = 5V 5 200 nA
Oscillator
FOSC Oscillator Frequency VSYNC = 0V 160 200 240 kHz
FOSCH Maximum SYNC Frequency 1500 kHz
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Electrical Characteristics (continued)
Unless otherwise stated, the following conditions apply: VVIN = 12V. Limits in standard type are for TJ= 25°C only, limits in
bold face type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and maximum limits are
specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at
TJ= 25°C, and are provided for reference purposes only.
Symbol Parameter Conditions Min Typ Max Units
FOSCL Minimum SYNC Frequency 250 kHz
VIH_SYNC SYNC pin Logic High 2V
VIL_SYNC SYNC pin Logic Low 0.8 V
ISYNC SYNC pin input leakage VSYNC = 5V 10 nA
TMIN Minimum Off Time ILOAD = 3A 170 ns
Error Amplifier
IFB Feedback Pin Bias Current VFB = 1V 50 nA
ICOMP(SRC) COMP Output Source Current VFB = 0V 200 400 µA
VCOMP = 0V
ICOMP(SNK) COMP Output Sink Current VFB = 1.6V 200 350 µA
VCOMP = 1.6V
gmError Amplifier DC Transconductance ICOMP = -50 µA to +50 µA 450 515 600 µmho
AVOL Error Amplifier Voltage Gain COMP pin open 2000 V/V
GBW Error Amplifier Gain-Bandwidth Product COMP pin open 7 MHz
Current Limit
ILIM Cycle By Cycle Positive Current Limit 4.3 5.2 6.0 A
ILIMNEG Cycle By Cycle Negative Current Limit 2.8 A
TILIM Cycle By Cycle Current Limit Delay 150 ns
Enable
VEN(RISING) EN Pin Rising Threshold 1.2 1.25 1.3 V
VEN(HYS) EN Pin Hysteresis 50 mV
IEN EN Source Current VEN = 0V, VVIN = 12V 2 µA
Thermal Shutdown
TSD Thermal Shutdown 170 °C
TSD(HYS) Thermal Shutdown Hysteresis 20 °C
Thermal Resistance
θJC Junction to Case 5.6 °C/W
θJA Junction to Ambient(1) 0 LFM airflow 27 °C/W
(1) Measured on a 4 layer 2" x 2" PCB with 1 oz. copper weight inner layers and 2 oz. outer layers.
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Typical Performance Characteristics
Unless otherwise specified: VVIN = 12V, VOUT = 3.3V, L= 4.7µH, fSW=750kHz, CSS = 100nF, TA= 25°C for efficiency curves,
loop gain plots and waveforms, and TJ= 25°C for all others.
Efficiency Efficiency
vs. vs.
Load Current Load Current
fSW = 350 kHz fSW = 500 kHz
Figure 2. Figure 3.
Efficiency
vs.
Load Current
fSW = 750 kHz Error Amplifier Gain
Figure 4. Figure 5.
Error Amplifier Phase Line Regulation
Figure 6. Figure 7.
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Typical Performance Characteristics (continued)
Unless otherwise specified: VVIN = 12V, VOUT = 3.3V, L= 4.7µH, fSW=750kHz, CSS = 100nF, TA= 25°C for efficiency curves,
loop gain plots and waveforms, and TJ= 25°C for all others. VCC
vs.
Load Regulation VIN
Figure 8. Figure 9.
Non-Switching IQShutdown IQ
vs. vs.
VIN VIN
Figure 10. Figure 11.
PGOOD Output Low Level Voltage Enable Threshold and Hysteresis
vs. vs.
IPGOOD Temperature
Figure 12. Figure 13.
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Typical Performance Characteristics (continued)
Unless otherwise specified: VVIN = 12V, VOUT = 3.3V, L= 4.7µH, fSW=750kHz, CSS = 100nF, TA= 25°C for efficiency curves,
loop gain plots and waveforms, and TJ= 25°C for all others.
UVLO Threshold and Hysteresis Enable Current
vs. vs.
Temperature Temperature
Figure 14. Figure 15.
High-Side FET Resistance
vs.
Clock Synchronization Temperature
Figure 16. Figure 17.
Low-Side FET Resistance
vs.
Temperature Load Transient Response
Figure 18. Figure 19.
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Typical Performance Characteristics (continued)
Unless otherwise specified: VVIN = 12V, VOUT = 3.3V, L= 4.7µH, fSW=750kHz, CSS = 100nF, TA= 25°C for efficiency curves,
loop gain plots and waveforms, and TJ= 25°C for all others.
Peak Current Limit
vs.
Temperature Startup with prebiased output
Figure 20. Figure 21.
Startup with CSS = 0 Startup with CSS = 100 nF
Figure 22. Figure 23.
Startup with applied Track Signal
Figure 24.
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5.2A
+
-
FB
COMP
CONTROL
LOGIC
EN
CURRENT LIMIT
OVERVOLTAGE
UNDERVOLTAGE
ERROR AMP
PWM COMPARATOR
SS/TRK
PGOOD
+
-
+5.5V
REGULATOR
VCC
BOOT
VCC
THERMAL
PROTECTION
GND
SW
VIN
CURRENT SENSE
VCC
1.25V
BOOT
BOOT
UVLO
4.25V
AGND
+
740 mV
880 mV PG-L
PG-L
2.7V
gm = 515 Pmho
VREF
+
-800 mV
+
-
+
2 PA
DISCHARGE
DISCHARGE
SLOPE COMP
4.5 PA
+
--2.8A
NEGATIVE
CURRENT LIMIT
+2.7V
REGULATOR
2.7V
+
-
+
-
+
-
+
-
PHASE LOCK
LOOP
SYNC
INTERNAL
+5.5V
REGULATOR
VCC_INT
VCC_INT
ENABLE_INT
ENABLE_INT
LM20333
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SNVS558D –MAY 2008–REVISED APRIL 2013
Block Diagram
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OPERATION DESCRIPTION
GENERAL
The LM20333 switching regulator features all of the functions necessary to implement an efficient buck regulator
using a minimum number of external components. This easy to use regulator features two integrated switches
and is capable of supplying up to 3A of continuous output current. The regulator utilizes peak current mode
control with nonlinear slope compensation to optimize stability and transient response over the entire output
voltage range. Peak current mode control also provides inherent line feed-forward, cycle-by-cycle current limiting
and easy loop compensation. The switching frequency can be synchronized to an external oscillator over the
range of 250 kHz to 1.5 MHz. The SYNC function allows the device to operate at high switching frequencies
minimizing the size of the inductor while still achieving efficiencies as high as 94%. The precision internal voltage
reference allows the output to be set as low as 0.8V. Fault protection features include: current limiting, thermal
shutdown, over voltage protection, and shutdown capability. The device is available in the HTSSOP package
featuring an exposed pad to aid thermal dissipation. The typical application circuit for the LM20333 is shown in
Figure 25 in the design guide.
PRECISION ENABLE
The enable (EN) pin allows the output of the device to be enabled or disabled with an external control signal.
This pin is a precision analog input that enables the device when the voltage exceeds 1.25V (typical). The EN pin
has 50 mV of hysteresis and will disable the output when the enable voltage falls below 1.2V (typical). If the EN
pin is not used, it should be disconnected so the internal 2 µA pull-up will default this function to the enabled
condition. Since the enable pin has a precise turn-on threshold it can be used along with an external resistor
divider network from VIN to configure the device to turn-on at a precise input voltage. The precision enable
circuitry will remain active even when the device is disabled.
FREQUENCY SYNCHRONIZATION
The frequency sychronization pin(SYNC) allows the switching frequency of the device to be controlled with an
external clock signal. This feature allows the user to sychronize multiple converters, avoiding undesirable
frequency bands of operation.
The switching frequency of the device will synchronize to the rising edge of the clock source that is driving the
SYNC pin. The logic low level for the input clock must be below 0.8V and the logic high level must exceed 2.0V
to ensure proper operation. The device will synchronize to frequencies from 250 kHz to 1.5 MHz. If the
synchronization clock is removed or not present during startup, the oscillator of the device will run at
approximately 200 kHz. If the SYNC pin is not used it should be connected to ground.
PEAK CURRENT MODE CONTROL
In most cases, the peak current mode control architecture used in the LM20333 only requires two external
components to achieve a stable design. The compensation can be selected to accommodate any capacitor type
or value. The external compensation also allows the user to set the crossover frequency and optimize the
transient performance of the device.
For duty cycles above 50% all peak current mode control buck converters require the addition of an artificial
ramp to avoid sub-harmonic oscillation. This artificial linear ramp is commonly referred to as slope compensation.
What makes the LM20333 unique is the amount of slope compensation will change depending on the output
voltage. When operating at high output voltages the device will have more slope compensation than when
operating at lower output voltages. This is accomplished in the LM20333 by using a non-linear parabolic ramp for
the slope compensation. The parabolic slope compensation of the LM20333 is an improvement over the
traditional linear slope compensation because it optimizes the stability of the device over the entire output voltage
range.
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CURRENT LIMIT
The precise current limit enables the device to operate with smaller inductors that have lower saturation currents.
When the peak inductor current reaches the current limit threshold, an over current event is triggered and the
internal high-side FET turns off and the low-side FET turns on, allowing the inductor current to ramp down until
the next switching cycle. For each sequential over-current event, the reference voltage is decremented and PWM
pulses are skipped resulting in a current limit that does not aggressively fold back for brief over-current events,
while at the same time providing frequency and voltage foldback protection during hard short circuit conditions.
SOFT-START AND VOLTAGE TRACKING
The SS/TRK pin is a dual function pin that can be used to set the startup time or track an external voltage
source. The startup or soft-start time can be adjusted by connecting a capacitor from the SS/TRK pin to ground.
The soft-start feature allows the regulator output to gradually reach the steady state operating point, thus
reducing stresses on the input supply and controlling startup current. If no soft-start capacitor is used the device
defaults to the internal soft-start circuitry resulting in a startup time of approximately 1 ms. For applications that
require a monotonic startup or utilize the PGOOD pin, an external soft-start capacitor is recommended. The
SS/TRK pin can also be set to track an external voltage source. The tracking behavior can be adjusted by two
external resistors connected to the SS/TRK pin as shown in Figure 30 in the design guide.
PRE-BIAS STARTUP CAPABILITY
The LM20333 is in a pre-biased state when it starts up with an output voltage greater than zero. This often
occurs in many multi-rail applications such as when powering an FPGA, ASIC, or DSP. In these applications the
output can be pre-biased through parasitic conduction paths from one supply rail to another. Even though the
LM20333 is a synchronous converter, it will not pull the output low when a pre-bias condition exists. During start
up the LM20333 will not sink current until the soft-start voltage exceeds the voltage on the FB pin. Since the
device cannot sink current, it protects the load from damage that might otherwise occur if current is conducted
through the parasitic paths of the load.
POWER GOOD AND OVER VOLTAGE FAULT HANDLING
The LM20333 has built in under and over voltage comparators that control the power switches. Whenever there
is an excursion in output voltage above the set OVP threshold, the part will terminate the present on-pulse, turn-
on the low-side FET, and pull the PGOOD pin low. The low-side FET will remain on until either the FB voltage
falls back into regulation or the negative current limit is triggered which in turn tri-states the FETs. If the output
reaches the UVP threshold the part will continue switching and the PGOOD pin will be deasserted and go low.
Typical values for the PGOOD resistor are on the order of 100 kΩor less. To avoid false tripping during transient
glitches the PGOOD pin has 20 µs of built in deglitch time to both rising and falling edges.
UVLO
The LM20333 has an internal under-voltage lockout protection circuit that keeps the device from switching until
the input voltage reaches 4.25V (typical). The UVLO threshold has 350 mV of hysteresis that keeps the device
from responding to power-on glitches during start up. If desired the turn-on point of the supply can be changed
by using the precision enable pin and a resistor divider network connected to VIN as shown in Figure 29 in the
design guide.
THERMAL PROTECTION
Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum
junction temperature is exceeded. When activated, typically at 170°C, the LM20333 tri-states the power FETs
and resets soft-start. After the junction cools to approximately 150°C, the part starts up using the normal start up
routine. This feature is provided to prevent catastrophic failures from accidental device overheating.
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LMIN = (VIN - VOUT) x D
'iL x fSW
D = VOUT
VIN
CIN1
VIN SW
AGND
FB
PGOOD
VOUT
RFB1
RFB2
COUT
EN
SS/TRK VCC
CVCC
CC1
SYNC
RC1
VIN
LM20333
BOOT
GND
L
CBOOT
D1
(Optional)
CSS
RPG
VPULLUP
CIN2
COMP
LM20333
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Design Guide
This section walks the designer through the steps necessary to select the external components to build a fully
functional power supply. As with any DC-DC converter numerous trade-offs are possible to optimize the design
for efficiency, size, or performance. These will be taken into account and highlighted throughout this discussion.
To facilitate component selection discussions the circuit shown in Figure 25 below may be used as a reference.
Unless otherwise indicated all formulas assume units of amps (A) for current, farads (F) for capacitance, henries
(H) for inductance and volts (V) for voltages.
Figure 25. Typical Application Circuit
The first equation to calculate for any buck converter is duty-cycle. Ignoring conduction losses associated with
the FETs and parasitic resistances it can be approximated by:
(1)
INDUCTOR SELECTION (L)
The inductor value is determined based on the operating frequency, load current, ripple current and duty cycle.
The inductor selected should have a saturation current rating greater than the peak current limit of the device.
Keep in mind the specified current limit does not account for delay of the current limit comparator, therefore the
current limit in the application may be higher than the specified value. To optimize the performance and prevent
the device from entering current limit at maximum load, the inductance is typically selected such that the ripple
current, ΔiL, is not greater than 30% of the rated output current. Figure 26 illustrates the switch and inductor
ripple current waveforms. Once the input voltage, output voltage, operating frequency and desired ripple current
are known, the minimum value for the inductor can be calculated by the formula shown below:
(2)
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'VOUT = 'iL x 1
8 x fSW x COUT
RESR +
VIN
IL AVG = IOUT 'iL
Time
Time
IL
VSW
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Figure 26. Switch and Inductor Current Waveforms
If needed, slightly smaller value inductors can be used, however, the peak inductor current, IOUT +ΔiL/2, should
be kept below the peak current limit of the device. In general, the inductor ripple current, ΔiL, should be more
than 10% of the rated output current to provide adequate current sense information for the current mode control
loop. If the ripple current in the inductor is too low, the control loop will not have sufficient current sense
information and can be prone to instability.
OUTPUT CAPACITOR SELECTION (COUT)
The output capacitor, COUT, filters the inductor ripple current and provides a source of charge for transient load
conditions. A wide range of output capacitors may be used with the LM20333 that provide excellent performance.
The best performance is typically obtained using ceramic, SP or OSCON type chemistries. Typical trade-offs are
that the ceramic capacitor provides extremely low ESR to reduce the output ripple voltage and noise spikes,
while the SP and OSCON capacitors provide a large bulk capacitance in a small volume for transient loading
conditions.
When selecting the value for the output capacitor, the two performance characteristics to consider are the output
voltage ripple and transient response. The output voltage ripple can be approximated by using the following
formula:
where
•ΔVOUT (V) is the amount of peak to peak voltage ripple at the power supply output
• RESR (Ω) is the series resistance of the output capacitor
• fSW(Hz) is the switching frequency
• COUT (F) is the output capacitance used in the design (3)
The amount of output ripple that can be tolerated is application specific; however a general recommendation is to
keep the output ripple less than 1% of the rated output voltage. Keep in mind ceramic capacitors are sometimes
preferred because they have very low ESR; however, depending on package and voltage rating of the capacitor
the value of the capacitance can drop significantly with applied voltage. The output capacitor selection will also
affect the output voltage droop during a load transient. The peak droop on the output voltage during a load
transient is dependent on many factors; however, an approximation of the transient droop ignoring loop
bandwidth can be obtained using the following equation:
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RFB1 = - 1
VOUT
0.8 x RFB2
IIN-RMS = IOUT D(1 - D)
VDROOP = 'IOUTSTEP x RESR + L x 'IOUTSTEP2
COUT x (VIN - VOUT)
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where
• COUT (F) is the minimum required output capacitance
• L (H) is the value of the inductor
• VDROOP (V) is the output voltage drop ignoring loop bandwidth considerations
•ΔIOUTSTEP (A) is the load step change
• RESR (Ω) is the output capacitor ESR
• VIN (V) is the input voltage
• VOUT (V) is the set regulator output voltage (4)
Both the tolerance and voltage coefficient of the capacitor should be examined when designing for a specific
output ripple or transient droop target.
INPUT CAPACITOR SELECTION
Good quality input capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the
switch current during the on-time. In general it is recommended to use a ceramic capacitor for the input as they
provide both a low impedance and small footprint. One important note is to use a good dielectric for the ceramic
capacitor such as X5R or X7R. These provide better over temperature performance and also minimize the DC
voltage derating that occurs on Y5V capacitors. The input capacitors CIN1 and CIN2 should be placed as close as
possible to the VIN and GND pins on both sides of the device.
Non-ceramic input capacitors should be selected for RMS current rating and minimum ripple voltage. A good
approximation for the required ripple current rating is given by the relationship:
(5)
As indicated by the RMS ripple current equation, highest requirement for RMS current rating occurs at 50% duty
cycle. For this case, the RMS ripple current rating of the input capacitor should be greater than half the output
current. For best performance, low ESR ceramic capacitors should be placed in parallel with higher capacitance
capacitors to provide the best input filtering for the device.
SETTING THE OUTPUT VOLTAGE (RFB1, RFB2)
The resistors RFB1 and RFB2 are selected to set the output voltage for the device. Table 1 provides suggestions
for RFB1 and RFB2 for common output voltages.
Table 1. Suggested Values for RFB1 and RFB2
RFB1(kΩ) RFB2(kΩ) VOUT
short open 0.8
4.99 10 1.2
8.87 10.2 1.5
12.7 10.2 1.8
21.5 10.2 2.5
31.6 10.2 3.3
52.3 10 5.0
If different output voltages are required, RFB2 should be selected to be between 4.99 kΩto 49.9 kΩand RFB1 can
be calculated using the equation below.
(6)
14 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LM20333
AM
fSW/2
0 dB
FREQUENCY (Hz)
GAIN (dB)
Error Amp Zero, fZ(EA)
Complex Double Pole, fP(MOD)
Optional Error Amp
Pole, fP2(EA)
0 dB
0 dB
AEA + AM
Error Amplifier
Transfer Function Modulator and Output Filter
Transfer Function
Compensated Open
Loop Transfer Function
AEA
Error Amp Pole, fP1(EA)
Complex Double Pole, fP(MOD)
Output Filter Zero, fZ(FIL)
Output Filter Pole, fP(FIL)
fC
Error Amp Pole, fP(EA)
LM20333
www.ti.com
SNVS558D –MAY 2008–REVISED APRIL 2013
LOOP COMPENSATION (RC1, CC1)
The purpose of loop compensation is to meet static and dynamic performance requirements while maintaining
adequate stability. Optimal loop compensation depends on the output capacitor, inductor, load and the device
itself. Table 2 below gives values for the compensation network that will result in a stable system when using a
150 µF, 6.3V POSCAP output capacitor (6TPB150MAZB).
Table 2. Recommended Compensation for
COUT = 150 µF, IOUT = 3A, fSW= 500kHz
VIN VOUT L (µH) RC(kΩ) CC1 (nF)
12 5 6.8 30.9 4.7
12 3.3 5.6 33.2 3.3
12 2.5 4.7 40.2 2.2
12 1.5 3.3 22.1 2.2
12 1.2 2.2 18.2 2.2
12 0.8 1.5 8.45 3.3
5 3.3 2.2 38.3 2.2
5 2.5 3.3 38.3 2.2
5 1.5 2.2 30.1 2.2
5 1.2 2 18.2 2.2
5 0.8 1.5 13 2.2
If the desired solution differs from the table above the loop transfer function should be analyzed to optimize the
loop compensation. The overall loop transfer function is the product of the power stage and the feedback network
transfer functions. For stability purposes, the objective is to have a loop gain slope that is -20dB/decade from a
very low frequency to beyond the crossover frequency. Figure 27 shows the transfer functions for power stage,
feedback/compensation network, and the resulting compensated loop for the LM20333.
Figure 27. LM20333 Loop Compensation
The power stage transfer function is dictated by the modulator, output LC filter, and load; while the feedback
transfer function is set by the feedback resistor ratio, error amp gain and external compensation network.
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LM20333
RC1 =x
CC1
COUT
IOUT
VOUT +
-1
2 x D
fSW x L
COMP
CC1
RC1
CC2
LM20333
(optional)
LM20333
SNVS558D –MAY 2008–REVISED APRIL 2013
www.ti.com
To achieve a -20dB/decade slope, the error amplifier zero, located at fZ(EA), should be positioned to cancel the
output filter pole (fP(FIL)).
Compensation of the LM20333 is achieved by adding an RC network as shown in Figure 28 below.
Figure 28. Compensation Network for LM20333
A good starting value for CC1 for most applications is 2.2 nF. Once the value of CC1 is chosen the value of RC
should be approximated using the equation below to cancel the output filter pole (fP(FIL)) as shown in Figure 27.
(7)
A higher crossover frequency can be obtained, usually at the expense of phase margin, by lowering the value of
CC1 and recalculating the value of RC1. Likewise, increasing CC1 and recalculating RC1 will provide additional
phase margin at a lower crossover frequency. As with any attempt to compensate the LM20333 the stability of
the system should be verified for desired transient droop and settling time.
For low duty cycle operation, when the on time of the switch node is less than 200ns, an additional capacitor
(CC2) should be added from the COMP pin to AGND. The recommended value of this capacitor is 20pF. If low
duty cycle jitter on the switch node is observed, the value of this capacitor can be increased to improve noise
immunity; however, values much larger than 100pF will cause the pole fP2(EA) to move to a lower frequency
degrading loop stability.
BOOT CAPACITOR (CBOOT)
The LM20333 integrates an N-channel buck switch and associated floating high voltage level shift / gate driver.
This gate driver circuit works in conjunction with an internal diode and an external bootstrap capacitor. A 0.1 µF
ceramic capacitor, connected with short traces between the BOOT pin and SW pin, is recommended. During the
off-time of the buck switch, the SW pin voltage is approximately 0V and the bootstrap capacitor is charged from
VCC through the internal bootstrap diode.
SUB-REGULATOR BYPASS CAPACITOR (CVCC)
The capacitor at the VCC pin provides noise filtering for the internal sub-regulator. The recommended value of
CVCC should be no smaller than 0.1 µF and no greater than 1 µF. The capacitor should be a good quality ceramic
X5R or X7R capacitor. In general, a 1 µF ceramic capacitor is recommended for most applications. The VCC
regulator should not be used for other functions since it isn't protected against short circuit.
SETTING THE START UP TIME (CSS)
The addition of a capacitor connected from the SS pin to ground sets the time at which the output voltage will
reach the final regulated value. Larger values for CSS will result in longer start up times. Table 3, shown below
provides a list of soft start capacitors and the corresponding typical start up times.
Table 3. Start Up Times for Different Soft-Start Capacitors
Start Up Time (ms) CSS (nF)
1 none
5 33
10 68
15 100
20 120
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Product Folder Links: LM20333
SS/TRK
VOUT1
R1
R2
EN LM20333
External
Power Supply
VOUT2
RA = - 1
VTO
VIH_EN x RB
EN
VOUT1
RA
RB
LM20333
External
Power Supply
VOUT2
22222
tSS = 0.8V x CSS
ISS
LM20333
www.ti.com
SNVS558D –MAY 2008–REVISED APRIL 2013
If different start up times are needed the equation shown below can be used to calculate the start up time.
(8)
As shown above, the start up time is influenced by the value of the soft-start capacitor CSS and the 4.5 µA soft-
start pin current ISS.
While the soft-start capacitor can be sized to meet many start up requirements, there are limitations to its size.
The soft-start time can never be faster than 1 ms due to the internal default 1 ms start up time. When the device
is enabled there is an approximate time interval of 50 µs when the soft-start capacitor will be discharged just
prior to the soft-start ramp. If the enable pin is rapidly pulsed or the soft-start capacitor is large there may not be
enough time for CSS to completely discharge resulting in start up times less than predicted. To aid in discharging
of soft-start capacitor during long disable periods an external 1MΩresistor from SS/TRK to ground can be used
without greatly affecting the start up time.
USING PRECISION ENABLE AND POWER GOOD
The precision enable (EN) and power good (PGOOD) pins of the LM20333 can be used to address many
sequencing requirements. The turn-on of the LM20333 can be controlled with the precision enable pin by using
two external resistors as shown in Figure 29 .
Figure 29. Sequencing LM20333 with Precision Enable
The value for resistor RBcan be selected by the user to control the current through the divider. Typically this
resistor will be selected to be between 10 kΩand 49.9 kΩ. Once the value for RBis chosen the resistor RAcan
be solved using the equation below to set the desired turn-on voltage.
(9)
When designing for a specific turn-on threshold (VTO) the tolerance on the input supply, enable threshold
(VIH_EN), and external resistors need to be considered to ensure proper turn-on of the device.
The LM20333 features an open drain power good (PGOOD) pin to sequence external supplies or loads and to
provide fault detection. This pin requires an external resistor (RPG) to pull PGOOD high when the output is within
the PGOOD tolerance window. Typical values for this resistor range from 10 kΩto 100 kΩ.
TRACKING AN EXTERNAL SUPPLY
By using a properly chosen resistor divider network connected to the SS/TRK pin, as shown in Figure 30, the
output of the LM20333 can be configured to track an external voltage source to obtain a simultaneous or
ratiometric start up.
Figure 30. Tracking an External Supply
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LM20333
VOUT1
VOUT2
VEN
VOLTAGE
TIME
VOLTAGE
TIME
SIMULTANEOUS START UP
RATIOMETRIC START UP
=1R
VOUT1
VOUT2
VEN
OUT12OUT Vx8.0<V
( ) x
-1
=1R 2R
V1OUT
2R
x
-1
V2OUT
V8.0 ¸
¹
·
¨
©
§
¸
¨
LM20333
SNVS558D –MAY 2008–REVISED APRIL 2013
www.ti.com
Since the soft-start charging current ISS is always present on the SS/TRK pin, the size of R2 should be less than
10 kΩto minimize the errors in the tracking output. Once a value for R2 is selected the value for R1 can be
calculated using appropriate equation in Figure 31, to give the desired start up. Figure 30 shows two common
start up sequences; the top waveform shows a simultaneous start up while the waveform at the bottom illustrates
a ratiometric start up.
Figure 31. Common Start Up Sequences
A simultaneous start up is preferred when powering most FPGAs, DSPs, or other microprocessors. In these
systems the higher voltage, VOUT1, usually powers the I/O, and the lower voltage, VOUT2, powers the core. A
simultaneous start up provides a more robust power up for these applications since it avoids turning on any
parasitic conduction paths that may exist between the core and the I/O pins of the processor.
The second most common power on behavior is known as a ratiometric start up. This start up is preferred in
applications where both supplies need to be at the final value at the same time.
Similar to the soft-start function, the fastest start up possible is 1ms regardless of the rise time of the tracking
voltage. When using the track feature the final voltage seen by the SS/TRACK pin should exceed 1V to provide
sufficient overdrive and transient immunity.
BENEFIT OF AN EXTERNAL SCHOTTKY
The LM20333 employs a 40ns dead time between conduction of the control and synchronous FETs in order to
avoid the situation where both FETs simultaneously conduct, causing shoot-through current. During the dead
time, the body diode of the synchronous FET acts as a free-wheeling diode and conducts the inductor current.
The structure of the high voltage DMOS is optimized for high breakdown voltage, but this typically leads to
inefficient body diode conduction due to the reverse recovery charge. The loss associated with the reverse
recovery of the body diode of the synchronous FET manifests itself as a loss proportional to load current and
switching frequency. The additional efficiency loss becomes apparent at higher input voltages and switching
frequencies. One simple solution is to use a small 1A external Schottky diode between SW and GND as shown
in Figure 38. The external Schottky diode effectively conducts all inductor current during the dead time,
minimizing the current passing through the synchronous MOSFET body diode and eliminating reverse recovery
losses.
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LM20333
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SNVS558D –MAY 2008–REVISED APRIL 2013
The external Schottky conducts currents for a very small portion of the switching cycle, therefore the average
current is low. An external Schottky rated for 1A will improve efficiency by several percent in some applications.
A Schottky rated at a higher current will not significantly improve efficiency and may be worse due to the
increased reverse capacitance. The forward voltage of the synchronous MOSFET body diode is approximately
700 mV, therefore an external Schottky with a forward voltage less than or equal to 700 mV should be selected
to ensure the majority of the dead time current is carried by the Schottky.
THERMAL CONSIDERATIONS
The thermal characteristics of the LM20333 are specified using the parameter θJA, which relates the junction
temperature to the ambient temperature. Although the value of θJA is dependant on many variables, it still can be
used to approximate the operating junction temperature of the device.
To obtain an estimate of the device junction temperature, one may use the following relationship:
TJ= PDxθJA + TA(10)
and PD= PIN x (1 - Efficiency) - 1.1 x (IOUT)2x DCR
where
• TJis the junction temperature in °C
• PIN is the input power in Watts (PIN = VIN x IIN)
•θJA is the junction to ambient thermal resistance for the LM20333
• TAis the ambient temperature in °C
• IOUT is the output load current
• DCR is the inductor series resistance (11)
It is important to always keep the operating junction temperature (TJ) below 125°C for reliable operation. If the
junction temperature exceeds 170°C the device will cycle in and out of thermal shutdown. If thermal shutdown
occurs it is a sign of inadequate heatsinking or excessive power dissipation in the device.
Figure 32,Figure 33,Figure 34 and Figure 35 can be used as a guide to avoid exceeding the maximum junction
temperature of 125°C provided an external 1A Schottky diode, such as Central Semiconductor's CMMSH1-40-
NST, is used to improve reverse recovery losses.
Figure 32. Safe Thermal Operating Areas (IOUT = 3A, fSW = 350kHz)
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 19
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www.ti.com
Figure 33. Safe Thermal Operating Areas (IOUT = 3A, fSW = 500kHz)
Figure 34. Safe Thermal Operating Areas (IOUT = 3A, fSW = 750kHz)
Figure 35. Safe Thermal Operating Areas (IOUT = 2.5A, fSW = 500kHz)
The dashed lines in the figures above show an approximation of the minimum and maximum duty cycle
limitations; while, the solid lines define areas of operation for a given ambient temperature. This data for the
figure was derived assuming the device is operating at 3A continuous output current on a 4 layer PCB with a
copper area greater than 4 square inches exhibiting a thermal characteristic less than 27 °C/W. Since the
internal losses are dominated by the FETs a slight reduction in current by 500mA allows for much larger regions
of operation, as shown in Figure 35.
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Product Folder Links: LM20333
LM20333
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SNVS558D –MAY 2008–REVISED APRIL 2013
Figure 36, shown below, provides a better approximation of the θJA for a given PCB copper area. The PCB used
in this test consisted of 4 layers: 1oz. copper was used for the internal layers while the external layers were
plated to 2oz. copper weight. To provide an optimal thermal connection, a 5 x 4 array of 12 mil thermal vias
located under the thermal pad was used to connect the 4 layers.
Figure 36. Thermal Resistance vs PCB Area (4 Layer Board)
PCB LAYOUT CONSIDERATIONS
PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance
of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss
in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability.
Good layout can be implemented by following a few simple design rules.
1. Minimize area of switched current loops. In a buck regulator there are two loops where currents are switched
at high slew rates. The first loop starts from the input capacitor, to the regulator VIN pin, to the regulator SW pin,
to the inductor then out to the output capacitor and load. The second loop starts from the output capacitor
ground, to the regulator GND pins, to the inductor and then out to the load (see Figure 37). To minimize both
loop areas the input capacitor should be placed as close as possible to the VIN pin. Grounding for both the input
and output capacitor should consist of a small localized top side plane that connects to GND and the exposed
pad (EP). The inductor should be placed as close as possible to the SW pin and output capacitor.
2. Minimize the copper area of the switch node. Since the LM20333 has the SW pins on opposite sides of the
package it is recommended that the SW pins should be connected with a trace that runs around the package.
The inductor should be placed at an equal distance from the SW pins using 100 mil wide traces to minimize
capacitive and conductive losses.
3. Have a single point ground for all device grounds located under the EP. The ground connections for the
compensation, feedback, and soft-start components should be connected together then routed to the EP pin of
the device. The AGND pin should connect to GND under the EP. If not properly handled poor grounding can
result in degraded load regulation or erratic switching behavior.
4. Minimize trace length to the FB pin. Since the feedback node can be high impedance the trace from the output
resistor divider to FB pin should be as short as possible. This is most important when high value resistors are
used to set the output voltage. The feedback trace should be routed away from the SW pin and inductor to avoid
contaminating the feedback signal with switch noise.
5. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input or
output of the converter and can improve efficiency. Voltage accuracy at the load is important so make sure
feedback voltage sense is made at the load. Doing so will correct for voltage drops at the load and provide the
best output accuracy.
6. Provide adequate device heatsinking. For most 3A designs a four layer board is recommended. Use as many
vias as is possible to connect the EP to the power plane heatsink. For best results use a 5x4 via array with a
minimum via diameter of 12 mils. "Via tenting" with the solder mask may be necessary to prevent wicking of the
solder paste applied to the EP. See the THERMAL CONSIDERATIONS section to ensure enough copper
heatsinking area is used to keep the junction temperature below 125°C.
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: LM20333
VIN
VOUT
C1
C9
R4
R3
R1
C8
C2
C4
D1
R2
C5
C3
LM20333
FB
AGND
SW
GND
GND
GND
U1
14
11
12
210
9
SW 13
SW 8
SW 7
BOOT 17
VIN 16
VIN 15
VIN 6
VIN 5
EP
COMP
4SS
1SYNC
20
PGOOD
3
EN
19
VCC
18
C7
L1
C6
VOUT
PGOOD
ENABLE
SYNC
GND
GND C2, C3 should be placed at VIN
pins 5,6 and 15,16 respectively.
(OPTIONAL
for improved
Efficiency)
PVIN SW
PGND
LVOUT
LM20333
CIN COUT
LOOP1 LOOP2
LM20333
SNVS558D –MAY 2008–REVISED APRIL 2013
www.ti.com
Figure 37. Schematic of LM20333 Highlighting Layout Sensitive Nodes
Figure 38. Typical Application Schematic
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LM20333
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SNVS558D –MAY 2008–REVISED APRIL 2013
Table 4. Bill of Materials (VIN = 12V, VOUT = 3.3V, IOUT = 3A, fSW = 500kHz)
ID Qty Part Number Size Description Vendor
U1 1 LM20333MH HTSSOP IC, Switching Regulator TI
C1 1 C3225X5R1E226M 1210 22µF, X5R, 25V, 20% TDK
C2, C3 2 GRM21BR61E475KA12L 0805 4.7µF, X5R, 25V, 10% MuRata
C5, C6 1 C1608X7R1H104K 0603 100nF, X7R, 50V, 10% TDK
C4 1 C1608X5R1A105K 0603 1µF, X7R, 10V, 10% TDK
C7 1 C1608C0G1H100J 0603 10pF, C0G, 50V, 5% TDK
C8 1 C1608C0G1H152J 0603 1.5nF, C0G, 50V, 5% TDK
C9 1 6TPB150MAZB B 150µF,POSCAP, 6.3V, 20% Sanyo
D1 1 CMMSH1-40-NST SOD123 Vr = 40V, Io = 1A, Vf = 0.55V Central
Semiconductor
L1 1 IHLP4040DZER5R6M01 IHLP4040 5.6µH, 0.018 Ohms, 16A Vishay
R1, R4 2 CRCW06031002F 0603 10kΩ, 1% Vishay
R2 1 CRCW06031502F 0603 15kΩ, 1% Vishay
R3 1 CRCW06033092F 0603 30.9kΩ, 1% Vishay
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Links: LM20333
LM20333
SNVS558D –MAY 2008–REVISED APRIL 2013
www.ti.com
REVISION HISTORY
Changes from Revision C (April 2013) to Revision D Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 23
24 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LM20333
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Top-Side Markings
(4)
Samples
LM20333MH/NOPB ACTIVE HTSSOP PWP 20 73 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 20333MH
LM20333MHE/NOPB ACTIVE HTSSOP PWP 20 250 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 20333MH
LM20333MHX/NOPB ACTIVE HTSSOP PWP 20 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 20333MH
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM20333MHE/NOPB HTSSOP PWP 20 250 178.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
LM20333MHX/NOPB HTSSOP PWP 20 2500 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 29-May-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM20333MHE/NOPB HTSSOP PWP 20 250 210.0 185.0 35.0
LM20333MHX/NOPB HTSSOP PWP 20 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 29-May-2013
Pack Materials-Page 2
MECHANICAL DATA
PWP0020A
www.ti.com
MXA20A (Rev C)
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