PD-9.625A IRLRO24 IRLU024 Voss = 60V International Rectifier HEXFET Power MOSFET Dynamic dv/dt Rating Surface Mount (IRLR024) D Straight Lead (IRLU024) Available in Tape & Reel Logic-Level Gate Drive Rosvon) Specified at Vas=4V & 5V @ Fast Switching Rps(on) = 0.1 0Q 5 Ip=14A Description / Third Generation HEXFETs from International Rectifier provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The D-Pak is designed for surface mounting using vapor phase, infrared, or wave soldering techniques. The straight lead version (IRFU series) is for through-hole mounting applications. Power dissipation levels up to 1.5 watts are possible in typical surface mount applications. D-PAK PAK TO-262AA TO-251AA Absolute Maximum Ratings Parameter Max. Units lo@ Tc =25C | Continuous Drain Current, Vas @ 5.0 V 14 Ip @ Tc = 100C | Continuous Drain Current, Vas @ 5.0 V 9.2 A lpm Pulsed Drain Current 56 Pp @ Tc = 25C _| Power Dissipation 42 w Pp @ Ta=25C_ | Power Dissipation (PCB Mount)** 2.5 Linear Derating Factor 0.33 WPC Linear Derating Factor (PCB Mount)** 0.020 Vas Gate-to-Source Voltage +10 Vv Eas Single Pulse Avalanche Energy @ 91 mJ dv/dt Peak Diode Recovery dv/dt @ 4.5 Vins Ts, Tsta Junction and Storage Temperature Range -55 to +150 C Soldering Temperature, for 10 seconds 260 (1.6mm from case) Thermal Resistance Parameter Min. Typ. Max. Units Rasc Junction-to-Case _ 3.0 Rea Junction-to-Ambient (PCB mount)** _ _ 50 C/W Roya Junction-to-Ambient _ _ 110 ** When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to application note #AN-994. 1439IRLRO24, IRLU024 Electrical Characteristics @ Ty = 25C (unless otherwise specified) Parameter Min. | Typ. | Max. | Units Test Conditions Vierypss Drain-to-Source Breakdown Voltage 60 _ _- Vi Vas=0V, Ib= 250uA AVerypss/ATy| Breakdown Voltage Temp. Coefficient _|0.068| | VC | Reference to 25C, Ip= 1mA . . Denies, = _ 0.10 Vas=5.0V, Ip=8.4A Rosvon) Static Drain-to-Source On-} nee = To14 Q Ves=4.0V. n=7.0A Vesith) Gate Threshold Voltage 1.0 _ 2.0 Vi Vos=Ves, Ip= 250A Ots Forward Transconductance 7.3 _ _ S| Vps=25V, lp=8.4A @ Ipss Drain-to-Source Leakage Current = 25 pA Vos=60V, Vase OV _ 250 Vps=48V, Vas=0V, Ty=125C less Gate-to-Source Forward Leakage _ | 100 nA Vas=10V Gate-to-Source Reverse Leakage _ _| -100 Vas=-10V Qg Total Gate Charge _ _ 18 Ip=17A Qgs Gate-to-Source Charge _ | 45 | nC | Vpg=48v Qga Gate-to-Drain ("Miller') Charge 12 Vas=5.0V See Fig. 6 and 13 tavon) Turn-On Delay Time _ 1 _ Vpp=30V t Rise Time _ 110 _ ns !o=17A tarotty Turn-Off Delay Time = 23 _ Re=9.00 tt Fall Time _ 41 RAp=1.7Q See Figure 10 @ Lp internal Drain Inductance _ 45 _ samo. ead ) =) nH | from package fis Ls Internal Source Inductance |/75} and center of die contact s Ciss Input Capacitance _ 870 _ Ves=0V Coss Output Capacitance | 360 | | PF | Vos=25V Crss Reverse Transfer Capacitance _ 53 _ f=1.0MHz See Figure 5 Source-Drain Ratings and Characteristics Parameter Min. | Typ. | Max. | Units Test Conditions Is Continuous Source Current | | 44 MOSFET symbol (Body Diode) A showing the Ism Pulsed Source Current _ _ 56 integral reverse @ (Body Diode) p-n junction diode. 8 Vsp Diode Forward Voltage _ _ 1.5 V1 Ty=25C, t9=14A, Vas=0V ter Reverse Recovery Time _ 130 | 260 ns | Ty=25C, Ir=17A On Reverse Recovery Charge | 0.75 | 15 | pC |di/dt=100A/us fon Forward Turn-On Time Intrinsic turn-on time is neglegibie (turn-on is dominated by Ls+Lp) Notes: Repetitive rating; pulse width limited by Ispsi7A, di/dts140A/us, Vop<V(BrR)pss, max. junction temperature (See Figure 11) Tys150C Vpp=25V, starting Ty=25C, L=541nH @ Pulse width < 300 ps; duty cycle <2%. Re=250, las=14A (See Figure 12) 1440IRLRO24, IRLU024 Ip, Drain Current (Amps) Ip, Drain Current (Amps) DB E tot <x c 2 5 O g oO a iil - 20Us PULSE WIDTH 20us PULSE WIDTH To = 25C 4 To = 150C soot 10 10! * to-t to! Vps, Drain-to-Source Voltage (voits) Vps, Drain-to-Source Voltage (volts) Fig 1. Typical Output Characteristics, Fig 2. Typical Output Characteristics, To=25C Tco=150C nm 8 Cc g Q 10! Q 2 em = og 8 gt 5 = w BE 0 556 10 21. eS i a = 0. 2 o Vos = 25v tot 20us PULSE WIDTH ec 00 Ves = 5V 2.0 2.5 3.0 3.5 4.0 45 5.0 -60 -40 -20 0 20 40 60 B80 100 120 140 160 Vas, Gate-to-Source Voltage (volts) Ty, Junction Temperature (C) Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance Vs. Temperature 1441IRLRO24, IRLU024 1400 GS = OV, f = IMHz Ciss = Cgs + Cgg, Cyg SHOR c TSS Cgq 1000 Capacitance (pF) Ves, Gate-to-Source Voltage (volts) SEE FIGURE 13 100 rot 4 8 12 16 20 24 Vps; Drain-to-Source Voltage (volts) Qe, Total Gate Charge (nC) Fig 5. Typical Capacitance Vs. Fig 6. Typical Gate Charge Vs. Drain-to-Source Voltage Gate-to-Source Voltage OPERATION IN THIS AREA LIMITED g DS (ON) E x Qo ~~ a c <x 3 5 5 5 8 & 2 S a > n o a z a To725C 1=150C Ves = OV INGLE PULSE 0.4 0.8 1.2 1.6 2.0 1 2 5 10 2 5 192 2 5 103 Vsp, Source-to-Drain Voltage (volts) Vps, Drain-to-Source Voltage (volts) Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area Forward Voltage 1442[p, Drain Current (Amps) IRLRO24, IRLU024 Ro Vos >- WA D.U.T. K ye \Es5.0v Pulse Width < 1ps Duty Factor < 0.1% L Fig 10a. Switching Time Test Circuit Vos 90% } f. } [ | | | | | | | 10% 4 | 7 25 50 75 100 425 450 Ves To, Case Temperature (C) tdfon) ty tyor tf Fig 9. Maximum Drain Current Vs. Fig 10b. Switching Time Waveforms Case Temperature 10 B Q SINGLE PULSE Pod (THERMAL RESPONSE) 1 ete tall Thermal Response (Zguc) NOTES: 4. DUTY FACTOR, D=t1i/t2 2. PEAK Ty=Ppm x Zthjc + To 10 105 10-4 1093 10? 0.4 1 10 ty, Rectangular Pulse Duration (seconds) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case 1443IRLRO24, IRLU024 Vary tp to obtain Vps > ired | required las D.UL. A > | AS B 0.019 2 iit} . - . Fig 12a. Unclamped Inductive Test Circuit 2 a 2 Do c t aH < ul pp = 25V Vops- / / 25 50 78 100 125 150 / Starting Ty, Junction Temperature(C) lag V Fig 12c. Maximum Avalanche Energy Fig 12b. Unclamped Inductive Waveforms Vs. Drain Current Current Regulator r ~~ Same Type as DUT. | | 50KQ lev .2uF | 3yF Q > | soVP. Ho eo A A SSSSSSSEEEES] | Qas Qep + Ves Ve ama tL. Charge >+ Ie * Ip Current Sampling Resistors Fig 13a. Basic Gate Charge Waveform Fig 13b. Gate Charge Test Circuit Appendix A: Figure 14, Peak Diode Recovery dv/dt Test Circuit See page 1505 Appendix B: Package Outline Mechanical Drawing See pages 1512, 1513 Appendix C: Part Marking Information See page 1518 Intemational Appendix D: Tape & Reel Information See page 1523 R ti fier 1444