LMV7235, LMV7239
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SNOS532M –SEPTEMBER 2000–REVISED FEBRUARY 2013
APPLICATION INFORMATION
The LMV7235/LMV7239/LMV7239Q are single supply comparators with 75ns of propagation delay and only
65µA of supply current.
The LMV7235/LMV7239/LMV7239Q are rail-to-rail input and output. The typical input common mode voltage
range of −0.2V below the ground to 0.2V above the supply. The LMV7235/LMV7239/LMV7239Q use a
complimentary PNP and NPN input stage in which the PNP stage senses common mode voltage near V−and the
NPN stage senses common mode voltage near V+. If either of the input signals falls below the negative common
mode limit, the parasitic PN junction formed by the substrate and the base of the PNP will turn on resulting in an
increase of input bias current.
If one of the input goes above the positive common mode limit, the output will still maintain the correct logic level
as long as the other input stays within the common mode range. However, the propagation delay will increase.
When both inputs are outside the common mode voltage range, current saturation occurs in the input stage, and
the output becomes unpredictable.
The propagation delay does not increase significantly with large differential input voltages. However, large
differential voltages greater than the supply voltage should be avoided to prevent damage to the input stage.
The LMV7239 has a push-pull output. When the output switches, there is a direct path between VCC and ground,
causing high output sinking or sourcing current during the transition. After the transition, the output current
decreases and the supply current settles back to about 65µA at 5V, thus conserving power consumption.
The LMV7235 has an open drain that requires a pull-up resistor to a positive supply voltage for the output to
switch properly. When the internal output transistor is off, the output voltage will be pulled up to the external
positive voltage.
CIRCUIT LAYOUT AND BYPASSING
The LMV7235/LMV7239/LMV7239Q require high speed layout. Follow these layout guidelines:
1. Use printed circuit board with a good, unbroken low-inductance ground plane.
2. Place a decoupling capacitor (0.1µF ceramic surface mount capacitor) as close as possible to VCC pin.
3. On the inputs and the output, keep lead lengths as short as possible to avoid unwanted parasitic feedback
around the comparator. Keep inputs away from output.
4. Solder the device directly to the printed circuit board rather than using a socket.
5. For slow moving input signals, take care to prevent parasitic feedback. A small capacitor (1000pF or less)
placed between the inputs can help eliminate oscillations in the transition region. This capacitor causes some
degradation to tPD when the source impedance is low.
6. The topside ground plane runs between the output and inputs.
7. Ground trace from the ground pin runs under the device up to the bypass capacitor, shielding the inputs from
the outputs.
COMPARATOR WITH HYSTERESIS
The basic comparator configuration may oscillate or produce a noisy output if the applied differential input
voltage is near the comparator's offset voltage. This usually happens when the input signal is moving very slowly
across the comparator's switching threshold. This problem can be prevented by the addition of hysteresis or
positive feedback.
INVERTING COMPARATOR WITH HYSTERESIS
The inverting comparator with hysteresis requires a three resistor network that is referenced to the supply voltage
VCC of the comparator, as shown in Figure 18. When VIN at the inverting input is less than VA, the voltage at the
non-inverting node of the comparator (VIN < VA), the output voltage is high (for simplicity assume VOswitches as
high as VCC). The three network resistors can be represented as R1||R3 in series with R2. The lower input trip
voltage VA1 is defined as:
VA1 = VCCR2 / [(R1||R3) + R2] (1)
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