Product Folder Order Now Technical Documents Support & Community Tools & Software TPS63024 TPS630241, TPS630242 SLVSCK8A - NOVEMBER 2014 - REVISED DECEMBER 2014 TPS63024x High Current, High Efficiency Single Inductor Buck-Boost Converter 1 Features 3 Description * The TPS63024 are high efficiency, low quiescent current buck-boost converters suitable for application where the input voltage is higher or lower than the output. Output currents can go as high as 1.5A in boost mode and as high as 3A in buck mode. The maximum average current in the switches is limited to a typical value of 3A. The TPS63024 regulates the output voltage over the complete input voltage range by automatically switching between buck or boost mode depending on the input voltage ensuring a seamless transition between modes. The buck-boost converter is based on a fixed frequency, pulse-widthmodulation (PWM) controller using synchronous rectification to obtain highest efficiency. At low load currents, the converter enters Power Save Mode to maintain high efficiency over the complete load current range. There is a PFM/PWM pin that allows the user to choose between automatic PFM/PWM mode operation and forced PWM operation. During PWM mode a fixed-frequency of typically 2.5MHz is used. The output voltage is programmable using an external resistor divider, or is fixed internally on the chip. The converter can be disabled to minimize battery drain. During shutdown, the load is disconnected from the battery. The device is packaged in a 20-pin WCSP package measuring 1.766 mm x 2.086mm. 1 * * * * * * * * * * * * * Real Buck or Boost operation with automatic and seamless transition between Buck and Boost operation 2.3V to 5.5V input voltage range 1.5A Continuous Output Current : VIN 2.5V, VOUT= 3.3V Adjustable and fixed output voltage Efficiency up to 95% in Buck or Boost mode and up to 97% when VIN=VOUT 2.5MHz typical switching frequency 35A operating quiescent current Integrated Soft -Start Power Save Mode True shutdown function Output capacitor discharge function Over-Temperature Protection and Over current Protection Wide capacitance selection Small 1.766 mm x 2.086mm, 20-pin WCSP 2 Applications * * * * * Cellular Phones, Smart Phones Tablets PC PC and Smart Phone accessories Point of load regulation Battery Powered Applications Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TPS63024 TPS630241 DSBGA (20) 1.766 mm x 2.086 mm TPS630242 (1) For all available packages, see the orderable addendum at the end of the datasheet. Device Comparison PART NUMBER VOUT TPS63024 Adjustable TPS630241 2.9 V TPS630242 3.3 V Typical Application Efficiency vs Output Current L1 1H 100 TPS63024 C1 L1 95 VIN VOUT EN FB 10F C2 2X22F VINA PFM/ PWM GND PGND 90 VOUT 3.3 V up to 1.5A L2 85 Efficiency (%) VIN 2.5 V to 5.5 V 80 75 70 65 60 VIN = 2.8V, V OUT = 3.3V VIN = 3.3V, V OUT = 3.3V VIN = 3.6V, V OUT = 3.3V VIN = 4.2V, V OUT = 3.3V 55 50 TPS630242 45 100 1m 10m 100m 1 1.5 Output Current (A) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS63024 TPS630241, TPS630242 SLVSCK8A - NOVEMBER 2014 - REVISED DECEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 6.1 6.2 6.3 6.4 6.5 6.6 6.7 3 4 4 4 5 6 7 Absolute Maximum Ratings ...................................... ESD Ratings ............................................................ Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Timing Requirements ................................................ Typical Characteristics .............................................. Detailed Description .............................................. 8 7.1 Overview ................................................................... 8 7.2 Functional Block Diagram ......................................... 8 7.3 Feature Description................................................... 9 7.4 Device Functional Modes........................................ 11 8 Application and Implementation ........................ 14 8.1 Application Information............................................ 14 8.2 Typical Application .................................................. 14 9 Power Supply Recommendations...................... 21 10 Layout................................................................... 21 10.1 Layout Guidelines ................................................. 21 10.2 Layout Example .................................................... 21 11 Device and Documentation Support ................. 22 11.1 11.2 11.3 11.4 11.5 11.6 Device Support .................................................... Documentation Support ....................................... Related Links ........................................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 22 22 22 22 22 22 12 Mechanical, Packaging, and Orderable Information ........................................................... 22 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (November 2014) to Revision A * 2 Page Added Specifications, Detailed Description section, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section; and, changed status to Production Data. .................................................................................................................................................................... 4 Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: TPS630241 TPS630242 TPS63024 TPS630241, TPS630242 www.ti.com SLVSCK8A - NOVEMBER 2014 - REVISED DECEMBER 2014 5 Pin Configuration and Functions WCSP 20-Pin YFF (TOP VIEW) E1 D1 C1 B1 A1 E2 D2 C2 B2 A2 E3 D3 C3 B3 A3 E4 D4 C4 B4 A4 Pin Functions PIN NAME NO. VOUT I/O A1,A2,A3 PWR FB A4 IN L2 B1,B2,B3 PWR PFM/PWM PGND GND L1 DESCRIPTION Buck-boost converter output Voltage feedback of adjustable version, must be connected to VOUT for fixed output voltage versions Connection for Inductor B4 IN C1,C2,C3 PWR set low for PFM mode, set high for forced PWM mode. It must not be left floating Power Ground C4 PWR Analog Ground D1,D2,D3 PWR Connection for Inductor EN D4 IN VIN E1,E2,E3 PWR Supply voltage for power stage E4 PWR Supply voltage for control stage. VINA Enable input. Set high to enable and low to disable. It must not be left floating. 6 Specifications 6.1 Absolute Maximum Ratings (1) over junction temperature range (unless otherwise noted) VALUE Voltage (2) MIN MAX UNIT VIN, L1, EN, VINA, PFM/PWM -0.3 7 V VOUT, FB -0.3 4 V L2 (3) -0.3 4 V L2 (4) -0.3 5.5 V 2.7 A (5) Input current Continuos average current into L1 TJ Operating junction temperature -40 125 Tstg Storage temperature range -65 150 (1) (2) (3) (4) (5) C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground pin. DC voltage rating. AC transient voltage rating. Maximum continuos average input current 3.5A, under those condition do not exceed 105C for more than 25% operating time. Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: TPS630241 TPS630242 3 TPS63024 TPS630241, TPS630242 SLVSCK8A - NOVEMBER 2014 - REVISED DECEMBER 2014 www.ti.com 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) 700 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions (1) MAX UNIT VIN Input Voltage Range MIN 2.3 5.5 V VOUT Output Voltage 2.5 3.6 V 1.3 H (2) TYP L Inductance Cout Output Capacitance (3) 16 TA Operating ambient temperature -40 85 C TJ Operating virtual junction temperature -40 125 C (1) (2) (3) 0.5 1 F Refer to the Application Information section for further information Effective inductance value at operating condition. The nominal value given matches a typical inductor to be chosen to meet the inductance required. Due to the dc bias effect of ceramic capacitors, the effective capacitance is lower then the nominal value when a voltage is applied. This is why the capacitance is specified to allow the selection of the nominal capacitor required with the dc bias effect for this type of capacitor. The nominal value given matches a typical capacitor to be chosen to meet the minimum capacitance required. 6.4 Thermal Information TPS63024x THERMAL METRIC (1) YFF UNIT 20 PINS RJA Junction-to-ambient thermal resistance 53.8 RJC(top) Junction-to-case (top) thermal resistance 0.5 RJB Junction-to-board thermal resistance 10.1 JT Junction-to-top characterization parameter 1.4 JB Junction-to-board characterization parameter 9.8 RJC(bot) Junction-to-case (bottom) thermal resistance N/A (1) 4 C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: TPS630241 TPS630242 TPS63024 TPS630241, TPS630242 www.ti.com SLVSCK8A - NOVEMBER 2014 - REVISED DECEMBER 2014 6.5 Electrical Characteristics VIN=2.3V to 5.5V, TJ= -40C to 125C, typical values are at TA=25C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VIN Input voltage range VIN_Min Minimum input voltage to turn on into full load 2.3 VIN A 12 A 0.1 2 A 1.7 2 35 Isd Shutdown current EN=low, TJ=-40C to 85C Under voltage lockout threshold VIN falling 1.6 Under voltage lockout hysteresis Thermal shutdown 70 IOUT=0mA, EN=VIN=3.6V, VOUT=3.3V TJ=-40C to 85C, not switching Quiescent current UVLO V 2.7 IQ VOUT 5.5 RLOAD= 2.2 Temperature rising V V 70 mV 140 C LOGIC SIGNALS EN, PFM/PWM VIH High level input voltage VIN=2.3V to 5.5V VIL Low level input voltage VIN=2.3V to 5.5V Ilkg Input leakage current PFM/PWM, EN=GND or VIN 1.2 V 0.01 0.4 V 0.2 A 3.6 V OUTPUT VOUT Output Voltage range VFB Feedback regulation voltage TPS63024 VFB Feedback voltage accuracy PWM mode, TPS63024 -1% VFB Feedback voltage accuracy PFM mode, TPS63024 -1% VOUT Output voltage accuracy PWM mode, TPS630241 VOUT Output voltage accuracy (1) PFM mode, TPS630241 VOUT Output voltage accuracy PWM mode, TPS630242 VOUT Output voltage accuracy (1) PFM mode, TPS630242 IPWM/PFM Output current to enter PFM mode VIN =3V; VOUT = 3.3V IFB Feedback input bias current VFB = 0.8V 10 High side FET on-resistance VIN=3.0V, VOUT=3.3V 35 m Low side FET on-resistance VIN=3.0V, VOUT=3.3V 50 m High side FET on-resistance VIN=3.0V, VOUT=3.3V 25 m Low side FET on-resistance VIN=3.0V, VOUT=3.3V 50 m RDS_Buck(on) RDS_Boost(on) IIN Average input current limit fs Switching Frequency RON_DISC Discharge ON-Resistance (1) (2) 2.5 (1) (2) 0.8 V 1% 1.3% +3% 2.871 2.9 2.929 V 2.871 2.938 2.987 V 3.267 3.3 3.333 V 3.267 3.343 3.399 350 VIN=3.0V, VOUT=3.3V TJ= 25C to 125C 2.12 3 100 3.54 2.5 EN=low V mA nA A MHz 120 Line regulation VIN=2.8V to 5.5V, IOUT=1.5A 7.4 mV/ V Load regulation VIN=3.6V,IOUT=0A to 1.5A 2.5 mV/ A Conditions: L=1 H, COUT= 2 x 22F. For variation of this parameter with Input voltage and temperature see Figure 8. To calculate minimum output current in a specific working point see Figure 8 and Equation 1 trough Equation 4. Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: TPS630241 TPS630242 5 TPS63024 TPS630241, TPS630242 SLVSCK8A - NOVEMBER 2014 - REVISED DECEMBER 2014 www.ti.com 6.6 Timing Requirements VIN= 2.3V to 5.5V, TJ= -40C to 125C, typical values are at TA= 25C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OUTPUT tSS td 6 Softstart time Start up delay EN=low to high, Buck mode VIN=3.6V, VOUT=3.3V, IOUT=1.5A 450 s EN=low to high, Boost mode VIN=2.8V, VOUT=3.3V, IOUT=1.5A 700 s Time from when EN=high to when device starts switching 100 s Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: TPS630241 TPS630242 TPS63024 TPS630241, TPS630242 www.ti.com SLVSCK8A - NOVEMBER 2014 - REVISED DECEMBER 2014 6.7 Typical Characteristics . . 0.016 60 TA = -40 C TA = 25 C TA = 85 C Quiescent Current (mA) Resistance (mS) 50 40 30 20 10 0 2.5 TA = -40 C TA = 25 C TA = 85 C 2.8 3.1 3.4 0.012 0.008 TPS630242 3.7 4 4.3 Input Voltage (V) 4.6 4.9 5.2 5.5 Figure 1. High Side FET On-Resistance vs VIN 0.004 2.5 2.8 3.1 3.4 3.7 4 4.3 4.6 Input Voltage (V) 4.9 5.2 5.5 Figure 2. Quiescent Current vs Input Voltage Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: TPS630241 TPS630242 7 TPS63024 TPS630241, TPS630242 SLVSCK8A - NOVEMBER 2014 - REVISED DECEMBER 2014 www.ti.com 7 Detailed Description 7.1 Overview The TPS63024x use 4 internal N-channel MOSFETs to maintain synchronous power conversion at all possible operating conditions. This enables the device to keep high efficiency over the complete input voltage and output power range. To regulate the output voltage at all possible input voltage conditions, the device automatically switches from buck operation to boost operation and back as required by the configuration. It always uses one active switch, one rectifying switch, one switch is held on, and one switch held off. Therefore, it operates as a buck converter when the input voltage is higher than the output voltage, and as a boost converter when the input voltage is lower than the output voltage. There is no mode of operation in which all 4 switches are switching at the same time. Keeping one switch on and one switch off eliminates their switching losses. The RMS current through the switches and the inductor is kept at a minimum, to minimize switching and conduction losses. Controlling the switches this way allows the converter to always keep higher efficiency. The device provides a seamless transition from buck to boost or from boost to buck operation. 7.2 Functional Block Diagram L1 L2 VIN VOUT Current Sensor VIN VOUT EN PGND _ + Oscillator PFM/PWM Device Control EN PGND Gate Control Modulator VINA PGND _ FB + + - VREF Temperature Control GND PGND PGND Figure 3. Functional Block Diagram (Adjustable Output Voltage) 8 Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: TPS630241 TPS630242 TPS63024 TPS630241, TPS630242 www.ti.com SLVSCK8A - NOVEMBER 2014 - REVISED DECEMBER 2014 Functional Block Diagram (continued) L1 L2 VIN VOUT Current Sensor EN PGND VIN VOUT + Oscillator PFM/PWM Device Control EN PGND FB _ Modulator VINA PGND Gate Control _ + + - VREF Temperature Control GND PGND PGND Figure 4. Functional Block Diagram (Fixed Output Voltage) 7.3 Feature Description 7.3.1 Undervoltage Lockout (UVLO) To avoid mis-operation of the device at low input voltages, an undervoltage lockout is included. UVLO shuts down the device at input voltages lower than typically 1.7V with a 70 mV hysteresis. 7.3.2 Output Discharge Function When the device is disabled by pulling enable low and the supply voltage is still applied, the internal transistor use to discharge the output capacitor is turned on, and the output capacitor is discharged until UVLO is reached. This means, if there is no supply voltage applied the output discharge function is also disabled. The transistor which is responsible of the discharge function, when turned on, operates like an equivalent 120 resistor, ensuring typically less than 10ms discharge time for 20uF output capacitance and a 3.3V output. 7.3.3 Thermal Shutdown The device goes into thermal shutdown once the junction temperature exceeds typically 140C. Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: TPS630241 TPS630242 9 TPS63024 TPS630241, TPS630242 SLVSCK8A - NOVEMBER 2014 - REVISED DECEMBER 2014 www.ti.com Feature Description (continued) 7.3.4 Softstart To minimize inrush current and output voltage overshoot during start up, the device has a Softstart. At turn on, the input current raises monotonically until the output voltage reaches regulation. During Softstart, the input current follows the current ramp charging the internal Softstart capacitor. The device smoothly ramps up the input current bringing the output voltage to its regulated value even if a large capacitor is connected at the output. The Softstart time is measured as the time from when the EN pin is asserted to when the output voltage has reached 90% of its nominal value. There is typically a 100s delay time from when the EN pin is asserted to when the device starts the switching activity. The Softstart time depends on the load current, the input voltage, and the output capacitor. The Softstart time in boost mode is longer then the time in buck mode. The total typical Softstart time is 1ms. The inductor current is able to increase and always assure a soft start unless a real short circuit is applied at the output. 7.3.5 Short Circuit Protection The TPS63024x provides short circuit protection to protect itself and the application. When the output voltage does not increase above 1.2V, the device assumes a short circuit at the output and limits the input current to 3A. 10 Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: TPS630241 TPS630242 TPS63024 TPS630241, TPS630242 www.ti.com SLVSCK8A - NOVEMBER 2014 - REVISED DECEMBER 2014 7.4 Device Functional Modes 7.4.1 Control Loop Description Ramp and Clock Generator 0.8V Figure 5. Average Current Mode Control The controller circuit of the device is based on an average current mode topology. The average inductor current is regulated by a fast current regulator loop which is controlled by a voltage control loop. Figure 5 shows the control loop. The non inverting input of the transconductance amplifier, gmv, is assumed to be constant. The output of gmv defines the average inductor current. The inductor current is reconstructed by measuring the current through the high side buck MOSFET. This current corresponds exactly to the inductor current in boost mode. In buck mode the current is measured during the on time of the same MOSFET. During the off time, the current is reconstructed internally starting from the peak value at the end of the on time cycle. The average current and the feedback from the error amplifier gmv forms the correction signal gmc. This correction signal is compared to the buck and the boost sawtooth ramp giving the PWM signal. Depending on which of the two ramps the gmc output crosses either the Buck or the Boost stage is initiated. When the input voltage is close to the output voltage, one buck cycle is always followed by a boost cycle. In this condition, no more than three cycles in a row of the same mode are allowed. This control method in the buck-boost region ensures a robust control and the highest efficiency. Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: TPS630241 TPS630242 11 TPS63024 TPS630241, TPS630242 SLVSCK8A - NOVEMBER 2014 - REVISED DECEMBER 2014 www.ti.com Device Functional Modes (continued) 7.4.2 Power Save Mode Operation Heavy Load transient step PFM mode at light load current Comparator High 30mV ripple Vo+1.3%*Vo Comparator low Vo PWM mode Absolute Voltage drop with positioning Figure 6. Power Save Mode Operation Depending on the load current, in order to provide the best efficiency over the complete load range, the device works in PWM mode at load currents of approximately 350 mA or higher. At lighter loads, the device switches automatically into Power Save Mode to reduce power consumption and extend battery life. The PFM/PWM pin is used to select between the two different operation modes. To enable Power Save Mode, the PFM/PWM pin must be set low. During Power Save Mode, the part operates with a reduced switching frequency and lowest supply current to maintain high efficiency. The output voltage is monitored with a comparator at every clock cycle by the thresholds comp low and comp high. When the device enters Power Save Mode, the converter stops operating and the output voltage drops. The slope of the output voltage depends on the load and the output capacitance. When the output voltage reaches the comp low threshold, at the next clock cycle the device ramps up the output voltage again, by starting operation. Operation can last for one or several pulses until the comp high threshold is reached. At the next clock cycle, if the load is still lower than about 350mA, the device switches off again and the same operation is repeated. Instead, if at the next clock cycle, the load is above 350mA, the device automatically switches to PWM mode. In order to keep high efficiency in PFM mode, there is only one comparator active to keep the output voltage regulated. The AC ripple in this condition is increased, compared to the PWM mode. The amplitude of this voltage ripple in the worst case scenario is 50mV pk-pk, (typically 30mV pk-pk), with 20F effective output capacitance. In order to avoid a critical voltage drop when switching from 0A to full load, the output voltage in PFM mode is typically 1.3% above the nominal value in PWM mode. This is called Dynamic Voltage Positioning and allows the converter to operate with a small output capacitor and still have a low absolute voltage drop during heavy load transients. Power Save Mode is disabled by setting the PFM/PWM pin high. 12 Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: TPS630241 TPS630242 TPS63024 TPS630241, TPS630242 www.ti.com SLVSCK8A - NOVEMBER 2014 - REVISED DECEMBER 2014 Device Functional Modes (continued) 7.4.3 Current Limit The current limit variation depends on the difference between the input and output voltage. The maximum current limit value is at the highest difference. Given the curves provided in Figure 8, it is possible to calculate the output current reached in boost mode, using Equation 1 and Equation 2 and in buck mode using Equation 3 and Equation 4. V -V IN OUT V OUT Duty Cycle Boost D= Output Current Boost IOUT = 0 x IIN (1-D) Duty Cycle Buck V D = OUT V IN Output Current Buck IOUT = ( 0 x IIN ) / D (1) (2) (3) where * * = Estimated converter efficiency (use the number from the efficiency curves or 0.90 as an assumption) IIN= Minimum average input current (Figure 8) (4) 7.4.4 Supply and Ground The TPS63024x provides two input pins (VIN and VINA) and two ground pins (PGND and GND). The VIN pin supplies the input power, while the VINA pin provides voltage for the control circuits. A similar approach is used for the ground pins. GND and PGND are used to avoid ground shift problems due to the high currents in the switches. The reference for all control functions is the GND pin. The power switches are connected to PGND. Both grounds must be connected on the PCB at only one point, ideally, close to the GND pin. 7.4.5 Device Enable The device starts operation when the EN pin is set high. The device enters shutdown mode when the EN pin is set low. In shutdown mode, the regulator stops switching, all internal control circuitry is switched off, and the load is disconnected from the input. Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: TPS630241 TPS630242 13 TPS63024 TPS630241, TPS630242 SLVSCK8A - NOVEMBER 2014 - REVISED DECEMBER 2014 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The TPS63024x are high efficiency, low quiescent current buck-boost converters suitable for application where the input voltage is higher, lower or equal to the output. Output currents can go as high as 1.5A in boost mode and as high as 3A in buck mode. The maximum average current in the switches is limited to a typical value of 3A. 8.2 Typical Application L1 1H TPS63024 VIN 2.5 V to 5.5 V L1 C1 VOUT 3.3 V up to 1.5A L2 VIN VOUT EN FB R1 VINA PFM/ PWM R2 GND PGND C2 /C3 560k 10F VIN or GND 2X22F 180k Figure 7. 3.3-V Adjustable Version 8.2.1 Design Requirements The design guideline provides a component selection to operate the device within the recommended operating conditions. Table 1 shows the list of components for the Application Characteristic Curves. Table 1. Components for Application Characteristic Curves (1) REFERENCE DESCRIPTION MANUFACTURER TPS63024 Texas Instruments L1 1 H, 8.75A, 13m, SMD XAL4020-102MEB, Coilcraft C1 10 F 6.3V, 0603, X5R ceramic Standard C2,C3 22 F 6.3V, 0603, X5R ceramic Standard R1 560k Standard R2 180k Standard (1) See Third-Party Products Discalimer 14 Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: TPS630241 TPS630242 TPS63024 TPS630241, TPS630242 www.ti.com SLVSCK8A - NOVEMBER 2014 - REVISED DECEMBER 2014 8.2.2 Detailed Design Procedure The first step is the selection of the output filter components. To simplify this process Table 2 outline possible inductor and capacitor value combinations. 8.2.2.1 Output Filter Design Table 2. Matrix of Output Capacitor and Inductor Combinations NOMINAL OUTPUT CAPACITOR VALUE [F] (2) NOMINAL INDUCTOR VALUE [H] (1) 44 47 + (3) + 0.680 1.0 1.5 (1) (2) (3) 66 88 100 + + + + + + + + + Inductor tolerance and current de-rating is anticipated. The effective inductance can vary by 20% and -30%. Capacitance tolerance and bias voltage de-rating is anticipated. The effective capacitance can vary by 20% and -50%. Typical application. Other check mark indicates recommended filter combinations 8.2.2.2 Inductor Selection The inductor selection is affected by several parameter like inductor ripple current, output voltage ripple, transition point into Power Save Mode, and efficiency. See Table 3 for typical inductors. Table 3. List of Recommended Inductors (1) (1) INDUCTOR VALUE COMPONENT SUPPLIER SIZE (LxWxH mm) Isat/DCR 1 H Coilcraft XAL4020-102ME 4 X 4 X 2.10 4.5A/10m 1 H Toko, DFE322512C 3.2 X 2.5 X 1.2 4.7A/34m 1 H TDK, SPM4012 4.4 X 4.1 X 1.2 4.1A/38m 1 H Wuerth, 74438334010 3 X 3 X 1.2 6.6A/42.10m 0.6 H Coilcraft XFL4012-601ME 4 X 4 X 1.2 5A/17.40m 0.68H Wuerth,744383340068 3 X 3 X 1.2 7.7A/36m See Third-Party Products Desclaimer For high efficiencies, the inductor should have a low dc resistance to minimize conduction losses. Especially at high-switching frequencies, the core material has a high impact on efficiency. When using small chip inductors, the efficiency is reduced mainly due to higher inductor core losses. This needs to be considered when selecting the appropriate inductor. The inductor value determines the inductor ripple current. The larger the inductor value, the smaller the inductor ripple current and the lower the conduction losses of the converter. Conversely, larger inductor values cause a slower load transient response. To avoid saturation of the inductor, the peak current for the inductor in steady state operation is calculated using Equation 6. Only the equation which defines the switch current in boost mode is shown, because this provides the highest value of current and represents the critical current value for selecting the right inductor. Duty Cycle Boost IPEAK D= V -V IN OUT V OUT (5) Iout Vin D = + (1 - D) 2 f L where * * * * * D =Duty Cycle in Boost mod = Converter switching frequency (typical 2.5MHz) L = Inductor value = Estimated converter efficiency (use the number from the efficiency curves or 0.90 as an assumption) Note: The calculation must be done for the minimum input voltage which is possible to have in boost mode (6) Calculating the maximum inductor current using the actual operating conditions gives the minimum saturation current of the inductor needed. It's recommended to choose an inductor with a saturation current 20% higher than the value calculated using Equation 6. Possible inductors are listed in Table 3. Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: TPS630241 TPS630242 15 TPS63024 TPS630241, TPS630242 SLVSCK8A - NOVEMBER 2014 - REVISED DECEMBER 2014 www.ti.com 8.2.2.3 Capacitor Selection 8.2.2.3.1 Input Capacitor At least a 10F input capacitor is recommended to improve line transient behavior of the regulator and EMI behavior of the total power supply circuit. An X5R or X7R ceramic capacitor placed as close as possible to the VIN and PGND pins of the IC is recommended. This capacitance can be increased without limit. If the input supply is located more than a few inches from the TPS63024x converter additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic or tantalum capacitor with a value of 47 F is a typical choice. 8.2.2.3.2 Output Capacitor For the output capacitor, use of a small ceramic capacitors placed as close as possible to the VOUT and PGND pins of the IC is recommended. The recommended nominal output capacitance value is 20 F with a variance as outlined in Table 2. There is also no upper limit for the output capacitance value. Larger capacitors causes lower output voltage ripple as well as lower output voltage drop during load transients. 8.2.2.4 Setting The Output Voltage When the adjustable output voltage version TPS63024x is used, the output voltage is set by an external resistor divider. The resistor divider must be connected between VOUT, FB and GND. When the output voltage is regulated properly, the typical value of the voltage at the FB pin is 800mV. The current through the resistive divider should be about 10 times greater than the current into the FB pin. The typical current into the FB pin is 0.1A, and the voltage across the resistor between FB and GND, R2, is typically 800 mV. Based on these two values, the recommended value for R2 should be lower than 180k, in order to set the divider current at 4A or higher. It is recommended to keep the value for this resistor in the range of 180k. From that, the value of the resistor connected between VOUT and FB, R1, depending on the needed output voltage (VOUT), can be calculated using Equation 7: aeV o R1 = R2 x c OUT - 1/ V e FB o (7) 8.2.3 Application Curves 100 TA = - 40 C TA = 25 C TA = 85 C TPS630242 4 3.5 95 90 85 Efficiency (%) Maximum Average Input Current (A) 4.5 3 2.5 2 80 75 70 65 60 1.5 1 0.5 2.3 50 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 TPS630242 45 100 1m 10m 100m 1 1.5 Output Current (A) Input Voltage (V) VOUT = 3.3 V PFM/PWM = Low Figure 8. Minimum Average Input Current vs Input Voltage 16 VIN = 2.8V, V OUT = 3.3V VIN = 3.3V, V OUT = 3.3V VIN = 3.6V, V OUT = 3.3V VIN = 4.2V, V OUT = 3.3V 55 Figure 9. Efficiency vs Output Current Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: TPS630241 TPS630242 TPS63024 TPS630241, TPS630242 www.ti.com SLVSCK8A - NOVEMBER 2014 - REVISED DECEMBER 2014 100 TPS630242 90 80 Efficiency (%) 70 60 50 40 30 VIN = 2.8V, V OUT = 3.3V VIN = 3.3V, V OUT = 3.3V VIN = 3.6V, V OUT = 3.3V VIN = 4.2V, V OUT = 3.3V 20 10 0 100 1m 10m 100m 1 1.5 Output Current (A) PFM/PWM = High Figure 10. Efficiency vs Output Current 100 100 TPS630241 90 90 80 85 70 Efficiency (%) Efficiency (%) 95 80 75 70 65 60 50 45 100 1m 10m 100m 60 50 40 30 VIN = 2.8V, V OUT = 2.9V VIN = 2.9V, V OUT = 2.9V VIN = 3.6V, V OUT = 2.9V VIN = 4.2V, V OUT = 2.9V 55 TPS630241 VIN = 2.8V, V OUT = 2.9V VIN = 2.9V, V OUT = 2.9V VIN = 3.6V, V OUT = 2.9V VIN = 4.2V, V OUT = 2.9V 20 10 0 100 1 1.5 1m 10m 100m 11.5 Output Current (A) PFM/PWM = High Output Current (A) PFM/PWM = Low Figure 12. Efficiency vs Output Current Figure 11. Efficiency vs Output Current 100 100 90 95 Efficiency (%) Efficiency (%) 80 90 85 80 IOUT = 10mA IOUT = 200mA IOUT = 1A IOUT = 1.5A 75 TPS630242 70 2.3 2.6 2.9 3.2 3.5 3.8 4.1 4.4 Input Voltage (V) PFM/PWM = Low 4.7 5 5.3 5.5 70 60 50 IOUT = 10mA IOUT = 200mA IOUT = 1A IOUT = 1.5A 40 30 20 2.3 2.6 2.9 3.5 3.8 4.1 4.4 Input Voltage (V) PFM/PWM = High VOUT = 3.3 V Figure 13. Efficiency vs Input Voltage 3.2 TPS630242 4.7 5 5.3 5.5 VOUT = 3.3 V Figure 14. Efficiency vs Input Voltage Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: TPS630241 TPS630242 17 TPS63024 TPS630241, TPS630242 SLVSCK8A - NOVEMBER 2014 - REVISED DECEMBER 2014 www.ti.com 100 100 90 95 Efficiency (%) Efficiency (%) 80 90 85 80 IOUT = 10mA IOUT = 200mA IOUT = 1A IOUT = 1.5A 75 70 2.3 2.6 2.9 3.2 3.5 70 60 50 IOUT = 10mA IOUT = 200mA IOUT = 1A IOUT = 1.5A 40 30 TPS630241 3.8 4.1 4.4 Input Voltage (V) PFM/PWM = Low 4.7 5 20 2.3 5.3 5.5 2.6 VOUT = 2.9 V 3.3050 Output Voltage (V) Output Voltage (V) 3.3000 3.3400 3.3300 3.3200 3.3100 VIN = 3.6V 3.2800 VIN = 4.2V 1 3.8 4.1 4.4 4.7 5 5.3 5.5 VOUT = 2.9 V VIN = 2.8V VIN = 3.3V 3.3500 3.2900 3.5 Figure 16. Efficiency vs Input Voltage 3.3600 3.3000 3.2 Input Voltage (V) PFM/PWM = High Figure 15. Efficiency vs Input Voltage VIN = 2.8V VIN = 3.3V 2.9 TPS630241 VIN = 3.6V VIN = 4.2V 3.2950 3.2900 3.2850 TPS630242 10 TPS630242 100 1k 1.5k 3.2800 1 10 Output Current (mA) 100 1k 1.5k Output Current (mA) PFM/PWM = Low PFM/PWM = High Figure 17. Output Voltage vs Output Current Figure 18. Output Voltage vs Output Current TPS630242 TPS630242 L2 L2 L1 L1 VOUT_Ripple 50mV/div Time 4s/div Time 4s/div VIN = 3.3 V IOUT = 290 mA Figure 19. Output Voltage Ripple in Buck-Boost Mode and PFM to PWM Transition 18 VOUT_Ripple 50mV/div VIN = 2.8 V IOUT = 16 mA Figure 20. Output Voltage Ripple in Boost Mode and PFM Operation Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: TPS630241 TPS630242 TPS63024 TPS630241, TPS630242 www.ti.com SLVSCK8A - NOVEMBER 2014 - REVISED DECEMBER 2014 TPS630242 TPS630242 L1 L2 L2 L1 VOUT_Ripple 50mV/div VOUT_Ripple 50mV/div Time 4s/div Time 1s/div VIN = 4.2 V IOUT = 16 mA Figure 21. Output Voltage Ripple in Buck Mode and PFM Operation TPS630242 VIN = 2.5 V IOUT = 1 A Figure 22. Switching Waveforms in Boost Mode and PWM Operation TPS630242 L1 L2 L2 L1 VOUT_Ripple 10mV/div VOUT_Ripple 50mV/div Time 1s/div Time 1s/div VIN = 4.5 V IOUT = 1 A Figure 23. Switching Waveforms in Buck Mode and PWM Operation VIN = 3.3 V IOUT = 1 A Figure 24. Switching Waveforms in Buck-Boost Mode and PWM Operation TPS630242 TPS630242 Output Current 1A/div Output Current 1A/div Output Voltage 200mV/div, AC Output Voltage 200mV/div, AC Time 200s/div Time 200s/div VIN = 2.8 V IOUT = 0 A to 1.5 A Figure 25. Load Transient Response Boost Mode VIN = 4.2 V IOUT = 0 A to 1.5 A Figure 26. Load Transient Response Buck Mode Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: TPS630241 TPS630242 19 TPS63024 TPS630241, TPS630242 SLVSCK8A - NOVEMBER 2014 - REVISED DECEMBER 2014 www.ti.com TPS630242 TPS630242 Enable 2V/div, DC Input Voltage 200mV/div, Offset 3V Output Voltage 1V/div, DC Output Voltage 50mV/div Inductor Current 500mA/div Time 100s/div Time 100s/div VIN = from 3.5 V to 3.6 V IOUT = 1.5 A VIN = 2.5 V Figure 27. Line Transient Response IOUT = 0 A Figure 28. Start Up After Enable TPS630242 Enable 2V/div, DC Output Voltage 1V/div, DC Inductor Current 500mA/div Time 100s/div VIN = 4.5 V IOUT = 0 A Figure 29. Start Up After Enable 20 Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: TPS630241 TPS630242 TPS63024 TPS630241, TPS630242 www.ti.com SLVSCK8A - NOVEMBER 2014 - REVISED DECEMBER 2014 9 Power Supply Recommendations The TPS63024x device family has no special requirements for its input power supply. The input power supply's output current needs to be rated according to the supply voltage, output voltage and output current of the TPS63024x. 10 Layout 10.1 Layout Guidelines The PCB layout is an important step to maintain the high performance of the TPS63024x devices. * Place input and output capacitors as close as possible to the IC. Traces need to be kept short. Routing wide and direct traces to the input and output capacitor results in low trace resistance and low parasitic inductance. * Use a common-power GND. * The sense trace connected to FB is signal trace. Keep these traces away from L1 and L2 nodes. 10.2 Layout Example L GND Cin Cout Cout Cin GND Vout Vin R1 R2 Figure 30. TPS63024x Layout Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: TPS630241 TPS630242 21 TPS63024 TPS630241, TPS630242 SLVSCK8A - NOVEMBER 2014 - REVISED DECEMBER 2014 www.ti.com 11 Device and Documentation Support 11.1 Device Support 11.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 11.2 Documentation Support 11.2.1 Related Documentation For related documentation see the following: TPS63024EVM-553 User's Guide, TPS63024 High Current, High Efficiency Single Inductor Buck-Boost Converter, SLVUA24 11.3 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 4. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY TPS63024 Click here Click here Click here Click here Click here TPS630241 Click here Click here Click here Click here Click here TPS630242 Click here Click here Click here Click here Click here 11.4 Trademarks All trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.6 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 22 Submit Documentation Feedback Copyright (c) 2014, Texas Instruments Incorporated Product Folder Links: TPS630241 TPS630242 PACKAGE OPTION ADDENDUM www.ti.com 11-Dec-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) TPS630241YFFR ACTIVE DSBGA YFF 20 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 TPS 630241 TPS630241YFFT ACTIVE DSBGA YFF 20 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 TPS 630241 TPS630242YFFR ACTIVE DSBGA YFF 20 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 TPS 630242 TPS630242YFFT ACTIVE DSBGA YFF 20 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 TPS 630242 TPS63024YFFR ACTIVE DSBGA YFF 20 3000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 TPS 63024 TPS63024YFFT ACTIVE DSBGA YFF 20 250 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 TPS 63024 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Dec-2014 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 17-Jun-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TPS630241YFFR DSBGA YFF 20 3000 180.0 8.4 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1.89 2.2 0.69 4.0 8.0 Q1 TPS630241YFFT DSBGA YFF 20 250 180.0 8.4 1.89 2.2 0.69 4.0 8.0 Q1 TPS630242YFFR DSBGA YFF 20 3000 180.0 8.4 1.89 2.2 0.69 4.0 8.0 Q1 TPS630242YFFT DSBGA YFF 20 250 180.0 8.4 1.89 2.2 0.69 4.0 8.0 Q1 TPS63024YFFR DSBGA YFF 20 3000 180.0 8.4 1.89 2.2 0.69 4.0 8.0 Q1 TPS63024YFFT DSBGA YFF 20 250 180.0 8.4 1.89 2.2 0.69 4.0 8.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-Jun-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS630241YFFR DSBGA YFF 20 3000 182.0 182.0 20.0 TPS630241YFFT DSBGA YFF 20 250 182.0 182.0 20.0 TPS630242YFFR DSBGA YFF 20 3000 182.0 182.0 20.0 TPS630242YFFT DSBGA YFF 20 250 182.0 182.0 20.0 TPS63024YFFR DSBGA YFF 20 3000 182.0 182.0 20.0 TPS63024YFFT DSBGA YFF 20 250 182.0 182.0 20.0 Pack Materials-Page 2 D: Max = 2.116 mm, Min =2.056 mm E: Max = 1.796 mm, Min =1.736 mm IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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