© 2005 Fairchild Semiconductor Corporation DS005336 www.fairchildsemi.com
September 1983
Revised May 2005
MM74HC374 3-STATE Octal D-Type Flip-Flop
MM74HC374
3-STATE Octal D-Type Flip-Flop
General Descript ion
The MM74 HC374 high speed Octal D-Type Flip-Flops uti-
lize advanced silicon-gate CMOS technology. They pos-
sess the hi gh noise immun ity an d low power consu mption
of standard CMOS integrated circuits, as well as the ability
to drive 15 LS-TTL loads. Due to the large output drive
capability and t he 3-STATE featu re, th ese de vices are ide-
ally suited for interfacing with bus lines in a bus organized
system.
These devices are positive edge triggered flip-flops. Data
at the D inputs, meeting the setup and hold time require-
ments, are transferred to the Q outputs on positive going
transitions of the CLOCK (CK) input. When a high logic
level is applied to the OUTPUT CONTROL (OC) input, all
outputs go to a high impedance state, regardless of what
signals are present at th e other inputs and the state of the
storage elements.
The 74H C logic f amily is sp eed, functio n, and pi nout com -
patible with the standard 74LS logic family. All inputs are
protect ed from damage due to static di scharge by in ternal
diode clamps to VCC and ground.
Features
■Typical propagation delay: 20 ns
■Wide operat i ng voltage range: 2–6V
■Low input current: 1
P
A maximum
■Low quiescent current: 80
P
A maximum
■Compatible with bus-oriented systems
■Output drive capability: 15 LS-TTL loads
Ordering Code:
Devices also available in Ta pe and Reel. Specif y by append ing the suffix let t er “X” to th e ordering co de.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP a nd TSSOP
Top View
Truth Table
H
HIGH Level
L
LOW Le vel
X
Don't Care
n
Transition f rom LOW-to-HIGH
Z
High Impedance State
Q0
The level of the output before steady state input conditions were
established
Order Number Package Number Package Description
MM74HC374WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
MM74HC374SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC374MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC374N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Output Clock Data Output
Control
L
n
HH
L
n
LL
LLXQ
0
HXXZ
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MM74HC374
Absolute Maximum Ratings(Note 1)
(Note 2) Recommended Operating
Conditions
Note 1: Absolute Maximum Ratings a re those va lues beyon d which d am-
age to the device may occur.
Note 2: Unless ot herwise sp ec ified all vo ltages ar e r ef erenced to ground .
Note 3: Power Dis sipation temp erature de rating — plastic “N” package:
12 mW/
q
C from 65
q
C to 85
q
C.
DC Electrical Characteristi cs
Note 4: For a power supply of 5V
r
10% t he wor st case ou tput vo ltages (V OH, and VOL) occur for HC a t 4.5V. Thus t he 4.5V values s hould be used w hen
designing with this supply. Worst case VIH and VIL occur at VCC
5.5V a nd 4.5V res pectively. (T he VIH value at 5. 5V is 3.85V.) The wo rs t c as e leakage cur-
rent (IIN, ICC, and IOZ) occur for CMOS at the hi gher voltage and so the 6.0V valu es s hould be u s ed.
Supply Voltage (VCC)
0.5 to
7.0V
DC Input Voltage (VIN)
1.5 to VCC
1.5V
DC Output Voltage (VOUT)
0.5 to VCC
0.5V
Clamp Diode Current (IIK, IOK)
r
20 mA
DC Output Current, per pin (IOUT)
r
35 mA
DC VCC or GND Current, per pin (ICC)
r
70 mA
Storage Temperature Range (TSTG)
65
q
C to
150
q
C
Power Dissipation (PD)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (TL)
(Soldering 10 seconds) 260
q
C
Min Max Units
Supply Voltage (VCC)26V
DC Input or Output Voltage
(VIN, VOUT)0V
CC V
Operati ng Temperatu re R ang e (TA)
40
85
q
C
Input Rise or Fall Times
(tr, tf) VCC
2.0V 1000 ns
VCC
4.5V 500 ns
VCC
6.0V 400 ns
Symbol Parameter Conditions VCC TA
25
q
CT
A
40 to 85
q
CT
A
55 to 125
q
CUnits
Typ Guar ant eed Lim i ts
VIH Minimum HIGH Level 2.0V 1.5 1.5 1.5 V
Input V olt age 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
VIL Maximum LOW Level 2.0V 0.5 0.5 0.5 V
Input V olt age 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
VOH Minimum HIGH Level VIN
VIH or VIL
Output Voltage |IOUT|
d
20
P
A 2.0V 2.0 1.9 1.9 1.9 V
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
VIN
VIH or VIL
|IOUT|
d
6.0 mA 4.5V 4.2 3.98 3.84 3.7 V
|IOUT|
d
7.8 mA 6.0V 5.7 5.48 5.34 5.2 V
VOL Maximum LOW Level VIN
VIH or VIL
Output Voltage |IOUT|
d
20
P
A 2.0V 0 0.1 0.1 0.1 V
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
VIN
VIH or VIL
|IOUT|
d
6.0 mA 4.5V 0.2 0.26 0.33 0.4 V
|IOUT|
d
7.8 mA 6.0V 0.2 0.26 0.33 0.4 V
IIN Maximum Input VIN
VCC or GND 6.0V
r
0.1
r
1.0
r
1.0
P
A
Current
IOZ Maximum 3-STATE VIN
VIH, OC
VIH 6.0V
r
0.5
r
5
r
10
P
A
Output Leakage VOUT
VCC or GND
Current
ICC Maximum Quiescent VIN
VCC or GND 6.0V 8.0 80 160
P
A
Supply Current IOUT
0
P
A
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MM74HC374
AC Electrical Characteristics
VCC
5V, TA
25
q
C, tr
tf
6 ns
Symbol Parameter Conditions Typ Guaranteed Units
Limit
fMAX Maximum Operating 50 35 MHz
Frequency
tPHL, tPLH Maximum Propagation CL
45 pF 20 32 ns
Delay Clock to Q
tPZH, tPZL Maximum Output Enable RL
k
:
Time CL
45 pF 19 28 ns
tPHZ, tPLZ Maximum Output Disable RL
k
:
17 25 ns
Time CL
5 pF
tSMinimum Setup Time 20 ns
tHMinimum Hold Time 5ns
tWMinimum Pulse Width 9 16 ns
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MM74HC374
AC Electrical Characteristi cs
VCC
2.0
6.0V, CL
50 pF, tr
tf
6 ns (unless otherwise specified)
Note 5: CPD determines the no load dynam ic pow er cons um ption, PD
CPD VCC2f
ICC VCC, and the no load dynamic current consumption,
IS
CPD VCC f
ICC.
Symbol Parameter Conditions VCC TA
25
q
CT
A
40 to 85
q
CT
A
55 to 125
q
CUnits
Typ Guar ant eed Lim i ts
fMAX Maximum Operating CL
50 pF 2.0V 6 5 4 MHz
Frequency 4.5V 30 24 20 MHz
6.0V 35 28 23 MHz
tPHL, tPLH Maximum Propagation CL
50 pF 2.0V 68 180 225 270 ns
Delay, Clock to Q CL
150 pF 2.0V 110 230 288 345 ns
CL
50 pF 4.5V 22 36 45 48 ns
CL
150 pF 4.5V 30 46 57 69 ns
CL
50 pF 6.0V 20 31 39 46 ns
CL
150 pF 6.0V 28 40 50 60 ns
tPZH, tPZL Maximum Output RL
1 k
:
Enable Time CL
50 pF 2.0V 50 150 189 225 ns
CL
150 pF 2.0V 80 200 250 300 ns
CL
50 pF 4.5V 21 30 37 45 ns
CL
150 pF 4.5V 30 40 50 60 ns
CL
50 pF 6.0V 19 26 31 39 ns
CL
150 pF 6.0V 26 35 44 53 ns
tPHZ, tPLZ Maximum Output RL
1 k
:
2.0V 50 150 189 225 ns
Disable Time CL
50 pF 4.5V 21 30 37 45 ns
6.0V 19 26 31 39 ns
tSMinimum Setup Time 2.0V 50 60 75 ns
4.5V 9 13 15 ns
6.0V 9 11 13 ns
tHMinimum Hold Time 2.0V 5 30 5 ns
4.5V 5 5 5 ns
6.0V 5 5 5 ns
tWMinimum Pulse Width 2.0V 30 80 100 120 ns
4.5V 9 16 20 24 ns
6.0V 8 14 18 20 ns
tTHL, tTLH Maximum Output Rise CL
50 pF 2.0V 25 60 75 90 ns
and Fall Time 4.5V 7 12 15 18 ns
6.0V 6 10 13 15 ns
tr, tfMaximum Input Rise and 2.0V 1000 1000 1000 ns
Fall Time, Clock 4.5V 500 500 500 ns
6.0V 400 400 400 ns
CPD Power Dissipation (per flip-flop)
Capacitance (Note 5) OC
VCC 30 pF
OC
GND 50 pF
CIN Maximum Input Capacitance 5 10 10 10 pF
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MM74HC374
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
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MM74HC374
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ T YPE II, 5.3mm Wide
Package Number M20D
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MM74HC374
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lea d Th in S hri nk Sm all Ou tlin e Pack age (TSSOP ), JED EC MO-1 53, 4.4mm Wide
Package Number MTC20
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MM74HC374 3-STATE Octal D-Type Flip-Flop
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N20A
Fairchild does no t assume any responsibility for use of any circui try described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life suppor t de vices o r systems a re devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical compon ent in any componen t of a life support
device or system whose failure to perform can be rea-
sonabl y ex pect ed to cause the fa ilu re of the li fe su pp ort
device or system, or to affect its safety or effectiveness.
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