DATA SH EET
Product specification
Supersedes data of 2001 Dec 05 2003 May 14
DISCRETE SEMICONDUCTORS
BLF1049
Base station LDMOS transistor
d
book, halfpage
M3D379
2003 May 14 2
Philips Semiconductors Product specification
Base station LDMOS transistor BLF1049
FEATURES
•Typical performance at a supply voltage of 27 V:
– 1-tone CW; IDQ = 1000 mA
– Output power = 125 W
– Gain = 16.5 dB
– Efficiency = 54%
– EDGE output power = 45 W (AV)
– ACPR400 = −64 dBc at 400 kHz
(EDGE; IDQ = 750 mA)
– EVM = 2% rms (AV)
(EDGE; IDQ = 750 mA)
•Easy power control
•Excellent ruggedness
•High power gain
•Excellent thermal stability
•Designed for broadband operation (800 to 1000 MHz)
•Internally matched for ease of use.
APPLICATIONS
•RF power amplifier for GSM, EDGE and CDMA base
stations and multicarrier applications in the
800 to 1000 MHz frequency range.
DESCRIPTION
125 W LDMOS power transistor for base station
applications at frequencies from 800 MHz to 1000 MHz.
PINNING - SOT502A
PIN DESCRIPTION
1 drain
2 gate
3 source; connected to flange
handbook, halfpage
Top view
MBK394
1
23
Fig.1 Simplified outline SOT502A .
QUICK REFERENCE DATA
Typical RF performance at Th=25°C in a common source test circuit.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
MODE OF OPERATION f
(MHz) PL
(W) Gp
(dB) ηD
(%) d3
(dBc) ACPR 400
(dBc)
EVM
% rms
(AV)
2-tone 920 125 (PEP) 15.5 37 −32 −−
1-tone CW 125 16.5 54 −−−
GSM EDGE 45 (AV) 15 32 −−64 2
SYMBOL PARAMETER MIN. MAX. UNIT
VDS drain-source voltage −75 V
VGS gate-source voltage −±15 V
Tstg storage temperature −65 150 °C
Tjjunction temperature −200 °C
2003 May 14 3
Philips Semiconductors Product specification
Base station LDMOS transistor BLF1049
THERMAL CHARACTERISTICS
Notes
1. Thermal resistance is determined under RF operating conditions.
2. Depending on mounting condition in application.
CHARACTERISTICS
Tj=25°C unless otherwise specified.
APPLICATION INFORMATION
RF performance in a common source class-AB circuit; VDS =27V; T
h=25°C; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS VALUE UNIT
Rth j-c thermal resistance from junction to case Th=25°C, PL= 35 W (AV), note 1 0.42 K/W
Rth j-h thermal resistance from junction to heatsink Th=25°C, PL= 35 W (AV), note 2 0.62 K/W
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V(BR)DSS drain-source breakdown voltage VGS = 0; ID= 3 mA 75 −−V
V
GSth gate-source threshold voltage VDS = 10 V; ID= 300 mA 4 −5V
I
DSS drain-source leakage current VGS = 0; VDS =36V −−3µA
I
DSX on-state drain current VGS =V
GSth +9V; V
DS =10V 45 −−A
I
GSS gate leakage current VGS =±20 V; VDS =0 −−1µA
g
fs forward transconductance VDS = 10 V; ID=10A −9−S
R
DSon drain-source on-state resistance VGS =9V; I
D=10A −60 −mΩ
Mode of operation: 2-tone CW, 100 kHz spacing; IDQ = 1130 mA; f = 890 MHz
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Gpgain power PL= 125 W (PEP) 14.6 15.5 −dB
ηDdrain efficiency 33 37 −%
IRL input return loss −−12 −6dB
d
3third order inter modulation
distortion −−32 −25 dBc
Mode of operation: GSM EDGE; IDQ = 750 mA; f = 920 MHz
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Gpgain power PL=45W(AV) −15 −dB
ηDdrain efficiency −32 −%
ACPR 400 adjacent channel power ratio −−64 −dBc
EVM (AV) EVM rms average signal distortion −2−%
EVM peak EVM rms peak signal distortion −2.2 −%
Mode of operation: 1-tone CW; IDQ = 1000 mA; f = 920 MHz
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Gpgain power PL=P
L 1 dB = 125 W −16.5 −dB
ηDdrain efficiency −54 −%
2003 May 14 4
Philips Semiconductors Product specification
Base station LDMOS transistor BLF1049
handbook, halfpage
010
G
p
(dB)
50
16
15
13
12
14
20 30 40
MLE061
ηD
(%)
ηD
Gp
40
30
10
0
20
PL (AV)(W)
Fig.2 GSM EDGE power gain and efficiency as
functions of load power; typical values.
VDS = 27 V; f = 920 MHz; IDQ = 750 mA; Th≤25 °C.
handbook, halfpage
010 P
L
(AV)(W)
50
−62
−64
−68
−70
−66
20 30 40
MLE062
EVMrms
(AV)
(%)
ACPR
400
(dBc)
2
1.5
0.5
0
1
EVM
ACPR400
Fig.3 GSM EDGE ACPR400 and EVM as
functions of average load power; typical
values.
VDS = 27 V; f = 920 MHz; IDQ = 750 mA; Th≤25 °C.
handbook, halfpage
0 50 100 150
MLE063
PL (AV) (W)
18
17
16
15
Gp
(dB) ηD
(%)
Gp
ηD
60
20
40
0
Fig.4 1-tone CW power gain and efficiency as
functions of load power; typical values.
VDS = 27 V; f = 920 MHz; IDQ = 1000 mA;
handbook, halfpage
0 50 100 150
50
0
40
30
20
10
17
14
16.5
16
15.5
14.5
15
MLE064
gain
(dB)
PL (PEP) (W)
η
(%) (4)
η(1,2,3)
(5)
(6)
Fig.5 2-tone power gain and efficiency as
functions of load power at different
temperatures.
VDS = 27 V; IDQ = 1.1 A; f1= 920.0 MHz; f2= 920.1 MHz.
(1) ηat Th=−40 °C.
(2) ηat Th=20°C.
(3) ηat Th=80°C.
(4) gain at Th=−40 °C.
(5) gain at Th=20°C.
(6) gain at Th=80°C.
2003 May 14 5
Philips Semiconductors Product specification
Base station LDMOS transistor BLF1049
handbook, halfpage
0 50 100 150
−20
−30
−50
−60
−40
MLE065
(3)
(2)
(1)
PL (PEP) (W)
d3
(dBc)
Fig.6 Third order intermodulation distortion as a
function of load power at different
temperatures.
(1) Th=−40 °C.
(2) Th=20°C. (3) Th=80°C.
VDS = 27 V; IDQ = 1.1 A; f1= 920.0 MHz; f2= 920.1 MHz.
handbook, halfpage
0 50 100 150
−30
−40
−60
−70
−50
MLE066
(1)
(3)
(2)
PL (PEP) (W)
d5
(dBc)
Fig.7 Fifth order intermodulation distortion as a
function of load power at different
temperatures.
(1) Th=−40 °C.
(2) Th=20°C. (3) Th=80°C.
VDS =27V;I
DQ = 1.1 A; f1= 920.0 MHz; f2= 920.1 MHz.
handbook, halfpage
0
−40
−50
−60
−70 50 100 150
MLE067
(1)
(2)
(3)
PL (PEP) (W)
d7
(dBc)
Fig.8 Seventh order intermodulation distortion as
a function of load power at different
temperatures.
(1) Th=−40 °C.
(2) Th=20°C. (3) Th=80°C.
VDS = 27 V; IDQ = 1.1 A; f1= 920.0 MHz;
handbook, halfpage
0 50 100 150
20
15
5
0
10
40
30
10
0
20
MLE068
gain
(dB)
PL (PEP) (W)
ηD
(%)
(2)
(3)
(4)
(1)
Fig.9 Powergainanddrainefficiencyasfunctions
of peak envelope load power;
typical values.
VDS = 27 V; f1= 920.0 MHz; f2= 920.1 MHz.
(1) IDQ =1A.
(2) IDQ = 1.45 A. (3) IDQ =1A.
(4) IDQ = 1.45 A.
2003 May 14 6
Philips Semiconductors Product specification
Base station LDMOS transistor BLF1049
handbook, halfpage
0 50 100 150
0
−20
−60
−80
−40
MLE069
dim
(dBc)
PL (PEP) (W)
(6)
(1) (5)
(2)
(3)
(4)
Fig.10 Intermodulation distortion as a function of
peak envelope load power; typical values.
VDS = 27 V; f1= 920.0 MHz; f2= 920.1 MHz.
(1) d3; IDQ =1A.
(2) d5; IDQ =1A. (3) d7; IDQ =1A.
(4) d3; IDQ = 1.3 A. (5) d5; IDQ = 1.3 A.
(6) d7; IDQ = 1.3 A.
handbook, halfpage
0.85
2
1
0
1.5
0.5
−0.5
−10.9 0.95 1
MLE070
Zi
(Ω)
f (GHz)
ri
xi
Fig.11 Input impedance as a function of frequency
(series components); typical values.
Class-AB operation; VDS = 27 V; IDQ = 1125 mA; PL=35W.
Values comprised for different parameters.
handbook, halfpage
0.85
2
1
0
−1
1.5
0.5
−0.5
0.9 0.95 1
MLE071
ZL
(Ω)
f (GHz)
RL
XL
Fig.12 Input impedance as a function of frequency
(series components); typical values.
Class-AB operation; VDS = 27 V; IDQ = 1125 mA; PL=35W.
Values comprised for different parameters.
handbook, halfpage
MGS998
ZL
drain
gate
ZIN
Fig.13 Definition of transistor impedance.
2003 May 14 7
Philips Semiconductors Product specification
Base station LDMOS transistor BLF1049
handbook, full pagewidth
MDB168
Vbias
RF in
C2
C1
R1
L5
L1 L2
L3
L4 L6
L7
L9
L8
L12
L11 L14
L10
L13
L15 L16
C3 C6
C5
C8
C14
C18
C15
C16
C12
C11
C13
C10
C9
C17
C7
Q1
Q2
C4
Vsupply
RF out
Fig.14 Test circuit for 860 to 900 MHz.
2003 May 14 8
Philips Semiconductors Product specification
Base station LDMOS transistor BLF1049
handbook, full pagewidth
PHILIPS
Output Rev C
PHILIPS
Input Rev C
BLF1049
PHILIPS
Output Rev C
PHILIPS
Input Rev C
MLE073
C2
Q1
C3
R1
C4
Vbias in
Vd
in
C6C6
L5
C11
C13
C18
C12
C14
C15
C16
C17
C16
C17
C9
C10
C7
C8
C5
C1L1 L2 L6 L7
L7 L8
L9
L10
L12
L13
L11
L16
L15
L14
L3
L4 L14
60 60
4040
Fig.15 Component layout for 860 to 900 MHz test circuit.
Dimensions in mm.
The components are situated on one side of the copper-clad Rogers 6006 printed-circuit board (εr= 6.15); thickness = 25 mm.
The other side is unetched and serves as a ground plane.
2003 May 14 9
Philips Semiconductors Product specification
Base station LDMOS transistor BLF1049
List of components (see Figs 14 and 15)
Notes
1. American Technical Ceramics type 100A or capacitor of same quality.
2. The striplines are on a double copper-clad Rogers 6006 printed-circuit board (εr= 6.15); thickness = 0.64 mm.
COMPONENT DESCRIPTION VALUE DIMENSIONS
C1, C6, C13, C14, C15,
C16, C17 multilayer ceramic chip capacitor; note 1 68 pF
C2 multilayer ceramic chip capacitor; note 1 330 nF
C3 multilayer ceramic chip capacitor; note 1 100 nF
C4, C9, C10, C11, C12 tantalum capacitor 10 µF
C5, C18 air trimmer capacitor 5 pF
C7, C8 multilayer ceramic chip capacitor 8.2 pF
R1 potentiometer 1 kΩ
Q1 7808 voltage regulator
Q2 BLF1049 LDMOS transistor
L1 stripline; note 2 5.22 ×0.92 mm
L2 stripline; note 2 6.47 ×0.92 mm
L3 stripline; note 2 5.38 ×4.8 mm
L4 stripline; note 2 2.4 ×0.92 mm
L5 ferroxcube
L6 stripline; note 2 9.73 ×0.92 mm
L7 stripline; note 2 1.82 ×9.3 mm
L8 stripline; note 2 8.15 ×17.9 mm
L9 stripline; note 2 44 ×0.92 mm
L10 stripline; note 2 18.45 ×28.3 mm
L11 stripline; note 2 9.95 ×5.38 mm
L12, L13 stripline; note 2 37.6 ×3.35 mm
L14 stripline; note 2 2.36 ×0.92 mm
L15, L16 stripline; note 2 4.22 ×0.92 mm
2003 May 14 10
Philips Semiconductors Product specification
Base station LDMOS transistor BLF1049
PACKAGE OUTLINE
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT502A 99-12-28
03-01-10
0 5 10 mm
scale
Flanged LDMOST ceramic package; 2 mounting holes; 2 leads SOT502A
p
L
AF
b
D
U2
H
Q
c
1
3
2
D1
E
A
C
q
U1
C
B
E1
M M
w2
UNIT A
mm
Db
12.83
12.57 0.15
0.08 20.02
19.61 9.53
9.25 19.94
18.92 9.91
9.65
4.72
3.43
cU2
0.25 0.5127.94
qw
2
w
1
F
1.14
0.89
U1
34.16
33.91
L
5.33
4.32
p
3.38
3.12
Q
1.70
1.45
EE
1
9.50
9.30
inches 0.505
0.495 0.006
0.003 0.788
0.772
D1
19.96
19.66
0.786
0.774 0.375
0.364 0.785
0.745 0.390
0.380
0.186
0.135 0.01 0.021.100
0.045
0.035 1.345
1.335
0.210
0.170 0.133
0.123 0.067
0.057
0.374
0.366
H
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
w1AB
M M M
2003 May 14 11
Philips Semiconductors Product specification
Base station LDMOS transistor BLF1049
DATA SHEET STATUS
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
LEVEL DATA SHEET
STATUS(1) PRODUCT
STATUS(2)(3) DEFINITION
I Objective data Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II Preliminary data Qualification This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III Product data Production This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
DEFINITIONS
Short-form specification The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
attheseorat anyotherconditionsabovethose giveninthe
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Application information Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentationorwarrantythatsuchapplicationswill be
suitable for the specified use without further testing or
modification.
DISCLAIMERS
Life support applications These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductorscustomersusingorselling theseproducts
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
© Koninklijke Philips Electronics N.V. 2003 SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
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Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
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Printed in The Netherlands 613524/03/pp12 Date of release: 2003 May 14 Document order number: 9397 750 11123
