SPICE Device Model Si5504DC Vishay Siliconix Complementary 20-V (D-S) MOSFET CHARACTERISTICS * N- and P-Channel Vertical DMOS * Macro Model (Subcircuit Model) * Level 3 MOS * Apply for both Linear and Switching Application * Applicable over the -55 to 125C Temperature Range * Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n- and p-channel vertical DMOS. The model subcircuit schematic is extracted and optimized over the -55 to 125C temperature ranges under the pulsed 0-to-5V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 71547 07-Oct-99 www.vishay.com 1 SPICE Device Model Si5504DC Vishay Siliconix SPECIFICATIONS (TJ = 25C UNLESS OTHERWISE NOTED) Parameter Symbol Test Conditions Typical Unit Static Gate Threshold Voltage VGS(th) a On-State Drain Current ID(on) a Drain-Source On-State Resistance rDS(on) Forward Transconductancea gfs Diode Forward Voltagea VSD Dynamic VDS = V, VGS, ID = 250 A N-Ch 1.94 VDS = V, VGS, ID = -250 A P-Ch 2.1 VDS 5 V, VGS = 10 V N-Ch 58 VDS -5 V, VGS = -10 V P-Ch 30 VGS = 10 V, ID = 2.9 A N-Ch 0.072 VGS = -10 V, ID = -2.1 A P-Ch 0.147 VGS = 4.5 V, ID = 2.2 A N-Ch 0.110 VGS = -4.5 V, ID = -1.6 A P-Ch 0.216 VDS = 15 V, ID = 2.9 A N-Ch 5 VDS = -15 V, ID = -2.1 A P-Ch 3.3 IS = 0.9 A, VGS = 0 V N-Ch 0.80 IS = -0.9 A, VGS = 0 V P-Ch -0.80 N-Ch 4.7 V A S V b Total Gate Chargeb Qg Gate-Source Chargeb Qgs Gate-Drain Chargeb Qgd Turn-On Delay Timeb td(on) Rise Timeb b Turn-Off Delay Time b Fall Time Source-Drain Reverse Recovery Time N-Channel VDS = 15 V, VGS = 10 V, ID = 2.9 A P-Channel VDS = -15 V, VGS = -10 V, ID = -2.1 A P-Ch 5.5 N-Ch 0.8 P-Ch 1.2 N-Ch 1 P-Ch 0.9 N-Ch 8 P-Ch 8 tr N-Channel VDD =15 V, RL = 15 ID 1 A, VGEN = 10 V, RG = 6 N-Ch 9 P-Ch 10 td(off) P-Channel VDD = -15 V, RL = 15 ID -1 A, VGEN = -10 V, RG = 6 N-Ch 11 P-Ch 14 N-Ch 12 tf trr P-Ch 17 IF = 0.9 A, di/dt = 100 A/s N-Ch 40 IF = -0.9 A, di/dt = 100 A/s P-Ch 30 nC ns Notes a. Guaranteed by design, not subject to production testing. b. Pulse test; pulse width 300 s, duty cycle 2%. www.vishay.com 2 Document Number: 71547 07-Oct-99 SPICE Device Model Si5504DC Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25C UNLESS OTHERWISE NOTED) N-Channel MOSFET Document Number: 71547 07-Oct-99 www.vishay.com 3 SPICE Device Model Si5504DC Vishay Siliconix P-Channel MOSFET www.vishay.com 4 Document Number: 71547 07-Oct-99