SPICE Device Model Si5504DC
Vishay Siliconix
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 71547 www.vishay.com
07-Oct-99 1
Complementary 20-V (D-S) MOSFET
CHARACTERISTICS
• N- and P-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Applicable over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n- and p-channel vertical DMOS. The model
subcircuit schematic is extracted and optimized over the
−55 to 125°C temperature ranges under the pulsed 0-to-5V gate
drive. The saturated output impedance is best fit at the gate bias
near the threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched C
g
d model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
SPICE Device Model Si5504DC
Vishay Siliconix
www.vishay.com Document Number: 71547
207-Oct-99
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Parameter Symbol Test Conditions Typical Unit
Static
VDS = V, VGS, ID = 250 µAN-Ch 1.94
Gate Threshold Voltage VGS(th)
VDS = V, VGS, ID = −250 µAP-Ch 2.1
V
VDS ≥ 5 V, VGS = 10 V N-Ch 58
On-State Drain CurrentaID(on)
VDS ≤ −5 V, VGS = −10 V P-Ch 30
A
VGS = 10 V, ID = 2.9 A N-Ch 0.072
VGS = −10 V, ID = −2.1 A P-Ch 0.147
VGS = 4.5 V, ID = 2.2 A N-Ch 0.110
Drain-Source On-State ResistancearDS(on)
VGS = −4.5 V, ID = −1.6 A P-Ch 0.216
Ω
VDS = 15 V, ID = 2.9 A N-Ch 5
Forward Transconductanceagfs VDS = −15 V, ID = −2.1 A P-Ch 3.3
S
IS = 0.9 A, VGS = 0 V N-Ch 0.80
Diode Forward VoltageaVSD IS = −0.9 A, VGS = 0 V P-Ch −0.80
V
Dynamicb
N-Ch 4.7
Total Gate ChargebQgP-Ch 5.5
N-Ch 0.8
Gate-Source ChargebQgs P-Ch 1.2
N-Ch 1
Gate-Drain ChargebQgd
N-Channel
VDS = 15 V, VGS = 10 V, ID = 2.9 A
P-Channel
VDS = −15 V, VGS = −10 V, ID = −2.1 A
P-Ch 0.9
nC
N-Ch 8
Turn-On Delay Timebtd(on) P-Ch 8
N-Ch 9
Rise TimebtrP-Ch 10
N-Ch 11
Turn-Off Delay Timebtd(off) P-Ch 14
N-Ch 12
Fall Timebtf
N-Channel
VDD =15 V, RL = 15 Ω
ID ≅ 1 A, VGEN = 10 V, RG = 6 Ω
P-Channel
VDD = −15 V, RL = 15 Ω
ID ≅ −1 A, VGEN = −10 V, RG = 6 Ω
P-Ch 17
ns
IF = 0.9 A, di/dt = 100 A/µsN-Ch 40
Source-Drain Reverse Recovery Time trr
IF = −0.9 A, di/dt = 100 A/µsP-Ch 30
Notes
a. Guaranteed by design, not subject to production testing.
b. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.
SPICE Device Model Si5504DC
Vishay Siliconix
Document Number: 71547 www.vishay.com
07-Oct-99 3
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
N-Channel MOSFET
SPICE Device Model Si5504DC
Vishay Siliconix
www.vishay.com Document Number: 71547
407-Oct-99
P-Channel MOSFET
