Real-time Clock 2 (RTC2) Alarm and Parallel Load - Atmel Corporation

Features

•Compatible with an Embedded ARM7TDMI™Processor

•Low Power Consumption

•Full Asynchronous Design

•Two-hundred Year Calendar, Year 2000 Compliant

•Programmable Periodic Interrupt

•Alarm and Update Parallel Load

•Control of Alarm and Update Time/Calendar Data In

•Full Scan Testable (up to 95% Fault Coverage)

•Very Small Silicon Area

•Can be Directly Connected to the Atmel Implementation

of the AMBA™Peripheral Bus (APB)

Description

The Real-time Clock 2 (RTC2) peripheral is designed for very low power consumption.

It combines a complete time-of-day clock with alarm and a two-hundred-year Grego-

rian calendar, complemented by a programmable periodic interrupt. The alarm and

calendar registers are accessed by a 32-bit data bus.

The time and calendar values are coded in binary-coded decimal (BCD) format. The

time format can be 24-hour mode or 12-hour mode with an AM/PM indicator.

Updating time and calendar fields and configuring the alarm fields is performed by a

parallel capture on the 32-bit data bus. An entry control is performed to avoid loading

registers with incompatible BCD format data or with an incompatible date according to

the current month/year/century.

This peripheral can be used with any 32-bit microcontroller core if the timing diagram

shown in Figure 4 on page 6 is respected. When using an ARM7TDMI as the core, the

Atmel Bridge must be used to provide the correct bus interface to the RTC2.

32-bit

Embedded ASIC

Core Peripheral

Real-time Clock

2(RTC2)Alarm

and Parallel

Load

Rev. 1245D–CASIC–03/02

2RTC2

1245D–CASIC–03/02

Scan Test Configuration

The fault coverage is maximum if all non-scan inputs can be controlled and all non-scan outputs can be observed. In order

to achieve this, the ATPG vectors must be generated on the entire circuit (top-level), which includes the RTC2, or all RTC2

I/Os must have a top-level access and ATPG vectors must be applied to these pins.

Figure 1. RTC2 Pin Configuration

P_D_IN[31:0]

P_A[13:0]

P_WRITE

P_STB

CLK32768

P_SEL_RTC

SCAN_TEST_MODE

RTC_INT

TEST_SO

RTC2

Functional

TEST_SE

TEST_SI

Test Scan

NRESET

P_D_OUT[31:0]

Table 1. RTC2 Pin Description

Name Function Type

Active

Level Comments

Functional

NRESET Reset system Input Low Resets all the counters and signals

CLK32768 Main clock for RTC2 Input – F = 32.768 kHz (Crystal Oscillator)

P_STB User interface clock signal Input High From host (bridge)

P_WRITE Write enable Input High From host (bridge)

P_A[13:0] Address bus Input – The address takes into account the 2 LSBs

[1:0], but the macrocell does not take these

bits into account (left unconnected).

P_D_IN[31:0] Input data bus Input – From host (bridge)

P_D_OUT[31:0] Output data bus Output – To host (bridge)

P_SEL_RTC Selection of the block Input High From host (bridge)

RTC_INT Interrupt Output High Programmable from alarm and/or event

Test Scan

SCAN_TEST_MODE Clock selection for test purposes Input High All sequentialcellsaredrivenwiththesame

clock phase (CLK32768).

TEST_SE Scan test enable Input High/Low Scan shift/scan capture

TEST_SI Scan test input Input High Entry of scan chain

TEST_SO Scan test output Output – Ouput of scan chain

RTC2

1245D–CASIC–03/02

Functional Diagram

Figure 2. RTC2 Block Diagram

Figure 3. Connecting the RTC2 to an ARM-based Microcontroller

Bus Interface

32768 Divider Time

Crystal Oscillator

CLK32768

Bus Interface

Date

RTC_INT

Entry

Control

Interrupt

Control

32-bit

Core

(ARM)

Atmel Bridge

P_WRITE

P_D_IN[31:0]

P_D_OUT[31:0]

P_STB

P_A[13:0]

P_SEL_RTC

Atmel Bus Interface

ASB

RTC2

CLOCK

NRESET

NRESETRTC_INT

To Advanced

Interrupt

Controller (AIC)

32768 kHz

Crystal Oscillator

4RTC2

1245D–CASIC–03/02

Functional

Description

The RTC2 provides a full binary-coded decimal (BCD) clock that includes century

(19/20), year (with leap years), month, date, day, hours, minutes and seconds.

The valid year range is 1900 to 2099, a two-hundred-year Gregorian calendar achieving

full Y2K compliance.

The RTC2 can operate in 24-hour mode or in 12-hour mode with an AM/PM indicator.

Corrections for leap years are included (all years divisible by 4 being leap years, includ-

ing year 2000). This is correct up to the year 2099.

Reference Clock The reference clock is CLK32768. It can be driven by the Atmel cell OSC33K (or an

equivalent cell) and an external 32.768 kHz crystal.

Timing The RTC2 is updated in real time at one-second intervals in normal mode for the

counters of seconds, at one-minute intervals for the counter of minutes and so on.

Due to the asynchronous operation of the RTC2 with respect to the rest of the chip, to

be certain that the value read in the RTC2 registers (century, year, month, date, day,

hours, minutes, seconds) are valid and stable, it is necessary to read these registers

twice. If the data is the same both times, then it is valid. Therefore, a minimum of two

and a maximum of three accesses is required.

Alarm The RTC2 has five programmable fields: month, date, hours, minutes and seconds.

Each of these fields can be enabled or disabled to match the alarm condition:

• If all the fields are enabled, an alarm flag is generated (the corresponding flag is

asserted and an interrupt generated if enabled) at a given month, date,

hour/minute/second.

• If only the “seconds” field is enabled, then an alarm is generated every minute.

• Depending on the combination of fields enabled, a large number of possibilities are

available to the user ranging from minutes to 365/366 days.

RTC2

1245D–CASIC–03/02

Error Checking A verification on user interface data is performed when accessing the century, year,

month, date, day, hours, minutes, seconds and alarms. A check is performed on illegal

BCD entries such as illegal date of the month with regards to the year and century

configured.

If one of the time fields is not correct, the data is not loaded into the register/counter and

a flag is set in the validity register. This flag cannot be reset by the user. It is reset as

soon as an acceptable value is programmed. This avoids any further side effects in the

hardware. The same procedure is done for the alarm.

The following checks are performed:

1. Century (check if it is in range 19-20)

2. Year (BCD entry check)

3. Date (check range 01-31)

4. Month (check if it is in BCD range 01-12,

check validity regarding “date”)

5. Day (check range 1-7)

6. Hour (BCD check: in 24-hour mode check range

00-23 and check that AM/PM flag is not set if RTC2 is set in 24-hour mode;in 12-

hour mode check range 01-12)

7. Minute (check BCD and range 00-59)

8. Second (check BCD and range 00-59)

Note: If the 12-hour mode is selected by means of the RTC_MODE register, a 12-hour value

can be programmed and the returned value on RTC_TIME will be the corresponding 24-

hour value. The entry control checks the value of the AM/PM indicator (bit 22 of

RTC_TIME register) to determine the range to be checked.

Updating Time/Calendar To update any of the time/calendar fields, the user must first stop the RTC2 by setting

the corresponding field in the Control Register. Bit UPDTIM must be set to update time

fields (hour, minute, second) and bit UPDCAL must be set to update calendar fields

(century, year, month, date, day).

Then the user must poll or wait for the interrupt (if enabled) of bit ACKUPD in the Status

Once the update is finished, the user must reset (0) UPDTIM and/or UPDCAL in the

Control Register.

When programming the calendar fields, the time fields remain enabled. This avoids a

time slip in case the user stays in the calendar update phase for several tens of seconds

or more.

In successive update operations, the user must wait at least one second after resetting

the UPDTIM/UPDCAL bit in the RTC_CR (Control Register) before setting these bits

again. This is done by waiting for the SEC flag in the Status Register before setting

UPDTIM/UPDCAL bit. After resetting UPDTIM/UPDCAL, the SEC flag must also be

cleared.

6RTC2

1245D–CASIC–03/02

Foundry Test In functional mode TEST_MODE, TEST_SE and TEST_SI inputs must be set to 0.

In scan test mode (foundry test mode), SCAN_TEST_MODE must be tied to 1 during

the entire test period. All the internal clocks are driven by the clock input “clk32768” in

this mode, providing a full synchronous design. This is done by means of internal multi-

plexers. The scan chain order is opposite that of the clock propagation (order of the

multiplexers) to avoid clock skew.

TEST_SE and TEST_SI are driven by the ATPG vectors.

Note: If all the I/Os are controllable/observable, the ATPG (scan vectors) fault coverage of the

RTC2 is greater than 94%. Higher fault coverage may be achieved by applying manual

vectors to the 32768 divider.

Timing Diagram

Figure 4. RTC2 Timing Diagram

CLK32768

Valid

tSU_A tHOLD_A

P_STB

P_A[13:0]

P_D_IN[31:0]

P_WRITE

P_D_OUT[31:0]

tPD1 tPD2

RTC_INT

tPD_IRQ, tPD_FIQ, tPD_INT

tSU_WRITE tHOLD_WRITE

tHOLD_DIN

tSU_DIN

tSU_SEL tHOLD_SEL

P_SEL_RTC

RTC2

1245D–CASIC–03/02

RTC2 User Interface

Notes: 1. The address takes into account the 2 LSBs [1:0], but the macrocell does not take these bits into account (left unconnected).

Therefore, loading 0x0001, 0x0002 or 0x0003 on P_A[13:0] addresses the Control Register.

2. In the following register description, all undefined bits (“–”) read “0”.

3. If the user selects an address that is not defined in the above table, the value of P_D_OUT[31:0] is 0x00000000.

Table 2. RTC2 Memory Map

Offset Register Name Access Reset State

0x0000 Control Register RTC_CR Read/Write 0x00000000

0x0004 Mode Register RTC_MR Read/Write 0x00000000

0x000C Calendar Register RTC_CALR Read/Write 0x01819819

0x0010 Time Alarm Register RTC_TIMALR Read/Write 0x00000000

0x0014 Calendar Alarm Register RTC_CALALR Read/Write 0x01010000

0x0018 Status Register RTC_SR Read-only 0x00000000

0x001C Status Clear Command Register RTC_SCCR Write-only –

0x0020 Interrupt Enable Register RTC_IER Write-only –

0x0024 Interrupt Disable Register RTC_IDR Write-only –

0x0028 Interrupt Mask Register RTC_IMR Read-only 0x00000000

0x002C Valid Entry Register RTC_VER Read-only 0x00000000

8RTC2

1245D–CASIC–03/02

RTC Control Register

Access: Read/Write

• UPDTIM: Update Request Time Register

0=Noeffect.

1 = Stops the RTC time counting.

Time counting consists of second, minute and hour counters. Time counters can be programmed once this bit is set and

acknowledged by the bit ACKUPD of the Status Register.

• UPDCAL: Update Request Calendar Register

0=Noeffect.

1 = Stops the RTC calendar counting.

Calendar counting consists of day, date, month, year and century counters. Calendar counters can be programmed once

this bit is set.

• TIMEVSEL: Time Event Selection

The event that generates the flag TIMEVin RTC_SR (Status Register) depends on the value of TIMEVSEL.

0 = Minute change.

1 = Hour change.

2 = Every day at midnight.

3 = Every day at noon.

• CALEVSEL: Calendar Event Selection

The event that generates the flag CALEVin RTC_SR depends on the value of CALEVSEL.

0 = Week change (every Monday at time 00:00:00).

1 = Month change (every 01 of each month at time 00:00:00).

2,3 = Year change (every January 1 at time 00:00:00).

31 30 2928 27 26 25 24

––––––––

23 22 21 20 1918 17 16

–––––– CALEVSEL

15 14 13 12 11 10 98

–––––– TIMEVSEL

76543210

––––––UPDCALUPDTIM

RTC2

1245D–CASIC–03/02

RTC Mode Register

Access Type: Read/Write

• HRMOD: 12-/24-hour Mode

0 = 24-hour mode is selected.

1 = 12-hour mode is selected.

All non-significant bits read zero.

31 30 2928 27 26 25 24

––––––––

23 22 21 20 1918 17 16

––––––––

15 14 13 12 11 10 98

––––––––

76543210

–––––––HRMOD

10 RTC2

1245D–CASIC–03/02

RTC Time Register

Access Type: Read/Write

• SEC: Current Second

The range that can be set is 0-59(BCD).

The lowest four bits encode the units. The higher bits encode the tens.

• MIN: Current Minute

The range that can be set is 0-59(BCD).

The lowest four bits encode the units. The higher bits encode the tens.

• HOUR: Current Hour

The range that can be set is 1-12 (BCD) in 12-hour mode or 0-23 (BCD) in 24-hour mode.

AMPM: Ante Meridiem Post Meridiem Indicator

This bit is the AM/PM indicator in 12-hour mode.

0=AM.

1=PM.

All non-significant bits read zero.

31 30 2928 27 26 25 24

––––––––

23 22 21 20 1918 17 16

–AMPM HOUR

15 14 13 12 11 10 98

–MIN

76543210

– SEC

RTC2

1245D–CASIC–03/02

RTC Calendar Register

Access Type: Read/Write

• CENT: Current Century

The range that can be set is 19-20 (BCD).

The lowest four bits encode the units. The higher bits encode the tens.

• YEAR: Current Year

The range that can be set is 00-99 (BCD).

The lowest four bits encode the units. The higher bits encode the tens.

• MONTH: Current Month

The range that can be set is 01-12 (BCD).

The lowest four bits encode the units. The higher bits encode the tens.

• DAY: Current Day

The range that can be set is 1-7 (BCD).

The significance of the number (which number represents which day) is user defined as it has no effect on the date counter.

• DATE: Current Date

The range that can be set is 01-31 (BCD).

The lowest four bits encode the units. The higher bits encode the tens.

All non-significant bits read zero.

31 30 2928 27 26 25 24

–– DATE

23 22 21 20 1918 17 16

DAYMONTH

15 14 13 12 11 10 98

YEAR

76543210

– – CENT

12 RTC2

1245D–CASIC–03/02

RTC Time Alarm Register

Access Type: Read/Write

• SEC: Second Alarm

This field is the alarm field corresponding to the BCD-coded second counter.

• SECEN: Second Alarm Enable

0 = The second-matching alarm is disabled.

1 = The second-matching alarm is enabled.

• MIN: Minte Alarm

This field is the alarm field corresponding to the BCD-coded minute counter.

• MINEN: Minute Alarm Enable

0 = The minute-matching alarm is disabled.

1 = The minute-matching alarm is enabled.

• HOUR: Hour Alarm

This field is the alarm field corresponding to the BCD-coded hour counter.

• AMPM: AM/PM Indicator

This field is the alarm field corresponding to the BCD-coded hour counter.

• HOUREN: Hour Alarm Enable

0 = The hour-matching alarm is disabled.

1 = The hour-matching alarm is enabled.

31 30 2928 27 26 25 24

–– –

23 22 21 20 1918 17 16

HOUREN AMPM HOUR

15 14 13 12 11 10 98

MINEN MIN

76543210

SECEN SEC

RTC2

1245D–CASIC–03/02

RTC Calendar Alarm Register

Access Type: Read/Write

• MONTH: Month Alarm

This field is the alarm field corresponding to the BCD-coded month counter.

• MTHEN: Month Alarm Enable

0=Themonth-matchingalarmisdisabled.

1 = The month-matching alarm is enabled.

• DATE: Date Alarm

This field is the alarm field corresponding to the BCD-coded date counter.

• DATEN: Date Alarm Enable

0 = The date-matching alarm is disabled.

1 = The date-matching alarm is enabled.

31 30 2928 27 26 25 24

DATEEN – DATE

23 22 21 20 1918 17 16

MTHEN – – MONTH

15 14 13 12 11 10 98

––––––––

76543210

––––––––

14 RTC2

1245D–CASIC–03/02

RTC Status Register

Access Type: Read-only

• ACKUPD: Acknowledge for Update

0 = Time and Calendar registers cannot be updated.

1 = Time and Calendar registers can be updated.

• ALARM: Alarm Flag

0 = No alarm matching condition occurred.

1 = An alarm matching condition has occurred.

• SEC: Second Event

0 = No second event has occurred since the last clear.

1 = At least one second event has occurred since the last clear.

• TIMEV: Time Event

0 = No time event has occurred since the last clear.

1 = At least one time event has occurred since the last clear.

The time event is selected in the TIMEVSEL field in RTC_CTRL (Control Register) and can be any one of the following

events: minute change, hour change, noon, midnight (day change).

• CALEV: Calendar Event

0 = No calendar event has occurred since the last clear.

1 = At least one calendar event has occurred since the last clear.

The calendar event is selected in the CALEVSEL field in RTC_CTRL and can be any one of the following events: week

change, month change, year change.s

31 30 2928 27 26 25 24

––––––––

23 22 21 20 1918 17 16

––––––––

15 14 13 12 11 10 98

––––––––

76543210

–––CALEVTIMEVSEC ALARM ACKUPD

RTC2

1245D–CASIC–03/02

RTC Status Clear Command Register

Access Type: Write-only

• Status Flag Clear

0=Noeffect.

1 = Clears corresponding status flag in the Status Register (RTC_SR).

31 30 2928 27 26 25 24

––––––––

23 22 21 20 1918 17 16

––––––––

15 14 13 12 11 10 98

––––––––

76543210

– – – CALCLR TIMCLR SECCLR ALRCLR ACKCLR

16 RTC2

1245D–CASIC–03/02

RTC Interrupt Enable Register

Access Type: Write-only

• ACKEN: Acknowledge Update Interrupt Enable

0=Noeffect.

1 = The acknowledge for update interrupt is enabled.

• ALREN: Alarm Interrupt Enable

0=Noeffect.

1 = The alarm interrupt is enabled.

• SECEN: Second Event Interrupt Enable

0=Noeffect.

1 = The second periodic interrupt is enabled.

• TIMEN: Time Event Interrupt Enable

0=Noeffect.

1 = The selected time event interrupt is enabled.

• CALEN: Calendar Event Interrupt Enable

0=Noeffect.

1 = The selected calendar event interrupt is enabled.

31 30 2928 27 26 25 24

––––––––

23 22 21 20 1918 17 16

––––––––

15 14 13 12 11 10 98

––––––––

76543210

– – – CALEN TIMEN SECEN ALREN ACKEN

RTC2

1245D–CASIC–03/02

RTC Interrupt Disable Register

Access Type: Write-only

• ACKDIS: Acknowledge Update Interrupt Disable

0=Noeffect.

1 = The acknowledge for update interrupt is disabled.

• ALRDIS: Alarm Interrupt Disable

0=Noeffect.

1 = The alarm interrupt is disabled.

• SECDIS: Second Event Interrupt Disable

0=Noeffect.

1 = The second periodic interrupt is disabled.

• TIMDIS: Time Event Interrupt Disable

0=Noeffect.

1=Theselectedtimeeventinterruptisdisabled.

• CALDIS: Calendar Event Interrupt Disable

0=Noeffect.

1 = The selected calendar event interrupt is disabled.

31 30 2928 27 26 25 24

––––––––

23 22 21 20 1918 17 16

––––––––

15 14 13 12 11 10 98

––––––––

76543210

– – – CALDIS TIMDIS SECDIS ALRDIS ACKDIS

18 RTC2

1245D–CASIC–03/02

RTC Interrupt Mask Register

Access Type: Read-only

• ACK: Acknowledge Update Interrupt Mask

0 = The acknowledge for update interrupt is disabled.

1 = The acknowledge for update interrupt is enabled.

• ALR: Alarm Interrupt Mask

0 = The alarm interrupt is disabled.

1 = The alarm interrupt is enabled.

• SEC: Second Event Interrupt Mask

0 = The second periodic interrupt is disabled.

1 = The second periodic interrupt is enabled.

• TIM: Time Event Interrupt Mask

0=Theselectedtimeeventinterruptisdisabled.

1 = The selected time event interrupt is enabled.

• CAL: Calendar Event Interrupt Mask

0 = The selected calendar event interrupt is disabled.

1 = The selected calendar event interrupt is enabled.

31 30 2928 27 26 25 24

––––––––

23 22 21 20 1918 17 16

––––––––

15 14 13 12 11 10 98

––––––––

76543210

– – – CAL TIM SEC ALR ACK

RTC2

1245D–CASIC–03/02

RTC Valid Entry Register

Access Type: Read-only

• NVTIM: Nonvalid Time

0 = No invalid data has been detected in RTC_TIMR (Time Register).

1 = RTC_TIMR has contained invalid data since it was last programmed.

• NVCAL: Nonvalid Calendar

0 = No invalid data has been detected in RTC_CALR (Calendar Register).

1 = RTC_CALR has contained invalid data since it was last programmed.

• NVTIMALR: Nonvalid Time Alarm

0 = No invalid data has been detected in RTC_TIMALR (Time Alarm Register).

1 = RTC_TIMALR has contained invalid data since it was last programmed.

• NVCALALR: Nonvalid Calendar Alarm

0 = No invalid data has been detected in RTC_CALALR (Calendar Alarm Register).

1 = RTC_CALALR has contained invalid data since it was last programmed.

31 30 2928 27 26 25 24

––––––––

23 22 21 20 1918 17 16

––––––––

15 14 13 12 11 10 98

––––––––

76543210

––––NVCALALR NVTIMALR NVCAL NVTIM

Printed on recycled paper.

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1245D–CASIC–03/02 0M

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