TLC5602C, TLC5602M
VIDEO 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS023D – FEBRUAR Y 1989 – REVISED JANUAR Y 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
8-Bit Resolution
D
±0.2% Linearity
D
Maximum Conversion Rate
30 MHz Typ
20 MHz Min
D
Analog Output Voltage Range
VDD to VDD –1 V
D
TTL Digital Input Voltage
D
5-V Single Power-Supply Operation
D
Low Power Consumption . . . 80 mW Typ
D
Interchangeable With Fujitsu MB40778
description
The TLC5602x devices are low-power, ultra-high-speed video, digital-to-analog converters that use the
LinEPIC 1-µm CMOS process. The TLC5602x converts digital signals to analog signals at a sampling rate
of dc to 20 MHz. Because of high-speed operation, the TLC5602x devices are suitable for digital video
applications such as digital television, video processing with a computer, and radar-signal processing.
The TLC5602C is characterized for operation from 0°C to 70°C. The TLC5602M is characterized over the full
military temperature range of –55°C to 125°C.
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
DGTL GND
DGTL VDD
COMP
REF
ANLG VDD1
A OUT
ANLG VDD2
DGTL VDD
ANLG GND
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7 (MSB)
CLK
N PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DGTL GND
DGTL VDD
COMP
REF
ANLG VDD1
A OUT
NC
ANLG VDD2
DGTL VDD
ANLG GND
NC
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7 (MSB)
CLK
NC—No internal connection
DW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
NC
DGTL GND
DGTL VDD
COMP
REF
ANLG VDD1
A OUT
ANLG VDD2
DGTL VDD
ANLG GND
NC
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7 (MSB)
CLK
J PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
D1
D2
D3
D4
D5
COMP
REF
ANLG VDD1
A OUT
ANLG VDD2
FK PACKAGE
(TOP VIEW)
DGTL V
DGTL GND
NC
D7 (MSB)
D6 NC
D0 (LSB)
ANLG GND
CLK
DD
DGTL V DD
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
LinEPIC is a trademark of Texas Instruments Incorporated.
TLC5602C, TLC5602M
VIDEO 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS023D – FEBRUARY 1989 – REVISED JANUARY 2002
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
AVAILABLE OPTIONS
PACKAGE
TAWIDE-BODY SMALL OUTLINE
(DW) CERAMIC CHIP CARRIER
(FK) CERAMIC DIP
(J) PLASTIC DIP
(N)
0°C to 70°C TLC5602CDW TLC5602CN
–55°C to 125°C TLC5602MFK TLC5602MJ
functional block diagram
Buffer
Driver With
Register
Current
Switches
With
Register
Decode
COMP
REF
CLK
D7–D0
A OUT
88 3
63 I x 4
I x 1
FUNCTION TABLE
STEP
DIGITAL INPUTS OUTPUT
STEP
D7 D6 D5 D4 D3 D2 D1 D0 VOLTAGE†
0 L L L L L L L L 3.980 V
1 L L L L L L L H 3.984 V
|||
127 L H H H H H H H 4.488 V
128 H L L L L L L L 4.492 V
129 H L L L L L L H 4.496 V
|||
254 H H H H H H H L 4.996 V
255 H H H H H H H H 5.000 V
†VDD = 5 V and Vref = 4.02 V
TLC5602C, TLC5602M
VIDEO 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS023D – FEBRUARY 1989 – REVISED JANUARY 2002
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematics of equivalent input and output
EQUIVALENT OF ANALOG OUTPUTEQUIVALENT OF EACH DIGITAL INPUT
ANLG‡
GND
A OUT
80 Ω
ANLG VDD1
ÎÎ
ÎÎ
Dn
DGTL VDD
ANLG‡
GND DGTL‡
GND
DGTL VDD
‡ANLG GND and DGTL GND do not connect internally and should be tied together as close to the device terminals as possible.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, ANLG VDD, DGTL VDD –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input voltage range, VI –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog reference voltage range, Vref V
DD – 1.7 V to VDD + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: TLC5602C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLC5602M –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, VDD 4.75 5 5.25 V
Analog reference voltage, V ref 3.8 4 4.2 V
High-level input voltage, VIH 2 V
Low-level input voltage, VIL 0.8 V
Pulse duration, CLK high or low, tw25 ns
Setup time, data before CLK↑, tsu 16.5 ns
Hold time, data after CLK↑, th12.5 ns
Phase compensation capacitance, Ccomp (see Note 1) 1µF
Load resistance, RL75 Ω
O
p
erating free air tem
p
erature TA
TLC5602C 0 70
°C
Operating
free
-
air
temperature
,
T
ATLC5602M –55 125
°C
NOTE 1: The phase compensation capacitor should be connected between COMP and ANLG GND.
TLC5602C, TLC5602M
VIDEO 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS023D – FEBRUARY 1989 – REVISED JANUARY 2002
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT
IIH High-level input current Di
g
ital VI = 5 V ±1µA
IIL Low-level input current
g
inputs VI = 0 V ±1µA
Iref Input reference current Vref = 4 V 10 µA
VFS Full-scale analog output voltage VDD = 5 V, Vref = 4.02 V VDD–15 VDD VDD+15 mV
V5V
V 4 02 V
TLC5602C 3.919 3.98 4.042
VZS Zero-scale analog output voltage VDD = 5 V,
TA= full range§
Vref = 4.02 V, TLC5602M 3.919 3.98 4.042 V
TA
=
full
range§
TLC5602M 3.919 3.98 4.062
r
p
TA = 25°C TLC5602C
60
80
120
Ω
r
o
TA = full range§TLC5602M
60
80
120
Ω
CiInput capacitance fclock = 1 MHz, TA = 25°C 15 pF
IDD Supply current fclock = 20 MHz, Vref = VDD–0.95 V 16 25 mA
‡All typical values are at VDD = 5 V and TA = 25°C.
§Full range for the TLC5602C is 0°C to 70°C, and full range for the TLC5602M is –55°C to 125°C.
operating characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
TA = full range‡TLC5602C ±0.2%
EL
(
ad
j)
Linearity error, best-straight-line TA = 25°C
TLC5602M
±0.2%
(j)
TA = full range‡
TLC5602M
±0.4%
ELLinearity error, end point ±0.15%
EDLinearity error, differential ±0.2%
Gdiff Dif ferential gain NTSC 40-IRE modulated ramp, 0.7%
fdiff Dif ferential phase
,
fclock = 14.3 MHz, ZL ≥75 kΩ0.4°
tpd Propagation delay time, CLK to analog output CL = 10 pF 25 ns
tsSettling time to within 1/2 LSB CL = 10 pF 30 ns
†All typical values are at VDD = 5 V and TA = 25°C.
‡Full range for the TLC5602C is 0°C to 70°C, and full range for the TLC5602M is –55°C to 125°C.
TLC5602C, TLC5602M
VIDEO 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS023D – FEBRUARY 1989 – REVISED JANUARY 2002
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
th
tsu
tw
tpd
50%50%
±1/2 LSB
50%
A OUT
CLK
D0–D7
ÏÏ
ÏÏ
ts
tw
50% 50% 50%
Figure 1. Voltage Waveforms
TLC5602C, TLC5602M
VIDEO 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS023D – FEBRUARY 1989 – REVISED JANUARY 2002
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 2
5
4.996
4.496
4.492
4.488
3.988
3.984
3.98
00000000
00000001
00001110
Digital Input Code
01111111
10000000
10000001
11111111
11111110
4.992
ÏÏÏÏÏ
ÏÏÏÏÏ
VDD = 5 V
Vref = 4.02 V
Step 2
Step 1
Step 127
Step 128
Step 129
Step 253
Step 254
IDEAL CONVERSION CHARACTERISTICS
V
O–
A
na
l
og
O
u
t
pu
t
V
o
lt
age –
V
Figure 3
00000000
00000001
00001110
01111111
10000000
10000001
11111111
11111110
ÏÏÏÏÏ
ÏÏÏÏÏ
VDD = 5 V
Vref = 4.02 V
5
4.996
4.496
4.492
4.488
3.988
3.984
3.98
Digital Input Code
4.992
EL127
EL128
EL129
EL254
EL253
EL0
EL2
VZS
ÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏ
Best-Fit Straight Line
BEST-STRAI
G
HT-LINE LINEARITY ERROR
VO– Analog Output Voltage – V
EL1
VFS EL255
3.96
3.95
3.93
3.92
– 55 – 35 – 15 5 25 45 65
3.97
3.99
ZERO-SCALE OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
4
85 105
3.94
3.98
4.01
4.02 VDD = 5 V
Vref = 4.02 V
See Note A
TA – Free-Air Temperature – °C
VZS – Zero-Scale Output Voltage – V
125
NOTE A: Vref is relative to ANLG GND. VDD is the voltage between
ANLG VDD and DGTL VDD tied together and ANLG GND
and DGTL GND tied together.
Figure 4
70
65
55
50
75
85
90
60
80
95
100
– Output Resistance –
OUTPUT RESISTANCE
vs
FREE-AIR TEMPERATURE
TA – Free-Air Temperature – °C
Ωro
– 55 – 35 – 155 25456585105125
VDD = 5 V
VDD = VO = 0.5 V
Data Input = FF
Figure 5
TLC5602C, TLC5602M
VIDEO 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS023D – FEBRUARY 1989 – REVISED JANUARY 2002
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
18
16
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
20
17
19
21
TA – Free-Air Temperature – °C
IDD – Supply Current – mA
– 55 – 35 – 155 25456585105125
VDD = 5 V
Vref = 4.02 V
fclock = 20 MHz
Figure 6
4.2
3.8
3.6
3.43.4 3.6 3.8 4 4.2 4.4
4.6
4.8
ZERO-SCALE OUTPUT VOLTAGE
vs
REFERENCE VOLTAGE
5
4.6 4.8 5
4.4
4
VZS – Zero-Scale Output Voltage – V
VDD = 5 V
TA = 25°C
See Note A
Vref – Reference Voltage – V
Figure 7
NOTE A: Vref is relative to ANLG GND. VDD is the voltage
between ANLG VDD and DGTL VDD tied together and
ANLG GND and DGTL GND tied together.
TLC5602C, TLC5602M
VIDEO 8-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS023D – FEBRUARY 1989 – REVISED JANUARY 2002
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
The following design recommendations benefit the TLC5602 user:
D
Physically separate and shield external analog and digital circuitry as much as possible to reduce system
noise.
D
Use RF breadboarding or RF printed-circuit-board (PCB) techniques throughout the evaluation and
production process.
D
Since ANLG GND and DGTL GND are not connected internally, these terminals need to be connected
externally. With breadboards, these ground lines should connect to the power-supply ground through
separate leads with proper supply bypassing. A good method is to use a separate twisted pair for the analog
and digital supply lines to minimize noise pickup.
Use wide ground leads or a ground plane on the PCB layouts to minimize parasitic inductance and
resistance. The ground plane is the better choice for noise reduction.
D
ANLG VDD and DGTL VDD are also separated internally, so they must connect externally. These external
PCB leads should also be made as wide as possible. Place a ferrite bead or equivalent inductance in series
with ANLG VDD and the decoupling capacitor as close to the device terminals as possible before the ANLG
VDD and DGTL VDD leads are connected together on the board.
D
Decouple ANLG VDD to ANLG GND and DGTL VDD to DGTL GND with a 1-µF and 0.01-µF capacitor,
respectively, as close as possible to the appropriate device terminals. A ceramic chip capacitor is
recommended for the 0.01-µF capacitor.
D
Connect the phase compensation capacitor between COMP and ANLG GND with as short a lead-in as
possible.
D
The no-connection (NC) terminals on the small-outline package should be connected to ANLG GND.
D
Shield ANLG VDD, ANLG GND, and A OUT from the high-frequency terminals CLK and D7–D0. Place
ANLG GND traces on both sides of the A OUT trace on the PCB.
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TLC5602CDW ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC5602CDWG4 ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC5602CDWR ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC5602CDWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC5602CN OBSOLETE PDIP N 18 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 1
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