Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
xr ST16C654/654D
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
AUGUST 2005 REV. 5.0.2
GENERAL DESCRIPTION
The ST16C654/654D1 (654) is an enhanced quad
Universal Asynchronous Receiver and Transmitter
(UART) each with 64 bytes of transmit and receive
FIFOs, transmit and receive FIFO trigger levels,
automatic hardware and software flow control, and
data rates of up to 1.5 Mbps. Each UART has a set
of registers that provide the user with operating status
and control, receiver error indications, and modem
serial interface controls. Selectable interrupt polarity
provides flexibility to meet design requirements. An
internal loopback capability allows onboard
diagnostics. The 654 is available in 64 pin LQFP, 68
pin PLCC and 100 pin QFP packages. The 64 pin
package only offers the 16 mode interface, but the 68
and 100 pin packages offer an additional 68 mode
interface which allows easy integration with Motorola
processors. The ST16C654CQ64 (64 pin) offers
three state interrupt output while the
ST16C654DCQ64 provides continuous interrupt
output. The 100 pin package provides additional
FIFO status outputs (TXRDY# and RXRDY# A-D),
separate infrared transmit data outputs (IRTX A-D)
and channel C external clock input (CHCCLK). The
ST16C654/654D is compatible with the industry
standard ST16C454 and ST16C654/554D.
NOTE: 1 Covered by U.S. Patent #5,649,122.
FEATURES
•Pin-to-pin compatible with ST16C454, ST16C554
and TI’s TL16C554AFN and TL16C754BFN
•Intel or Motorola Data Bus Interface select
•Four independent UART channels
■Register Set Compatible to 16C550
■Data rates of up to 1.5 Mbps
■64 Byte Transmit FIFO
■64 Byte Receive FIFO with error tags
■4 Selectable TX and RX FIFO Trigger Levels
■Automatic Hardware (RTS/CTS) Flow Control
■Automatic Software (Xon/Xoff) Flow Control
■Progammable Xon/Xoff characters
■Wireless Infrared (IrDA 1.0) Encoder/Decoder
■Full modem interface
•2.97V to 5.5V supply operation
•Sleep Mode (200 uA typical)
•Crystal oscillator or external clock input
APPLICATIONS
•Portable Appliances
•Telecommunication Network Routers
•Ethernet Network Routers
•Cellular Data Devices
•Factory Automation and Process Controls
FIGURE 1. ST16C654 BLOCK DIAGRAM
XTAL1
XTAL2
Crystal Osc/Buffer
Data Bus
Interface
UART Channel A
64 Byte TX FIFO
64 Byte RX FIFO
BRG
IR
ENDEC
TX & RX
UART
Regs
2.97V to 5.5V VCC
GND
654 BLK
TXB, RXB, IRTXB, DTRB#,
DSRB#, RTSB#, CTSB#,
CDB#, RIB#
UART Channel B
(same as Channel A)
A2:A0
D7:D0
CSA#
16/68#
CSB#
INTA
INTB
IOW#
IOR#
Reset
INTSEL
CHCCLK
TXRDY# A-D
RXRDY# A-D
UART Channel C
(same as Channel A)
TXA, RXA, IRTXA, DTRA#,
DSRA#, RTSA#, CTSA#,
CDA#, RIA#
TXC, RXC, IRTXC, DTRC#,
DSRC#, RTSC#, CTSC#,
CDC#, RIC#
UART Channel D
(same as Channel A)
TXD, RXD, IRTXD, DTRD#,
DSRD#, RTSD#, CTSD#,
CDD#, RID#
CSC#
CSD#
INTC
INTD
CLKSEL
ST16C654/654D xr
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0.2
2
FIGURE 2. PIN OUT ASSIGNMENT FOR 100-PIN QFP PACKAGES IN 16 AND 68 MODE
ST16C654
100-pin QFP
Intel Mode
Connect 16/68# pin to VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
N.C.
N.C.
N.C.
N.C.
TXRDYA#
IRTXA
DSRA#
CTSA#
DTRA#
VCC
RTSA#
INTA
CSA#
TXA
IOW#
TXB
CSB#
INTB
RTSB#
GND
DTRB#
CTSB#
DSRB#
IRTXB
TXRDYB#
N.C.
N.C.
N.C.
N.C.
N.C.
RXRDYB#
CDB#
RIB#
RXB
CLKSEL
16/68#
A2
A1
A0
XTAL1
XTAL2
CHCCLK
RESET
RXRDY#
TXRDY#
GND
RXC
RIC#
CDC#
RXRDYC#
N.C.
N.C.
N.C.
N.C.
FSRS#
IRTXD
DSRD#
CTSD#
DTRD#
GND
RTSD#
INTD
CSD#
TXD
IOR#
TXC
CSC#
INTC
RTSC#
VCC
DTRC#
CTSC#
DSRC#
IRTXC
TXRDYC#
N.C.
N.C.
N.C.
N.C.
N.C.
RXRDYA#
CDA#
RIA#
RXA
GND
D7
D6
D5
D4
D3
D2
D1
D0
INTSEL
VCC
RXD
RID#
CDD#
RXRDYD#
TXRDYD#
ST16C654
100-pin QFP
Motorola Mode
Connect 16/68# pin to GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
N.C.
N.C.
N.C.
N.C.
TXRDYA#
IRTXA
DSRA#
CTSA#
DTRA#
VCC
RTSA#
IRQ#
CSA#
TXA
R/W#
TXB
A3
N.C.
RTSB#
GND
DTRB#
CTSB#
DSRB#
IRTXB
TXRDYB#
N.C.
N.C.
N.C.
N.C.
N.C.
RXRDYB#
CDB#
RIB#
RXB
CLKSEL
16/68#
A2
A1
A0
XTAL1
XTAL2
CHCCLK
RESET
RXRDY#
TXRDY#
GND
RXC
RIC#
CDC#
RXRDYC#
N.C.
N.C.
N.C.
N.C.
FSRS#
IRTXD
DSRD#
CTSD#
DTRD#
GND
RTSD#
N.C.
N.C.
TXD
N.C.
TXC
A4
N.C.
RTSC#
VCC
DTRC#
CTSC#
DSRC#
IRTXC
TXRDYC#
N.C.
N.C.
N.C.
N.C.
N.C.
RXRDYA#
CDA#
RIA#
RXA
GND
D7
D6
D5
D4
D3
D2
D1
D0
INTSEL
VCC
RXD
RID#
CDD#
RXRDYD#
TXRDYD#
xr ST16C654/654D
REV. 5.0.2 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
3
FIGURE 3. PIN OUT ASSIGNMENT FOR PLCC PACKAGES IN 16 AND 68 MODE AND LQFP PACKAGES
ORDERING INFORMATION
PART NUMBER PACKAGE
OPERATING
TEMPERATURE
RANGE
DEVICE
STATUS PART NUMBER PACKAGE
OPERATING
TEMPERATURE
RANGE
DEVICE
STATUS
ST16C654CJ68 68-Lead PLCC 0°C to +70°C Active ST16C654DCQ64 64-Lead LQFP 0°C to +70°C Active
ST16C654IJ68 68-Lead PLCC -40°C to +85°C Active ST16C654DIQ64 64-Lead LQFP -40°C to +85°C Active
ST16C654CQ64 64-Lead LQFP 0°C to +70°C Active ST16C654CQ100 100-Lead QFP 0°C to +70°C Active
ST16C654IQ64 64-Lead LQFP -40°C to +85°C Active ST16C654IQ100 100-Lead QFP -40°C to +85°C Active
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
DSRA#
CTSA#
DTRA#
VCC
RTSA#
INTA
CSA#
TXA
IOW#
TXB
CSB#
INTB
RTSB#
GND
DTRB#
CTSB#
DSRB#
CDB#
RIB#
RXB
CLKSEL
A2
A1
A0
XTAL1
XTAL2
RESET
GND
RXC
RIC#
CDC#
DSRC#
DSRD#
CTSD#
DTRD#
GND
RTSD#
INTD
CSD#
TXD
IOR#
TXC
CSC#
INTC
RTSC#
VCC
DTRC#
CTSC#
CDA#
RIA#
RXA
GND
D7
D6
D5
D4
D3
D2
D1
D0
VCC
RXD
RID#
CDD#
ST16C654
ST16C654D
64-pin TQFP
Intel Mode Only
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
63
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
DSRA#
CTSA#
DTRA#
VCC
RTSA#
INTA
CSA#
TXA
IOW#
TXB
CSB#
INTB
RTSB#
GND
DTRB#
CTSB#
DSRB#
CDB#
RIB#
RXB
CLKSEL
16/68#
A2
A1
A0
XTAL1
XTAL2
RESET
RXRDY#
TXRDY#
GND
RXC
RIC#
CDC#
DSRD#
CTSD#
DTRD#
GND
RTSD#
INTD
CSD#
TXD
IOR#
TXC
CSC#
INTC
RTSC#
VCC
DTRC#
CTSC#
DSRC#
CDA#
RIA#
RXA
GND
D7
D6
D5
D4
D3
D2
D1
D0
INTSEL
VCC
RXD
RID#
CDD#
ST16C654
68-pin PLCC
Intel Mode
(16/68# pin connected to VCC)
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
63
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
DSRA#
CTSA#
DTRA#
VCC
RTSA#
IRQ#
CS#
TXA
R/W#
TXB
A3
N.C.
RTSB#
GND
DTRB#
CTSB#
DSRB#
CDB#
RIB#
RXB
CLKSEL
16/68#
A2
A1
A0
XTAL1
XTAL2
RESET
RXRDY#
TXRDY#
GND
RXC
RIC#
CDC#
DSRD#
CTSD#
DTRD#
GND
RTSD#
N.C.
N.C.
TXD
N.C.
TXC
A4
N.C.
RTSC#
VCC
DTRC#
CTSC#
DSRC#
CDA#
RIA#
RXA
GND
D7
D6
D5
D4
D3
D2
D1
D0
GND
VCC
RXD
RID#
CDD#
ST16C654
68-pin PLCC
Motorola Mode
(16/68# pin connected to GND)
ST16C654/654D xr
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0.2
4
PIN DESCRIPTIONS
Pin Description
NAME 64-LQFP
PIN #
68-PLCC
PIN#
100-QFP
PIN # TYPE DESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
22
23
24
32
33
34
37
38
39
IAddress data lines [2:0]. These 3 address lines select one of the
internal registers in UART channel A-D during a data bus transac-
tion.
D7
D6
D5
D4
D3
D2
D1
D0
60
59
58
57
56
55
54
53
5
4
3
2
1
68
67
66
95
94
93
92
91
90
89
88
I/O Data bus lines [7:0] (bidirectional).
IOR#
(VCC)
40 52 66 IWhen 16/68# pin is at logic 1, the Intel bus interface is selected and
this input becomes read strobe (active low). The falling edge insti-
gates an internal read cycle and retrieves the data byte from an
internal register pointed by the address lines [A2:A0], puts the data
byte on the data bus to allow the host processor to read it on the ris-
ing edge.
When 16/68# pin is at logic 0, the Motorola bus interface is selected
and this input is not used and should be connected to VCC.
IOW#
(R/W#)
918 15 IWhen 16/68# pin is at logic 1, it selects Intel bus interface and this
input becomes write strobe (active low). The falling edge instigates
the internal write cycle and the rising edge transfers the data byte on
the data bus to an internal register pointed by the address lines.
When 16/68# pin is at logic 0, the Motorola bus interface is selected
and this input becomes read (logic 1) and write (logic 0) signal.
CSA#
(CS#)
716 13 IWhen 16/68# pin is at logic 1, this input is chip select A (active low)
to enable channel A in the device.
When 16/68# pin is at logic 0, this input becomes the chip select
(active low) for the Motorola bus interface.
CSB#
(A3)
11 20 17 IWhen 16/68# pin is at logic 1, this input is chip select B (active low)
to enable channel B in the device.
When 16/68# pin is at logic 0, this input becomes address line A3
which is used for channel selection in the Motorola bus interface.
CSC#
(A4)
38 50 64 IWhen 16/68# pin is at logic 1, this input is chip select C (active low)
to enable channel C in the device.
When 16/68# pin is at logic 0, this input becomes address line A4
which is used for channel selection in the Motorola bus interface.
CSD#
(VCC)
42 54 68 IWhen 16/68# pin is at logic 1, this input is chip select D (active low)
to enable channel D in the device.
When 16/68# pin is at logic 0, this input is not used and should be
connected VCC.
xr ST16C654/654D
REV. 5.0.2 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
5
INTA
(IRQ#)
615 12 O
(OD)
When 16/68# pin is at logic 1 for Intel bus interface, this ouput
becomes channel A interrupt output. The output state is defined by
the user and through the software setting of MCR[3]. INTA is set to
the active mode when MCR[3] is set to a logic 1. INTA is set to the
three state mode when MCR[3] is set to a logic 0 (default). See
MCR[3].
When 16/68# pin is at logic 0 for Motorola bus interface, this output
becomes device interrupt output (active low, open drain). An exter-
nal pull-up resistor is required for proper operation.
INTB
INTC
INTD
(N.C.)
12
37
43
21
49
55
18
63
69
OWhen 16/68# pin is at logic 1 for Intel bus interface, these ouputs
become the interrupt outputs for channels B, C, and D. The output
state is defined by the user through the software setting of MCR[3].
The interrupt outputs are set to the active mode when MCR[3] is set
to a logic 1 and are set to the three state mode when MCR[3] is set
to a logic 0 (default). See MCR[3].
When 16/68# pin is at logic 0 for Motorola bus interface, these out-
puts are unused and will stay at logic zero level. Leave these out-
puts unconnected.
INTSEL -65 87 IInterrupt Select (active high, input with internal pull-down).
When 16/68# pin is at logic 1 for Intel bus interface, this pin can be
used in conjunction with MCR bit-3 to enable or disable the INT A-D
pins or override MCR bit-3 and enable the interrupt outputs. Inter-
rupt outputs are enabled continuously by making this pin a logic 1.
Making this pin a logic 0 allows MCR bit-3 to enable and disable the
interrupt output pins. In this mode, MCR bit-3 is set to a logic 1 to
enable the continuous output. See MCR bit-3 description for full
detail. This pin must be at logic 0 in the Motorola bus interface
mode. Due to pin limitations on 64 pin packages, this pin is not
available. To cover this limitation, two 64 pin LQFP packages ver-
sions are offered. This pin is bonded to VCC internally in the
ST16C654D so the INT outputs operate in the continuous interrupt
mode. This pin is bonded to GND internally in the ST16C654 and
therefore requires setting MCR bit-3 for enabling the interrupt output
pins.
TXRDYA#
TXRDYB#
TXRDYC#
TXRDYD#
-
-
-
-
-
-
-
-
5
25
56
81
OUART channels A-D Transmitter Ready (active low). The outputs
provide the TX FIFO/THR status for transmit channels A-D. See
Table 5. If these outputs are unused, leave them unconnected.
RXRDYA#
RXRDYB#
RXRDYC#
RXRDYD#
-
-
-
-
-
-
-
-
100
31
50
82
OUART channels A-D Receiver Ready (active low). This output pro-
vides the RX FIFO/RHR status for receive channels A-D. See
Table 5. If these outputs are unused, leave them unconnected.
TXRDY# -39 45 OTransmitter Ready (active low). This output is a logically ANDed
status of TXRDY# A-D. See Table 5. If this output is unused, leave
it unconnected.
RXRDY# -38 44 OReceiver Ready (active low). This output is a logically ANDed status
of RXRDY# A-D. See Ta b l e 5. If this output is unused, leave it
unconnected.
Pin Description
NAME 64-LQFP
PIN #
68-PLCC
PIN#
100-QFP
PIN # TYPE DESCRIPTION
ST16C654/654D xr
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0.2
6
FSRS# - - 76 IFIFO Status Register Select (active low input with internal pull-up).
The content of the FSTAT register is placed on the data bus when
this pin becomes active. However it should be noted, D0-D3 contain
the inverted logic states of TXRDY# A-D pins, and D4-D7 the logic
states (un-inverted) of RXRDY# A-D pins. A valid address is not
required when reading this status register.
MODEM OR SERIAL I/O INTERFACE
TXA
TXB
TXC
TXD
8
10
39
41
17
19
51
53
14
16
65
67
OUART channels A-D Transmit Data and infrared transmit data.
Standard transmit and receive interface is enabled when MCR[6] =
0. In this mode, the TX signal will be a logic 1 during reset, or idle
(no data). Infrared IrDA transmit and receive interface is enabled
when MCR[6] = 1. In the Infrared mode, the inactive state (no data)
for the Infrared encoder/decoder interface is a logic 0.
IRTXA
IRTXB
IRTXC
IRTXD
-
-
-
-
-
-
-
-
6
24
57
75
OUART channel A-D Infrared Transmit Data. The inactive state (no
data) for the Infrared encoder/decoder interface is a logic 0.
Regardless of the logic state of MCR bit-6, this pin will be operating
in the Infrared mode.
RXA
RXB
RXC
RXD
62
20
29
51
7
29
41
63
97
34
47
85
IUART channel A-D Receive Data or infrared receive data. Normal
receive data input must idle at logic 1 condition.
RTSA#
RTSB#
RTSC#
RTSD#
5
13
36
44
14
22
48
56
11
19
62
70
OUART channels A-D Request-to-Send (active low) or general pur-
pose output. This output must be asserted prior to using auto RTS
flow control, see EFR[6], MCR[1], and IER[6]. Also see Figure 11.
If these outputs are not used, leave them unconnected.
CTSA#
CTSB#
CTSC#
CTSD#
2
16
33
47
11
25
45
59
8
22
59
73
IUART channels A-D Clear-to-Send (active low) or general purpose
input. It can be used for auto CTS flow control, see EFR[7], and
IER[7]. Also see Figure 11. These inputs should be connected to
VCC when not used.
DTRA#
DTRB#
DTRC#
DTRD#
3
15
34
46
12
24
46
58
9
21
60
72
OUART channels A-D Data-Terminal-Ready (active low) or general
purpose output. If these outputs are not used, leave them uncon-
nected.
DSRA#
DSRB#
DSRC#
DSRD#
1
17
32
48
10
26
44
60
7
23
58
74
IUART channels A-D Data-Set-Ready (active low) or general pur-
pose input. This input should be connected to VCC when not used.
This input has no effect on the UART.
CDA#
CDB#
CDC#
CDD#
64
18
31
49
9
27
43
61
99
32
49
83
IUART channels A-D Carrier-Detect (active low) or general purpose
input. This input should be connected to VCC when not used. This
input has no effect on the UART.
Pin Description
NAME 64-LQFP
PIN #
68-PLCC
PIN#
100-QFP
PIN # TYPE DESCRIPTION
xr ST16C654/654D
REV. 5.0.2 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
7
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
RIA#
RIB#
RIC#
RID#
63
19
30
50
8
28
42
62
98
33
48
84
IUART channels A-D Ring-Indicator (active low) or general purpose
input. This input should be connected to VCC when not used. This
input has no effect on the UART.
ANCILLARY SIGNALS
XTAL1 25 35 40 ICrystal or external clock input.
XTAL2 26 36 41 OCrystal or buffered clock output.
16/68# -31 36 IIntel or Motorola Bus Select (input with internal pull-up).
When 16/68# pin is at logic 1, 16 or Intel Mode, the device will oper-
ate in the Intel bus type of interface.
When 16/68# pin is at logic 0, 68 or Motorola mode, the device will
operate in the Motorola bus type of interface.
Motorola bus interface is not available on the 64 pin package.
CLKSEL 21 30 35 IBaud-Rate-Generator Input Clock Prescaler Select for channels A-
D. This input is only sampled during power up or a reset. Connect to
VCC for divide by 1 (default) and GND for divide by 4. MCR[7] can
override the state of this pin following a reset or initialization. See
MCR bit-7 and Figure 6 in the Baud Rate Generator section.
CHCCLK - - 42 IThis input provides the clock for UART channel C. An external 16X
baud clock or the crystal oscillator’s output, XTAL2, must be con-
nected to this pin for normal operation. This input may also be used
with MIDI (Musical Instrument Digital Interface) applications when
an external MIDI clock is provided. This pin is only available in the
100-pin QFP package.
RESET
(RESET#)
27 37 43 IWhen 16/68# pin is at logic 1 for Intel bus interface, this input becomes the
Reset pin (active high). In this case, a 40 ns minimum logic 1 pulse
on this pin will reset the internal registers and all outputs. The UART
transmitter output will be held at logic 1, the receiver input will be
ignored and outputs are reset during reset period (Table 16). When
16/68# pin is at a logic 0 for Motorola bus interface, this input
becomes Reset# pin (active low). This pin functions similarly, but
instead of a logic 1 pulse, a 40 ns minimum logic 0 pulse will reset
the internal registers and outputs.
Motorola bus interface is not available on the 64 pin package.
VCC 4, 35, 52 13, 47,
64
10, 61,
86
Pwr 2.97V to 5.5V power supply. The inputs are not 5V tolerant when
operating at 3.3V.
GND 14, 28,
45, 61
6, 23, 40,
57
20, 46,
71, 96
Pwr Power supply common, ground.
N.C. - - 1- 4, 26-
28, 29,
30, 51-
55, 77,
78, 79,
80
No Connection. These pins are not used in either the Intel or Motor-
ola bus modes. These pins are open, but typically, should be con-
nected to GND for good design practice.
Pin Description
NAME 64-LQFP
PIN #
68-PLCC
PIN#
100-QFP
PIN # TYPE DESCRIPTION
ST16C654/654D xr
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0.2
8
1.0 PRODUCT DESCRIPTION
The ST16C654 (654) integrates the functions of 4 enhanced 16C550 Universal Asynchrounous Receiver and
Transmitter (UART). Each UART is independently controlled having its own set of device configuration
registers. The configuration registers set is 16550 UART compatible for control, status and data transfer.
Additionally, each UART channel has 64-bytes of transmit and receive FIFOs, automatic RTS/CTS hardware
flow control, automatic Xon/Xoff and special character software flow control, infrared encoder and decoder
(IrDA ver 1.0), programmable baud rate generator with a prescaler of divide by 1 or 4, and data rate up to 1.5
Mbps. The ST16C654 can operate from 2.97 to 5.5 volts. The 654 is fabricated with an advanced CMOS
process.
Enhanced FIFO
The 654 QUART provides a solution that supports 64 bytes of transmit and receive FIFO memory, instead of
16 bytes in the ST16C554, or one byte in the ST16C454. The 654 is designed to work with high performance
data communication systems, that require fast data processing time. Increased performance is realized in the
654 by the larger transmit and receive FIFOs, FIFO trigger level control and automatic flow control mechanism.
This allows the external processor to handle more networking tasks within a given time. For example, the
ST16C554 with a 16 byte FIFO, unloads 16 bytes of receive data in 1.53 ms (This example uses a character
length of 11 bits, including start/stop bits at 115.2Kbps). This means the external CPU will have to service the
receive FIFO at 1.53 ms intervals. However with the 64 byte FIFO in the 654, the data buffer will not require
unloading/loading for 6.1 ms. This increases the service interval giving the external CPU additional time for
other applications and reducing the overall UART interrupt servicing time. In addition, the programmable FIFO
level trigger interrupt and automatic hardware/software flow control is uniquely provided for maximum data
throughput performance especially when operating in a multi-channel system. The combination of the above
greatly reduces the CPU’s bandwidth requirement, increases performance, and reduces power consumption.
Data Rate
The 654 is capable of operation up to 1.5 Mbps at 5V with 16x internal sampling clock rate. The device can
operate at 5V with a crystal oscillator of up to 24 MHz crystal on pins XTAL1 and XTAL2, or external clock
source of 24 MHz on XTAL1 pin. With a typical crystal of 14.7456 MHz and through a software option, the user
can set the prescaler bit for data rates of up to 921.6 kbps.
Enhanced Features
The rich feature set of the 654 is available through the internal registers. Automatic hardware/software flow
control, selectable transmit and receive FIFO trigger levels, selectable baud rates, infrared encoder/decoder
interface, modem interface controls, and a sleep mode are all standard features. MCR bit-5 provides a facility
for turning off (Xon) software flow control with any incoming (RX) character. In the 16 mode INTSEL and MCR
bit-3 can be configured to provide a software controlled or continuous interrupt capability. Due to pin limitations
for the 64 pin 654 this feature is offered by two different LQFP packages. The ST16C654DCV operates in the
continuous interrupt enable mode by internally bonding INTSEL to VCC. The ST16C654CV operates in
conjunction with MCR bit-3 by internally bonding INTSEL to GND.
The ST16C654 offers a clock prescaler select pin to allow system/board designers to preset the default baud
rate table on power up. The CLKSEL pin selects the div-by-1 or div-by-4 prescaler for the baud rate generator.
It can then be overridden following initialization by MCR bit-7.
The 100 pin packages offer several other enhanced features. These features include a CHCCLK clock input,
FSTAT register and separate IrDA TX outputs. The CHCCLK must be connected to the XTAL2 pin for normal
operation or to external MIDI (Music Instrument Digital Interface) oscillator for MIDI applications. A separate
register (FSTAT) is provided for monitoring the real time status of the FIFO signals TXRDY# and RXRDY# for
each of the four UART channels (A-D). This reduces polling time involved in accessing individual channels.
The 100 pin QFP package also offers four separate IrDA (Infrared Data Association Standard) TX outputs for
Infrared applications. These outputs are provided in addition to the standard asynchronous modem data
outputs.
xr ST16C654/654D
REV. 5.0.2 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
9
2.0 FUNCTIONAL DESCRIPTIONS
2.1 CPU Interface
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The 654 data interface supports the Intel compatible types of CPUs and it is compatible to
the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus
transaction. Each bus cycle is asynchronous using CS# A-D, IOR# and IOW# or CS#, R/W#, A4 and A3 inputs.
All four UART channels share the same data bus for host operations. A typical data bus interconnection for
Intel and Motorola mode is shown in Figure 4.
FIGURE 4. ST16C654/654D TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS
VCC
VCC
DSRA#
CTSA#
RTSA#
DTRA#
RXA
TXA
RIA#
CDA#
GND
A0
A1
A2
UART_CSA#
UART_CSB#
IOR#
IOW#
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
CSA#
CSB#
D0
D1
D2
D3
D4
D5
D6
D7
IOR#
IOW#
UART
Channel A
UART
Channel B
UART_INTB
UART_INTA
INTB
INTA
UART_RESET RESET
Serial Interface of
RS-232
Serial Interface of
RS-232
Intel Data Bus (16 Mode) Interconnections
UART
Channel C
UART
Channel D
Similar
to Ch A
Similar
to Ch A
Similar
to Ch A
UART_INTD
UART_INTC
INTD
INTC
UART_CSC#
UART_CSD#
CSC#
CSD#
VCC 16/68#
VCC
VCC
GND
A0
A1
A2
UART_CS#
A3
R/W#
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
CSA#
CSB#
D0
D1
D2
D3
D4
D5
D6
D7
IOR#
IOW#
UART_IRQ#
INTB
INTA
RESET#
Serial Interface of
RS-232
Serial Interface of
RS-232
Motorola Data Bus (68 Mode) Interconnections
VCC
UART_RESET#
(no connect)
DSRA#
CTSA#
RTSA#
DTRA#
RXA
TXA
RIA#
CDA#
UART
Channel A
UART
Channel B
UART
Channel C
Similar
to Ch A
Similar
to Ch A
Similar
to Ch A
INTC
(no connect)
INTD
(no connect)
A4 CSC#
CSD#
VCC
16/68#
UART
Channel D
ST16C654/654D xr
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0.2
10
2.2 Device Reset
The RESET input resets the internal registers and the serial interface outputs in both channels to their default
state (see Table 16). An active high pulse of longer than 40 ns duration will be required to activate the reset
function in the device. Following a power-on reset or an external reset, the 654 is software compatible with
previous generation of UARTs, 16C454 and 16C554.
2.3 Channel Selection
The UART provides the user with the capability to bi-directionally transfer information between an external
CPU and an external serial communication device. During Intel Bus Mode (16/68# pin is connected to VCC), a
logic 0 on chip select pins, CSA#, CSB#, CSC# or CSD# allows the user to select UART channel A, B, C or D
to configure, send transmit data and/or unload receive data to/from the UART. Selecting all four UARTs can be
useful during power up initialization to write to the same internal registers, but do not attempt to read from all
four uarts simultaneously. Individual channel select functions are shown in Tabl e 1.
During Motorola Bus Mode (16/68# pin is connected to GND), the package interface pins are configured for
connection with Motorola, and other popular microprocessor bus types. In this mode the 654 decodes two
additional addresses, A3 and A4, to select one of the four UART ports. The A3 and A4 address decode
function is used only when in the Motorola Bus Mode. See Table 2.
TABLE 1: CHANNEL A-D SELECT IN 16 MODE
CSA
#
CSB
#
CSC
#
CSD
#FUNCTION
1111 UART de-selected
0111 Channel A selected
1011 Channel B selected
1101 Channel C selected
1110 Channel D selected
0000 Channels A-D selected
TABLE 2: CHANNEL A-D SELECT IN 68 MODE
CS# A4 A3 FUNCTION
1 N/A N/A UART de-selected
000 Channel A selected
001 Channel B selected
010 Channel C selected
011 Channel D selected
xr ST16C654/654D
REV. 5.0.2 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
11
2.4 Channels A-D Internal Registers
Each UART channel in the 654 has a set of enhanced registers for control, monitoring and data loading and
unloading. The configuration register set is compatible to those already available in the standard single
16C550. These registers function as data holding registers (THR/RHR), interrupt status and control registers
(ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/LCR), modem status
and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM), and a user
accessible scratchpad register (SPR).
Beyond the general 16C550 features and capabilities, the 654 offers enhanced feature registers (EFR, Xon/
Xoff 1, Xon/Xoff 2, FSTAT) that provide automatic RTS and CTS hardware flow control and automatic Xon/Xoff
software flow control. All the register functions are discussed in full detail later in “Section 3.0, UART
INTERNAL REGISTERS” on page 22.
2.5 INT Ouputs for Channels A-D
The interrupt outputs change according to the operating mode and enhanced features setup. Tab l e 3 and 4
summarize the operating behavior for the transmitter and receiver. Also see Figure 20 through 25.
2.6 DMA Mode
The device does not support direct memory access. The DMA Mode (a legacy term) in this document does not
mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of
the RXRDY# A-D and TXRDY# A-D output pins. The transmit and receive FIFO trigger levels provide
additional flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the
transmitter is empty or has an empty location(s) for more data. The user can optionally operate the transmit
and receive FIFO in the DMA mode (FCR bit-3=1). When the transmit and receive FIFOs are enabled and the
DMA mode is disabled (FCR bit-3 = 0), the 654 is placed in single-character mode for data transmit or receive
operation. When DMA mode is enabled (FCR bit-3 = 1), the user takes advantage of block mode operation by
loading or unloading the FIFO in a block sequence determined by the programmed trigger level. The following
table show their behavior. Also see Figure 20 through 25.
TABLE 3: INT PINS OPERATION FOR TRANSMITTER FOR CHANNELS A-D
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1 (FIFO ENABLED)
FCR Bit-3 = 0
(DMA Mode Disabled)
FCR Bit-3 = 1
(DMA Mode Enabled)
INT Pin 0 = a byte in THR
1 = THR empty
0 = FIFO above trigger level
1 = FIFO below trigger level or FIFO
empty
0 = FIFO above trigger level
1 = FIFO below trigger level or FIFO
empty
TABLE 4: INT PIN OPERATION FOR RECEIVER FOR CHANNELS A-D
FCR BIT-0 = 0
(FIFO DISABLED)FCR BIT-0 = 1 (FIFO ENABLED)
FCR Bit-3 = 0
(DMA Mode Disabled)
FCR Bit-3 = 1
(DMA Mode Enabled)
INT Pin 0 = no data
1 = 1 byte
0 = FIFO below trigger level
1 = FIFO above trigger level
0 = FIFO below trigger level
1 = FIFO above trigger level
ST16C654/654D xr
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0.2
12
2.7 Crystal Oscillator or External Clock Input
The 654 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the
device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin being the output. For programming details, see “Section
2.8, Programmable Baud Rate Generator” on page 12
FIGURE 5. TYPICAL OSCILLATOR CONNECTIONS
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins. Typical oscillator connections are shown
in Figure 5. Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal baud rate
generator for standard or custom rates. For further reading on oscillator circuit please see application note
DAN108 on EXAR’s web site.
2.8 Programmable Baud Rate Generator
Each UART has its own Baud Rate Generator (BRG) with a prescaler. The prescaler is controlled by a
software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide the input crystal or external
clock by 1 or 4. The clock output of the prescaler goes to the BRG. The BRG further divides this clock by a
programmable divisor between 1 and (216 -1) to obtain a 16X sampling rate clock of the serial data rate. The
sampling rate clock is used by the transmitter for data bit shifting and receiver for data sampling.
TABLE 5: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE FOR CHANNELS A-D
PINS FCR BIT-0=0
(FIFO DISABLED)FCR BIT-0=1 (FIFO ENABLED)
FCR BIT-3 = 0
(DMA MODE DISABLED)
FCR BIT-3 = 1
(DMA MODE ENABLED)
RXRDY# 0 = 1 byte
1 = no data
0 = at least 1 byte in FIFO
1 = FIFO empty
1 to 0 transition when FIFO reaches the trigger
level, or timeout occurs.
0 to 1 transition when FIFO empties.
TXRDY# 0 = THR empty
1 = byte in THR
0 = FIFO empty
1 = at least 1 byte in FIFO
0 = FIFO has at least 1 empty location.
1 = FIFO is full.
C1
22-47pF
C2
22-47pF
14.7456
MHz
XTAL1 XTAL2
R=300K to 400K
xr ST16C654/654D
REV. 5.0.2 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
13
Tab l e 6 shows the standard data rates available with a 14.7456 MHz crystal or external clock at 16X sampling
rate. When using a non-standard frequency crystal or external clock, the divisor value can be calculated for
DLL/DLM with the following equation.
2.9 Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 64 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal
clock. A bit time is 16 clock periods. The transmitter sends the start-bit followed by the number of data bits,
inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are reported in
the Line Status Register (LSR bit-5 and bit-6).
2.9.1 Transmit Holding Register (THR) - Write Only
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 64 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
FIGURE 6. BAUD RATE GENERATOR AND PRESCALER
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16)
TABLE 6: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK
OUTPUT Data Rate
MCR Bit-7=1
OUTPUT Data Rate
MCR Bit-7=0
(DEFAULT)
DIVISOR FOR 16x
Clock (Decimal)
DIVISOR FOR 16x
Clock (HEX)
DLM
PROGRAM
VALUE (HEX)
DLL
PROGRAM
VALUE (HEX)
DATA RATE
ERROR (%)
100
600
1200
2400
4800
9600
19.2k
38.4k
57.6k
115.2k
230.4k
400
2400
4800
9600
19.2k
38.4k
76.8k
153.6k
230.4k
460.8k
921.6k
2304
384
192
96
48
24
12
6
4
2
1
900
180
C0
60
30
18
0C
06
04
02
01
09
01
00
00
00
00
00
00
00
00
00
00
80
C0
60
30
18
0C
06
04
02
01
0
0
0
0
0
0
0
0
0
0
0
XTAL1
XTAL2
Crystal
Osc/
Buffer
MCR Bit-7=0
(default)
MCR Bit-7=1
DLL and DLM
Registers
Prescaler
Divide by 1
Prescaler
Divide by 4
16X
Sampling
Rate Clock to
Transmitter
Baud Rate
Generator
Logic
ST16C654/654D xr
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0.2
14
2.9.2 Transmitter Operation in non-FIFO Mode
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
2.9.3 Transmitter Operation in FIFO Mode
The host may fill the transmit FIFO with up to 64 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
FIFO becomes empty. The transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set
when TSR/FIFO becomes empty.
FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE
FIGURE 8. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE
Transmit
Holding
Register
(THR)
Transmit Shift Register (TSR)
Data
Byte
L
S
B
M
S
B
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
TXNOFIFO1
16X
Clock
Transmit Data Shift Register
(TSR)
Data Byte
THR Interrupt (ISR bit-1) falls
below the programmed Trigger
Level and then when becomes
empty. FIFO is Enabled by FCR
bit-0=1
RX FIFO
16X Clock
Auto CTS Flow Control (CTS# pin)
Auto Software Flow Control
Flow Control Characters
(Xoff1/2 and Xon1/2 Reg.
TXFIFO1
THR
xr ST16C654/654D
REV. 5.0.2 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
15
2.10 Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and 64 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X clock for timing. It verifies and validates
every bit on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit,
an internal receiver counter starts counting at the 16X clock rate. After 8 clocks the start bit period should be at
the center of the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating
the start bit in this manner prevents the receiver from assembling a false character. The rest of the data bits
and stop bits are sampled and validated in this same manner to prevent false framing. If there were any
error(s), they are reported in the LSR register bits 2-4. Upon unloading the receive data byte from RHR, the
receive FIFO pointer is bumped and the error tags are immediately updated to reflect the status of the data
byte in RHR register. RHR can generate a receive data ready interrupt upon receiving a character or delay until
it reaches the FIFO trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready
time-out interrupt when data is not received for 4 word lengths as defined by LCR[1:0] plus 12 bits time. This is
equivalent to 3.7-4.6 character times. The RHR interrupt is enabled by IER bit-0.
2.10.1 Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 64 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE
Receive Data Shift
Register (RSR)
Receive
Data Byte
and Errors
RHR Interrupt (ISR bit-2)
Receive Data
Holding Register
(RHR)
RXFIFO1
16X Clock
Receive Data Characters
Data Bit
Validation
Error
Tags in
LSR bits
4:2
ST16C654/654D xr
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0.2
16
2.11 Auto RTS Hardware Flow Control
Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS#
output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control
features is enabled to fit specific application requirement (see Figure 11):
•Enable auto RTS flow control using EFR bit-6.
•The auto RTS function must be started by asserting RTS# output pin (MCR bit-1 to logic 1 after it is enabled).
If needed, the RTS interrupt can be enabled through IER bit-6 (after setting EFR bit-4). The UART issues an
interrupt when the RTS# pin makes a transition from low to high: ISR bit-5 will be set to logic 1.
2.12 Auto CTS Flow Control
Automatic CTS flow control is used to prevent data overrun to the remote receiver FIFO. The CTS# input is
monitored to suspend/restart the local transmitter. The auto CTS flow control feature is selected to fit specific
application requirement (see Figure 11):
•Enable auto CTS flow control using EFR bit-7.
If needed, the CTS interrupt can be enabled through IER bit-7 (after setting EFR bit-4). The UART issues an
interrupt when the CTS# pin is de-asserted (logic 1): ISR bit-5 will be set to 1, and UART will suspend
transmission as soon as the stop bit of the character in process is shifted out. Transmission is resumed after
the CTS# input is re-asserted (logic 0), indicating more data may be sent.
FIGURE 10. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE
Receive Data Shift
Register (RSR)
RXFIFO1
16X Clock
Error Tags
(64-sets)
Error Tags in
LSR bits 4:2
64 bytes by 11-bit
wide
FIFO
Receive Data Characters
FIFO
Trigger=16
Example
:
- RX FIFO trigger level selected at 16 bytes
Data fills to
56
Data falls to
8
Data Bit
Validation
Receive
Data FIFO
Receive
Data
Receive Data
Byte and Errors
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
RTS# de-asserts when data fills above the flow
control trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
RTS# re-asserts when data falls below the flow
control trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
xr ST16C654/654D
REV. 5.0.2 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
17
FIGURE 11. AUTO RTS AND CTS FLOW CONTROL OPERATION
The local UART (UARTA) starts data transfer by asserting RTSA# (1). RTSA# is normally connected to CTSB# (2) of
remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO
(4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and con-
tinues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA
monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows
(7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its trans-
mit shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9),
UARTA re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until
next receive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB
with RTSB# and CTSA# controlling the data flow.
TABLE 7: AUTO RTS/CTS FLOW CONTROL
SELECTED TRIGGER
LEVEL INT PIN ACTIVATION
RTS# PIN
DE-ASSERTED
(LOGIC 1)
RTS# PIN
RE-ASSERTED
(LOGIC 0)
8 8 16 0
16 16 56 8
56 56 60 16
60 60 60 56
RTSA# CTSB#
RXA TXB Transmitter
Receiver FIFO
Trigger Reached
Auto RTS
Trigger Level
Auto CTS
Monitor
RTSA#
TXB
RXA FIFO
CTSB#
Remote UART
UARTB
Local UART
UARTA
ON OFF ON
Suspend Restart
RTS High
Threshold
Data Starts
ON OFF ON
Assert RTS# to Begin
Transmission
1
2
3
4
5
6
7
Receive
Data RTS Low
Threshold
9
10
11
Receiver FIFO
Trigger Reached
Auto RTS
Trigger Level
Transmitter
Auto CTS
Monitor
RTSB#CTSA#
RXBTXA
INTA
(RXA FIFO
Interrupt)
RX FIFO
Trigger Level
RX FIFO
Trigger Level
8
12
RTSCTS1
ST16C654/654D xr
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0.2
18
2.13 Auto Xon/Xoff (Software) Flow Control
When software flow control is enabled (See Table 15), the 654 compares one or two sequential receive data
characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the
programmed values, the 654 will halt transmission (TX) as soon as the current character has completed
transmission. When a match occurs, the Xoff (if enabled via IER bit-5) flag will be set and the interrupt output
pin will be activated. Following a suspension due to a match of the Xoff character, the 654 will monitor the
receive data stream for a match to the Xon-1,2 character. If a match is found, the 654 will resume operation
and clear the flags (ISR bit-4).
Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0. Following reset the user
can write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/
Xoff characters (See Table 15) and suspend/resume transmissions. When double 8-bit Xon/Xoff characters are
selected, the 654 compares two consecutive receive characters with two software flow control 8-bit values
(Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above described flow control
mechanisms, flow control characters are not placed (stacked) in the user accessible RX data buffer or FIFO.
In the event that the receive buffer is overfilling and flow control needs to be executed, the 654 automatically
sends an Xoff message (when enabled) via the serial TX output to the remote modem. The 654 sends the Xoff-
1,2 characters two-character-times (= time taken to send two characters at the programmed baud rate) after
the receive FIFO crosses the programmed trigger level. To clear this condition, the 654 will transmit the
programmed Xon-1,2 characters as soon as receive FIFO is less than one trigger level below the programmed
trigger level. Ta b l e 8 below explains this.
* After the trigger level is reached, an xoff character is sent after a short span of time (= time required to send 2
characters); for example, after 2.083ms has elapsed for 9600 baud and 10-bit word length setting.
2.14 Special Character Detect
A special character detect feature is provided to detect an 8-bit character when bit-5 is set in the Enhanced
Feature Register (EFR). When this character (Xoff2) is detected, it will be placed in the FIFO along with normal
incoming RX data.
The 654 compares each incoming receive character with Xoff-2 data. If a match exists, the received data will
be transferred to the RX FIFO and ISR bit-4 will be set to indicate detection of special character. Although the
Internal Register Table shows Xon, Xoff Registers with eight bits of character information, the actual number of
bits is dependent on the programmed word length. Line Control Register (LCR) bits 0-1 defines the number of
character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. The word length selected by LCR bits 0-1 also
determines the number of bits that will be used for the special character comparison. Bit-0 in the Xon, Xoff
Registers corresponds with the LSB bit for the receive character.
TABLE 8: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL
RX TRIGGER LEVEL INT PIN ACTIVATION XOFF CHARACTER(S) SENT
(CHARACTERS IN RX FIFO)
XON CHARACTER(S) SENT
(CHARACTERS IN RX FIFO)
8 8 8* 0
16 16 16* 8
56 56 56* 16
60 60 60* 56
xr ST16C654/654D
REV. 5.0.2 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
19
2.15 Infrared Mode
The 654 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association)
version 1.0. The IrDA 1.0 standard that stipulates the infrared encoder sends out a 3/16 of a bit wide HIGH-
pulse for each “0” bit in the transmit data stream. This signal encoding reduces the on-time of the infrared LED,
hence reduces the power consumption. See Figure 12 below.
The infrared encoder and decoder are enabled by setting MCR register bit-6 to a ‘1’. When the infrared feature
is enabled, the transmit data output, TX, idles at logic zero level. Likewise, the RX input assumes an idle level
of logic zero from a reset and power up, see Figure 12.
Typically, the wireless infrared decoder receives the input pulse from the infrared sensing diode on the RX pin.
Each time it senses a light pulse, it returns a logic 1 to the data bit stream.
FIGURE 12. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING
Character
Data Bits
Start
Stop
0000 0
11 111
Bit Time
1/16 Clock Delay
IRdecoder
-
RX Data
Receive
IR Pulse
(RX pin)
Character
Data Bits
Start
Stop
0000 0
11 111
TX Data
Transmit
IR Pulse
(TX Pin)
Bit Time 1/2 Bit Time
3/16 Bit Time
IrEncoder-1
ST16C654/654D xr
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0.2
20
2.16 Sleep Mode with Auto Wake-Up
The 654 supports low voltage system designs, hence, a sleep mode is included to reduce its power
consumption when the chip is not actively used.
All of these conditions must be satisfied for the 654 to enter sleep mode:
■no interrupts pending for all four channels of the 654 (ISR bit-0 = 1)
■sleep mode of both channels are enabled (IER bit-4 = 1)
■modem inputs are not toggling (MSR bits 0-3 = 0)
■RX input pins are idling at a logic 1
The 654 stops its crystal oscillator to conserve power in the sleep mode. User can check the XTAL2 pin for no
clock output as an indication that the device has entered the sleep mode.
The 654 resumes normal operation by any of the following:
■a receive data start bit transition (logic 1 to 0)
■a data byte is loaded to the transmitter, THR or FIFO
■a change of logic state on any of the modem or general purpose serial inputs: CTS#, DSR#, CD#, RI#
If the 654 is awakened by any one of the above conditions, it will return to the sleep mode automatically after
all interrupting conditions have been serviced and cleared. If the 2750 is awakened by the modem inputs, a
read to the MSR is required to reset the modem inputs. In any case, the sleep mode will not be entered while
an interrupt is pending from any channel. The 654 will stay in the sleep mode of operation until it is disabled by
setting IER bit-4 to a logic 0.
If the address lines, data bus lines, IOW#, IOR#, CSA#, CSB#, CSC#, CSD# and modem input lines remain
steady when the 654 is in sleep mode, the maximum current will be in the microamp range as specified in the
DC Electrical Characteristics on page 37. If the input lines are floating or are toggling while the 654 is in sleep
mode, the current can be up to 100 times more. If any of those signals are toggling or floating, then an external
buffer would be required to keep the address, data and control lines steady to achieve the low current.
A word of caution: owing to the starting up delay of the crystal oscillator after waking up from sleep mode, the
first few receive characters may be lost. Also, make sure the RX A-D pins are idling at logic 1 or “marking”
condition during sleep mode. This may not occur when the external interface transceivers (RS-232, RS-485 or
another type) are also put to sleep mode and cannot maintain the “marking” condition. To avoid this, the
system design engineer can use a 47k ohm pull-up resistor on each of the RX A-D inputs.
2.17 Internal Loopback
The 654 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback
mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 13 shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX pin is held at logic 1 or mark condition while RTS# and DTR# are de-asserted, and
CTS#, DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held to a logic 1 during loopback
test else upon exiting the loopback test the UART may detect and report a false “break” signal.
xr ST16C654/654D
REV. 5.0.2 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
21
FIGURE 13. INTERNAL LOOP BACK IN CHANNEL A AND B
TX A-D
RX A-D
Modem / General Purpose Control Logic
Internal Data Bus Lines and Control Signals
RTS# A-D
MCR bit-4=1
VCC
VCC
Transmit Shift Register
(THR/FIFO)
Receive Shift Register
(RHR/FIFO)
CTS# A-D
DTR# A-D
DSR# A-D
RI# A-D
CD# A-D
OP1#
OP2#
RTS#
CTS#
DTR#
DSR#
RI#
CD#
VCC
ST16C654/654D xr
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0.2
22
3.0 UART INTERNAL REGISTERS
Each UART channel in the 654 has its own set of configuration registers selected by address lines A0, A1 and
A2 with a specific channel selected (See Table 1 and Tab l e 2). The complete register set is shown on Table 9
and Table 10.
.
TABLE 9: UART CHANNEL A AND B UART INTERNAL REGISTERS
A2,A1,A0 ADDRESSES REGISTER READ/WRITE COMMENTS
16C550 COMPATIBLE REGISTERS
0 0 0 RHR - Receive Holding Register
THR - Transmit Holding Register
Read-only
Write-only LCR[7] = 0
0 0 0 DLL - Div Latch Low Byte Read/Write
LCR[7] = 1, LCR ≠ 0xBF
0 0 1 DLM - Div Latch High Byte Read/Write
0 0 1 IER - Interrupt Enable Register Read/Write
LCR[7] = 0
0 1 0 ISR - Interrupt Status Register
FCR - FIFO Control Register
Read-only
Write-only
0 1 1 LCR - Line Control Register Read/Write
1 0 0 MCR - Modem Control Register Read/Write
LCR[7] = 0
1 0 1 LSR - Line Status Register
Reserved
Read-only
Write-only
1 1 0 MSR - Modem Status Register
Reserved
Read-only
Write-only
1 1 1 SPR - Scratch Pad Register Read/Write
ENHANCED REGISTERS
0 1 0 EFR - Enhanced Function Reg Read/Write
LCR = 0xBF
1 0 0 Xon-1 - Xon Character 1 Read/Write
1 0 1 Xon-2 - Xon Character 2 Read/Write
1 1 0 Xoff-1 - Xoff Character 1 Read/Write
1 1 1 Xoff-2 - Xoff Character 2 Read/Write
X X X FSTAT - FIFO Status Register Read-only FSRS# pin is logic 0
xr ST16C654/654D
REV. 5.0.2 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
23
TABLE 10: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS
A2-A0
REG
NAME
READ/
WRITE BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0 COMMENT
16C550 Compatible Registers
0 0 0 RHR RD Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
LCR[7] = 0
0 0 0 THR WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
0 0 1 IER RD/WR 0/ 0/ 0/ 0/ Modem
Stat. Int.
Enable
RX Line
Stat.
Int.
Enable
TX
Empty
Int
Enable
RX
Data
Int.
Enable
CTS#
Int.
Enable
RTS#
Int.
Enable
Xoff Int.
Enable
Sleep
Mode
Enable
0 1 0 ISR RD FIFOs
Enabled
FIFOs
Enabled
0/ 0/ INT
Source
Bit-3
INT
Source
Bit-2
INT
Source
Bit-1
INT
Source
Bit-0
INT
Source
Bit-5
INT
Source
Bit-4
0 1 0 FCR WR RX FIFO
Trigger
RX FIFO
Trigger
0/ 0/ DMA
Mode
Enable
TX
FIFO
Reset
RX
FIFO
Reset
FIFOs
Enable
TX FIFO
Trigger
TX FIFO
Trigger
0 1 1 LCR RD/WR Divisor
Enable
Set TX
Break
Set Par-
ity
Even
Parity
Parity
Enable
Stop
Bits
Word
Length
Bit-1
Word
Length
Bit-0
1 0 0 MCR RD/WR 0/ 0/ 0/ Internal
Lopback
Enable
INT Out-
put
Enable
(OP2#)
Rsvd
(OP1#)
RTS#
Output
Control
DTR#
Output
Control
LCR[7] = 0
BRG
Pres-
caler
IR Mode
ENable
XonAny
1 0 1 LSR RD RX FIFO
Global
Error
THR &
TSR
Empty
THR
Empty
RX
Break
RX Fram-
ing Error
RX
Parity
Error
RX
Over-
run
Error
RX
Data
Ready
1 1 0 MSR RD CD#
Input
RI#
Input
DSR#
Input
CTS#
Input
Delta
CD#
Delta
RI#
Delta
DSR#
Delta
CTS#
1 1 1 SPR RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 LCR[7] = 0
Baud Rate Generator Divisor
0 0 0 DLL RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 LCR[7] = 1
LCR ≠ 0xBF
0 0 1 DLM RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
ST16C654/654D xr
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0.2
24
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1 Receive Holding Register (RHR) - Read- Only
See “Receiver” on page 15.
4.2 Transmit Holding Register (THR) - Write-Only
See “Transmitter” on page 13.
4.3 Interrupt Enable Register (IER) - Read/Write
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
4.3.1 IER versus Receive FIFO Interrupt Mode Operation
When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts
(see ISR bits 2 and 3) status will reflect the following:
A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed
trigger level. It will be cleared when the FIFO drops below the programmed trigger level.
B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register
status bit and the interrupt will be cleared when the FIFO drops below the trigger level.
C. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to
the receive FIFO. It is reset when the FIFO is empty.
Enhanced Registers
0 1 0 EFR RD/WR Auto
CTS#
Enable
Auto
RTS#
Enable
Special
Char
Select
Enable
IER [7:4],
ISR [5:4],
FCR[5:4],
MCR[7:5]
Soft-
ware
Flow
Cntl
Bit-3
Soft-
ware
Flow
Cntl
Bit-2
Soft-
ware
Flow
Cntl
Bit-1
Soft-
ware
Flow
Cntl
Bit-0
LCR=0XBF
1 0 0 XON1 RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
1 0 1 XON2 RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
1 1 0 XOFF1 RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
1 1 1 XOFF2 RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
X X X FSTAT RD RX-
RDYD#
RX-
RDYC#
RX-
RDYB#
RX-
RDYA#
TX-
RDYD#
TX-
RDYC#
TX-
RDYB#
TX-
RDYA#
FSRS# pin is
a logic 0. No
address lines
required.
TABLE 10: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS
A2-A0
REG
NAME
READ/
WRITE BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0 COMMENT
xr ST16C654/654D
REV. 5.0.2 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
25
4.3.2 IER versus Receive/Transmit FIFO Polled Mode Operation
When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the ST16C654 in the FIFO
polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can
be used in the polled mode by selecting respective transmit or receive control bit(s).
A. LSR BIT-0 indicates there is data in RHR or RX FIFO.
B. LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid.
C. LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.
D. LSR BIT-5 indicates THR is empty.
E. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty.
F. LSR BIT-7 indicates a data error in at least one character in the RX FIFO.
IER[0]: RHR Interrupt Enable
The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when
the receive FIFO has reached the programmed trigger level in the FIFO mode.
Logic 0 = Disable the receive data ready interrupt (default).
Logic 1 = Enable the receiver data ready interrupt.
IER[1]: THR Interrupt Enable
This bit enables the Transmit Ready interrupt which is issued whenever the THR becomes empty in the non-
FIFO mode or when data in the FIFO falls below the programmed trigger level in the FIFO mode. If the THR is
empty when this bit is enabled, an interrupt will be generated.
Logic 0 = Disable Transmit Ready interrupt (default).
Logic 1 = Enable Transmit Ready interrupt.
IER[2]: Receive Line Status Interrupt Enable
If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller
about the error status of the current data byte in FIFO. LSR bit-1 generates an interrupt immediately when an
overrun occurs. LSR bits 2-4 generate an interrupt when the character in the RHR has an error.
•Logic 0 = Disable the receiver line status interrupt (default).
•Logic 1 = Enable the receiver line status interrupt.
IER[3]: Modem Status Interrupt Enable
•Logic 0 = Disable the modem status register interrupt (default).
•Logic 1 = Enable the modem status register interrupt.
IER[4]: Sleep Mode Enable (requires EFR[4] = 1)
•Logic 0 = Disable Sleep Mode (default).
•Logic 1 = Enable Sleep Mode. See Sleep Mode section for further details.
IER[5]: Xoff Interrupt Enable (requires EFR[4]=1)
•Logic 0 = Disable the software flow control, receive Xoff interrupt. (default)
•Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for
details.
IER[6]: RTS# Output Interrupt Enable (requires EFR[4]=1)
•Logic 0 = Disable the RTS# interrupt (default).
•Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition
from low to high (if enabled by EFR bit-6).
ST16C654/654D xr
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0.2
26
IER[7]: CTS# Input Interrupt Enable (requires EFR[4]=1)
•Logic 0 = Disable the CTS# interrupt (default).
•Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from
low to high (if enabled by EFR bit-7).
4.4 Interrupt Status Register (ISR) - Read-Only
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table, Ta b l e 11, shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources
associated with each of these interrupt levels.
4.4.1 Interrupt Generation:
•LSR is by any of the LSR bits 1, 2, 3 and 4.
•RXRDY is by RX trigger level.
•RXRDY Time-out is by a 4-char plus 12 bits delay timer.
•TXRDY is by TX trigger level or TX FIFO empty.
•MSR is by any of the MSR bits 0, 1, 2 and 3.
•Receive Xoff/Special character is by detection of a Xoff or Special character.
•CTS# is when the remote transmitter toggles the input pin (from low to high) during auto CTS flow control.
•RTS# is when its receiver toggles the output pin (from low to high) during auto RTS flow control.
4.4.2 Interrupt Clearing:
•LSR interrupt is cleared by a read to the LSR register (LSR bits 1-4 will clear but LSR bit-7 will not clear until
character(s) that generated the interrupt(s) has been emptied or cleared from FIFO).
•RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
•RXRDY Time-out interrupt is cleared by reading RHR.
•TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
•MSR interrupt is cleared by a read to the MSR register.
•Xoff interrupt is cleared by a read to ISR.
•Special character interrupt is cleared by a read to ISR register or after next character is received.
•RTS# and CTS# flow control interrupts are cleared by a read to the MSR register.
xr ST16C654/654D
REV. 5.0.2 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
27
]
ISR[0]: Interrupt Status
•Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
•Logic 1 = No interrupt pending (default condition).
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source Tab l e 11).
ISR[4]: Interrupt Status
This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that the receiver detected a data match
of the Xoff character(s) or a special character.
ISR[5]: Interrupt Status
This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-5 indicates that CTS# or RTS# has changed state
from a logic low to logic high.
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
4.5 FIFO Control Register (FCR) - Write-Only
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode. The DMA, and FIFO modes are defined as follows:
FCR[0]: TX and RX FIFO Enable
•Logic 0 = Disable the transmit and receive FIFO (default).
•Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
TABLE 11: INTERRUPT SOURCE AND PRIORITY LEVEL
PRIORITY ISR REGISTER STATUS BITS SOURCE OF INTERRUPT
LEVEL BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0
1 0 0 0 1 1 0 LSR (Receiver Line Status Register)
2 0 0 1 1 0 0 RXRDY (Receive Data Time-out)
3 0 0 0 1 0 0 RXRDY (Received Data Ready)
4 0 0 0 0 1 0 TXRDY (Transmit Ready)
5 0 0 0 0 0 0 MSR (Modem Status Register)
6 0 1 0 0 0 0 RXRDY (Received Xoff or Special character)
7 1 0 0 0 0 0 CTS#, RTS# change of state
- 0 0 0 0 0 1 None (default)
ST16C654/654D xr
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0.2
28
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
•Logic 0 = No receive FIFO reset (default)
•Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
•Logic 0 = No transmit FIFO reset (default).
•Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[3]: DMA Mode Select
Controls the behavior of the -TXRDY and -RXRDY pins. See DMA operation section for details.
•Logic 0 = Normal Operation (default).
•Logic 1 = DMA Mode.
FCR[5:4]: Transmit FIFO Trigger Select
(logic 0 = default, TX trigger level = one)
These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the
number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the
FIFO did not get filled over the trigger level on last re-load. Tabl e 12 below shows the selections. EFR bit-4
must be set to ‘1’ before these bits can be accessed. Note that the receiver and the transmitter cannot use
different trigger tables. Whichever selection is made last applies to both the RX and TX side.
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO crosses the trigger level. Table 12 shows the complete selections.
TABLE 12: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION
FCR
BIT-7
FCR
BIT-6
FCR
BIT-5
FCR
BIT-4
RECEIVE
TRIGGER
LEVEL
TRANSMIT
TRIGGER
LEVEL
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
8
16
56
60
8
16
32
56
xr ST16C654/654D
REV. 5.0.2 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
29
4.6 Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in conjunction with the programmed word length.
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See Tab l e 13 for parity selection summary below.
•Logic 0 = No parity.
•Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.
LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format.
•Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format (default).
•Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format.
BIT-1 BIT-0 WORD LENGTH
0 0 5 (default)
0 1 6
1 0 7
1 1 8
BIT-2 WORD
LENGTH
STOP BIT LENGTH
(BIT TIME(S))
05,6,7,8 1 (default)
1 5 1-1/2
16,7,8 2
ST16C654/654D xr
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0.2
30
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR BIT-5 selects the forced parity format.
•LCR BIT-5 = logic 0, parity is not forced (default).
•LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive
data.
•LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive
data.
LCR[6]: Transmit Break Enable
When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a
“space’, logic 0, state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.
•Logic 0 = No TX break condition. (default)
•Logic 1 = Forces the transmitter output (TX) to a “space”, logic 0, for alerting the remote receiver of a line
break condition.
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL/DLM) enable.
•Logic 0 = Data registers are selected. (default)
•Logic 1 = Divisor latch registers are selected.
4.7 Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write
The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Output
The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
•Logic 0 = Force DTR# output to a logic 1 (default).
•Logic 1 = Force DTR# output to a logic 0.
MCR[1]: RTS# Output
The RTS# pin is a modem control output and may be used for automatic hardware flow control by enabled by
EFR bit-6. If the modem interface is not used, this output may be used as a general purpose output.
•Logic 0 = Force RTS# output to a logic 1 (default).
•Logic 1 = Force RTS# output to a logic 0.
MCR[2]: Reserved
OP1# is not available as an output pin on the 654. But it is available for use during Internal Loopback Mode. In
the Loopback Mode, this bit is used to write the state of the modem RI# interface signal.
TABLE 13: PARITY SELECTION
LCR BIT-5 LCR BIT-4 LCR BIT-3 PARITY SELECTION
X X 0 No parity
0 0 1 Odd parity
0 1 1 Even parity
1 0 1 Force parity to mark,
“1”
1 1 1 Forced parity to
space, “0”
xr ST16C654/654D
REV. 5.0.2 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
31
MCR[3]: INT Output Enable
Enable or disable INT outputs to become active or in three-state. This function is associated with the INTSEL
input, see below table for details. This bit is also used to control the OP2# signal during internal loopback
mode. INTSEL pin must be set to a logic zero during 68 mode.
•Logic 0 = INT (A-D) outputs disabled (three state) in the 16 mode (default). During loopback mode, it sets
OP2# internally to a logic 1.
•Logic 1 = INT (A-D) outputs enabled (active) in the 16 mode. During loopback mode, it sets OP2# internally
to a logic 0.
MCR[4]: Internal Loopback Enable
•Logic 0 = Disable loopback mode (default).
•Logic 1 = Enable local loopback mode, see loopback section and Figure 13.
MCR[5]: Xon-Any Enable
•Logic 0 = Disable Xon-Any function (for 16C550 compatibility, default).
•Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation.
The RX character will be loaded into the RX FIFO , unless the RX character is an Xon or Xoff character and
the 654 is programmed to use the Xon/Xoff flow control.
MCR[6]: Infrared Encoder/Decoder Enable
•Logic 0 = Enable the standard modem receive and transmit input/output interface. (Default)
•Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. The TX/RX output/input are routed to the
infrared encoder/decoder. The data input and output levels conform to the IrDA infrared interface
requirement. The RX FIFO may need to be flushed upon enable. While in this mode, the infrared TX output
will be a logic 0 during idle data conditions.
MCR[7]: Clock Prescaler Select
•Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the Programmable
Baud Rate Generator without further modification, i.e., divide by one (default).
•Logic 1 = Divide by four. The prescaler divides the input clock from the crystal or external clock by four and
feeds it to the Programmable Baud Rate Generator, hence, data rates become one forth.
4.8 Line Status Register (LSR) - Read Only
This register provides the status of data transfers between the UART and the host. If IER bit-2 is enabled, LSR
bit 1 will generate an interrupt immediately and LSR bits 2-4 will generate an interrupt when a character with an
error is in the RHR.
LSR[0]: Receive Data Ready Indicator
•Logic 0 = No data in receive holding register or FIFO (default).
•Logic 1 = Data has been received and is saved in the receive holding register or FIFO.
TABLE 14: INT OUTPUT MODES
INTSEL
PIN
MCR
BIT-3 INT A-D OUTPUTS IN 16 MODE
0 0 Three-State
0 1 Active
1 X Active
ST16C654/654D xr
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0.2
32
LSR[1]: Receiver Overrun Flag
•Logic 0 = No overrun error (default).
•Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens
when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register
is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into
the FIFO, therefore the data in the FIFO is not corrupted by the error.
LSR[2]: Receive Data Parity Error Tag
•Logic 0 = No parity error (default).
•Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect.
This error is associated with the character available for reading in RHR.
LSR[3]: Receive Data Framing Error Tag
•Logic 0 = No framing error (default).
•Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with
the character available for reading in RHR.
LSR[4]: Receive Break Tag
•Logic 0 = No break condition (default).
•Logic 1 = The receiver received a break signal (RX was a logic 0 for at least one character frame time). In the
FIFO mode, only one break character is loaded into the FIFO. The break indication remains until the RX
input returns to the idle condition, “mark” or logic 1.
LSR[5]: Transmit Holding Register Empty Flag
This bit is the Transmit Holding Register Empty indicator. The THR bit is set to a logic 1 when the last data byte
is transferred from the transmit holding register to the transmit shift register. The bit is reset to logic 0
concurrently with the data loading to the transmit holding register by the host. In the FIFO mode this bit is set
when the transmit FIFO is empty, it is cleared when the transmit FIFO contains at least 1 byte.
LSR[6]: THR and TSR Empty Flag
This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or
TSR contains a data character. In the FIFO mode this bit is set to a logic 1 whenever the transmit FIFO and
transmit shift register are both empty.
LSR[7]: Receive FIFO Data Error Flag
•Logic 0 = No FIFO error (default).
•Logic 1 = A global indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error
or break indication is in the FIFO data. This bit clears when there is no more error(s) in any of the bytes in the
RX FIFO.
4.9 Modem Status Register (MSR) - Read Only
This register provides the current state of the modem interface input signals. Lower four bits of this register are
used to indicate the changed information. These bits are set to a logic 1 whenever a signal from the modem
changes state. These bits may be used for general purpose inputs when they are not used with modem
signals.
MSR[0]: Delta CTS# Input Flag
•Logic 0 = No change on CTS# input (default).
•Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
xr ST16C654/654D
REV. 5.0.2 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
33
MSR[1]: Delta DSR# Input Flag
•Logic 0 = No change on DSR# input (default).
•Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[2]: Delta RI# Input Flag
•Logic 0 = No change on RI# input (default).
•Logic 1 = The RI# input has changed from a logic 0 to a logic 1, ending of the ringing signal. A modem status
interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[3]: Delta CD# Input Flag
•Logic 0 = No change on CD# input (default).
•Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem
status interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[4]: CTS Input Status
CTS# pin may function as automatic hardware flow control signal input if it is enabled and selected by Auto
CTS (EFR bit-7). Auto CTS flow control allows starting and stopping of local data transmissions based on the
modem CTS# signal. A logic 1 on the CTS# pin will stop UART transmitter as soon as the current character
has finished transmission, and a logic 0 will resume data transmission. Normally MSR bit-4 bit is the
compliment of the CTS# input. However in the loopback mode, this bit is equivalent to the RTS# bit in the MCR
register. The CTS# input may be used as a general purpose input when the modem interface is not used.
MSR[5]: DSR Input Status
DSR# (active high, logical 1). Normally this bit is the compliment of the DSR# input. In the loopback mode, this
bit is equivalent to the DTR# bit in the MCR register. The DSR# input may be used as a general purpose input
when the modem interface is not used.
MSR[6]: RI Input Status
RI# (active high, logical 1). Normally this bit is the compliment of the RI# input. In the loopback mode this bit is
equivalent to bit-2 in the MCR register. The RI# input may be used as a general purpose input when the
modem interface is not used.
MSR[7]: CD Input Status
CD# (active high, logical 1). Normally this bit is the compliment of the CD# input. In the loopback mode this bit
is equivalent to bit-3 in the MCR register. The CD# input may be used as a general purpose input when the
modem interface is not used.
4.10 Scratch Pad Register (SPR) - Read/Write
This is a 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
4.11 Baud Rate Generator Registers (DLL and DLM) - Read/Write
The concatenation of the contents of DLM and DLL gives the 16-bit divisor value which is used to calculate the
baud rate:
•Baud Rate = (Clock Frequency / 16) / Divisor
See MCR bit-7 and the baud rate table also.
4.12 Enhanced Feature Register (EFR) - Read/Write
Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see Tab le 15). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
ST16C654/654D xr
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0.2
34
EFR[3:0]: Software Flow Control Select
Single character and dual sequential characters software flow control is supported. Combinations of software
flow control can be selected by programming these bits.
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7 to be
modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the new values. This
feature prevents legacy software from altering or overwriting the enhanced functions once set. Normally, it is
recommended to leave it enabled, logic 1.
•Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR
bits 5-7 are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and
MCR bits 5-7are set to a logic 0 to be compatible with ST16C550 mode (default).
•Logic 1 = Enables the above-mentioned register bits to be modified by the user.
EFR[5]: Special Character Detect Enable
•Logic 0 = Special Character Detect Disabled (default).
•Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with
data in Xoff-2 register. If a match exists, the receive data will be transferred to FIFO and ISR bit-4 will be set
to indicate detection of the special character. Bit-0 corresponds with the LSB bit of the receive character. If
flow control is set for comparing Xon1, Xoff1 (EFR [1:0]= ‘10’) then flow control and special character work
normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]= ‘01’) then flow control works
normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character
interrupt, if enabled via IER bit-5.
TABLE 15: SOFTWARE FLOW CONTROL FUNCTIONS
EFR BIT-3
CONT-3
EFR BIT-2
CONT-2
EFR BIT-1
CONT-1
EFR BIT-0
CONT-0 TRANSMIT AND RECEIVE SOFTWARE FLOW CONTROL
0 0 0 0 No TX and RX flow control (default and reset)
0 0 X X No transmit flow control
1 0 X X Transmit Xon1, Xoff1
0 1 X X Transmit Xon2, Xoff2
1 1 X X Transmit Xon1 and Xon2, Xoff1 and Xoff2
X X 0 0 No receive flow control
X X 1 0 Receiver compares Xon1, Xoff1
X X 0 1 Receiver compares Xon2, Xoff2
1 0 1 1 Transmit Xon1, Xoff1
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
0 1 1 1 Transmit Xon2, Xoff2
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
1 1 1 1 Transmit Xon1 and Xon2, Xoff1 and Xoff2,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
0 0 1 1 No transmit flow control,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
xr ST16C654/654D
REV. 5.0.2 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
35
EFR[6]: Auto RTS Flow Control Enable
RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is
selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and
RTS de-asserts to a logic 1 at the next upper trigger level/hysteresis level. RTS# will return to a logic 0 when
FIFO data falls below the next lower trigger level/hysteresis level. The RTS# output must be asserted (logic 0)
before the auto RTS can take effect. RTS# pin will function as a general purpose output when hardware flow
control is disabled.
•Logic 0 = Automatic RTS flow control is disabled (default).
•Logic 1 = Enable Automatic RTS flow control.
EFR[7]: Auto CTS Flow Control Enable
Automatic CTS Flow Control.
•Logic 0 = Automatic CTS flow control is disabled (default).
•Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS# input de-asserts to logic
1. Data transmission resumes when CTS# returns to a logic 0.
4.13 Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write
These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2.
For more details, see Tab le 8.
4.14 FIFO Status Register (FSTAT) - Read/Write
This register is applicable only to the 100 pin QFP ST16C654. The FIFO Status Register provides a status
indication for each of the transmit and receive FIFO. These status bits contain the inverted logic states of the
TXRDY# A-D outputs and the (un-inverted) logic states of the RXRDY# A-D outputs. The contents of the
FSTAT register are placed on the data bus when the FSRS# pin (pin 76) is a logic 0. Also see FSRS# pin
description.
FSTAT[3:0]: TXRDY# A-D Status Bits
Please see Table 5 for the interpretation of the TXRDY# signals.
FSTAT[7:4]: RXRDY# A-D Status Bits
Please see Table 5 for the interpretation of the RXRDY# signals.
ST16C654/654D xr
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0.2
36
TABLE 16: UART RESET CONDITIONS FOR CHANNELS A-D
REGISTERS RESET STATE
DLL Bits 7-0 = 0xXX
DLM Bits 7-0 = 0xXX
RHR Bits 7-0 = 0xXX
THR Bits 7-0 = 0xXX
IER Bits 7-0 = 0x00
FCR Bits 7-0 = 0x00
ISR Bits 7-0 = 0x01
LCR Bits 7-0 = 0x00
MCR Bits 7-0 = 0x00
LSR Bits 7-0 = 0x60
MSR Bits 3-0 = Logic 0
Bits 7-4 = Logic levels of the inputs inverted
SPR Bits 7-0 = 0xFF
EFR Bits 7-0 = 0x00
XON1 Bits 7-0 = 0x00
XON2 Bits 7-0 = 0x00
XOFF1 Bits 7-0 = 0x00
XOFF2 Bits 7-0 = 0x00
FSTAT Bits 7-0 = 0xFF
I/O SIGNALS RESET STATE
TX Logic 1
IRTX Logic 0
RTS# Logic 1
DTR# Logic 1
RXRDY# Logic 1
TXRDY# Logic 0
INT ST16C654 = Three-State Condition
ST16C654D = Logic 0
IRQ# Three-State Condition (68 mode, INTSEL = 0)
xr ST16C654/654D
REV. 5.0.2 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
37
Test 1: The following inputs remain steady at VCC or GND state to minimize Sleep current: A0-A2, D0-D7, IOR#, IOW#,
CSA#, CSB#, CSC#, and CSD#. Also, RXA, RXB, RXC, and RXD inputs idle at logic 1 state while asleep.
ABSOLUTE MAXIMUM RATINGS
Power Supply Range 7 Volts
Voltage at Any Pin GND-0.3 V to 7 V
Operating Temperature -40o to +85oC
Storage Temperature -65o to +150oC
Package Dissipation 500 mW
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)
Thermal Resistance (64-LQFP) theta-ja = 49oC/W, theta-jc = 10oC/W
Thermal Resistance (68-PLCC) theta-ja = 39oC/W, theta-jc = 17oC/W
Thermal Resistance (100-QFP) theta-ja = 45oC/W, theta-jc = 12oC/W
ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS
UNLESS OTHERWISE NOTED: TA=0O TO 70OC (-40O TO +85OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 2.97 TO
5.5V
SYMBOL PARAMETER
LIMITS
3.3V
MIN MAX
LIMITS
5.0V
MIN MAX
UNITS CONDITIONS
VILCK Clock Input Low Level -0.3 0.6 -0.5 0.6 V
VIHCK Clock Input High Level 2.4 VCC 3.0 VCC V
VIL Input Low Voltage -0.3 0.8 -0.5 0.8 V
VIH Input High Voltage 2.0 VCC 2.2 VCC V
VOL Output Low Voltage 0.4 V IOL = 6 mA
VOL Output Low Voltage 0.4 V IOL = 4 mA
VOH Output High Voltage 2.4 V IOH = -6 mA
VOH Output High Voltage 2.0 V IOH = -1 mA
IIL Input Low Leakage Current ±10 ±10 uA
IIH Input High Leakage Current ±10 ±10 uA
CIN Input Pin Capacitance 5 5 pF
ICC Power Supply Current 3 6 mA
ISLEEP Sleep Current 100 200 uA See Test 1
ST16C654/654D xr
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0.2
38
AC ELECTRICAL CHARACTERISTICS
TA=0O TO 70OC (-40O TO +85OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 2.97 TO 5.5V
SYMBOL PARAMETER
LIMITS
3.3
MIN MAX
LIMITS
5.0
MIN MAX
UNIT CONDITIONS
CLK Clock Pulse Duration 40 30 ns
OSC Crystal Frequency 824 MHz
OSC External Clock Frequency 24 32 MHz
TAS Address Setup Time (16 Mode) 10 5ns
TAH Address Hold Time (16 Mode) 5 5 ns
TCS Chip Select Width (16 Mode) 66 50 ns
TRD IOR# Strobe Width (16 Mode) 50 30 ns
TDY Read Cycle Delay (16 Mode) 50 50 ns
TRDV Data Access Time (16 Mode) 45 35 ns
TDD Data Disable Time (16 Mode) 030 020 ns
TWR IOW# Strobe Width (16 Mode) 40 30 ns
TDY Write Cycle Delay (16 Mode) 50 50 ns
TDS Data Setup Time (16 Mode) 20 15 ns
TDH Data Hold Time (16 Mode) 15 10 ns
TADS Address Setup (68 Mode) 10 10 ns
TADH Address Hold (68 Mode) 15 15 ns
TRWS R/W# Setup to CS# (68 Mode) 10 10 ns
TRDA Data Access Time (68 mode) 35 25 ns
TRDH Data Disable Time (68 mode) 25 15 ns
TWDS Write Data Setup (68 mode) 20 15 ns
TWDH Write Data Hold (68 Mode) 10 10 ns
TRWH CS# De-asserted to R/W# De-asserted (68 Mode) 10 10 ns
TCSL CS# Strobe Width (68 Mode) 66 50 ns
TCSD CS# Cycle Delay (68 Mode) 70 70 ns
TWDO Delay From IOW# To Output 50 50 ns 100 pF load
TMOD Delay To Set Interrupt From MODEM Input 50 35 ns 100 pF load
TRSI Delay To Reset Interrupt From IOR# 50 35 ns 100 pF load
xr ST16C654/654D
REV. 5.0.2 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
39
TSSI Delay From Stop To Set Interrupt 1 1 Bclk
TRRI Delay From IOR# To Reset Interrupt 200 200 ns 100 pF load
TSI Delay From Start To Interrupt 100 100 ns
TINT Delay From Initial INT Reset To Transmit Start 824 824 Bclk
TWRI Delay From IOW# To Reset Interrupt 175 175 ns
TSSR Delay From Stop To Set RXRDY# 1 1 Bclk
TRR Delay From IOR# To Reset RXRDY# 175 175 ns
TWT Delay From IOW# To Set TXRDY# 175 175 ns
TSRT Delay From Center of Start To Reset TXRDY# 8 8 Bclk
TRST Reset Pulse Width 40 40 ns
NBaud Rate Divisor 1216-1 1216-1 -
Bclk Baud Clock 16X of data rate Hz
FIGURE 14. CLOCK TIMING
AC ELECTRICAL CHARACTERISTICS
TA=0O TO 70OC (-40O TO +85OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 2.97 TO 5.5V
SYMBOL PARAMETER
LIMITS
3.3
MIN MAX
LIMITS
5.0
MIN MAX
UNIT CONDITIONS
OSC
CLK
CLK
EXTERNAL
CLOCK
ST16C654/654D xr
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0.2
40
FIGURE 15. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A-D
FIGURE 16. 16 MODE (INTEL) DATA BUS READ TIMING FOR CHANNELS A-D
IO W #
IO W
RTS#
DTR#
CD#
CTS#
DSR#
IN T
IO R #
RI#
TWDO
TMOD TMOD
TRSI
TMOD
Active
Active
Change of state Change of state
Active Active Active
Change of state Change of state
Change of state
A c tive A c tive
TAS
TDD
TAH
TRD
TRDV
TDY
TDD
TRDV
TAH
TAS
TCS
Valid Address Valid Address
Valid Data Valid Data
A0-A7
CS#
IOR#
D0-D7
RDTm
TCS
TRD
xr ST16C654/654D
REV. 5.0.2 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
41
FIGURE 17. 16 MODE (INTEL) DATA BUS WRITE TIMING FOR CHANNELS A-D
FIGURE 18. 68 MODE (MOTOROLA) DATA BUS READ TIMING FOR CHANNELS A-D
16Write
TAS
TDH
TAH
TWR
TDS
TDY
TDH
TDS
TAH
TAS
TCS
Valid Address Valid Address
Valid Data Valid Data
A0-A7
CS#
IOW#
D0-D7
TCS
TWR
68Read
TADS
TRDH
TADHTCSL
TRDA
TCSD
TRWS
Valid Address Valid Address
Valid Data
A0-A7
CS#
R/W#
D0-D7
TRWH
Valid Data
ST16C654/654D xr
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0.2
42
FIGURE 19. 68 MODE (MOTOROLA) DATA BUS WRITE TIMING FOR CHANNELS A-D
FIGURE 20. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A-D
68Write
TADS TADHTCSL
TWDS
TCSD
TRWS
Valid Address Valid Address
Valid Data
A0-A7
CS#
R/W#
D0-D7
TRWH
Valid Data
TWDH
RX
RXRDY#
IOR#
INT
D0:D7
Start
Bit D0:D7
Stop
Bit D0:D7
TSSR
1 Byte
in RHR
Active
Data
Ready
Active
Data
Ready
Active
Data
Ready
1 Byte
in RHR
1 Byte
in RHR
TSSR TSSR
RXNFM
TRR TRR TRR
TSSR TSSR TSSR
(Reading data
out of RHR)
xr ST16C654/654D
REV. 5.0.2 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
43
FIGURE 21. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A-D
FIGURE 22. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A-D
TX
TXRDY#
IOW#
INT*
D0:D7
Start
Bit D0:D7
Stop
Bit D0:D7
TWT
TXNonFIFO
TWT TWT
TWRI TWRI TWRI
TSRT TSRT TSRT
*INT is cleared when the ISR is read or when data is loaded into the THR.
ISR is read ISR is readISR is read
(Loading data
into THR)
(Unloading)
IER[1]
enabled
RX
RXRDY#
IOR#
INT
D0:D7
S
TSSR
RXINTDMA#
RX FIFO fills up to RX
Trigger Level or RX Data
Timeout
RX FIFO drops
below RX
Trigger Level
FIFO
Empties
First Byte is
Received in
RX FIFO
D0:D7
SD0:D7TD0:D7
SD0:D7
S
TD0:D7
S
TTD0:D7
ST
Start
Bit
Stop
Bit
TRR
TRRI
TSSI
(Reading data out
of RX FIFO)
ST16C654/654D xr
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0.2
44
FIGURE 23. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A-D
FIGURE 24. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A-D
RX
RXRDY#
IOR#
INT
D0:D7
S
TSSR
RXFIFODMA
RX FIFO fills up to RX
Trigger Level or RX Data
Timeout
RX FIFO drops
below RX
Trigger Level
FIFO
Empties
D0:D7
SD0:D7TD0:D7
SD0:D7
S
TD0:D7
S
TTD0:D7
ST
Start
Bit
Stop
Bit
TRR
TRRI
TSSI
(Reading data out
of RX FIFO)
TX
TXRDY#
IOW#
INT*
TXDMA#
D0:D7
SD0:D7TD0:D7
SD0:D7
S
TD0:D7
S
TTD0:D7
ST
Start
Bit
Stop
Bit
TWRI
(Unloading)
(Loading data
into FIFO)
Last Data Byte
Transmitted
TX FIFO fills up
to trigger level TX FIFO drops
below trigger level
Data in
TX FIFO
TX FIFO
Empty
TWT
TSRT
TX FIFO
Empty
T
TS
TSI
ISR is read
IER[1]
enabled
ISR is read
*INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level.
xr ST16C654/654D
REV. 5.0.2 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
45
FIGURE 25. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A-D
TX
TXRDY#
IOW#
INT*
D0:D7
S
TXDMA
D0:D7
SD0:D7
TD0:D7
SD0:D7S
TD0:D7
S
TTD0:D7ST
Start
Bit
Stop
Bit
TWRI
T
(Unloading)
(Loading data
into FIFO)
Last Data Byte
Transmitted
TX FIFO fills up
to trigger level
TX FIFO drops
below trigger level
At least 1
empty location
in FIFO
TSRT
TX FIFO
Full
TWT
TSI
ISR Read ISR Read
*INT cleared when the ISR is read or when TX FIFO fills up to trigger level.
IER[1]
enabled
ST16C654/654D xr
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0.2
46
PACKAGE DIMENSIONS
64 LEAD LOW-PROFILE QUAD FLAT PACK (10 x 10 x 1.4 mm LQFP)
Note: The control dimension is the millimeter column
INCHES MILLIMETERS
SYMBOL MIN MAX MIN MAX
A0.055 0.063 1.40 1.60
A1 0.002 0.006 0.05 0.15
A2 0.053 0.057 1.35 1.45
B0.007 0.011 0.17 0.27
C0.004 0.008 0.09 0.20
D0.465 0.480 11.80 12.20
D1 0.390 0.398 9.90 10.10
e0.020 BSC 0.50 BSC
L0.018 0.030 0.45 0.75
α0°7°0°7°
48 33
32
17
116
49
64
D
D1
DD1
B
e
A2
α
A1
A
Seating Plane
L
C
xr ST16C654/654D
REV. 5.0.2 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
47
68 LEAD PLASTIC LEADED CHIP CARRIER (PLCC)
Note: The control dimension is the inch column
INCHES MILLIMETERS
SYMBOL MIN MAX MIN MAX
A0.165 0.200 4.19 5.08
A10.090 0.130 2.29 3.30
A20.020 ---. 0.51 ---
B0.013 0.021 0.33 0.53
B10.026 0.032 0.66 0.81
C0.008 0.013 0.19 0.32
D0.985 0.995 25.02 25.27
D10.950 0.958 24.13 24.33
D20.890 0.930 22.61 23.62
D30.800 typ. 20.32 typ.
e0.050 BSC 1.27 BSC
H10.042 0.056 1.07 1.42
H20.042 0.048 1.07 1.22
R0.025 0.045 0.64 1.14
1
D
D
1
D D
1
D
3
D
2
A
A
1
268
B
A
2
B
1
e
Seating Plane
D
3
45
°
x H
2
45
°
x H
1
C
R
ST16C654/654D xr
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0.2
48
100 LEAD PLASTIC QUAD FLAT PACK (14 mm x 20 mm QFP, 1.95 mm Form)
Note: The control dimension is the millimeter column
INCHES MILLIMETERS
SYMBOL MIN MAX MIN MAX
A0.102 0.134 2.60 3.40
A10.002 0.014 0.05 0.35
A20.100 0.120 2.55 3.05
B0.009 0.015 0.22 0.38
C0.004 0.009 0.11 0.23
D0.931 0.951 23.65 24.15
D10.783 0.791 19.90 20.10
E0.695 0.715 17.65 18.15
E10.547 0.555 13.90 14.10
e0.0256 BSC 0.65 BSC
L0.029 0.040 0.73 1.03
α0°7°0°7°
80 51
50
31
130
81
100
D
D
1
E
E
1
B
e
A
2
α
A
1
A
Seating Plane
L
C
p
xr ST16C654/654D
REV. 5.0.2 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
49
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2005 EXAR Corporation
Datasheet August 2005.
Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
REVISION HISTORY
DATE REVISION DESCRIPTION
October 2003 Rev 5.00 Changed to standard style single-column format. Text descriptions were clarified and
simplified (eg. DMA operation, FIFO mode vs. Non-FIFO mode operations etc). Clari-
fied timing diagrams. Renamed Rclk (Receive Clock) to Bclk (Baud Clock) and timing
symbols. Added TCS, TRWS and TRST
.Renamed FIFORdy register to FSTAT register.
March 2005 Rev 5.0.1 Added separate spec for External Clock Frequency in AC Electrical Characteristics.
August 2005 Rev 5.0.2 Updated the 1.4mm-thick Quad Flat Pack package description from "TQFP" to
"LQFP" to be consistent with JEDEC and Industry norms.
ST16C654/654D xr
REV. 5.0.2 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
I
TABLE OF CONTENTS
GENERAL DESCRIPTION .................................................................................................1
FEATURES .....................................................................................................................................................1
APPLICATIONS................................................................................................................................................1
FIGURE 1. ST16C654 BLOCK DIAGRAM ........................................................................................................................................... 1
FIGURE 2. PIN OUT ASSIGNMENT FOR 100-PIN QFP PACKAGES IN 16 AND 68 MODE........................................................................ 2
FIGURE 3. PIN OUT ASSIGNMENT FOR PLCC PACKAGES IN 16 AND 68 MODE AND LQFP PACKAGES................................................ 3
ORDERING INFORMATION.................................................................................................................................3
PIN DESCRIPTIONS .........................................................................................................4
1.0 PRODUCT DESCRIPTION .....................................................................................................................8
2.0 FUNCTIONAL DESCRIPTIONS .............................................................................................................9
2.1 CPU INTERFACE .............................................................................................................................................. 9
FIGURE 4. ST16C654/654D TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS ................................................................... 9
2.2 DEVICE RESET .............................................................................................................................................. 10
2.3 CHANNEL SELECTION .................................................................................................................................. 10
TABLE 1: CHANNEL A-D SELECT IN 16 MODE ................................................................................................................................. 10
TABLE 2: CHANNEL A-D SELECT IN 68 MODE ................................................................................................................................. 10
2.4 CHANNELS A-D INTERNAL REGISTERS .................................................................................................... 11
2.5 INT OUPUTS FOR CHANNELS A-D .............................................................................................................. 11
TABLE 3: INT PINS OPERATION FOR TRANSMITTER FOR CHANNELS A-D ......................................................................................... 11
TABLE 4: INT PIN OPERATION FOR RECEIVER FOR CHANNELS A-D ................................................................................................. 11
2.6 DMA MODE ..................................................................................................................................................... 11
TABLE 5: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE FOR CHANNELS A-D ........................................................... 12
2.7 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT ........................................................................... 12
FIGURE 5. TYPICAL OSCILLATOR CONNECTIONS............................................................................................................................... 12
2.8 PROGRAMMABLE BAUD RATE GENERATOR ........................................................................................... 12
FIGURE 6. BAUD RATE GENERATOR AND PRESCALER ..................................................................................................................... 13
TABLE 6: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK ...................................................................... 13
2.9 TRANSMITTER ............................................................................................................................................... 13
2.9.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY......................................................................................... 13
2.9.2 TRANSMITTER OPERATION IN NON-FIFO MODE .................................................................................................. 14
FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE .............................................................................................................. 14
2.9.3 TRANSMITTER OPERATION IN FIFO MODE ........................................................................................................... 14
FIGURE 8. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE ..................................................................................... 14
2.10 RECEIVER .................................................................................................................................................... 15
2.10.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY .......................................................................................... 15
FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE .................................................................................................................... 15
FIGURE 10. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE ....................................................................... 16
2.11 AUTO RTS HARDWARE FLOW CONTROL ................................................................................................ 16
2.12 AUTO CTS FLOW CONTROL ..................................................................................................................... 16
FIGURE 11. AUTO RTS AND CTS FLOW CONTROL OPERATION ....................................................................................................... 17
TABLE 7: AUTO RTS/CTS FLOW CONTROL .................................................................................................................................... 17
2.13 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL ................................................................................... 18
TABLE 8: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL ............................................................................................................... 18
2.14 SPECIAL CHARACTER DETECT ............................................................................................................... 18
2.15 INFRARED MODE ........................................................................................................................................ 19
FIGURE 12. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING .......................................................................... 19
2.16 SLEEP MODE WITH AUTO WAKE-UP ....................................................................................................... 20
2.17 INTERNAL LOOPBACK .............................................................................................................................. 20
FIGURE 13. INTERNAL LOOP BACK IN CHANNEL A AND B ................................................................................................................ 21
3.0 UART INTERNAL REGISTERS ...........................................................................................................22
TABLE 9: UART CHANNEL A AND B UART INTERNAL REGISTERS...................................................................................... 22
TABLE 10: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1....................................... 23
4.0 INTERNAL REGISTER DESCRIPTIONS .............................................................................................24
4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY ............................................................................... 24
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................ 24
4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE .............................................................................. 24
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................. 24
4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION................................................................ 25
4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ............................................................................... 26
xr ST16C654/654D
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO REV. 5.0.2
II
4.4.1 INTERRUPT GENERATION: ...................................................................................................................................... 26
4.4.2 INTERRUPT CLEARING: ........................................................................................................................................... 26
TABLE 11: INTERRUPT SOURCE AND PRIORITY LEVEL ..................................................................................................................... 27
4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ..................................................................................... 27
TABLE 12: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION ............................................................................................ 28
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ..................................................................................... 29
TABLE 13: PARITY SELECTION ........................................................................................................................................................ 30
4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE 30
TABLE 14: INT OUTPUT MODES ..................................................................................................................................................... 31
4.8 LINE STATUS REGISTER (LSR) - READ ONLY ........................................................................................... 31
4.9 MODEM STATUS REGISTER (MSR) - READ ONLY .................................................................................... 32
4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE .................................................................................... 33
4.11 BAUD RATE GENERATOR REGISTERS (DLL AND DLM) - READ/WRITE .............................................. 33
4.12 ENHANCED FEATURE REGISTER (EFR) - READ/WRITE ........................................................................ 33
TABLE 15: SOFTWARE FLOW CONTROL FUNCTIONS ........................................................................................................................ 34
4.13 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE ................ 35
4.14 FIFO STATUS REGISTER (FSTAT) - READ/WRITE ................................................................................... 35
TABLE 16: UART RESET CONDITIONS FOR CHANNELS A-D ................................................................................................. 36
ABSOLUTE MAXIMUM RATINGS .................................................................................. 37
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%) 37
ELECTRICAL CHARACTERISTICS................................................................................ 37
DC ELECTRICAL CHARACTERISTICS.............................................................................................................. 37
AC ELECTRICAL CHARACTERISTICS.............................................................................................................. 38
TA=0O TO 70OC (-40O TO +85OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 2.97 TO 5.5V ........................ 38
FIGURE 14. CLOCK TIMING............................................................................................................................................................. 39
FIGURE 15. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A-D .................................................................................................... 40
FIGURE 16. 16 MODE (INTEL) DATA BUS READ TIMING FOR CHANNELS A-D ................................................................................... 40
FIGURE 17. 16 MODE (INTEL) DATA BUS WRITE TIMING FOR CHANNELS A-D .................................................................................. 41
FIGURE 18. 68 MODE (MOTOROLA) DATA BUS READ TIMING FOR CHANNELS A-D........................................................................... 41
FIGURE 20. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A-D ............................................................ 42
FIGURE 19. 68 MODE (MOTOROLA) DATA BUS WRITE TIMING FOR CHANNELS A-D ......................................................................... 42
FIGURE 21. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A-D .......................................................... 43
FIGURE 22. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A-D........................................... 43
FIGURE 23. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A-D............................................ 44
FIGURE 24. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A-D .............................. 44
FIGURE 25. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A-D ............................... 45
PACKAGE DIMENSIONS................................................................................................................................. 46
REVISION HISTORY ...................................................................................................................................... 49
TABLE OF CONTENTS ............................................................................................................ I
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Exar:
ST16C654CQ100-F ST16C654CQ64-F ST16C654CJ68-F ST16C654CQ100-0A-EB ST16C654CQ64-0A-EVB
ST16C654DCQ64-0A-EB ST16C654CJ-0A-EVB ST16C654CJ68TR-F ST16C654DCQ64-F ST16C654IQ100-F
ST16C654IQ64-F ST16C654CQ64TR-F ST16C654DIQ64-F ST16C654IJ68-F ST16C654IQ100TR-F
ST16C654DCQ64TR-F ST16C654IQ64TR-F ST16C654CQ100TR-F ST16C654DIQ64TR-F ST16C654IJ68TR-F
