1
LTC1645
1645fa
Dual-Channel Hot Swap
Controller/Power Sequencer
The LTC
®
1645 is a 2-channel Hot Swap
TM
controller that
allows a board to be safely inserted and removed from a
live backplane. Using external N-channel pass transistors,
the supply voltages can be ramped at a programmable
rate. Two high side switch drivers control the N-channel
gates for supply voltages ranging from 1.2V to 12V. The
two channels can be set to ramp up and down separately,
or they can be programmed to rise and fall simultaneously,
ensuring power supply tracking at the two outputs.
Programmable electronic circuit breakers protect against
shorts at either output. The RESET output can be used to
generate a system reset when a supply voltage falls below
a user-programmed voltage. An additional spare com-
parator is available for monitoring a second supply
voltage.
The LTC1645 is available in the 8- and 14-pin SO packages.
■
Hot Board Insertion
■
Power Supply Sequencing
■
Electronic Circuit Breaker
■
Allows Safe Board Insertion and Removal from a
Live Backplane
■
Programmable Power Supply Sequencing
■
Programmable Electronic Circuit Breaker
■
User-Programmable Supply Voltage Power-Up and
Power-Down Rate
■
High Side Drivers for External N-Channel FETs
■
Controls Supply Voltages from 1.2V to 12V
■
Ensures Proper Power-Up Behavior
■
Undervoltage Lockout
■
Glitch Filter Protects Against Spurious RESET Signals
■
8- and 14-Pin SO Packages
, LTC and LT are registered trademarks of Linear Technology Corporation.
Hot Swap is a trademark of Linear Technology Corporation.
5V and 3.3V Hot Swap 5V and 3.3V Hot Swap Waveforms
ON
5V/DIV
GATE
n
10V/DIV
V
OUT2
5V/DIV
V
OUT1
5V/DIV
0.005Ω*IRF7413
IRF7413
0.005Ω*
10Ω10Ω
10k
CLOAD2
CLOAD1
VOUT1
5V
5A
VOUT2
3.3V
5A
1645 TA01
0.01µF
25V
0.01µF
25V
ON
VIN2
VIN1
ON
GND
GND
PLUG-IN CARDBACKPLANE
SENSE1 VCC2
GATE1 SENSE2 GATE2
LTC1645
(8-LEAD)
+
+
CONNECTOR 1
CONNECTOR 2
VCC1
*LRF1206-01-R005-J (IRC)
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
TYPICAL APPLICATIO
U
2
LTC1645
1645fa
Supply Voltage (V
CC1
, V
CC2
) ................................. 13.2V
Input Voltage
FB, ON, COMP
+
..................... –0.3V to (V
CC1
+ 0.3V)
TIMER ................................................. –0.3V to 2.5V
SENSE1 ..................... (V
CC1
– 0.7V) to (V
CC1
+ 0.3V)
SENSE2 ...................... (V
CC1
– 0.7V) to (V
CC2
+ 0.3V)
Output Voltage
RESET, COMPOUT, FAULT .....................–0.3V to 16V
GATE1, GATE2................. Internally Limited (Note 3)
Output Current
GATE1, GATE2............................................... ±20mA
Operating Temperature Range
LTC1645C ............................................... 0°C to 70°C
LTC1645I............................................ –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
DC Characteristics
I
CC1
V
CC1
Supply Current ON = V
CC1
= 5V, V
CC2
= 3.3V ●1.1 2.0 mA
I
CC2
V
CC2
Supply Current ON = V
CC1
= 5V, V
CC2
= 3.3V ●0.28 0.4 mA
V
LKO1
V
CC1
Undervoltage Lockout High to Low ●2.16 2.23 2.3 V
V
LKO2
V
CC2
Undervoltage Lockout High to Low ●1.06 1.12 1.18 V
V
LKH
n
V
CC
n
Undervoltage Lockout Hysteresis 25 mV
V
FB
FB Pin Voltage Threshold High to Low ●1.226 1.238 1.250 V
∆V
FB
FB Pin Threshold Line Regulation High to Low, V
CC1
= 2.375V to 12V ●14 mV
V
FBHST
FB Pin Voltage Threshold Hysteresis 5 mV
V
COMP
COMP
+
Pin Voltage Threshold High to Low ●1.226 1.238 1.250 V
∆V
COMP
COMP
+
Pin Threshold Line Regulation High to Low, V
CC1
= 2.375V to 12V ●14 mV
V
COMPHST
COMP
+
Pin Voltage Threshold Hysteresis 5 mV
(Note 1)
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
2.375V ≤ VCC1 ≤ 12V, 1.2V ≤ VCC2 ≤ 12V unless otherwise noted (Note 2).
TOP VIEW
S PACKAGE
14-LEAD PLASTIC SO
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC2
SENSE2
GATE2
FAULT
RESET
FB
GND
V
CC1
SENSE1
GATE1
TIMER
ON
COMPOUT
COMP
+
T
JMAX
= 125°C, θ
JA
= 110°C/W
TOP VIEW
VCC1
SENSE1
GATE1
ON
VCC2
SENSE2
GATE2
GND
S8 PACKAGE
8-LEAD PLASTIC SO
1
2
3
4
8
7
6
5
T
JMAX
= 125°C, θ
JA
= 150°C/W
ORDER PART
NUMBER
S8 PART MARKING
1645
1645I
LTC1645CS8
LTC1645IS8
ORDER PART
NUMBER
LTC1645CS
LTC1645IS
ABSOLUTE AXI U RATI GS
WWWU
PACKAGE/ORDER I FOR ATIO
UU
W
ELECTRICAL CHARACTERISTICS
Consult LTC Marketing for parts specified with wider operating temperature ranges.
3
LTC1645
1645fa
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
TM
TIMER Pin Voltage Threshold ●1.212 1.230 1.255 V
∆V
TM
TIMER Pin Threshold Line Regulation V
CC1
= 2.375V to 12V ●19 mV
I
TM
TIMER Pin Current Timer On, V
TIMER
= 0.6V, V
CC1
= 5V ●–2.3 –2 –1.7 µA
Timer Off, V
TIMER
= 1.5V 12 mA
V
CB1
Circuit Breaker Trip Voltage 1 V
CB1
= (V
CC1
– V
SENSE1
)●46 50 56 mV
V
CB2
Circuit Breaker Trip Voltage 2 V
CB2
= (V
CC2
– V
SENSE2
)●46 50 56 mV
t
CBD
n
Circuit Breaker Trip Delay V
CB
n
= (V
CC
n
– V
SENSE
n
) > 60mV 1.5 µs
I
CP
GATE
n
Pin Output Current ON = 2.2V, V
GATE
n
= V
CC
n
, V
CC1
= 5V, V
CC2
= 3.3V ●–12.5 – 10 –7.5 µA
ON = 0.7V, V
GATE
n
= V
CC
n
, V
CC1
= 5V, V
CC2
= 3.3V ● 30 40 50 µA
ON = 0.3V, V
GATE
n
= V
CC
n
, V
CC1
= 5V, V
CC2
= 3.3V 12 mA
I
SENSE
SENSE Pin Current V
CC
n
– 0.3V ≤ V
SENSE
n
≤ V
CC
n
+ 0.3V ●–10 10 µA
∆V
GATE
n
External N-Channel Gate Drive ∆V
SENSE
= V
CC
– 0.5V ●4.5 16 V
V
ONFPD
ON Pin Fast Pull-Down Threshold Low to High ●0.375 0.4 0.425 V
High to Low, Fast Pull-Down Engaged ●0.35 0.375 0.4 V
V
ON1
ON Pin Threshold #1 Low to High, GATE1 Turns On ●0.8 0.825 0.85 V
High to Low, GATE1 Turns Off ●0.775 0.8 0.825 V
V
ON2
ON Pin Threshold #2 Low to High, GATE2 Turns On ●2 2.025 2.050 V
High to Low, GATE2 Turns Off ●1.975 2 2.025 V
V
ONHYST
ON Pin Hysteresis 25 mV
I
ON
ON Pin Input Current V
CC1
= 5V, V
CC2
= 3.3V ●±0.01 ±2µA
V
OL
Output Low Voltage RESET, FAULT, COMPOUT, I
OUT
= 1.6mA, V
CC1
= 5V ●0.16 0.4 V
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
2.375V ≤ VCC1 ≤ 12V, 1.2V ≤ VCC2 ≤ 12V unless otherwise noted (Note 2).
Note 3: An internal zener on the GATE
n
pins clamps the charge pump
voltage to a typical maximum operating voltage of 22V. External overdrive
of a GATE pin (for example, from capacitive coupling of V
CC
n
glitches)
beyond the internal zener voltage may damage the device. If a lower
GATE
n
pin clamp voltage is desired, use an external zener diode.
VCC1 Supply Current vs Voltage VCC2 Supply Current vs Voltage
V
CC1
(V)
0
I
CC1
(mA)
1.0
2.0
3.0
0.5
1.5
2.5
46810
1645 G01
123257911
T
A
= 25°C
V
CC2
= 1.5V
V
CC2
= 12V
V
CC2
(V)
0
I
CC2
(mA)
0.5
1.5
2.0
2.5
3.5
157
1645 G02
1.0
3.0
4910 11 12
2368
T
A
= 25°C
V
CC1
= 2.375V
V
CC1
= 12V
Supply Current vs Temperature
TEMPERATURE (°C)
–40
0.8
1.0
1.4
20 60
1645 G03
0.6
0.4
–20 0 40 80 100
0.2
0
1.2
I
CC
n
(mA)
V
CC1
= 5V
V
CC2
= 3.3V
I
CC1
I
CC2
ELECTRICAL CHARACTERISTICS
TYPICAL PERFOR A CE CHARACTERISTICS
UW
4
LTC1645
1645fa
GATE Voltage vs Supply Voltage GATE Voltage vs Temperature Glitch Filter Time
vs Feedback Transient
RESET, FAULT, COMPOUT Output
Voltage vs Temperature RESET, FAULT, COMPOUT Output
Voltage vs VCC1 Fast Pull-Down Current vs VCC1
HIGHEST V
CC
(V)
2
GATE
n
(V)
15
20
25
10
1645 G04
10
5
0468
311
57912
T
A
= 25°C
TEMPERATURE (°C)
–40
14.0
GATE
n
(V)
14.2
14.6
14.8
15.0
16.0
15.4
040 60
1645 G05
14.4
15.6
15.8
15.2
–20 20 80 100
V
CC1
= 5V
V
CC2
= 3.3V
FEEDBACK TRANSIENT (mV)
0
0
GLITCH FILTER TIME (µs)
10
30
40
50
100
70
80 160 200
1645 G06
20
80
90
60
40 120 240 280
T
A
= 25°C
TEMPERATURE (°C)
–40
0
OUTPUT VOLTAGE (mV)
50
150
200
250
40 60 80
450
1645 G07
100
–20 0 20 100
300
350
400
V
CC1
= 5V
SINK CURRENT = 3mA
SINK CURRENT = 1.6mA
V
CC1
(V)
2
OUTPUT VOLTAGE (mV)
800
700
600
500
400
300
200
100
010
1645 G08
468 129357 11
T
A
= 25°C
SINK CURRENT = 3mA
SINK CURRENT = 1.6mA
V
CC1
(V)
23 5 9 11
FAST PULL-DOWN CURRENT (mA)
14
16
18
10
1645 G09
12
10
13
15
17
11
9
8468
712
T
A
= 25°C
V
CC2
= 1.5V
TYPICAL PERFOR A CE CHARACTERISTICS
UW
5
LTC1645
1645fa
V
CC2
(Pin 1/Pin 1): Positive Supply Input. V
CC2
can range
from 1.2V to 12V for normal operation. I
CC2
is typically
0.2mA. An undervoltage lockout circuit disables the
LTC1645 whenever the voltage at V
CC2
is less than 1.12V.
SENSE2 (Pin 2/Pin 2): V
CC2
Circuit Breaker Set Pin. With
a sense resistor placed in the supply path between V
CC2
and SENSE2, the circuit breaker trips when the voltage
across the resistor exceeds 50mV for more than 1.5µs. If
the circuit breaker trip current is set to twice the normal
operating current, only 25mV is dropped across the sense
resistor during normal operation. To disable the circuit
breaker, short V
CC2
and SENSE2 together.
GATE2 (Pin 3/Pin 3): Channel 2 High Side Gate Drive.
Connect to the gate of an external N-channel MOSFET. An
internal charge pump guarantees at least 4.5V of gate
drive. The charge pump is powered by the higher of V
CC1
and V
CC2
. When the ON pin exceeds 2V, GATE2 is turned
on by connecting a 10µA current source from the charge
pump output to the GATE2 pin and the voltage starts to
ramp up with a slope dv/dt = 10µA/C
GATE2
. While the ON
pin is below 2V but above 0.4V, a 40µA current source
pulls GATE2 toward ground. If the ON pin is below 0.4V,
the circuit breaker trips or the undervoltage lockout circuit
trips, the GATE2 pin is immediately pulled to ground with
a 12mA (typ) current source.
FAULT (Pin 4/NA): Circuit Breaker Fault. FAULT is an
open-drain output that pulls low when the circuit breaker
function trips. The circuit breaker is reset by pulling the ON
pin below 0.4V. An external pull-up is required to generate
a logic high at the FAULT pin. When the ON pin is low,
FAULT will release.
The circuit breaker can be programmed to automatically
reset by connecting the FAULT pin to the ON pin. In this
circuit configuration, if a logic device is driving the ON pin,
use a series resistor between the logic output and the ON
pin to prevent large currents from flowing.
RESET (Pin 5/NA): Open-Drain RESET Output. The RESET
pin is pulled low when the voltage at the FB pin goes below
1.238V or V
CC1
is below the undervoltage lockout thresh-
old. The RESET pin goes high one timing cycle after the
voltage at the FB pin goes above the FB pin threshold. The
ON pin must remain above 0.8V during this timing cycle.
An external pull-up is required to generate a logic high at
the RESET pin.
FB (Pin 6/NA): RESET Comparator Input. The FB pin is
used to monitor the output supply voltage with an external
resistive divider. When the voltage on the FB pin is lower
than 1.238V, the RESET pin is pulled low. A glitch filter on
the FB pin prevents fast transients from forcing RESET
low. When the voltage on the FB pin rises above the trip
point, the RESET pin goes high after one timing cycle.
GND (Pin 7/Pin 4): Ground. Connect to a ground plane for
optimum performance.
COMP
+
(Pin 8/NA): Spare Comparator Noninverting In-
put. When the voltage on COMP
+
is lower than 1.238V,
COMPOUT pulls low.
COMPOUT (Pin 9/NA): Open-Drain Spare Comparator
Output. COMPOUT pulls low when the voltage on COMP
+
is below 1.238V or V
CC1
is below the undervoltage lockout
threshold. An external pull-up is required to generate a
logic high at the COMPOUT pin.
ON (Pin 10/Pin 5): Analog Control Input. If the ON pin
voltage is below 0.4V, both GATE1 and GATE2 are imme-
diately pulled to ground. While the voltage is between 0.4V
and 0.8V, both GATE1 and GATE2 are each pulled to
ground with a 40µA current source. While the voltage is
between 0.8V and 2V, the GATE1 pull-up is turned on after
one timing cycle, but GATE2 continues to be pulled to
ground with a 40µA current source. When the voltage
exceeds 2V, both the GATE1 and GATE2 pull-ups are
turned on one timing cycle after the voltage exceeds 0.8V.
The ON pin is also used to reset the electronic circuit
breaker. If the ON pin is brought below and then above
0.4V following the trip of the circuit breaker, the circuit
breaker resets, and a normal power-up sequence occurs.
TIMER: (Pin 11/NA): System Timing Pin. The TIMER pin
requires an external capacitor to ground to generate a
timing delay. The pin is used to set the delay before the
RESET pin goes high after the output supply voltage is
good as sensed by the FB pin. It is also used to set the delay
between the ON pin exceeding 0.8V and the GATE1 and
GATE2 pins turning on (GATE2 turns on only if the ON pin
exceeds 2V).
(14-Lead Package/8-Lead Package)
UU
U
PI FU CTIO S
6
LTC1645
1645fa
(14-Lead Package/8-Lead Package)
Whenever the timer is inactive, an internal N-channel FET
shorts the TIMER pin to ground. Activating the timer
connects a 2µA current source from V
CC1
to the TIMER pin
and the voltage starts to ramp up with a slope dv/dt = 2µA/
C
TIMER
. When the voltage reaches the trip point (1.23V),
the timer is reset by pulling the TIMER pin back to ground.
The timer period is (1.23V • C
TIMER
)/2µA.
GATE1 (Pin 12/Pin 6): Channel 1 High Side Gate Drive.
Connect to the gate of an external N-channel MOSFET. An
internal charge pump guarantees at least 4.5V of gate
drive. The charge pump is powered by the higher of V
CC1
and V
CC2
. When the ON pin exceeds 0.8V, GATE1 is turned
on by connecting a 10µA current source from the charge
pump output to the GATE1 pin and the voltage starts to
ramp up with a slope dv/dt = 10µA/C
GATE1
. While the ON
pin is below 0.8V but above 0.4V, a 40µA current source
pulls GATE1 toward ground. If the ON pin is below 0.4V,
the circuit breaker trips or the undervoltage lockout circuit
trips, the GATE1 pin is immediately pulled to ground with
a 12mA (typ) current source.
SENSE1 (Pin 13/Pin 7): V
CC1
Circuit Breaker Set Pin. With
a sense resistor placed in the supply path between V
CC1
and SENSE1, the circuit breaker trips when the voltage
across the resistor exceeds 50mV for more than 1.5µs. If
the circuit breaker trip current is set to twice the normal
operating current, only 25mV is dropped across the sense
resistor during normal operation. To disable the circuit
breaker, short V
CC1
and SENSE1 together.
V
CC1
(Pin 14/Pin 8): Positive Supply Input. V
CC1
can range
from 2.375V to 12V for normal operation. I
CC1
is typically
1mA. An undervoltage lockout circuit disables the chip
whenever the voltage at V
CC1
is less than 2.23V. All internal
logic is powered by V
CC1
.
+
–
+
–
+
–
+
–
+–+–
+
–
+
–
2.23V
UVL
2V
ON
0.8V
0.4V
REF
1.5µs
FILTER 1.12V
UVL 1.5µs
FILTER
LOGIC
GLITCH
FILTER
REF
REF
4× CHARGE
PUMP
1.238V
REFERENCE
50mV 50mV
2µA
+
–+
–
10
V
CC1
14
SENSE1
13
V
CC2
1
SENSE2
2
GATE1
12
GATE2
3
FB
6
RESET
5
GND
7
COMP
+
8
COMPOUT
9
FAULT 4
1645 BD
TIMER 11
UU
U
PI FU CTIO S
BLOCK DIAGRA
W
7
LTC1645
1645fa
Hot Circuit Insertion
When a circuit board is inserted into a live backplane, the
supply bypass capacitors on the board can draw huge
transient currents from the backplane power bus as they
charge. These transient currents can cause permanent
damage to the connector pins and produce glitches on the
system supply, resetting other boards in the system.
The LTC1645 is designed to turn a board’s supply voltages
on and off in a controlled manner, allowing the board to be
safely inserted or removed from a live backplane. The chip
provides a system reset signal and a spare comparator to
indicate when board supply voltages drop below user-
programmable voltages, and a fault signal to indicate if an
overcurrent condition has occurred.
The LTC1645 can be located before or after the connector
as shown in Figure 1. A staggered PCB connector can
sequence pin connections when plugging and unplugging
circuit boards. Alternatively, the control signal can be
generated by processor control.
Power Supply Tracking and Sequencing
Some applications require that the potential difference
between two power supplies not exceed a certain voltage.
This requirement applies during power-up and power-
down as well as during steady state operation, often to
prevent latch-up in a dual supply ASIC. Other systems
require one supply to come up after another, for example,
if a system clock needs to start before a block of logic.
Typical dual supplies or backplane connections may come
up at arbitrary rates depending on load current, capacitor
size, soft-start rates, etc. Traditional solutions are cum-
bersome and require complex circuitry to meet the power
supply requirements.
The LTC1645 provides a simple solution to power supply
tracking and sequencing needs. The LTC1645 guarantees
supply tracking by ramping the supplies up and down
together (see Figure 15). The sequencing capabilities of
the LTC1645 allow nearly any combination of supply
ramping (e.g., see Figure 17) to satisfy various sequenc-
ing specifications. See the Power Supply Tracking and
Sequencing Applications section for more information.
APPLICATIO S I FOR ATIO
WUUU
SENSE
FAULT
V
CC
V
OUT
FAULT
ON
ON
GND
GATE
LTC1645
BACKPLANE
CONNECTOR STAGGERED PCB
EDGE CONNECTOR
C
LOAD
+
V
CC
(a) Hot Swap Controller on Motherboard
SENSE
FAULT
V
CC
V
OUT
FAULT
ON
GND
GATE
LTC1645
1645 F01
C
LOAD
+
V
CC
BACKPLANE
CONNECTOR STAGGERED PCB
EDGE CONNECTOR
(b) Hot Swap Controller on Daughterboard
Figure 1. Staggered Pins Connection
8
LTC1645
1645fa
Power Supply Ramping
The power supplies on a board are controlled by placing
external N-channel pass transistors in the power paths as
shown in Figure 2. Consult Table 1 for a selection of
N-channel FETs suitable for use with the LTC1645. R
SENSE1
and R
SENSE2
provide current fault detection and R1 and R2
prevent high frequency oscillation. By ramping the gates
of the pass transistors up and down at a controlled rate,
the transient surge current (I = C • dv/dt) drawn from the
main backplane supply is limited to a safe value when the
board makes connection.
When power is first applied to the chip, the gates of the
N-channels (GATE1 and GATE2 pins) are pulled low. After
the ON pin is held above 0.8V for at least one timing cycle,
the voltage at GATE1 begins to rise with a slope equal to
dv/dt = 10µA/C1 (Figure 3), where C1 is the external
capacitor connected between the GATE1 pin and GND. If
the ON pin is brought above 2V (and the ON pin has been
held above 0.8V for at least one timing cycle), the voltage
at GATE2 begins to rise with a slope equal to dv/dt =
10µA/C2.
The ramp time for each supply is t = (V
CC
n
• C
n
)/10µA. If
the ON pin is pulled below 2V for GATE2 or 0.8V for GATE1
(but above 0.4V), a 40µA current source is connected from
GATE
n
to GND, and the voltage at the GATE
n
pin will ramp
down, as shown in Figure 4.
Ringing
Good engineering practice calls for bypassing the supply
rail of any circuit. Bypass capacitors are often placed at the
supply connection of every active device, in addition to one
or more large value bulk bypass capacitors per supply rail.
If power is connected abruptly, the bypass capacitors slow
the rate of rise of voltage and heavily damp any parasitic
resonance of lead or trace inductance working against the
supply bypass capacitors.
The opposite is true for LTC1645 Hot Swap circuits on a
daughterboard. In most cases, on the powered side of the
N-channel FET switches (V
CC
n
) there is no supply bypass
capacitor present. An abrupt connection, produced by
plugging a board into a backplane connector, results in a
fast rising edge applied to the V
CC
n
line of the LTC1645.
APPLICATIO S I FOR ATIO
WUUU
Figure 4. Supply Turning Off
Figure 3. Supply Turning On
Figure 2. Typical Hot Swap Connection
RSENSE2
Q1
Q2
R2
10Ω
C2
CTIMER
CLOAD1
CLOAD2
R1
10Ω
C1
12 123
8
9
6
5
11 7
1314
10
4
VCC1
ON
FAULT
SENSE1 GATE2
VCC2
VCC2
VCC1
VOUT2
VOUT1
LTC1645
(14-LEAD)
TIMER GND
COMP+
COMPOUT
FB
SENSE2GATE1
1645 F02
RESET
+
+
RSENSE1
V
CC
n
V
OUT
n
V
CC
n
+ ∆V
GATE
1645 F03
t
1
t
2
GATE
n
SLOPE = 10µA/C
n
V
CC
n
V
OUT
n
V
CC
n
+ ∆V
GATE
1645 F04
t
3
t
4
GATE
n
SLOPE = 40µA/C
n
9
LTC1645
1645fa
APPLICATIO S I FOR ATIO
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(a) Undamped VCC Waveform (48" Leads) (b) Undamped VCC Waveform (8" Leads)
Figure 5. Ring Experiment
No bulk capacitance is present to slow the rate of rise and
heavily damp the parasitic resonance. Instead, the fast
edge shock excites a resonant circuit formed by a combi-
nation of wiring harness, backplane and circuit board
parasitic inductances and FET capacitance. In theory, the
peak voltage should rise to 2X the input supply, but in
practice the peak can reach 2.5X, owing to the effects of
voltage dependent FET capacitance.
The absolute maximum V
CC
n
potential for the LTC1645 is
13.2V; any circuit with an input of 5V or greater should be
scrutinized for ringing. A well-bypassed backplane should
not escape suspicion: circuit board trace inductances of as
little as 10nH can produce sufficient ringing to overvoltage
V
CC
.
Check ringing with a fast storage oscilloscope (such as a
LECROY 9314AL DSO) by attaching coax or a probe to V
CC
and GND, then repeatedly inserting the circuit board into
the backplane. Figures 5a and 5b show typical results in a
12V application with different V
CC
lead lengths. The peak
amplitude reaches 22V, breaking down the ESD protection
diode in the process.
There are two methods for eliminating ringing: clipping
and snubbing. A transient voltage suppressor is an effec-
tive means of limiting peak voltage to a safe level.
Figure␣ 6 shows the effect of adding an ON Semiconductor,
1SMA12CAT3, on the waveform of Figure 5.
Figures 7a and 7b show the effects of snubbing with
different RC networks. The capacitor value is chosen as
10X to 100X the FET C
OSS
under bias and R is selected for
best damping—1Ω to 50Ω depending on the value of
parasitic inductance.
VOUT
0.1µF
1645 F05
10Ω
R1
0.01Ω
12V
IRF7413
CLOAD
+
+
–
LTC1645
POWER
LEADS SCOPE
PROBE
8'
1µs/DIV 1645 F05a
4V/DIV
0V
24V
1µs/DIV
4V/DIV
1645 F05b
0V
24V
10
LTC1645
1645fa
APPLICATIO S I FOR ATIO
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VCC Waveform Clamped by a Transient Suppressor
Figure 6. Transient Suppressor Clamp
V
OUT
0.1µF
1645 F06
10Ω
D1*
ON SEMICONDUCTOR
* 1SMA12CAT3
R1
0.01Ω
12V
IRF7413
C
LOAD
+
+
–
LTC1645
POWER
LEADS
BACKPLANE CONNECTOR
PCB EDGE CONNECTOR
1µs/DIV
1645 F06a
2V/DIV
0V
12V
(a) VCC Waveform Damped by a Snubber (15Ω, 6.8nF) (b) VCC Waveform Damped by a Snubber (10Ω, 0.1µF)
Figure 7. Snubber “Fixes”
V
OUT
0.1µF
1645 F07
10Ω
R1
0.01Ω
12V
IRF7413
C
LOAD
+
+
–
LTC1645
POWER
LEADS
BACKPLANE CONNECTOR
PCB EDGE CONNECTOR
10Ω
0.1µF
1µs/DIV
1645 F07a
2V/DIV
0V
12V
1µs/DIV
1645 F07b
2V/DIV
0V
12V
11
LTC1645
1645fa
APPLICATIO S I FOR ATIO
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(a) VCC Short-Circuit Supply Current Glitch Without Any Limiting (b) VCC Supply Glitch Without Any Limiting
(c) VCC Short-Circuit Supply Current Glitch
with 2µH Series Inductor (d) VCC Supply Glitch with 2µH Series Inductor
Figure 8. Supply Glitch
Supply Glitching
LTC1645 Hot Swap circuits on the backplane are generally
used to provide power-up/down sequence at insertion/
removal as well as overload/short-circuit protection. If a
short-circuit occurs at supply ramp-up, the circuit breaker
trips. The partially enhanced FET is easily disconnected
without any supply glitch.
If a dead short occurs after a supply connection is made
(Figure 8), the sense resistor R1 and the R
DS(ON)
of the
fully enhanced FET provide a low impedance path for
0.1µF
1645 F08
10Ω
R1
0.01Ω
12V
IRF7413 2µH
+
–
LTC1645
SUPPLY
GLITCH
BACKPLANE CONNECTOR
BOARD WITH POSSIBLE
SHORT-CIRCUIT FAULT
100µF
+
1µs/DIV
25A/DIV
1645 F08a
1µs/DIV
4V/DIV
1645 F08b
V
CC
GATE
1µs/DIV
5A/DIV
1645 F08c
1µs/DIV
4V/DIV
1645 F08d
GATE
V
CC
12
LTC1645
1645fa
nearly unlimited current flow. The LTC1645 discharges
the GATE pin in a few microseconds, but during this
discharge time current on the order of 150 amperes flows
from the V
CC
power supply. This current spike glitches the
power supply, causing V
CC
to dip (Figure 8a and 8b).
On recovery from overload, some supplies may over-
shoot. Other devices attached to this supply may reset or
malfunction and the overshoot may also damage some
components. An inductor (1µH to 10µH) in series with the
FET’s source limits the short-circuit di/dt, thereby limiting
the peak current and the supply glitch (Figure 8c and 8d).
Additional power supply bypass capacitance also reduces
the magnitude of the V
CC
glitch.
Reset
The LTC1645 uses an internal 1.238V bandgap reference,
a precision voltage comparator, and a resistive divider to
monitor the output supply voltage (Figure 9).
Whenever the voltage at the FB pin rises above its reset
threshold (1.238V), the comparator output goes high, and
a timing cycle starts (see Figure 10, time points 1 and 4).
After a complete timing cycle, RESET is released. An
external pull-up is required for the RESET pin to rise to a
logic high.
When the voltage at the FB pin drops below its reset
threshold, the comparator output goes low. After passing
through a glitch filter, RESET is pulled low (time point 2).
If the FB pin rises above the reset threshold for less than
a timing cycle, the RESET output remains low (time
point 3).
APPLICATIO S I FOR ATIO
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Glitch Filter
The LTC1645 has a glitch filter to prevent RESET from
generating a spurious system reset in the presence of
transients on the FB pin. The filter is 20µs for large
transients (greater than 150mV) and up to 80µs for
smaller transients. The relationship between glitch filter
time and the transient voltage is shown in Typical Perfor-
mance Characteristics: Glitch Filter Time vs Feedback
Transient.
Timer
The system timing for the LTC1645 is generated by the
circuitry shown in Figure 11. The timer is used to set the
turn-on delay after the ON pin goes high. It also sets the
delay before the RESET pin goes high after the FB pin
exceeds 1.238V.
Whenever the timer is off, the internal N-channel shorts
the TIMER pin to ground (Figure 11). Activating the timer
connects a 2µA current from V
CC1
to the TIMER pin and the
Figure 10. Supply Monitor Waveforms
Figure 9. Supply Monitor Block Diagram Figure 11. System Timing Block Diagram
–
+
COMP
TIMER
C
TIMER
FB
RESET
V
OUT
ON
TIMER
µP
10k
1645 F09
RESET
LOGIC
1.238V
REFERENCE
V2
1
1.23V 1.23V
1645 F10
23 4
V1
V
OUT
TIMER
RESET
V2 V1 V2
–
+
COMP
TIMER
2µA
C
TIMER
ON
1.23V
SUPPLY
MONITOR
1645 F11
LOGIC
13
LTC1645
1645fa
voltage on the external capacitor C
TIMER
starts to ramp up
with a slope dv/dt = 2µA/C
TIMER
. When the voltage reaches
the trip point (1.23V), the timer is reset by pulling the
TIMER pin back to ground. The timer period is
t = (1.23V • C
TIMER
)/2µA. For a 200ms delay, use a 0.33µF
capacitor.
Electronic Circuit Breaker
The LTC1645 features an electronic circuit breaker func-
tion that protects against short circuits or excessive out-
put currents. By placing sense resistors between the
supply inputs and sense pins of the supplies, the circuit
breaker trips whenever the voltage across either sense
resistor is greater than 50mV for more than 1.5µs. If the
circuit breaker trips, both GATE
pins are immediately
pulled to ground and the external N-channels FETs are
quickly turned off (time point 6 in Figure 12). The circuit
breaker resets and another timing cycle starts by taking
the ON pin below 0.4V and then high as shown at time
point 7.
At the end of the timer cycle (time point 8), the charge
pump turns on again. If the circuit breaker feature is not
required, short the SENSE
n
pin to V
CC
n
.
If the 1.5µs response time is too fast to reject supply noise,
add external resistors and capacitors R
F
and C
F
to the
sense circuit as shown in Figure 13.
The ON Pin
The ON pin is used to control system operation as shown
in Figure 14. At time point 1, the board makes connection
and the supplies power up the chip. At time point 2, the ON
pin goes high and a timer cycle starts as long as both V
CC
pins are higher than the undervoltage lockout trip point
(2.23V for V
CC1
and 1.12V for V
CC2
) and an overcurrent
fault is not detected. At the end of the timer cycle (time
point 3), the charge pump is turned on and the GATE
n
pin
voltages start to ramp up with the output supply voltages,
V
OUT
n
, following one gate-to-source voltage drop lower.
At time point 4, V
OUT2
reaches its power-good trip level
(this example assumes the FB pin resistive divider is
connected to V
OUT2
) and a timing cycle starts. At the end
of the timing cycle (time point 5), RESET goes high and the
power-up process is complete.
APPLICATIO S I FOR ATIO
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Figure 13. Extending the Short-Circuit Protection Delay
Figure 12. Current Fault Timing
Figure 14. ON Pin Waveforms
1645 F14
ON
0.8V
0.4V
0V
2V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
GATE1
GATE2
V
OUT1
V
OUT2
TIMER
V
CC
n
RESET
RAMPING UP AND
DOWN TOGETHER RAMPING UP AND
TURNING OFF FAST
RAMPING UP AND
DOWN SEPARATELY
SENSE
n
LTC1645
GATE
n
VCC
n
1645 G13
CF
RF
RESET
V
OUT
n
GATE
n
1645 F12
TIMER
ON
V
CC
n
– V
SENSE
n
V
CC
n
12 3 4
RAMPING UP RESET FAULT
AND RAMP UP
CURRENT
FAULT
56 7 89 10
14
LTC1645
1645fa
An external hard reset is initiated at time point 6. The ON
pin is forced below 0.8V but above 0.4V, and the GATE
n
pin voltages start to ramp down. V
OUT
n
also starts to ramp
down, and RESET goes low when V
OUT2
drops below the
power-good trip level at time point 7.
Time points 8 to 15 are similar to time points 1 to 7, except
the ON pin’s different voltage thresholds are used to ramp
V
OUT1
and V
OUT2
separately. At time point 8, the ON pin
goes above 0.8V but below 2V, and one timing cycle later
(time point 9) GATE1 begins to ramp up with V
OUT1
following one gate-to-source voltage drop lower. At time
point 10, the ON pin goes above 2V and GATE2 immedi-
ately begins ramping up with V
OUT2
following one gate-to-
source voltage drop lower. As soon as V
OUT2
reaches its
power-good trip level at time point 11, a timing cycle
starts. At the end of the timing cycle (time point 12),
RESET goes high and the power-up process is complete.
The ON pin is forced below 2V but above 0.8V at time point
13 and the GATE2 pin voltage starts to ramp down. V
OUT2
also starts to ramp down and RESET goes low when V
OUT2
drops below the power-good trip level at time point 14.
When the ON pin goes below 0.8V but above 0.4V at time
point 15, GATE1 and V
OUT1
ramp down.
Time points 16 to 19 show the same power-up sequence
as time points 2 to 5, while time point 20 demonstrates the
GATE
n
pins being pulled immediately to ground (instead
of ramping down) by the ON pin going below 0.4V.
Power Supply Tracking and Sequencing Applications
The LTC1645 is able to sequence V
OUT
n
in a number of
ways, including ramping V
OUT1
up first and down last;
ramping V
OUT1
up first and down first; ramping V
OUT1
up
first and V
OUT1
and V
OUT2
down together; and ramping
V
OUT1
and V
OUT2
up and down together.
Figure 15 shows an application ramping V
OUT1
and V
OUT2
up and down together. The ON pin must reach 0.8V to
ramp up V
OUT1
and V
OUT2
. The spare comparator pulls the
ON pin low until V
CC2
is above 2.3V, and the ON pin cannot
reach 0.8V before V
CC1
is above 3V. Thus, both input
supplies must be within regulation before a timing cycle
can start. At the end of the timing cycle, the output voltages
ramp up together. If either input supply falls out of
regulation, the gates of Q1 and Q2 are pulled low together.
Figure 16 shows an oscilloscope photo of the circuit in
Figure 15.
APPLICATIO S I FOR ATIO
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Figure 15. Ramping 3.3V and 2.5V Up and Down Together
Q1
1/2 Si4920DY
Q2
1/2 Si4920DY
0.01Ω*
0.01Ω*
10Ω
10Ω
1.18k
1%
10k
1.37k
1%
0.1µF
25V
0.33µF
*WSL1206-01-1% (VISHAY DALE)
C
LOAD1
C
LOAD2
D1
1N4002 D3
MBR0530T1
D2
1N4002
123
8
9
6
5
11 7
13 1214
BOTH CURRENT LIMITS: 5A
10
4
V
CC1
ON
FAULT
TIMER GND
SENSE1 GATE2GATE1 V
CC2
TRIP
POINT:
3V
V
IN1
3.3V
V
IN2
2.5V
V
OUT1
3.3V
2.5A
V
OUT2
2.5V
2.5A
µP RESET
LTC1645
(14-LEAD)
COMP
+
COMPOUT
FB
SENSE2
1645 F15
RESET
+
+
1.18k
1%
4.99k
1%
10k
1.37k
1%
1.82k
1%
15
LTC1645
1645fa
V
IN2
5V/DIV
V
IN1
5V/DIV
V
OUT2
5V/DIV
V
OUT1
5V/DIV
TIMER
2V/DIV
RESET
5V/DIV
Figure 16. Ramping 3.3V and 2.5V Up and Down Together
APPLICATIO S I FOR ATIO
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This circuit guarantees that: (1) V
OUT1
never exceeds
V
OUT2
by more than 1.2V, and (2) V
OUT2
is never greater
than V
OUT1
by more than 0.4V. On power-up, V
OUT1
and
V
OUT2
ramp up together. On power-down, the LTC1645
turns off Q1 and Q2 simultaneously. Charge remains
stored on C
LOAD1
and C
LOAD2
and the output voltages will
vary depending on the loads. D1 and D2 turn on at ≈1V
(≈0.5V each), ensuring condition 1 is satisfied, while D3
prevents violations of condition 2. Different diodes may be
necessary for different output voltage configurations.
Barring an overvoltage condition at the input(s), the only
time these diodes might conduct current is during a
power-down event, and then only to discharge C
LOAD1
or
C
LOAD2
. In the case of an input overvoltage condition that
causes excess current to flow, the circuit breaker will trip
if the current limit level is set appropriately.
Figure 17 shows an application circuit where VOUT1
ramps up before VOUT2. VOUT1 is initially discharged and
D1 is reverse-biased, thus the voltage at the ON pin is
determined only by VCC1 through the resistor divider R1
and R2. The voltage at the ON pin exceeds 0.8V if VCC1 is
above 4.6V and VOUT1 begins to ramp up after a timing
cycle. As VOUT1 ramps up, D1 becomes forward-biased
and pulls the ON pin above 2V when VOUT1 ≈4.5V. This
turns on GATE2 and VOUT2 ramps up. The FB comparator
monitors VOUT2, and the spare comparator monitors
VOUT1 with RHYST creating ≈50mV of hysteresis.
Power Supply Multiplexer
Using back-to-back FETs, the LTC1645 can Hot Swap two
supplies to the same output, automatically selecting the
primary supply if present or the secondary supply if the
primary supply is not available. Referring to Figure 18, a
diode-or circuit provides power to the LTC1645 if either
supply is up. Schottky diodes are used to prevent the
voltage at V
CC1
from approaching the undervoltage lock-
out threshold. This application assumes that if a supply is
not present, the supply input is floating.
If only the 3.3V supply is present, the voltage at the COMP
+
pin is below the trip point and COMPOUT pulls the base of
Q3 low, allowing the GATE1 pin to ramp up normally. The
voltage at the ON pin exceeds 0.8V if the 3.3V supply is
greater than 3V, ramping up GATE1 and turning on Q1A and
Q1B. The ON pin does not exceed 2V (unless the 3.3V supply
exceeds 7.5V!), keeping GATE2 low and Q2A and Q2B off.
If only the 5V supply is present or if both supplies are
present, the COMP
+
pin is above 1.238V and COMPOUT
allows the base of Q3 to be pulled high by R2. This turns
Q3 on, keeping GATE1 low and Q1A and Q1B off. The
voltage at the ON pin is pulled above 2V by R1 and GATE2
turns Q2A and Q2B on.
16
LTC1645
1645fa
Figure 17. Ramping Up 5V Followed by 3.3V
IRF7413
IRF7413
10Ω
10Ω
28k
1%
R
HYST
681k
14.7k
1%
10k
1%
0.01µF
25V
0.33µF
112 23
8
9
6
5
11 7
10
4
ON
FAULT
TIMER GND
1314
V
CC1
SENSE1 GATE2
GATE1 V
CC2
V
IN2
3.3V
V
IN1
5V
V
OUT1
5V
5A
D1
1N4148
V
OUT2
3.3V
5A
LTC1645
(14-LEAD)
COMP
+
COMPOUT
FB
SENSE2
FAULT
1645 F17
0.01µF
25V
RESET
+
C
LOAD1
C
LOAD2
+
10k
R1
47.5k
1%
R2
10k
1%
10k 10k
10k
1%
µP RESET2
µP RESET
0.005Ω*
0.005Ω*
13k
1%
*LRF1206-01-R005-J (IRC)
BOTH CURRENT LIMITS: 10A
APPLICATIO S I FOR ATIO
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Figure 18. Power Supply Multiplexer
Q1A Q1B
10ΩR2
10k
0.1µF
25V
0.33µF
10Ω
112 23
8
9
6
5
11 7
1314
10
4
V
CC1
ON
FAULT
TIMER GND
SENSE1 GATE2
GATE1 V
CC2
V
IN1
3.3V
V
IN2
5V
D1
1/2 BAT54C
D2
1/2
BAT54C
Q3
PN2222
V
OUT
5V OR
3.3V
5A
LTC1645
(14-LEAD)
COMP
+
COMPOUT
FB
SENSE2
1645 F18
0.1µF
25V
RESET
22.6k
1%
R1
10k
10k
10k 11.3k
1%
IRF7313
Q2A Q2B
IRF7313
17
LTC1645
1645fa
APPLICATIO S I FOR ATIO
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Using the LTC1645 as a Linear Regulator
This application uses the LTC1645 to Hot Swap one
primary supply and generate a secondary low dropout
regulated supply. Figure 19 shows how to switch a 5V
supply and create a 3.3V supply using the spare compara-
tor and one additional transistor. The COMP
+
pin is used
to monitor the 3.3V output. As the voltage on the gate of
Q2 increases, the 3.3V output increases. At the 3.3V
threshold the spare comparator trips. The COMPOUT pin
goes high which turns on Q3. This lowers the voltage on
the gate of Q2. This feedback loop is compensated by
capacitors C1 and C2 and resistor R1. When power is first
applied, the FB pin is low and RESET holds one side of C2
low, slowing the ramp-up of V
OUT2
. As V
OUT2
exceeds
2.75V, RESET releases to allow improved loop transient
response. Figure 20 shows the load transient response
and voltage ripple of the generated supply.
Q1
IRF7413
0.01Ω*
0.01Ω*
Q2
IRFZ24
10Ω
10k
10Ω
R1
200k
1M
Q3
PN2222 1.5k
1% 12.1k
1%
10k
1%
2.49k
1%
C2
0.1µF
25V
C1
0.033µF
0.1µF
25V
0.33µF
470µF**
6V
×2
CLOAD1
12 123
8
9
6
BOTH CURRENT LIMITS: 5A
5
11 7
1314
10
4
VCC1
ON
FAULT
SENSE1
TIMER GND
GATE2
VCC2
VIN
5V
VOUT2
3.3V
2.5A
VOUT1
5V
2.5A
LTC1645
(14-LEAD)
COMP+
COMPOUT
FB
SENSE2GATE1
1645 F19
RESET
+
+
LRF1206-01-R010-J (IRC)
T510X477K006AS (KEMET)
*
**
Figure 19. Switching 5V and Generating 3.3V
V
OUT2
0.1V/DIV
I
OUT2
1A/DIV
2.5A
0.5A
Figure 20. Load Transient Response and Voltage Ripple
18
LTC1645
1645fa
APPLICATIO S I FOR ATIO
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Switching Regulator Supply Sequencing
Figure 21 shows the LTC1645 sequencing two power
supplies, the lower of which is generated by the LTC1430A
switching regulator. Connecting the regulator’s FB pin
resistor divider (R1 and R2) to the other side of the pass
FET (Q1) allows the LTC1430A to compensate for the
voltage drop across R
SENSE1
and Q1, assuring an accurate
voltage output. The spare comparator holds the LTC1645’s
ON pin low until the LTC1430A’s output is at least 3V, and
shuts both channels off if it drops below 3V. When the
ON/OFF signal is taken high to 5V (turn-on), the voltage at
the ON pin rises with an RC exponential characteristic,
reaching 0.8V first. This starts a timing cycle, and GATE1
begins to rise. GATE2 starts to ramp up after the ON pin
reaches 2V. As long as the timing cycle is shorter than the
time for the ON pin to rise from 0.8V to 2V, V
OUT2
ramps
up after V
OUT1
. RESET goes high one timing cycle after
V
OUT1
exceeds 3V. When the ON/OFF signal is brought
low, the voltage at the ON pin exponentially decays and
GATE2 ramps down before GATE1. RESET goes low as
soon as V
OUT1
falls below 3V. Figure 22 shows the power-
up and power-down sequences of the circuit in Figure 21.
Switching Regulator Hot Swapping
High current switching regulators usually require large
bypass capacitors on both input and output for proper
operation. The application in Figure 23 controls the inrush
current to the LTC1649’s input bypass capacitors and
ramps the two output voltages up and down together. As
with the previous application, connecting the regulator’s
FB pin resistor divider to the other side of the output pass
FET (Q2) allows the LTC1649 to compensate for the
voltage drop across Q2, assuring an accurate voltage
output. The voltage at the LTC1645’s ON pin reaches 0.8V
when V
IN
exceeds 3V, and GATE1 begins to ramp up one
timing cycle later. As the regulator’s output rises, D2 pulls
the ON pin above 2V and GATE2 begins to rise, ramping
V
OUT1
and V
OUT2
up together. RESET goes high one timing
cycle after V
OUT1
exceeds 3V and V
OUT2
exceeds 2.35V.
Figure 24 shows the circuit in Figure 23 powering up.
Care should be taken connecting a switching regulator’s
FB or SENSE pins to a node other than its output. Depend-
ing on the regulator’s internal architecture, unusual be-
havior may occur as it tries in vain to raise the voltage at
ON
2V/DIV
V
OUT1
2V/DIV
V
REGOUT
2V/DIV
Figure 22. Switching Regulator Supply Sequencing
V
OUT2
2V/DIV
RESET
5V/DIV
19
LTC1645
1645fa
Q2
1/2 Si4920DY
Q1
1/2 Si4920DY
10Ω
10Ω
2.67k
1%
3.16k
1%
1.87k
1%
0.047µF
25V
1µF
V
REGOUT
1µF
4700pF
0.1µF2.4µH
CDRH1272R4
0.33µF
1
12 23
8
9
6
5
11 7
10
4
ON
FAULT
TIMER GND
1314
SENSE1
V
CC1
GATE2
GATE1 V
CC2
V
IN
5V
V
OUT1
3.3V
2.5A
V
OUT2
5V
2.5A
LTC1645
(14-LEAD)
COMP
+
COMPOUT
FB
SENSE2
ON/OFF
FAULT
1645 F21
0.047µF
25V
RESET
+
C
LOAD1
C
LOAD2
+
1500µF
6.3V
× 2
+
130k
1%
162k
1%
22k
10k
51Ω
1Ω
MBRS130T3
Si4410DY
Si4410DY
MBR0530T1
10k
1.15k
1%
RESET
R
SENSE2
*
0.01Ω
R
SENSE1
*
0.01Ω
R1
16.5k
1%
R2
16.9k
1%
*LRF1206-01-R010-J (IRC)
0.1µF
15µF
10V
1500µF
6.3V
× 3
1µF
4700pF
270pF
680pF
2
1
4
3
7
8
5
6
PV
CC2
G2
SHDN
COMP
PV
CC1
G1
FB
GND
LTC1430ACS8
+
+
Figure 21. Switching Regulator Supply Sequencing
APPLICATIO S I FOR ATIO
WUUU
20
LTC1645
1645fa
Figure 23. Switching Regulator Hot Swap
Q1
FDB8030L
Q2
FDB8030L
Q3
FDS6680
10Ω
1500µF
6.3V
× 6
1500µF
6.3V
× 4
10Ω
220Ω
MBR0530LT1
1.02k
1%
2.67k
1%
1.13k
1%
0.01µF
25V
1µF
220pF
0.015µF
0.01µF
1µF
1µF
2200pF
5.1Ω
1.2µH
†
V
REGOUT
V
REGIN
**
100µF
0.33µF
0.1µF
100k
MBR0530LT1
0.1µF
0.1µF
0.33µF
0.01µF
112 23
8
9
6
5
11 7
10
4
ON
FAULT
TIMER GND
1314
V
CC1
SENSE1 GATE2
GATE1 V
CC2
V
OUT1
3.3V
10A
LTC1645
(14-LEAD) COMP
+
COMPOUT
FB
SENSE2
FAULT
1645 F23
0.047µF
25V
3.01k
1%
3.09k
1%
RESET
+
+
C
LOAD2
+
C
LOAD1
+
V
OUT2
2.5V
15A
V
IN
3.3V
GND
10k
4.99k
1%
1.82k
1%
D2
MBR0530T1
10k
33k
R2
1k
R1
1.8k
D1
1N4148
1.87k
1%
GND
RESET
0.003Ω*
0.003Ω*
*LRF2010-01-R003-J (IRC)
**MBRS340T (ON SEMICONDUCTOR)
†
ETQP6F1R2HFA (PANASONIC)
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
0.33µF
0.1µF
18k
1k
IRF7801
IRF7801 IRF7801
IRF7801
G2
PV
CC2
V
CC
I
FB
I
MAX
COMP
CPOUT
C
+
G1
PV
CC1
GND
FB
SHDN
SS
V
IN
C
–
LTC1649
10µF
+
+
10Ω
APPLICATIO S I FOR ATIO
WUUU
21
LTC1645
1645fa
Table 1. N-Channel Selection Guide
CURRENT PART
LEVEL NUMBER MANUFACTURER DESCRIPTION
1A to 2A NDH8503N Fairchild Dual N-Channel
R
DS(ON)
= 0.033
SuperSOT-8
1A to 2A Si6928DQ Vishay/Siliconix Dual N-Channel
R
DS(ON)
= 0.035
TSSOP-8
2A to 5A Si4920DY Vishay/Siliconix Dual N-Channel
R
DS(ON)
= 0.025
SO-8
2A to 5A IRF7313 International Dual N-Channel
Rectifier R
DS(ON)
= 0.029
SuperSOT-8
5A to 10A Si4420 Vishay/Siliconix Single N-Channel
R
DS(ON)
= 0.009
SO-8
5A to 10A FDS6680 Fairchild Single N-Channel
R
DS(ON)
= 0.01
SO-8
5A to 10A IRF7413 International Single N-Channel
Rectifier R
DS(ON)
= 0.011
SO-8
5A to 10A MMSF3300 ON Semiconductor Single N-Channel
R
DS(ON)
= 0.0125
SO-8
10A to 20A FDB8030L Fairchild Single N-Channel
R
DS(ON)
= 0.0035
TO-263AB
10A to 20A SUB75N03-04 Vishay/Siliconix Single N-Channel
R
DS(ON)
= 0.004
D
2
PAK
ON
2V/DIV
V
OUT2
2V/DIV
V
REGOUT
2V/DIV
Figure 24. Switching Regulator Hot Swap
V
OUT1
2V/DIV
V
REGIN
2V/DIV
RESET
5V/DIV
APPLICATIO S I FOR ATIO
WUUU
V
CC
V
OUT
*USER SELECTED VOLTAGE CLAMP
1N4688 (5V)
1N4692 (7V): LOGIC-LEVEL MOSFET
1N4695 (9V)
1N4702 (15V): STANDARD-LEVEL MOSFET
1645 F25
R1
D1* D2
1N4148 D4*
D2
1N4148
Q1
Figure 25. Optional Gate Clamp
its FB or SENSE pin. In the case of the LTC1649, large peak
currents result if the FB pin is at ground and not connected
directly to the output inductor and capacitors. To keep the
peak currents under control, R1, R2 and D1 hold the FB pin
above ground but below its normal regulated value until
V
OUT2
ramps up and D1 reverse-biases.
Power N-Channel Selection
The R
DS(ON)
of the external pass transistors must be low
enough so that the voltage drop across them is 100mV or
less at full current. If the R
DS(ON)
is too high, the voltage
drop across the transistor can cause the output voltage to
trip the reset circuit. The transistors listed in Table 1 or
other similar transistors are recommended for use with
the LTC1645.
Low voltage applications may require the use of logic-level
FETs; ensure their maximum V
GS
rating is sufficient for the
application. GATE voltage as a function of V
CC
is illustrated
in the Typical Performance curves. If lower GATE drive is
desired, connect a diode in series with a zener between
GATE and V
CC
or between GATE and V
OUT
as shown in
Figure 25.
22
LTC1645
1645fa
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
U
PACKAGE DESCRIPTIO
.016 – .050
(0.406 – 1.270)
.010 – .020
(0.254 – 0.508)× 45°
0°– 8° TYP
.008 – .010
(0.203 – 0.254)
SO8 0303
.053 – .069
(1.346 – 1.752)
.014 – .019
(0.355 – 0.483)
TYP
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
1234
.150 – .157
(3.810 – 3.988)
NOTE 3
8765
.189 – .197
(4.801 – 5.004)
NOTE 3
.228 – .244
(5.791 – 6.197)
.245
MIN .160 ±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
.050 BSC
.030 ±.005
TYP
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
23
LTC1645
1645fa
S Package
14-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
U
PACKAGE DESCRIPTIO
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
1
N
234
.150 – .157
(3.810 – 3.988)
NOTE 3
14 13
.337 – .344
(8.560 – 8.738)
NOTE 3
.228 – .244
(5.791 – 6.197)
12 11 10 9
567
N/2
8
.016 – .050
(0.406 – 1.270)
.010 – .020
(0.254 – 0.508)× 45°
0° – 8° TYP
.008 – .010
(0.203 – 0.254)
S14 0502
.053 – .069
(1.346 – 1.752)
.014 – .019
(0.355 – 0.483)
TYP
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
.245
MIN
N
123 N/2
.160 ±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
.050 BSC
.030 ±.005
TYP
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
24
LTC1645
1645fa
LT/TP 0404 1K REV A • PRINTED IN USA
LINEAR T ECHNOLOGY CORPORATION 1999
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
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Current Control
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
Q1
1/2 Si4920DY
Q2
1/2 Si4920DY
0.01Ω*
0.01Ω*
10Ω
10Ω
1.18k
1%
10k
1.37k
1%
0.1µF
25V
0.33µF
*WSL1206-01-1% (VISHAY DALE)
C
LOAD1
C
LOAD2
D1
1N4002 D3
MBR0530T1
D2
1N4002
123
8
9
6
5
11 7
13 1214
BOTH CURRENT LIMITS: 5A
10
4
V
CC1
ON
FAULT
TIMER GND
SENSE1 GATE2GATE1 V
CC2
TRIP
POINT:
3V
V
IN1
3.3V
V
IN2
2.5V
V
OUT1
3.3V
2.5A
V
OUT2
2.5V
2.5A
µP RESET
LTC1645
(14-LEAD)
COMP
+
COMPOUT
FB
SENSE2
1645 F15
RESET
+
+
1.18k
1%
4.99k
1%
10k
1.37k
1%
1.82k
1%
Dual Supply Hot Swap with Tracking Outputs
TYPICAL APPLICATIO
U
