Product Folder Sample & Buy Support & Community Tools & Software Technical Documents INA129-EP SBOS508A - DECEMBER 2009 - REVISED DECEMBER 2015 INA129-EP Precision, Low Power Instrumentation Amplifiers 1 Features 3 Description * * * * * * The INA129-EP device is a low power, generalpurpose instrumentation amplifier offering excellent accuracy. The versatile 3-op amp design and small size make the device ideal for a wide range of applications. Current-feedback input circuitry provides wide bandwidth even at high gain (200 kHz at G = 100). 1 Low Offset Voltage Low Input Bias Current High CMR: 95 dB (Typical) Inputs Protected to 40 V Wide Supply Range: 2.25 V to 18 V Low Quiescent Current: 2 mA (Typical) A single external resistor sets any gain from 1 to 10,000. The INA129-EP provides an industrystandard gain equation; the INA129-EP gain equation is compatible with the AD620. 2 Applications * * * * * * (1) Bridge Amplifier Thermocouple Amplifier RTD Sensor Amplifier Medical Instrumentation Data Acquisition Supports Extreme Temperature Applications: - Controlled Baseline - One Assembly and Test Site - One Fabrication Site - Available in Military (-55C to +125C) Temperature Range (1) - Extended Product Life Cycle - Extended Product-Change Notification - Product Traceability The INA129-EP device is laser trimmed for very low offset voltage, drift, and high common-mode rejection (113 dB at G 100). It operates with power supplies as low as 2.25 V, and quiescent current is only 750 A-ideal for battery operated systems. Internal input protection can withstand up to 40 V without damage. The INA129-EP is available in a 8-Pin SOIC surfacemount package specified for the -55C to 125C temperature range. Device Information(1) PART NUMBER INA129-EP PACKAGE SOIC (8) BODY SIZE (NOM) 4.90 mm x 3.91 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Custom temperature ranges available Simplified Schematic V+ 7 G=1+ INA129 2 VIN 49.4 kW RG Over-Voltage Protection A1 40 kW 1 A3 RG 8 + VIN 40 kW 24.7 kW 3 6 VO 24.7 kW Over-Voltage Protection 5 A2 40 kW Ref 40 kW 4 V- 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. INA129-EP SBOS508A - DECEMBER 2009 - REVISED DECEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 5 6.1 6.2 6.3 6.4 6.5 6.6 5 5 5 5 6 8 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 11 7.1 Overview ................................................................. 11 7.2 Functional Block Diagram ....................................... 11 7.3 Feature Description................................................. 11 7.4 Device Functional Modes........................................ 12 8 Application and Implementation ........................ 13 8.1 Application Information............................................ 13 8.2 Typical Application ................................................. 13 9 Power Supply Recommendations...................... 17 9.1 Low Voltage Operation ........................................... 17 10 Layout................................................................... 18 10.1 Layout Guidelines ................................................. 18 10.2 Layout Example .................................................... 18 11 Device and Documentation Support ................. 19 11.1 11.2 11.3 11.4 Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 19 19 19 19 12 Mechanical, Packaging, and Orderable Information ........................................................... 19 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (December 2009) to Revision A Page * Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................. 1 * Removed junction-to-ambient thermal resistance value for 8-pin DIP package, and updated SOIC package thermal information. ............................................................................................................................................................................ 5 2 Submit Documentation Feedback Copyright (c) 2009-2015, Texas Instruments Incorporated Product Folder Links: INA129-EP INA129-EP www.ti.com SBOS508A - DECEMBER 2009 - REVISED DECEMBER 2015 5 Pin Configuration and Functions D Package 8-Pin SOIC Top View RG 1 8 RG V- IN 2 7 V+ V+IN 3 6 VO V- 4 5 Ref Pin Functions PIN NAME NO. I/O DESCRIPTION Ref 5 I Output voltage reference RG 1, 8 O Gain resistor connection V+ 7 Power Positive power supply voltage from 2.25 V to 18 V V- 4 Power Negative power supply voltage from -2.25 V to -18 V V+IN 3 I Non-inverting input voltage V-IN 2 I Inverting input voltage VO 6 O Output voltage Bare Die Information DIE THICKNESS BACKSIDE FINISH BACKSIDE POTENTIAL BOND PAD METALLIZATION COMPOSITION 15 mils Silicon with backgrind GND Al-Si-Cu (0.5%) Origin a c b d Submit Documentation Feedback Copyright (c) 2009-2015, Texas Instruments Incorporated Product Folder Links: INA129-EP 3 INA129-EP SBOS508A - DECEMBER 2009 - REVISED DECEMBER 2015 www.ti.com Bond Pad Coordinates in Mils (1) DESCRIPTION PAD NUMBER a b c d NC 1 -57.4 -31.1 -53.3 -27 V-IN 2 -9.85 -31.4 -5.75 -27.3 V+IN 3 25.05 -31.4 29.15 -27.3 -30.2 V- 4 56.2 -34.3 60.3 Ref 5 53.75 -17.6 57.85 -11 VO 6 50.35 27.8 56.95 31.9 V+ 7 7.75 30.2 11.85 34.3 32.5 NC 8 -57.4 28.4 -53.3 RG (1) 9 -57.4 13.4 -53.3 20 RG (1) 10 -57.5 2.7 -53.4 9.3 RG (1) 11 -57.5 -7.9 -53.4 -1.3 RG (1) 12 -57.4 -18.6 -53.3 -12 Pads 9 and 10 must both be bonded to a common point and correspond to package pin 8. Pads 11 and 12 must both be bonded to a common point and correspond to package pin 1. NC RG RG RG RG NC PAD #1 V-IN V+ V+IN VO V- 4 Ref Submit Documentation Feedback Copyright (c) 2009-2015, Texas Instruments Incorporated Product Folder Links: INA129-EP INA129-EP www.ti.com SBOS508A - DECEMBER 2009 - REVISED DECEMBER 2015 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN VS MAX UNIT 18 V 40 V 125 C Supply voltage Analog input voltage Output short-circuit (to ground) Continuous TA Operating temperature TJ Junction temperature 150 C Lead temperature (soldering, 10s) 300 C 125 C Tstg (1) -55 Storage temperature -55 Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) 4000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) 200 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) V power supply Input common-mode voltage range for VO = 0 TA operating temperature INA129-EP MIN NOM MAX UNIT 2.25 15 18 V V-2V V + -2 V -55 125 C 6.4 Thermal Information INA129-EP THERMAL METRIC (1) D (SOIC) UNIT 8 PINS RJA Junction-to-ambient thermal resistance 110 C/W RJC(top) Junction-to-case (top) thermal resistance 57 C/W RJB Junction-to-board thermal resistance 54 C/W JT Junction-to-top characterization parameter 11 C/W JB Junction-to-board characterization parameter 53 C/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright (c) 2009-2015, Texas Instruments Incorporated Product Folder Links: INA129-EP 5 INA129-EP SBOS508A - DECEMBER 2009 - REVISED DECEMBER 2015 www.ti.com 6.5 Electrical Characteristics At TA = 25C, VS = 15 V, RL = 10 k (unless otherwise noted) PARAMETER TEST CONDITIONS TA = 25C MIN TA = 25C TYP MAX MIN TYP MAX UNIT INPUT Offset Voltage, RTI 100 800/G TA = 25C Initial 150 2050/G Overtemperature vs power supply TA = 25C, VS = 2.25 V to 18 V 1.6 175/G 1.8 175/G Overtemperature V V/V Long-term stability 1 3/G V/mo Impedance, differential 1010 || 2 || pF 1011||9 || pF Common mode Common mode voltage range (1) VO = 0 V (V+) - 2 (V+) - 1.4 V (V-) + 2 (V-) + 1.7 V 75 86 Safe input voltage 40 G=1 Overtemperature G = 10 VCM = 13 V, Overtemperature Common-mode rejection RS = 1 k G = 100 67 93 106 113 125 84 Overtemperature G = 1000 V dB 98 113 130 Overtemperature 98 CURRENT Bias current Offset Current 2 8 Overtemperature 16 1 8 Overtemperature 16 nA nA NOISE Noise voltage, RTI Noise current G = 1000, RS = 0 G = 1000, RS = 0 f = 10 Hz 10 f = 100 Hz 8 f = 1 kHz 8 nV/Hz fB = 0.1 Hz to 10 Hz 0.2 f = 10 Hz 0.9 f = 1 kHz 0.3 fB = 0.1 Hz to 10 Hz 30 pAPP 1+ (49.4 k/RG) V/V Vpp pA/Hz GAIN Gain equation Range of gain (1) 6 1 10000 V/V Input common-mode range varies with output voltage -- see Typical Characteristics. Submit Documentation Feedback Copyright (c) 2009-2015, Texas Instruments Incorporated Product Folder Links: INA129-EP INA129-EP www.ti.com SBOS508A - DECEMBER 2009 - REVISED DECEMBER 2015 Electrical Characteristics (continued) At TA = 25C, VS = 15 V, RL = 10 k (unless otherwise noted) PARAMETER TEST CONDITIONS TA = 25C MIN G=1 TA = 25C TYP MAX 0.05% 0.1% MIN Overtemperature 0.02% 0.5% 0.05% 0.65% Overtemperature 0.65% G = 100 Overtemperature 1.1% G = 1000 Gain vs temperature (2) G=1 49.4-k resistance (2) (3) VO = 13.6 V, G=1 0.5% 2% 1 10 ppm/C 25 100 ppm/C 0.0001 0.0018 Overtemperature 0.0035 G = 10 Nonlinearity UNIT MAX 0.15% G = 10 Gain error TYP 0.0003 0.0035 Overtemperature 0.0055 G = 100 0.0005 % of FSR 0.0035 Overtemperature 0.0055 G = 1000 0.001 See (4) OUTPUT Positive RL = 10 k (V+) - 1.4 (V+) - 0.9 Negative RL = 10 k (V-) + 1.4 (V-) + 0.8 Voltage Load capacitance stability Short-circuit current V 1000 pF +6/-15 mA FREQUENCY RESPONSE Bandwidth, -3 dB Slew rate Settling time, 0.01% Overload recovery G=1 1300 G = 10 700 G = 100 200 G = 1000 20 VO = 10 V, G = 10 4 G=1 7 G = 10 7 G = 100 9 G = 1000 80 50% overdrive kHz V/s s 4 s POWER SUPPLY Voltage range Current, total 2.25 VIN = 0 V 15 18 700 750 V Overtemperature 1200 A TEMPERATURE RANGE Specification -55 125 C Operating -55 125 C (2) (3) (4) Specified by wafer test. Temperature coefficient of the 49.4-k term in the gain equation. Nonlinearity measurements in G = 1000 are dominated by noise. Typical nonlinearity is 0.001%. Submit Documentation Feedback Copyright (c) 2009-2015, Texas Instruments Incorporated Product Folder Links: INA129-EP 7 INA129-EP SBOS508A - DECEMBER 2009 - REVISED DECEMBER 2015 www.ti.com 6.6 Typical Characteristics At TA = 25C, VS = 15 V, unless otherwise noted. 60 140 G =1000V/V G =100V/V G = 1000V/V Common-Mode Rejection (dB) 50 40 Gain (dB) G = 100V/V 30 20 G = 10 V/V 10 0 G = 1V/V - 10 120 G =10V/V 100 G =1V/V 80 60 40 20 - 20 0 10k 1k 100k 10M 1M 10 100 10k 1k Frequency (Hz) 100k 1M Frequency (Hz) Figure 1. Gain vs Frequency Figure 2. Common-Mode Rejection vs Frequency 140 140 Power Supply Rejection (dB) Power Supply Rejection (dB) G = 1000V/V 120 G =1000V/V 100 G =100V/V 80 60 G= 10V/V 40 G=1V/V 20 120 80 60 100 10k 1k 100k G=1V/V 20 0 10 1M Frequency (Hz) Frequency (Hz) Figure 3. Positive Power-Supply Rejection vs Frequency Figure 4. Negative Power-Supply Rejection vs Frequency 5 15 G 10 G 10 G=1 G=1 5 +15V VD/2 0 VD/2 5 + VO Ref + VCM -15V 10 3 2 G=1 G=1 G 10 1 0 G=1 1 2 3 VS = 5V VS = 2.5V 4 5 15 -15 -10 -5 0 5 10 15 -5 -4 -3 -2 -1 0 1 2 3 4 5 Output Voltage (V) Output Voltage (V) VS = 5 V, 2.5 V VS = 15 V Figure 5. Input Common-Mode Range vs Output Voltage 8 G 10 G 10 4 10 Common-Mode Voltage (V) Common-Mode Voltage (V) G=10V/V 40 0 10 G =100V/V 100 Figure 6. Input Common-Mode Range vs Output Voltage Submit Documentation Feedback Copyright (c) 2009-2015, Texas Instruments Incorporated Product Folder Links: INA129-EP INA129-EP www.ti.com SBOS508A - DECEMBER 2009 - REVISED DECEMBER 2015 Typical Characteristics (continued) 1k 100 100 3/4 Input Bias Current Noise (pA/Hz) 3/4 G = 1V / V 100 10 G =10V/V 10 1 G =100, 1000V/V Current Noise 1 0.01% Settling Time (ms) Input-Referred Voltage Noise (nV/Hz) At TA = 25C, VS = 15 V, unless otherwise noted. 0.1% 10 1 0.1 1 10 100 10 1 10k 1k Figure 7. Input-Referred Noise vs Frequency 4 8 Input Current (mA) Flat region represents normal linear operation. Offset Voltage Change (mV) 10 2 G = 1000V/V 1 G = 1V / V 0 1 +15V G=1V/V 2 3 VIN G = 1000V/V 4 6 4 2 0 -2 -4 -6 -8 IIN 15V 5 -10 -50 -40 -30 -20 -10 0 10 20 30 40 200 100 0 50 500 400 300 Input Voltage (V) Time (ms) Figure 9. Input Overvoltage Voltage-to-Current Characteristics Figure 10. Input Offset Voltage Warm-Up (V+) (V+) (V+)-0.4 (V+)-0.4 Output Voltage Swing (V) Output Voltage (V) 1000 Figure 8. Settling Time vs Gain 5 3 100 Gain (V/V) Frequency (Hz) (V+)-0.8 (V+)-1.2 (V-)+1.2 (V-)+0.8 +25C (V+)-0.8 (V+)-1.2 +85C -40 C RL = 10 k +25C (V-)+1.2 -40 C +85C (V-)+0.8 +85C -40 C (V-)+0.4 (V-)+0.4 (V-) (V-) 0 1 2 3 4 0 5 10 15 20 Power Supply Voltage (V) Output Current (mA) Figure 11. Output Voltage Swing vs Output Current Figure 12. Output Voltage Swing vs Power Supply Voltage Submit Documentation Feedback Copyright (c) 2009-2015, Texas Instruments Incorporated Product Folder Links: INA129-EP 9 INA129-EP SBOS508A - DECEMBER 2009 - REVISED DECEMBER 2015 www.ti.com Typical Characteristics (continued) At TA = 25C, VS = 15 V, unless otherwise noted. 1 G =10, 100 25 VO = 1 Vrms 500kHz Measurement Bandwidth G=1 G = 1000 TH D + N (% ) Peak-to-Peak Output Voltage (VPP) 30 20 15 10 G =100, RL = 100kW 0.01 G =10V/V RL = 100kW G =1, RL = 100kW 5 Dashed Portion is noise limited. 0 1k 10 0.1 G=1 RL = 10kW 10k 100k 1M 0.001 100 1k 10k 100k Frequency (Hz) Frequency (Hz) Figure 13. Maximum Output Voltage vs Frequency Figure 14. Total Harmonic Distortion + Noise vs Frequency Submit Documentation Feedback Copyright (c) 2009-2015, Texas Instruments Incorporated Product Folder Links: INA129-EP INA129-EP www.ti.com SBOS508A - DECEMBER 2009 - REVISED DECEMBER 2015 7 Detailed Description 7.1 Overview The INA129-EP instrumentation amplifier is a type of differential amplifier that has been outfitted with input protection circuit and input buffer amplifiers, which eliminate the need for input impedance matching and make the amplifier particularly suitable for use in measurement and test equipment. Additional characteristics of the INA129-EP include a very low DC offset, low drift, low noise, very high open-loop gain, very high common-mode rejection ratio, and very high input impedances. The INA129-EP is used where great accuracy and stability of the circuit both short and long-term are required. 7.2 Functional Block Diagram V+ 7 G=1+ INA129 2 VIN 49.4 kW RG Over-Voltage Protection A1 40 kW 1 A3 RG 8 + VIN 40 kW 24.7 kW 3 6 VO 24.7 kW Over-Voltage Protection 5 A2 40 kW Ref 40 kW 4 V- 7.3 Feature Description The INA129-EP device is a low power, general-purpose instrumentation amplifier that offers excellent accuracy. The versatile three-operational-amplifier design and small size make the amplifier ideal for a wide range of applications. Current-feedback input circuitry provides wide bandwidth, even at high gain. A single external resistor sets any gain from 1 to 10,000. The INA129-EP device is laser trimmed for very low offset voltage (50 V) and high common-mode rejection (93 dB at G 100). This device operates with power supplies as low as 2.25 V, and quiescent current of 2 mA, typically. The internal input protection can withstand up to 40 V without damage. Submit Documentation Feedback Copyright (c) 2009-2015, Texas Instruments Incorporated Product Folder Links: INA129-EP 11 INA129-EP SBOS508A - DECEMBER 2009 - REVISED DECEMBER 2015 www.ti.com 7.4 Device Functional Modes A single external resistor sets the any gain from 1 to 10000. TI INA129-EP provides an industry standard gain equation, as highlighted in Figure 16. 7.4.1 Noise Performance The INA129-EP provides very low noise in most applications. Low frequency noise is approximately 0.2 VPP measured from 0.1 Hz to 10 Hz (G 100). This provides dramatically improved noise when compared to stateof-the-art chopper-stabilized amplifiers. 0.1mV/div 1s/div G 100 Figure 15. 0.1-Hz to 10-Hz Input-Referred Voltage Noise 7.4.2 Input Common-Mode Range The linear input voltage range of the input circuitry of the INA129-EP is from approximately 1.4 V below the positive supply voltage to 1.7 V above the negative supply. As a differential input voltage causes the output voltage increase, however, the linear input range will be limited by the output voltage swing of amplifiers A1 and A2. So the linear common-mode input range is related to the output voltage of the complete amplifier. This behavior also depends on supply voltage (see Figure 5 and Figure 6). Input-overload can produce an output voltage that appears normal. For example, if an input overload condition drives both input amplifiers to their positive output swing limit, the difference voltage measured by the output amplifier will be near zero. The output of A3 will be near 0 V even though both inputs are overloaded. 12 Submit Documentation Feedback Copyright (c) 2009-2015, Texas Instruments Incorporated Product Folder Links: INA129-EP INA129-EP www.ti.com SBOS508A - DECEMBER 2009 - REVISED DECEMBER 2015 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The INA129-EP device measures small differential voltage with high common-mode voltage developed between the non-inverting and inverting input. The high-input voltage protection circuit in conjunction with high input impedance make the INA129-EP suitable for a wide range of applications. The ability to set the reference pin to adjust the functionality of the output signal offers additional flexibility that is practical for multiple configurations. 8.2 Typical Application Figure 16 shows the basic connections required for operation of the INA129-EP. Applications with noisy or high impedance power supplies may require decoupling capacitors close to the device pins as shown. The output is referred to the output reference (Ref) terminal which is normally grounded. This must be a lowimpedance connection to assure good common-mode rejection. A resistance of 8 in series with the Ref pin will cause a typical device to degrade to approximately 80 dB CMR (G = 1). V+ 0.1F 49.4k G=1+ RG DESIRED GAIN (V/V) RG () NEAREST 1% RG () 1 2 5 10 20 50 100 200 500 1000 2000 5000 10000 NC 49.4K 12.35K 5489 2600 1008 499 248 99 49.5 24.7 9.88 4.94 NC 49.9K 12.4K 5.49K 2.61K 1K 499 249 100 49.9 24.9 9.76 4.87 7 VIN- 2 Over Voltage Protection A1 40k 1 VO = G * (VIN- - VIN+) A3 RG VIN 3 24.74k Over Voltage Protection A2 40k 4 NC: No Connection 6 + 8 + 40k 24.7k 40k 5 Ref Load VO - 0.1F V IN V- Also drawn in simplified form: VO RG + V IN Ref Figure 16. Basic Connections 8.2.1 Design Requirements The device can be configured to monitor the input differential voltage when the gain of the input signal is set by the external resistor RG. The output signal references to the REF pin. The most common application is where the output is referenced to ground when no input signal is present by connecting the REF pin to ground, as Figure 16 shows. When the input signal increases, the output voltage at the OUT pin increases, too. Submit Documentation Feedback Copyright (c) 2009-2015, Texas Instruments Incorporated Product Folder Links: INA129-EP 13 INA129-EP SBOS508A - DECEMBER 2009 - REVISED DECEMBER 2015 www.ti.com Typical Application (continued) 8.2.2 Detailed Design Procedure 8.2.2.1 Setting the Gain Gain is set by connecting a single external resistor, RG, between pins 1 and 8. 49.4 kW G=1+ 3/4 RG (1) Commonly used gains and resistor values are shown in Figure 16. The 49.9-k term in Equation 1 comes from the sum of the two internal feedback resistors of A1 and A2. These on-chip metal film resistors are laser trimmed to accurate absolute values. The accuracy and temperature coefficient of these internal resistors are included in the gain accuracy and drift specifications of the INA129-EP. The stability and temperature drift of the external gain setting resistor, RG, also affects gain. RG's contribution to gain accuracy and drift can be directly inferred from Equation 1. Low resistor values required for high gain can make wiring resistance important. Sockets add to the wiring resistance which will contribute additional gain error (possibly an unstable gain error) in gains of approximately 100 or greater. 8.2.2.2 Dynamic Performance Figure 1 shows that, despite its low quiescent current, the INA129-EP achieves wide bandwidth, even at high gain. This is due to the current-feedback topology of the input stage circuitry. Settling time also remains excellent at high gain. 8.2.2.3 Offset Trimming The INA129-EP is laser trimmed for low offset voltage and offset voltage drift. Most applications require no external offset adjustment. Figure 17 shows an optional circuit for trimming the output offset voltage. The voltage applied to Ref terminal is summed with the output. The operational amplifier buffer provides low impedance at the Ref terminal to preserve good common-mode rejection. VIN V+ RG + VIN INA129 VO 100mA 1/2 REF200 Ref OPA177 10mV Adjustment Range 10kW 100W 100W 100mA 1/2 REF200 V- Figure 17. Optional Trimming of Output Offset Voltage 8.2.2.4 Input Bias Current Return Path The input impedance of the INA129-EP is extremely high (approximately 1010 ). However, a path must be provided for the input bias current of both inputs. This input bias current is approximately 2 nA. High input impedance means that this input bias current changes very little with varying input voltage. Input circuitry must provide a path for this input bias current for proper operation. Figure 18 shows various provisions for an input bias current path. Without a bias current path, the inputs will float to a potential which exceeds the common-mode range, and the input amplifiers will saturate. 14 Submit Documentation Feedback Copyright (c) 2009-2015, Texas Instruments Incorporated Product Folder Links: INA129-EP INA129-EP www.ti.com SBOS508A - DECEMBER 2009 - REVISED DECEMBER 2015 Typical Application (continued) If the differential source resistance is low, the bias current return path can be connected to one input (see the thermocouple example in Figure 18). With higher source impedance, using two equal resistors provides a balanced input with possible advantages of lower input offset voltage due to bias current and better highfrequency common-mode rejection. Microphone, Hydrophone etc. INA129 47kW 47kW Thermocouple INA129 10kW INA129 Center-tap provides bias current return. Figure 18. Providing an Input Common-Mode Current Path 8.2.3 Application Curves G=1 G = 10 0 20mV/div 20mV/div G = 10 G = 10 0 0 20ms/div 5ms/div G = 100, 1000 G = 1, 10 Figure 20. Small Signal Figure 19. Small Signal Submit Documentation Feedback Copyright (c) 2009-2015, Texas Instruments Incorporated Product Folder Links: INA129-EP 15 INA129-EP SBOS508A - DECEMBER 2009 - REVISED DECEMBER 2015 www.ti.com Typical Application (continued) G=1 G =100 5V/div 5V/div G = 10 G =1000 5ms/div 20ms/div G = 1, 10 G = 100, 1000 Figure 21. Large Signal 16 Figure 22. Large Signal Submit Documentation Feedback Copyright (c) 2009-2015, Texas Instruments Incorporated Product Folder Links: INA129-EP INA129-EP www.ti.com SBOS508A - DECEMBER 2009 - REVISED DECEMBER 2015 9 Power Supply Recommendations The minimum power supply voltage for INA129-EP is 2.25 V and the maximum power supply voltage is 18 V. This minimum and maximum range covers a wide range of power supplies; but for optimum performance, 15 V is recommended. TI recommends adding a bypass capacitor at the input to compensate for the layout and power supply source impedance. 9.1 Low Voltage Operation The INA129-EP can be operated on power supplies as low as 2.25 V. Performance remains excellent with power supplies ranging from 2.25 V to 18 V. Most parameters vary only slightly throughout this supply voltage range. Operation at very low supply voltage requires careful attention to assure that the input voltages remain within their linear range. Voltage swing requirements of internal nodes limit the input common-mode range with low power supply voltage. Figure 5 and Figure 6 show the range of linear operation for 15 V, 5 V, and 2.5 V supplies. +5V 2.5V - V VIN + RG 300W RG VO INA129 Ref VO INA129 R1 1MW C1 0.1mF Ref 2.5V + V 1 f-3dB= 2pR1C1 OPA130 = 1.59 Hz Figure 23. Bridge Amplifier Figure 24. AC-Coupled Instrumentation Amplifier V+ 10.0V 6 REF102 R1 VIN 2 IO = R1 RG INA129 V IN * G R1 + Ref R2 IB 4 A1 Pt100 Cu K VO Cu RG INA129 E J K T MATERIAL +Chromel -Constantan +Iron -Constantan +Chromel -Alumel +Copper -Constantan IB ERROR OPA177 1.5 nA OPA131 50 pA OPA602 1 pA OPA128 75 fA IO Load Ref R3 100 = Pt100 at 0C ISA TYPE A1 SEEBECK COEFFICIENT (mV/C) R1, R2 58.5 66.5kW 50.2 76.8kW 39.4 97.6kW 38 102kW Figure 25. Thermocouple Amplifier With RTD ColdJunction Compensation Figure 26. Differential Voltage to Current Converter Submit Documentation Feedback Copyright (c) 2009-2015, Texas Instruments Incorporated Product Folder Links: INA129-EP 17 INA129-EP SBOS508A - DECEMBER 2009 - REVISED DECEMBER 2015 www.ti.com Low Voltage Operation (continued) RG = 5.6kW 2.8kW G = 10 LA RA RG/2 INA129 VO Ref 2.8kW 390kW VG 1/2 OPA2131 RL VG 1/2 OPA2131 10kW 390kW NOTE: Due to the INA129's current-feedback topology, VG is approximately 0.7 V less than the common-mode input voltage. This DC offset in this guard potential is satisfactory for many guarding applications. Figure 27. ECG Amplifier With Right-Leg Drive 10 Layout 10.1 Layout Guidelines Place the power-supply bypass capacitor as closely as possible to the supply and ground pins. The recommended value of this bypass capacitor is 0.1 F to 1 F. If necessary, additional decoupling capacitance can be added to compensate for noisy or high-impedance power supplies. These decoupling capacitors must be placed between the power supply and INA129-EP device. The gain resistor must be placed close to pin 1 and pin 8. This placement limits the layout loop and minimizes any noise coupling into the part. 10.2 Layout Example Gain Resistor Bypass Capacitor VIN VIN - + R6 R6 V-IH V+ V+IH VO V- REF V+ VOUT GND Bypass Capacitor V- GND Figure 28. Recommended Layout 18 Submit Documentation Feedback Copyright (c) 2009-2015, Texas Instruments Incorporated Product Folder Links: INA129-EP INA129-EP www.ti.com SBOS508A - DECEMBER 2009 - REVISED DECEMBER 2015 11 Device and Documentation Support 11.1 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.2 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.4 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright (c) 2009-2015, Texas Instruments Incorporated Product Folder Links: INA129-EP 19 PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) INA129MDREP ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -55 to 125 129EP V62/10605-01XE ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -55 to 125 129EP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2014 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF INA129-EP : * Catalog: INA129 NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 9-Oct-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device INA129MDREP Package Package Pins Type Drawing SOIC D 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.4 B0 (mm) K0 (mm) P1 (mm) 5.2 2.1 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 9-Oct-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) INA129MDREP SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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