A1
A2
A3
40 kW40 kW
40 kW
40 kW
VIN
2
1
8
3
6
5
VIN
RG
V+
V-
Ref
VO
G = 1 + 49.4 kW
RG
+
4
7
INA129
Over-Voltage
Protection
Over-Voltage
Protection
24.7 kW
24.7 kW
-
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Folder
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INA129-EP
SBOS508A –DECEMBER 2009–REVISED DECEMBER 2015
INA129-EP Precision, Low Power Instrumentation Amplifiers
1 Features 3 Description
The INA129-EP device is a low power, general-
1• Low Offset Voltage purpose instrumentation amplifier offering excellent
• Low Input Bias Current accuracy. The versatile 3-op amp design and small
• High CMR: 95 dB (Typical) size make the device ideal for a wide range of
applications. Current-feedback input circuitry provides
• Inputs Protected to ±40 V wide bandwidth even at high gain (200 kHz at G =
• Wide Supply Range: ±2.25 V to ±18 V 100).
• Low Quiescent Current: 2 mA (Typical) A single external resistor sets any gain from 1 to
10,000. The INA129-EP provides an industry-
2 Applications standard gain equation; the INA129-EP gain equation
• Bridge Amplifier is compatible with the AD620.
• Thermocouple Amplifier The INA129-EP device is laser trimmed for very low
• RTD Sensor Amplifier offset voltage, drift, and high common-mode rejection
(113 dB at G ≥100). It operates with power supplies
• Medical Instrumentation as low as ±2.25 V, and quiescent current is only 750
• Data Acquisition μA–ideal for battery operated systems. Internal input
• Supports Extreme Temperature Applications: protection can withstand up to ±40 V without damage.
– Controlled Baseline The INA129-EP is available in a 8-Pin SOIC surface-
– One Assembly and Test Site mount package specified for the –55°C to 125°C
temperature range.
– One Fabrication Site
– Available in Military (–55°C to +125°C) Device Information(1)
Temperature Range (1) PART NUMBER PACKAGE BODY SIZE (NOM)
– Extended Product Life Cycle INA129-EP SOIC (8) 4.90 mm × 3.91 mm
– Extended Product-Change Notification (1) For all available packages, see the orderable addendum at
– Product Traceability the end of the data sheet.
(1) Custom temperature ranges available
Simplified Schematic
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
INA129-EP
SBOS508A –DECEMBER 2009–REVISED DECEMBER 2015
www.ti.com
Table of Contents
7.4 Device Functional Modes........................................ 12
1 Features.................................................................. 18 Application and Implementation ........................ 13
2 Applications ........................................................... 18.1 Application Information............................................ 13
3 Description............................................................. 18.2 Typical Application ................................................. 13
4 Revision History..................................................... 29 Power Supply Recommendations...................... 17
5 Pin Configuration and Functions......................... 39.1 Low Voltage Operation ........................................... 17
6 Specifications......................................................... 510 Layout................................................................... 18
6.1 Absolute Maximum Ratings ...................................... 510.1 Layout Guidelines ................................................. 18
6.2 ESD Ratings.............................................................. 510.2 Layout Example .................................................... 18
6.3 Recommended Operating Conditions....................... 511 Device and Documentation Support................. 19
6.4 Thermal Information.................................................. 511.1 Community Resources.......................................... 19
6.5 Electrical Characteristics........................................... 611.2 Trademarks........................................................... 19
6.6 Typical Characteristics.............................................. 811.3 Electrostatic Discharge Caution............................ 19
7 Detailed Description............................................ 11 11.4 Glossary................................................................ 19
7.1 Overview................................................................. 11 12 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagram....................................... 11 Information........................................................... 19
7.3 Feature Description................................................. 11
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (December 2009) to Revision A Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
• Removed junction-to-ambient thermal resistance value for 8-pin DIP package, and updated SOIC package thermal
information. ............................................................................................................................................................................ 5
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Product Folder Links: INA129-EP
a
b
c
d
Origin
R
V-
G
IN
V+
IN
V-
V+
VO
Ref
1
2
3
4
8
7
6
5
RG
INA129-EP
www.ti.com
SBOS508A –DECEMBER 2009–REVISED DECEMBER 2015
5 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
Pin Functions
PIN I/O DESCRIPTION
NAME NO.
Ref 5 I Output voltage reference
RG 1, 8 O Gain resistor connection
V+ 7 Power Positive power supply voltage from 2.25 V to 18 V
V– 4 Power Negative power supply voltage from –2.25 V to –18 V
V+IN 3 I Non-inverting input voltage
V–IN 2 I Inverting input voltage
VO 6 O Output voltage
Bare Die Information
BACKSIDE BOND PAD
DIE THICKNESS BACKSIDE FINISH POTENTIAL METALLIZATION COMPOSITION
15 mils Silicon with backgrind GND Al-Si-Cu (0.5%)
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Product Folder Links: INA129-EP
PAD #1
NC
V-IN
V+IN
V- Ref
VO
V+
NC
RGRG
RGRG
INA129-EP
SBOS508A –DECEMBER 2009–REVISED DECEMBER 2015
www.ti.com
Bond Pad Coordinates in Mils
DESCRIPTION PAD NUMBER a b c d
NC 1 -57.4 -31.1 -53.3 -27
V-IN 2 -9.85 -31.4 -5.75 -27.3
V+IN 3 25.05 -31.4 29.15 -27.3
V- 4 56.2 -34.3 60.3 -30.2
Ref 5 53.75 -17.6 57.85 -11
VO6 50.35 27.8 56.95 31.9
V+ 7 7.75 30.2 11.85 34.3
NC 8 -57.4 28.4 -53.3 32.5
RG(1) 9 -57.4 13.4 -53.3 20
RG(1) 10 -57.5 2.7 -53.4 9.3
RG(1) 11 -57.5 -7.9 -53.4 -1.3
RG(1) 12 -57.4 -18.6 -53.3 -12
(1) Pads 9 and 10 must both be bonded to a common point and correspond to package pin 8. Pads 11 and 12 must both be bonded to a
common point and correspond to package pin 1.
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SBOS508A –DECEMBER 2009–REVISED DECEMBER 2015
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VSSupply voltage ±18 V
Analog input voltage ±40 V
Output short-circuit (to ground) Continuous
TAOperating temperature –55 125 °C
TJJunction temperature 150 °C
Lead temperature (soldering, 10s) 300 °C
Tstg Storage temperature –55 125 °C
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
6.2 ESD Ratings VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±4000
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC specification JESD22-C101, all ±200
pins(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT
V power supply ±2.25 ±15 ±18 V
Input common-mode voltage range for VO= 0 V - 2 V V + –2 V
TAoperating temperature INA129-EP –55 125 °C
6.4 Thermal Information INA129-EP
THERMAL METRIC(1) D (SOIC) UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance 110 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 57 °C/W
RθJB Junction-to-board thermal resistance 54 °C/W
ψJT Junction-to-top characterization parameter 11 °C/W
ψJB Junction-to-board characterization parameter 53 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 5
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INA129-EP
SBOS508A –DECEMBER 2009–REVISED DECEMBER 2015
www.ti.com
6.5 Electrical Characteristics
At TA= 25°C, VS= ±15 V, RL= 10 kΩ(unless otherwise noted) TA= 25°C TA= 25°C
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX MIN TYP MAX
INPUT
Offset Voltage, RTI ±100
TA= 25°C ±800/G
Initial µV
±150
Overtemperature ±2050/G
TA= 25°C, VS= ±2.25 V to ±18 ±1.6
V ±175/G
vs power supply µV/V
±1.8
Overtemperature ±175/G
Long-term stability ±1 ±3/G µV/mo
Impedance, differential 1010 || 2 Ω|| pF
Common mode 1011||9 Ω|| pF
Common mode voltage (V+) −
VO= 0 V (V+) −1.4 V
range(1) 2
(V−) + (V−) + 1.7 V
2
Safe input voltage ±40 V
G = 1 75 86
Overtemperature 67
G = 10 93 106
Overtemperature 84
VCM = ±13 V,
Common-mode rejection dB
ΔRS= 1 kΩG = 100 113 125
Overtemperature 98
G = 1000 113 130
Overtemperature 98
CURRENT
±2 ±8
Bias current nA
Overtemperature ±16
±1 ±8
Offset Current nA
Overtemperature ±16
NOISE
f = 10 Hz 10
f = 100 Hz 8 nV/√Hz
G = 1000,
Noise voltage, RTI f = 1 kHz 8
RS= 0 ΩfB= 0.1 Hz to 10 0.2 µVpp
Hz
f = 10 Hz 0.9 pA/√Hz
G = 1000, f = 1 kHz 0.3
Noise current RS= 0 ΩfB= 0.1 Hz to 10 30 pAPP
Hz
GAIN
1 +
Gain equation (49.4 V/V
kΩ/RG)
Range of gain 1 10000 V/V
(1) Input common-mode range varies with output voltage — see Typical Characteristics.
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SBOS508A –DECEMBER 2009–REVISED DECEMBER 2015
Electrical Characteristics (continued)
At TA= 25°C, VS= ±15 V, RL= 10 kΩ(unless otherwise noted) TA= 25°C TA= 25°C
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX MIN TYP MAX
G = 1 ±0.05% ±0.1%
Overtemperature ±0.15%
G = 10 ±0.02% ±0.5%
Gain error Overtemperature ±0.65%
G = 100 ±0.05% ±0.65%
Overtemperature ±1.1%
G = 1000 ±0.5% ±2%
Gain vs temperature(2) G = 1 ±1 ±10 ppm/°C
49.4-kΩ±25 ±100 ppm/°C
resistance(2)(3)
VO= ±13.6 V, ±0.0001 ±0.0018
G = 1
Overtemperature ±0.0035
G = 10 ±0.0003 ±0.0035 % of
Nonlinearity Overtemperature ±0.0055 FSR
G = 100 ±0.0005 ±0.0035
Overtemperature ±0.0055
G = 1000 ±0.001 See (4)
OUTPUT
(V+) −
Positive RL= 10 kΩ(V+) −0.9
1.4
Voltage V
(V−) +
Negative RL= 10 kΩ(V−) + 0.8
1.4
Load capacitance 1000 pF
stability
Short-circuit current +6/−15 mA
FREQUENCY RESPONSE
G = 1 1300
G = 10 700
Bandwidth, −3 dB kHz
G = 100 200
G = 1000 20
VO= ±10 V,
Slew rate 4 V/µs
G = 10
G = 1 7
G = 10 7
Settling time, 0.01% µs
G = 100 9
G = 1000 80
Overload recovery 50% overdrive 4 µs
POWER SUPPLY
Voltage range ±2.25 ±15 ±18 V
VIN = 0 V ±700 ±750
Current, total µA
Overtemperature ±1200
TEMPERATURE RANGE
Specification −55 125 °C
Operating −55 125 °C
(2) Specified by wafer test.
(3) Temperature coefficient of the 49.4-kΩterm in the gain equation.
(4) Nonlinearity measurements in G = 1000 are dominated by noise. Typical nonlinearity is ±0.001%.
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Output Voltage (V)
Common-Mode Voltage (V)
0
15
10
5
0
10
G=1 G = 1
G≥10 G≥10
VD/2 +
+
VCM
V
VO
D/2 Ref
-15V
+15V
-10-15
5
10
15
-5 5 15
Output Voltage (V)
Common-Mode Voltage (V)
5
4
3
2
1
0
0
G=1 G=1
G≥10 G≥10
G≥10
G=1
1
2
3
4
5
-1
-2-3-4-5
VS=±2.5V
VS=±5V
1 2 345
Frequency (Hz)
Power Supply Rejection (dB)
140
120
100
80
60
40
20
0
10
G =100V/V
G =1000V/V
G=1V/V
G= 10V/V
100k100 1k 10k 1M
Frequency (Hz)
Power Supply Rejection (dB)
140
120
100
80
60
40
20
0
10
G =100V/V
G = 1000V/V
G=1V/V
G=10V/V
Frequency (Hz)
Common-Mode Rejection (dB)
10
140
120
100
80
60
40
20
0
100k
G =1V/V
G =10V/V
G =100V/V
G =1000V/V
100 1k 10k 1M
−
60
50
40
30
20
10
0
10
20
Gain (dB)
Frequency (Hz)
1k
G = 100V/V
G = 10 V/V
G = 1V/V
G = 1000V/V
−
10k 100k 1M 10M
INA129-EP
SBOS508A –DECEMBER 2009–REVISED DECEMBER 2015
www.ti.com
6.6 Typical Characteristics
At TA= 25°C, VS= ±15 V, unless otherwise noted.
Figure 1. Gain vs Frequency Figure 2. Common-Mode Rejection vs Frequency
Figure 3. Positive Power-Supply Rejection vs Frequency Figure 4. Negative Power-Supply Rejection vs Frequency
VS= ±5 V, ±2.5 V
VS= ±15 V
Figure 6. Input Common-Mode Range vs Output Voltage
Figure 5. Input Common-Mode Range vs Output Voltage
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(V-)+1.2
(V-)
(V+)
0 1 2 3 4
Output Current (mA)
Output Voltage (V)
(V+)-0.4
(V+)-0.8
(V+)-1.2
(V-)+0.8
(V-)+0.4
(V-)+1.2
(V-)
(V+)
(V+)-0.4
(V+)-0.8
(V+)-1.2
(V-)+0.8
(V-)+0.4
Power Supply Voltage (V)
RL= 10 kΩ
-40 °C
+85 C°
+25 C°
-40 °C
+85 C°
-40 °C
+25 C°
+85 C°
0 5 10 15 20
Output Voltage Swing (V)
5
4
3
2
1
0
Input Current (mA)
Input Voltage (V)
G = 1 V / V
G = 1V / V
G = 1000V/V
G = 1000V/V VIN IIN
+15V
Flat region represents
normal linear operation.
1
2
3
4
5
-50
15V
-40 -30 -20 -10 0 10 20 30 40 50
10
8
6
4
2
0
0100 200 300 400 500
-2
-4
-6
-8
-10
Time (ms)
Offset Voltage Change (mV)
Gain (V/V)
Settling Time (ms)
100
10
1
0.01%
0.1%
110 100 1000
Frequency (Hz)
1 10 100
1k
100
10
1
10k
G = 1V / V
G =10V/V
100
10
1
0.1
Current Noise
G =100, 1000V/V
Input Bias Current Noise (pA/√Hz)
Input-Referred Voltage Noise (nV/
√Hz
)
¾
¾
1k
INA129-EP
www.ti.com
SBOS508A –DECEMBER 2009–REVISED DECEMBER 2015
Typical Characteristics (continued)
At TA= 25°C, VS= ±15 V, unless otherwise noted.
Figure 7. Input-Referred Noise vs Frequency Figure 8. Settling Time vs Gain
Figure 10. Input Offset Voltage Warm-Up
Figure 9. Input Overvoltage Voltage-to-Current
Characteristics
Figure 11. Output Voltage Swing vs Output Current Figure 12. Output Voltage Swing vs Power Supply Voltage
Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 9
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Frequency (Hz)
Peak-to-Peak Output Voltage (V )
PP
30
25
20
15
10
5
0
1k
G = 1
G =10, 100
G = 1000
10k 100k 1M
Frequency (Hz)
TH D + N (% )
100 1k
1
0.1
0.01
0.001
100k
VO=G = 1
RL
= 100kW
G =100, R = 100k
LW
500kHz Measurement
Bandwidth
Dashed Portion
is noise limited.
10k
G =1, R = 100k
LW
R = 10k
LW
G =10V/V
1 Vrms
INA129-EP
SBOS508A –DECEMBER 2009–REVISED DECEMBER 2015
www.ti.com
Typical Characteristics (continued)
At TA= 25°C, VS= ±15 V, unless otherwise noted.
Figure 14. Total Harmonic Distortion + Noise vs Frequency
Figure 13. Maximum Output Voltage vs Frequency
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A1
A2
A3
40 kW40 kW
40 kW
40 kW
VIN
2
1
8
3
6
5
VIN
RG
V+
V-
Ref
VO
G = 1 + 49.4 kW
RG
+
4
7
INA129
Over-Voltage
Protection
Over-Voltage
Protection
24.7 kW
24.7 kW
-
INA129-EP
www.ti.com
SBOS508A –DECEMBER 2009–REVISED DECEMBER 2015
7 Detailed Description
7.1 Overview
The INA129-EP instrumentation amplifier is a type of differential amplifier that has been outfitted with input
protection circuit and input buffer amplifiers, which eliminate the need for input impedance matching and make
the amplifier particularly suitable for use in measurement and test equipment. Additional characteristics of the
INA129-EP include a very low DC offset, low drift, low noise, very high open-loop gain, very high common-mode
rejection ratio, and very high input impedances. The INA129-EP is used where great accuracy and stability of the
circuit both short and long-term are required.
7.2 Functional Block Diagram
7.3 Feature Description
The INA129-EP device is a low power, general-purpose instrumentation amplifier that offers excellent accuracy.
The versatile three-operational-amplifier design and small size make the amplifier ideal for a wide range of
applications. Current-feedback input circuitry provides wide bandwidth, even at high gain. A single external
resistor sets any gain from 1 to 10,000. The INA129-EP device is laser trimmed for very low offset voltage (50
μV) and high common-mode rejection (93 dB at G ≥100). This device operates with power supplies as low as
±2.25 V, and quiescent current of 2 mA, typically. The internal input protection can withstand up to ±40 V without
damage.
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1s/div
0.1 V/divm
INA129-EP
SBOS508A –DECEMBER 2009–REVISED DECEMBER 2015
www.ti.com
7.4 Device Functional Modes
A single external resistor sets the any gain from 1 to 10000. TI INA129-EP provides an industry standard gain
equation, as highlighted in Figure 16.
7.4.1 Noise Performance
The INA129-EP provides very low noise in most applications. Low frequency noise is approximately 0.2 μVPP
measured from 0.1 Hz to 10 Hz (G ≥100). This provides dramatically improved noise when compared to state-
of-the-art chopper-stabilized amplifiers.
G≥100
Figure 15. 0.1-Hz to 10-Hz Input-Referred Voltage Noise
7.4.2 Input Common-Mode Range
The linear input voltage range of the input circuitry of the INA129-EP is from approximately 1.4 V below the
positive supply voltage to 1.7 V above the negative supply. As a differential input voltage causes the output
voltage increase, however, the linear input range will be limited by the output voltage swing of amplifiers A1 and
A2. So the linear common-mode input range is related to the output voltage of the complete amplifier. This
behavior also depends on supply voltage (see Figure 5 and Figure 6).
Input-overload can produce an output voltage that appears normal. For example, if an input overload condition
drives both input amplifiers to their positive output swing limit, the difference voltage measured by the output
amplifier will be near zero. The output of A3 will be near 0 V even though both inputs are overloaded.
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RG
Also drawn in simplified form:
Ref
VO
VIN
VIN
+
49.4kΩ
RG
NC: No Connection
A1
A2
A
3
6
7
4
3
8
1
2
VIN
VIN
RG
V+
+
5
Over Voltage
Protection
Over Voltage
Protection
Load
+
O
V
Ref
0.1 Fµ
0.1 F
V-
µ
24.7kΩ
24.74kΩ
40kΩ40kΩ
40kΩ40kΩ
VO
=
G (V - V )· IN IN
- +
-
-
-
G = 1 +
DESIRED
GAIN (V/V)
R
(Ω)
GNEAREST
1% R ( )
GΩ
1
2
5
10
20
50
100
200
500
1000
2000
5000
10000
NC
49.4K
12.35K
5489
2600
1008
499
248
99
49.5
24.7
9.88
4.94
NC
49.9K
12.4K
5.49K
2.61K
1K
499
249
100
49.9
24.9
9.76
4.87
INA129-EP
www.ti.com
SBOS508A –DECEMBER 2009–REVISED DECEMBER 2015
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The INA129-EP device measures small differential voltage with high common-mode voltage developed between
the non-inverting and inverting input. The high-input voltage protection circuit in conjunction with high input
impedance make the INA129-EP suitable for a wide range of applications. The ability to set the reference pin to
adjust the functionality of the output signal offers additional flexibility that is practical for multiple configurations.
8.2 Typical Application
Figure 16 shows the basic connections required for operation of the INA129-EP. Applications with noisy or high
impedance power supplies may require decoupling capacitors close to the device pins as shown.
The output is referred to the output reference (Ref) terminal which is normally grounded. This must be a low-
impedance connection to assure good common-mode rejection. A resistance of 8 Ωin series with the Ref pin will
cause a typical device to degrade to approximately 80 dB CMR (G = 1).
Figure 16. Basic Connections
8.2.1 Design Requirements
The device can be configured to monitor the input differential voltage when the gain of the input signal is set by
the external resistor RG. The output signal references to the REF pin. The most common application is where the
output is referenced to ground when no input signal is present by connecting the REF pin to ground, as
Figure 16 shows. When the input signal increases, the output voltage at the OUT pin increases, too.
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10kW
OPA177 100W
100W
1/2 REF200
1/2 REF200
V+
RGINA129
Ref
VO
VIN
VIN
+
10mV±
Adjustment Range
V-
100mA
100mA
-
G = 1 + 49.4 kW
¾
RG
INA129-EP
SBOS508A –DECEMBER 2009–REVISED DECEMBER 2015
www.ti.com
Typical Application (continued)
8.2.2 Detailed Design Procedure
8.2.2.1 Setting the Gain
Gain is set by connecting a single external resistor, RG, between pins 1 and 8.
(1)
Commonly used gains and resistor values are shown in Figure 16.
The 49.9-kΩterm in Equation 1 comes from the sum of the two internal feedback resistors of A1 and A2. These
on-chip metal film resistors are laser trimmed to accurate absolute values. The accuracy and temperature
coefficient of these internal resistors are included in the gain accuracy and drift specifications of the INA129-EP.
The stability and temperature drift of the external gain setting resistor, RG, also affects gain. RG’s contribution to
gain accuracy and drift can be directly inferred from Equation 1. Low resistor values required for high gain can
make wiring resistance important. Sockets add to the wiring resistance which will contribute additional gain error
(possibly an unstable gain error) in gains of approximately 100 or greater.
8.2.2.2 Dynamic Performance
Figure 1 shows that, despite its low quiescent current, the INA129-EP achieves wide bandwidth, even at high
gain. This is due to the current-feedback topology of the input stage circuitry. Settling time also remains excellent
at high gain.
8.2.2.3 Offset Trimming
The INA129-EP is laser trimmed for low offset voltage and offset voltage drift. Most applications require no
external offset adjustment. Figure 17 shows an optional circuit for trimming the output offset voltage. The voltage
applied to Ref terminal is summed with the output. The operational amplifier buffer provides low impedance at
the Ref terminal to preserve good common-mode rejection.
Figure 17. Optional Trimming of Output Offset Voltage
8.2.2.4 Input Bias Current Return Path
The input impedance of the INA129-EP is extremely high (approximately 1010 Ω). However, a path must be
provided for the input bias current of both inputs. This input bias current is approximately ±2 nA. High input
impedance means that this input bias current changes very little with varying input voltage.
Input circuitry must provide a path for this input bias current for proper operation. Figure 18 shows various
provisions for an input bias current path. Without a bias current path, the inputs will float to a potential which
exceeds the common-mode range, and the input amplifiers will saturate.
14 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated
Product Folder Links: INA129-EP
G = 1
20mV/div
G = 10
5 s/divm
G = 10 0
20mV/div
G = 10 0 0
20 s/divm
47kW47kW
10kW
Microphone,
Hydrophone
etc.
Thermocouple
Center-tap provides
bias current return.
INA129
INA129
INA129
INA129-EP
www.ti.com
SBOS508A –DECEMBER 2009–REVISED DECEMBER 2015
Typical Application (continued)
If the differential source resistance is low, the bias current return path can be connected to one input (see the
thermocouple example in Figure 18). With higher source impedance, using two equal resistors provides a
balanced input with possible advantages of lower input offset voltage due to bias current and better high-
frequency common-mode rejection.
Figure 18. Providing an Input Common-Mode Current Path
8.2.3 Application Curves
G = 100, 1000
G = 1, 10
Figure 20. Small Signal
Figure 19. Small Signal
Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: INA129-EP
G = 1
5V/div
G = 10
5 s/divm
5V/div
G =1000
20 s/divm
G =100
INA129-EP
SBOS508A –DECEMBER 2009–REVISED DECEMBER 2015
www.ti.com
Typical Application (continued)
G = 1, 10 G = 100, 1000
Figure 21. Large Signal Figure 22. Large Signal
16 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated
Product Folder Links: INA129-EP
REF102
R2
R1
Pt100
Cu
Cu
V+
K
6
10.0V
4
2
INA129
VO
Ref
R
R3
G
100Ω = Pt100 at 0°C
ISA
TYPE MATERIAL
SEEBECK
COEFFICIENT
( V/°C)m
R , R
1 2
E
J
K
T
+Chromel
-Constantan
+Iron
-Constantan
+Chromel
-Alumel
+Copper
-Constantan
58.5
50.2
39.4
38
66.5k
76.8k
97.6k
102k
W
W
W
W
INA129
RG
IB
R
V
1
IN
+
A1IO
Load
Ref
IO
VIN
R1
· G
A I
1 B ERROR
OPA177 ±1.5 nA
OPA131 ±50 pA
OPA602 ±1 pA
OPA128 ±75 fA
-=
INA129
RG
VO
OPA130
Ref R1
1MW
=1
2pR C
1 1
= 1.59 Hz
VIN
+
f-3dB
C1
0.1mF
-
300W
+5V
RGINA129 VO
Ref
2.5V ∆V
2.5V + ∆V
-
INA129-EP
www.ti.com
SBOS508A –DECEMBER 2009–REVISED DECEMBER 2015
9 Power Supply Recommendations
The minimum power supply voltage for INA129-EP is ±2.25 V and the maximum power supply voltage is ±18 V.
This minimum and maximum range covers a wide range of power supplies; but for optimum performance, ±15 V
is recommended. TI recommends adding a bypass capacitor at the input to compensate for the layout and power
supply source impedance.
9.1 Low Voltage Operation
The INA129-EP can be operated on power supplies as low as ±2.25 V. Performance remains excellent with
power supplies ranging from ±2.25 V to ±18 V. Most parameters vary only slightly throughout this supply voltage
range.
Operation at very low supply voltage requires careful attention to assure that the input voltages remain within
their linear range. Voltage swing requirements of internal nodes limit the input common-mode range with low
power supply voltage. Figure 5 and Figure 6 show the range of linear operation for ±15 V, ±5 V, and ±2.5 V
supplies.
Figure 23. Bridge Amplifier Figure 24. AC-Coupled Instrumentation Amplifier
Figure 25. Thermocouple Amplifier With RTD Cold- Figure 26. Differential Voltage to Current Converter
Junction Compensation
Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: INA129-EP
Bypass
Capacitor
Bypass
Capacitor
Gain Resistor
R6
V–IH
V+IH
V–
R6
V+
VO
REF
–
+
V+
VOUT
GND
VIN
VIN
GNDV–
INA129
RG/2
R = 5.6k
GW
VO
LA
RL
RA
10kW
Ref
G = 10
2.8kW
VV
G
G
2.8kW
1/2
OPA2131
390kW
390kW
1/2
OPA2131 NOTE: Due to the INA129’s current-feedback
topology, VGis approximately 0.7 V less than
the common-mode input voltage. This DC offset
in this guard potential is satisfactory for many
guarding applications.
INA129-EP
SBOS508A –DECEMBER 2009–REVISED DECEMBER 2015
www.ti.com
Low Voltage Operation (continued)
Figure 27. ECG Amplifier With Right-Leg Drive
10 Layout
10.1 Layout Guidelines
Place the power-supply bypass capacitor as closely as possible to the supply and ground pins. The
recommended value of this bypass capacitor is 0.1 μF to 1 μF. If necessary, additional decoupling capacitance
can be added to compensate for noisy or high-impedance power supplies. These decoupling capacitors must be
placed between the power supply and INA129-EP device.
The gain resistor must be placed close to pin 1 and pin 8. This placement limits the layout loop and minimizes
any noise coupling into the part.
10.2 Layout Example
Figure 28. Recommended Layout
18 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated
Product Folder Links: INA129-EP
INA129-EP
www.ti.com
SBOS508A –DECEMBER 2009–REVISED DECEMBER 2015
11 Device and Documentation Support
11.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2009–2015, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: INA129-EP
PACKAGE OPTION ADDENDUM
www.ti.com 9-Oct-2014
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
INA129MDREP ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -55 to 125 129EP
V62/10605-01XE ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR -55 to 125 129EP
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 9-Oct-2014
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF INA129-EP :
•Catalog: INA129
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
INA129MDREP SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Oct-2014
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
INA129MDREP SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Oct-2014
Pack Materials-Page 2
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