2013 Microchip Technology Inc. DS60001239A-page 1
®
OCTOBER 2013
OS81092 Evaluation Board
User’s Guide
DB81092PCB5.A
Supporting
MOST®
Media Oriented Systems Transport
OS81092 Evaluation Board User’s Guide
DS60001239A-page 2 2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be
superseded by updates. It is your responsibilit y to ensure that your app lication meet s with your specif icat ions. MI CROCHIP M AKES NO
REPRESENTATIONS OR WARRANTIES OF ANY KIND WHET HER EX PRESS OR IMPLIE D, WRITTE N OR O RAL, STATUT OR Y OR
OTHERWISE, RELA TED TO THE INFORMA TION, INCLUDING BU T NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
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hold harmless Microchip from any and all damages, claims, suit s, or expenses resulting from such use. No license s are conveyed, implic-
itly or otherwise, under any Microchip intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICST ART, PIC32
logo, rfPIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip T echnology Incorporated in the U.S.A. and
other countries.
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registered trademarks of Microchip Technology Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM,
MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-
Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other coun tries.
A more complete list of registered trademarks and common law trademarks owned by St andard Microsystems Corporation (“SMSC”)
is available at: www.smsc.com. The absence of a trademark (name, logo, etc.) from the list does not constitute a waiver of any
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All other trademarks mentioned herein are property of their respective companies.
© 2013, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-62077-325-3
Microchip received ISO/TS-16949:2009 certification for its worldwide
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Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microp eriph erals, no nvolatile memory a nd
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and manufacture of development systems is ISO 9001:2000 certified.
QUALITYMANAGEMENTSYSTEM
CERTIFIEDBYDNV
== ISO/TS16949==
2013 Microchip Technology Inc. DS60001239A-page 3
OS81092 Evaluation Board User’s Guide
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OS81092 Evaluation Board User’s Guide
DS60001239A-page 4 2013 Microchip Technology Inc.
Table of Contents
1 OVERVIEW ............................................................................................................................7
2 CONFIGURATION AND STA TU S ......... ................ ... ................. ... ................ ... ... ................ ..11
3 POWER DISTRIBUTION ......................................................................................................12
4 RESET ARCHITECTURE ............... ... ................ ... ... .... ................ ... ... ... ................. ... ... ... .....14
5 DAUGHTER BOARD AND AUXILIARY CONNECTORS .....................................................16
6 OS81092 INIC ......................................................................................................................18
7 OS85650 IOC .......................................................................................................................23
8 PIC32 EHC ...........................................................................................................................26
9 AUDIO AND LOW FREQUENCY SIGNAL TUNNELI NG (LFST) .... ... ... .... ................ ... ... .....39
10 POWER MANAGEMENT .....................................................................................................42
11 MCP2200 COMMBRIDGE .... ... ... .... ... ... ... ................ .... ... ................ ... ... ................. ... ... ........47
APPX A OPERATING CONDITIONS . ... ... ... ... .... ... ... ... ................. ... ... ... ... .... ... ................ ... ... ..49
APPX B PCB DETAILS .......... ... ... ................ ... .... ... ................ ... .... ... ................ ... ... .... ..............50
APPX C COMPONENT PLACEMENT ... ... ................ ... .... ... ... ... .... ................ ... ... ... .... ... ... ... .....51
APPX D DB81092PCB5.A SILK SCREENS WITH COMPONENT GRID PLACEMENTS ......56
APPX E DB81092PCB5.A SCHEMATIC LAYOUT FILES .......................................................66
APPX F REFERENCES ............................ ... ... .... ................ ... ... .... ................ ... ... ... .... ..............91
APPX G USER’S GUIDE REVISION HISTORY .......................................................................93
APPX H LIST OF FIGURES ............ .... ................ ... ... ... ................. ... ... ... ................ .... ... ... ........94
Conventions
The following abbreviations and symbols are used to improve readability.
Example Description
BIT Name of a single bit within a field
FIELD.BIT Name of a single bit (BIT) in FIELD
x…y Range from x to y, inclusive
BITS[m:n] Groups of bits from m to n, inclusive
PIN Pin Name
SIGNAL Signal Name
msb, lsb Most significant bit, least significant bit
MSB, LSB Most significant byte, least significant byte
zzzzb Binary number (value zzzz)
0xzzz Hexadecimal number (val ue zzz)
zzh Hexadecimal number (value zz)
rsvd Reserved memory location. Must write 0, read value indeterminate
code Instruction code, or API function or parameter
Multi Word Name Used for multiple words that are considered a single uni t, such as:
Resource Allocate message, or Connection Label, or Decrement Stack Pointer instruction.
Section Name Emphasis, Reference, Section or Document name.
VAL Over-bar indicates active low pin or register bit
xDon’t care
<Parameter> <> indicate a Parameter is optional or is only used under some conditions
{,Parameter} Braces indicate Parameter(s) that repeat one or more times.
[Parameter] Brackets in dicate a nest ed Parameter. This Parameter is not real an d actually de codes into one or
more real p arameters.
2013 Microchip Technology Inc. DS60001239A-page 5
OS81092 Evaluation Board User’s Guide
DB81092PCB5.A FRONT PHOTO
The OS81092 Evaluation Board User’s Guide contains Silkscreen, Layout and Schematic draw-
ings corresponding to Evaluation Board DB81092PCB5.A. This board uses a Microchip
OS81092 INIC (Intelligent Network Interface Controller) specifi c ally for MOST50 proto c ol appli-
cations, including MOST ToGo Applications. Please note, the name “Eval92 Board” “Eval92,”
Eval92 MOST ToGo” and “Eval92-MTG” are also used within reference drawings and on the
board itself. These alternative names all refer to the DB81092PCB5.A evaluation board.
OS81092 Evaluation Board User’s Guide
DS60001239A-page 6 2013 Microchip Technology Inc.
DB81092PCB5.A BACK PHOTO
2013 Microchip Technology Inc. DS60001239A-page 7
OS81092 Evaluation Board User’s Guide
1.0 OVERVIEW
The OS81092 Evaluation Board, also referenced within this document as “Eval92 Board” (DB81092PCB5.A) is a com-
plete MOST50 Network device, utilizing the Microchip OS81092 (INIC) device [1]. An on-board Microchip PIC32
External Host Controller (EHC) is available for development of custom application code or use of application code avail-
able from Microchip. An integrated Microchip OS85650/2 (IOC) device [2] provides I/O port expansion for additional
application flexibility. The Eval92 Board also supports power management, controlled by the Microchip MPM85000
Power Manager Device (PwrMgr) [3], a MOST-compliant power management device.
The INIC Streaming Port, in conjunction with an on-board ADC and DAC, supports 2 channel (e.g. stereo) audio
exchange on the network. The ster eo audio COD EC device is capable of driving headphones at the aud io output jack
with stereo audio data it sinks from the network. Additionally, a line-level input jack conn ected to th e CODEC suppo rts
sourcing stereo audio data to the network.
An overview of the Eval92 Board hardwa re is shown in Figure 1-1.
FIGURE 1-1: HARDWARE BLOCK DIAGRAM
Used in conjunction with other Microchip hardware, software, and tools, the Eval92 Board provides a platform for com-
prehensive understanding of a complete MOST50 Network device. While the Eval92 Board was developed for the
MOST ToGo network demo system, it is also a useful as a stand alone evaluation board and reference design with both
schematics and layouts for customer boards. The platform is also useful for software programmers writing custom EHC
applications, as well as users who simply want to work with the standard EHC application code available for the board.
Refer to the MOST ToGo Basic Appl ication Code Firmware Manual [4] for information on the available standard EHC
application code load(s). Contact Microchip for information on other application code available for the Eval92 Board.
MLB 3-Pin
MOST I2C Bus
Board Peripheral
I2C Bus
SPI
Debug
Port
CANIF
UART (LIN/ECL)
PIC32
EHC
PIC32MX795
USB-to-UART
Serial
Converter
MCP2200
24 Channel
I/O E x p an d e r
TCA6424
Stereo Audio
CODEC
UDA1380
SingleWire
CAN PHY
MC33897 DIP Switch
Rotary
Switch
I2S
Jump er
Selection
Options
DaughterBoard
Connector
MOST50
INIC
OS81092
IOC
OS85650
Power
Manager
MPM85000
Microchip Components
32 k b it
EEPROM
24LC32AT
OS81092 Evaluation Board User’s Guide
DS60001239A-page 8 2013 Microchip Technology Inc.
1.1 Board Features
Primary hardware features of the Eval92 Board include:
• Integrated Intelligent Network Interface Controller (INIC) [1]
• Electrical Physical Layer (ePHY) interface to a MOST50 Network
• Integrated I/O Companion (IOC), including DTCP coprocessor
• Integrated External Host Controller (EHC), supporting:
- Single-wire CAN interface in conjunction with on-board CAN PHY device
- USB host functionality with connecti on to external device(s) using standard Type A receptacle
- UART connection to on-board CommBridge (for USB debug print terminal output on PC)
• Feature set expansion via Daughter Board and Auxiliary connectors supporting additional application options (e.g.
video sourcing/sinking and low fre quency signal tunneling)
• Stereo audio capabilities (via INIC or IOC Streaming Port), supporting:
- sourcing stere o audio to the network from an on-board line-l e ve l i nput jack, and
- sinking stereo audio from the network and driving an on-board headphone jack
• MOST-compliant power management capabilities, including:
- Network activity detection
- Control of switched application power regulators (3.3 V and 1.8 V supplies)
- Contin uous 3.3 V power supply
- EHC Reset generator based on 3.3 V switched power
- INIC and IOC reset generator, powered by 3.3V switched power, conditional on 1.8V switched power
- Support for MOST Sleep Mode with very low quiescent current
- INIC power management, including voltage level reportin g per levels defined in the MOST Specification
3.0 [5]
- Support for wakeup signaling and MOST System Test via MOST Electrical Control Line [6]
- Serial interface for configuration and status information
1.2 Typical Applications
The INIC device contains the INIC Software Stack which manages the netwo rk with mini mal interaction with the EHC.
This allows network nodes to start up without having to wait for the EHC to power-up/initialize. Application functionality
in MOST Network devices is implemented with Function Blocks (FBlocks). In addition to application FBlocks that may
be supported by EHC application code, FBlock INIC (contained within the INIC itself) is used for configuring and con-
trolling INIC. A complete FBlock INIC reference guide is available in the OS81092 MOST50 INIC API User’s
Manual [7].
The MOST ToGo boards are meant to serve as a platform to create a variety of example applications and support many
different network configurations and demos. T herefore, application code fo r the on-bo ard EHC may use only a subset
of the available hardware devices and interfaces for communication. In general there are two main types of EHC appli-
cation code for the Eval92 Board:
•A Standard Application uses simple I2C communication between the INIC and the EHC to implement a basic net-
work node. The application may also manage the on-board ADC and DAC (connected to the INIC S treaming Port)
for sourcing/sinking stereo audio to/from the network. The on-board IOC is not used. These applications are good
learning examples, and are suitable for simple synchronous sources and sinks.
•An Expanded Application includes use of the IOC and other EHC peripherals. The IOC can be utilized such that it
is between the EHC and the INIC to take advantage of its high speed interfaces such as SPI. These applications
offer the possibility of much higher asynchronous (packet data) bandwidth, with the added complexity of having to
configure the IOC. The application may also include further functionality provided by external devices attached to
the DAUGHTERBOARD connector (J21) or the AUX connector (J33).
EHC application code for the Eval92 Board (including custom code) should provide a Stand-Alone mode option (typically
implemented using the on-board DIP switch). When ena bled, this mode should allow INIC to function completely inde-
pendent of the EHC, with all INIC-EHC interacti on disabled. This mode illustrates network interactio n, independent of
the application, where INIC powers up, enters the network, and autonomously manages the low-level network manage-
ment function s.
2013 Microchip Technology Inc. DS60001239A-page 9
OS81092 Evaluation Board User’s Guide
1.2.1 STANDARD APPLICATION
In an Eval92 Board Standard Application, the EHC communicates with INIC (and other board peripherals) via the
I2C bus(es). Power mana gement capabilities are availabl e, and the INIC Streaming Port can be used for stereo audio
exchange between the network and the AUDIO IN (J2) and AUDIO OUT (J3) jacks. The EHC may support FBlocks AuxIn
and AudioAmp for managing the streaming audio exchange remotely . In an Eval92 Board Standard Application, the IOC
is not used.
Figure 1-2 shows the Eval92 Board hardware components typically used by a Standard Application.
FIGURE 1-2: STANDARD APPLICATION DIAGRAM
Eval92 Board St andard Application source code is available from Microchip. Refer to the MOST ToGo Basic Application
Code Firmware Manual [4] for more information.
1.2.2 EXPANDED APPLICATION
In an Eval92 Board Expanded Application, the functionality of a St andard Application is extended to include the IOC and
other EHC interfaces and peripherals. An Expanded Application may also utilize the INIC-IOC communication via the
Media Local Bus (MediaLB®) 3-pin interface. In this case, the IOC acts a bridge between the INIC and EHC for exchang-
ing various data types including control and packet. Th e IOC Streaming Port A can be used for expanded streaming
audio exchange between the ne twork and the COD EC whil e IOC Streaming Port B is available for u se with the EH C’s
IISC (I2S) port. The application may also include further functionality provided by external devices attached to the
daughterboard connector (J21) or the auxiliary connector (J33).
Figure 1-3 shows the Eval92 Board hardware components typically used by an Expanded Application.
MediaLB
3-pin Po rt
Network Port
Power
Monitor
& Control
IN
OUT
CODEC
SWA EHC
Application Code
Low-Leve l Driver: I2C Master
NBEHC:
FBlock
Enhanced
Testability:
FBlock
CB USB
AuxIn:
FBlock
AudioAmp:
FBlock
ERXP/ERXN
PwrMgr
Streaming
Port
18.432 MHz
Crystal
INIC
RMCK Port
Clock
Manager
INIC SW Stack
INIC:
FBlock
NBMIN:
FBlock
BOARD
OPTIONS
PS0, PS1, PWROFF
WAKE/SLEEP
12345678
O P E N
Control Port
AUDIO
ePHY Front End
Circuitry
MOST
Network
SWB
(Debug Output)
Comm
Bridge
OS81092 Evaluation Board User’s Guide
DS60001239A-page 10 2013 Microchip Technology Inc.
FIGURE 1-3: EXPANDED APPLICATION DIAGRAM
Contact Microchip for information on availability of Expanded Application source code for the Eval92 Board.
ERXP/ERXN PwrMgr
PS0, PS1, PWROFF
WAKE/SLEEP
INIC
INIC SW Stack
INIC:
FBlock
NBMIN:
FBlock
EHC
Application Code
NBEHC:
FBlock Enhanced
Testability:
FBlock
FBlock
2 x AudioAmp:
FBlock
2 x AuxIn:
Low-Level Drivers
I2C Master SPI
Streaming
Port
RMCK Port
Clock
Manager
MediaLB
3-pin Port
Network Port
Power
Monitor
& Control
Control Port
IN
OUT
CODEC
AUDIO
18.432 MHz
Crystal ePHY Front End
Circuitry
MOST
Network
SWA
CB USB
BOARD
OPTIONS
12345678
O P E N
SWB
(Debug Output)
Comm
Bridge
IOC
SPI/TSI
Ports
MediaLB
3-Pin Port
Streaming
Port A
HBI Port
MediaLB
6-Pin Port
Control
Port
Streaming
Port B
CAN
PHY CAN
(Gateway Application)
IISC (I2S)
(Streaming Audio Application)
2013 Microchip Technology Inc. DS60001239A-page 11
OS81092 Evaluation Board User’s Guide
2.0 CONFIGURATION AND STATUS
2.1 LEDs
A number of LEDs are us ed on the Eval92 Board to convey board an d application status informa tion to the user. The
following LEDs have dedicated functionality controlled by on-board hardware:
•The BOARD PO W E R red LED (D209) indicates that the INIC, IOC and EHC are powered up. The LED is lit when
both the MAIN_3V3 and MAIN_1V8 supplies are on.
•The CB PWR red LED (D207) indicates that the CommBridge is powered up. The LED is lit when both the CB_3V3
and CB_1V8 supplies are on.
•The LOCK green LED (D217) is controlled by the INIC ERR/BOOT pin. The LED is lit when the network is locked .
•The IOC ERROR orange LED (D221) is controlled by the IOC ERROR pin. An inverter is used so that this LED is lit
whenever the IOC PLL is unlocked (i.e . error condition).
•The INIC RESET yellow LED (D218) is lit whenever the INIC_RST signal is asserted (Section 4.1 “INIC Reset”).
•The IOC RESET yellow LED (D219) is lit whenever the IOC_RST signal is asserted (Section 4.2 “IOC Reset”).
•The EHC RESET yellow LED (D220) is lit whenever the EHC_RST signal is asserted (Section 4.3 “EHC Reset”).
•The EHC DFU orange LED (D206) is lit whenever the EHC_DFU signal is asserted. Ty pically, this signal is only
used when the EHC bootloader is active (i.e. during a firmware update).
•The USB TX yellow LED (D205) and USB RX yellow-green LED (D6) flicker to indicate traffic to / from the Comm
Bridge and the EHC.
The remaining LEDs are general purpose LEDs available to the EHC application code, where:
• The green LED (D203) is active-low and available at I/O expander (U200) channel P14 (LED1).
• The yellow LED (D202) is active-low and available on I/O expander (U200) channel P15 (LED2).
• The orange LED (D201) is active-low and available on I/O expander (U200) channel P16 (LED3).
• The red LED (D200) is active-low and avai lable on I/O expander (U200) channel P17 (LED4).
2.2 Switches
The Eval92 Board provides an 8-position DIP switch (BOARD OPTIONS, S2) for EHC configuration options. The exact
functionality depends on the application code; however , DIP switch settings are typically latched at startup and used as
run-time configuration settings. Examples of run-time options include enabling/disabling debug print output and
enabling/disabling Stand-Alone mode.
The DIP switch itself is connected to the I/O expander (U200); therefore, the EHC uses the I2C Boar d Peripheral Bus
to determine the values. See Section 8.4.1 “I2C Communication” for more information about the EHC’s I2C buses. The
DIP switch connections to the I/O expander are as follows:
The Eval92 Board also supports a 16-position rotary switch (ID, S1) which allows the user to set unique identifiers on up
to 16 different MOST ToGo boards. EHC application code can set various application values/fields appropriately, based
on the switch setting. One such example is setting the board’s unique ECL Node Class, for use during the MOST System
Test. Refer to the MOST Electrical Control Line Specification [6] for more information.
The Eval92 Board also supports two general-purpose push-button switches (SWA and SWB) connected to the EHC at
RD8 and RE6, respectively . These switches are debounced by a specialized debounce device (U210) that uses a 40 ms
qualification timer. The debounced outputs are push-pull outputs and do not require pull-u p resistors.
Note: DIP switch 6 is also used by hardware to override power management shut-
down capabilities. Refer to Section 10.4 “Disabling Power Management” for
more information.
• DIP switch 1 connects to U200 channel P00
• DIP switch 2 connects to U200 channel P01
• DIP switch 3 connects to U200 channel P02
• DIP switch 4 connects to U200 channel P03
• DIP switch 5 connects to U200 channel P04
• DIP switch 6 connects to U200 channel P05
• DIP switch 7 connects to U200 channel P06
• DIP switch 8 connects to U200 channel P07
OS81092 Evaluation Board User’s Guide
DS60001239A-page 12 2013 Microchip Technology Inc.
3.0 POWER DISTRIBUTION
The Eval92 Board prov ides a sing le h arness co nne ctor (ePHY NETWORK, J18) fo r supplying ePHY network signals and
power (12 V typical) to the module. Once filtered, power from the cable harness supplies the PwrMgr (U3) and the CAN
transceiver (U202). The power management device provides a constant 3.3 V supply (VDDU) and controls 12 V switched
power (12VP_SW) that supplies the on-board regulators. 12 V switched and protected power is also available at sev era l
headers for off-board use (J21, J200 and J33). The PwrMgr supports Sleep Mode, where the board is mostly powered
off (e.g. all switched supplies disabled). When the switched supplies are active, all board circuitry is powered.
A POWER ja ck (J6) suppo rts a Binder 99 3403 282 03 (or equivalent) connector, to provide main board power from an
external lab supply, rather than from the ePHY connector. By defa ult, this power connector is not populated.
A 2-position micro-fit Molex 43650-0209 connector (J203) provides external devices with direct access to unprotected
and unswitched battery power from the cable harness. A second 2-position Molex connector (J200) and a firmware con-
trolled switch (U201) allow the EHC to provide a connected load with protected and switched 12 V power.
The Eval92 Board includes a 5 V charge pump device (U14) to supply bus power for the USB type A receptacle (J20).
This regulator is controlled by th e EHC USB_VBUS_EN sign al. The charge pu mp sources up to 125 mA for connected
devices.
Figure 3-1 shows an overview of the Eval92 Board power distribution scheme.
FIGURE 3-1: POWER DISTRIBUTION
ON/OFF
12VP
S3
VDDU
NO POP
VDDU
J18
+
_
HARNESS_BATT_NEG
HARNESS_BATT_POS
VBATT
High-Side
Switch
Application Specific Load Dump Filter
CAN PHY
(MC33897)
VBATT
ENABLE
VPRO VPRO
HOLD
PwrMgr
(MPM85000)
3.3 V
Switching
Regulator
1.8 V
Linear
Regulator
12VP_SW MAIN_3V3 MAIN_1V8
AUX
Conn.
U211
U202
U3
U5 U13
Dau
Crd
Conn.
J21
J33
U201
High-Side
Switch
Remote
Power
Connector
J200
Battery
Power Ou t
Connector
J203
EHC
(PIC32)
5 V Charge
Pump
USB_5V
U4 U1
U2
U14
IOC
(OS85650)
INIC
(OS81092)
CB_3V3
EN
EN
EHC USB
Connector
J20
Comm
Bridge
(MCP2200)
J7
U7
U11
CB_USB_5V
3.3 V Linear
Regulator
U9
OUT IN
OUT
IN
EN
CB USB
Connector
IN OUT
OUT IN
J6
OUT
IN
IN OUT
CB_USB_3V3
0
R212
ePHY + PWR
Cable Harness
OUT
A
B
2013 Microchip Technology Inc. DS60001239A-page 13
OS81092 Evaluation Board User’s Guide
For proper operation, the main board power switch (S3) must be ON and the main board power supply (e.g. through the
ePHY NETWORK connector) must be above the minimum Power On Voltage, as defined in Appendix A: “Operating Con-
ditions” on page 49. The power switch is not part of the power managemen t a rchitecture an d should re main i n the ON
position for normal operation. When in Sleep Mode, the power switch should not be used to power cycle the Eval92
Board, as the load-dump capacitors can ma intain voltage for hundred s of seconds when the switch is in th e OFF posi-
tion.
The Eval92 Board implemen ts an automatic po wer switch (U7) to control the CommBridge power source. If the board
is connected to a PC with a USB cable via J7, the CommBridge always runs from the external USB power (even when
the board is in Sleep Mode). If the external supply is removed, the CommBridge automatically switches over to the
MAIN_3V3 supply. Refer to Chapter 11.0 for more information on CommBridge functionality.
Note: Although the board contains typical load-dump circuitry, it is not guaranteed
to pass any particular OEM specifications. For production systems, the load-
dump circuitry should be designed to meet the required OEM specifications
while ensuring that the PwrMgr and associated circuitry remain within their
respective specifications at all times.
OS81092 Evaluation Board User’s Guide
DS60001239A-page 14 2013 Microchip Technology Inc.
4.0 RESET ARCHITECTURE
The Eval92 Board provides the flexibility to reset the main devices on the board either simultaneously (via the
BOARD RESET switch S9) or separately (via independent reset switches). The PwrMgr provides a system-wide POR sig-
nal and monitors the MAIN 3V3 supply . Individual voltage supervisor devices monitor the secondary core supply for each
main IC while simultaneously debouncing reset input signals from the hardware switches. Additionally:
• INIC and the IOC can be reset independently by the EHC,
• INIC and the IOC can be reset independently by the CommBridge,
• the IOC and EHC can be reset by INIC (via the RSOUT pin), and
• header access allows each reset signal to be controlled independently.
Figure 4-1 shows an overview of the Eval92 Board reset implementation.
FIGURE 4-1: BOARD RESET ARCHITECTURE
Note: The robust reset architecture shown above is provided on the Eval92 Board
for flexibility in software development and is not required for production
applications. Refer to the MOST INIC Hardware Concepts Technical
Bulletin [8] for more information on typical ECU reset architectures.
MAIN_1V8
Reset
Generator
* Reset signal from EHC, Com m Bridge,
MOST CONTROL header and INIC DEBUG header.
MAIN_3V3
INIC
RSOUT
RST
EHC
RESET
IOC
RST
INIC RESET
S8 MAIN_3V3
INIC_RST
MAIN_1V8
Reset
Generator
* Reset signal from EHC, INIC, CommBridge,
MOST CONTROL header and IO C DEBUG header.
MAIN_3V3
15 k
IOC RESET
S7
IOC_RST
EHC_1V8
Reset
Generator
* Reset signal from INIC, CommBridge, E HC DEBUG
header, EHC JTAG header, and EHC NEXUS header.
MAIN_3V3
15 k
EHC RESET
S6
EHC_RST
* Also resets serial data flash (U11)
and I/O expa nder (U200) devi ces .
IOC_RST
EHC_RST
S9
BOARD RESET
PM_PWROFF
* Prevents power-down while
board reset i s a sserted.
PwrMgr
RESET
PWROFF
47 k
MAIN_3V3
MAIN_3V3
15 k
MAIN_3V3
15 k
MAIN_3V3
* Available at PWR MGMT header.
(This signal is used for PHY_RST in
MOST150 applications)
PM_RST
D10
D11
BOARD_RST
D223
U207
15 k
15 k
D224
U208
D225
U209
U4
U2
U1
U3
D222
2013 Microchip Technology Inc. DS60001239A-page 15
OS81092 Evaluation Board User’s Guide
4.1 INIC Reset
INIC on the Eval92 Board can be reset by:
• the PwrMgr internal reset generator (RESET output pin) that monitors the 3.3 V supply (MAIN_3V3) for predefined
under-voltage conditions,
• the on-board reset generator (U207) when the 1.8 V supply (MAIN_1V8) crosses a predefined threshold,
• the application (via EHC INIC_RST signal RA9),
• pressing the INIC RESET switch (S8),
• pressing the BOARD RESET switch (S9) when D223 is installed (default), or
• external devices connected to the INIC DEBUG or MOST CONTROL headers J31 and J17, respectively).
A yellow LED (D218) is lit whenever the INIC_RST signal is driven low (active).
The Eval92 Board supports the use of INIC’s application reset output. Th e INIC RSOUT pin is connected to the reset
input of the IOC and EHC. INIC drives RSOUT low (and resets the IOC and EHC) when:
•the INIC.Reset() function is received from the network with the EHC parame ter set (requires the
INIC.RemoteAccess() function to be enabled), or
• a Watch dog timeout occurs while the Mode parameter of the INIC.WatchdogMode() function is set to Reset.
4.2 IOC Reset
The IOC on the Eval92 Board can be reset by:
• the PwrMgr internal reset generator (RESET output pin) that monitors the 3.3 V supply (MAIN_3V3) for predefined
under-voltage conditions,
• the on-board reset generator (U208) when the 1.8 V supply (MAIN_1V8) crosses a predefined threshold,
•INIC RSOUT pin (as described in Section 4.1 “INIC Reset”) when D11 is installed (default),
• the application (via EHC RB10),
• pressing the IOC RESET switch (S7),
• pressing the BOARD RESET switch (S9) when D224 is installed (default), or
• external devices connected to the IOC DEBUG or MOST CONTROL headers (J30 and J17, respectively).
A yellow LED (D219) is lit whenever the IOC_RST signal is driven low (active).
4.3 EHC Reset
The EHC can be reset on the Eval92 Board by:
• the INIC RSOUT pin (as described in Section 4.1 “INIC Reset”) when D10 is installed (default),
• pressing the EHC RESET switch (S61F),
• pressing the BOARD RESET switch (S9) when D225 is installed (default), or
• an external device (or jumper shunt) on any of the following headers:
-EHC ICSP Programming/Debug header, J27
-EHC JTAG header, J24
-CommBridge GP0 signal
A yellow LED (D220) is lit whenever the EHC reset signal is driven low (active). The EHC reset signal (EHC_RST) also
issues reset conditions to on-board EHC peripheral devices such as the I/O expander (D220), and the Daughter Board
if D227 is populated (not by default).
OS81092 Evaluation Board User’s Guide
DS60001239A-page 16 2013 Microchip Technology Inc.
5.0 DAUGHTER BOARD AND AUXILIARY CONNECTORS
The Eval92 Board supports feature set expansion using off-board hardware by offering two connector options for inter-
facing to other PCBs and/or external devices. The first option is the 40-pin DAUGHTERBOARD connector (J21). The sec-
ond option is the 12-pin AUX connector (J33). Refer to Section 5.3 “Off-Board Applications” for possible application
examples utilizing these connectors.
5.1 Daughter Board Connector
The DAUGHTERBOARD connector is a hi gh-spe ed, 44-pin, Samte c so cket h eader (part number QSH-020-01-L-D-D P-A)
that is designed to be mated with the Sa mtec QTH series of terminal headers. In order to provide clearance to all on-
board components and headers, external PCBs connecting to J21 should utilize a QTH con nector specifying a mated
height of at least 11 mm. The DAUGHTERBOARD connector defin i ti on is provided in Table 5-1.
TABLE 5-1: DAUGHTER BOARD CONNECTOR DEFINITION
Pin # * Net Name Description / Notes
1 Unused signal - connects to TP26.
2INIC_MLBCLK MediaLB Clock line - connects to the MediaLB 3-pin bus between the INIC and IOC.
3DC_I/O_INT Daughter Board I/O expander interrupt signal - connects to EHC RD6.
6INIC_MLBSIG MediaLB Signal line - connects to the MediaLB 3-pin bus between the INIC and IOC.
10 INIC_MLBDAT MediaLB Data line - connects to the MediaLB 3-pin bus between the INIC and IOC.
13 DC_ATT Daughter Board attached signal - connects to I/O expander channel P27 with a weak
pull-up resistor. Should be tied directly to ground on the daughterboard PCB.
14 DC_READY Daughter Board ready signal - connects to EHC RE0. The daughterboa rd application
should drive this signal low to indicate it is ready for access by the host application on
the Eval92 Board.
15 DC_INT Daughter Board interrupt signal - connects to EHC RD13.
16 DC_RST Daughter Board reset input - connects to EHC RE3 through a 0 resistor (R309). This
signal can also be influenced by the IOC_RST and EHC_RST signals through series
diode options.
29 MOST_SCL I2C Clock line - connects to the MOST Control Bus I2C bus
30 PERIPH_SCL I2C Clock line - connects to the Board Peripheral Bus I2C bus
31 MOST_SDA I2C Data line - connects to the MOST Control Bus I2C bus
32 PERIPH_SDA I2C Data line - connects to the Board Peripheral Bus I2C bus
33 MAIN_1V8 Main board 1.8 V switched power supply.
35 MAIN_1V8 Main board 1.8 V switched power supply.
37 MAIN_3V3 Main board 3.3 V switched power supply.
38 12VP_SW Main board 12 V protected and switched battery power.
39 MAIN_3V3 Main board 3.3 V switched power supply.
40 12VP_SW Main board 12 V protected and switched battery power.
41 GND Main board ground.
42 GND Main board ground.
43 GND Main board ground.
44 GND Main board ground.
* Connector pins omitted from this table are not connected on the Eval92 Board and are reserved for future use.
2013 Microchip Technology Inc. DS60001239A-page 17
OS81092 Evaluation Board User’s Guide
5.2 Auxiliary Connector
The AUX connector J33 is a 12-pin, Wuerth Electronics ZIF WR-FPC connector (part number 68711214522) that is
designed to be mated with a flat, flexible ribbon cable. The AUX connector defin i ti on is pro v i d ed in Table 5-2.
5.3 Off-Board Applications
The DAUGHTERBOARD connector inclu des signals for both I2C buses and the MediaLB 3-pin bus signals, the reby per-
mitting a variety of application possibilities when an external PCB is attached. One such example is an external control-
ler that replaces the on-board EHC. W hen the EHC is placed in Stand-Alone mode, an external device is capable of
controlling INIC and certain peripheral ICs such as the IOC and PwrMgr.
The DAUGHTERBOARD connector can also be used to extend the feature set of the board while still using the on-bo ard
EHC. For example, a daughterboard featuring an OS85621 Video I/O Companion device [9] can be attached to add
video sourcing and sinking capabilities to the application.
The AUX connector is intended to support an external device that is managed by the on-board EHC. Possible implemen-
tations include I/O feature set expansion such as a remote display board (with a UAR T interface) for use in LFST appli-
cations, as described in Section 9.2 “Low Frequency Signal Tunneling”.
TABLE 5-2: AUXILIARY CONNECTOR DEFINITION
Pin # Net Name Description / Notes
1AUX_ATT Auxiliary attached signal - connects to I/O expander channel P23 with a weak pull-up
resistor. Should be tied directly to ground on the auxiliary PCB/device.
2AUX_SX Auxiliary data signal - connects to pin 2 of AUX CONFIG header (J11). A shunt can be
used on J11 to connect this signal to either the INIC Streaming Port or the EHC I2S
Port. Refer to Section 9.2 “Low Frequency Signal Tun neling” for more information.
3 Unused signal - connects to TP34.
4GND Main board ground.
5MAIN_3V3 Main board 3.3 V switched power supply.
612VP_SW Main board 12 V protected and switched battery power.
712VP_SW Main board 12 V protected and switched battery power.
8MAIN_3V3 Main board 3.3 V switched power supply.
9GND Main board ground.
10 PERIPH_SDA I2C Data line - connects to the Board Peripheral Bus I2C bus
11 PERIPH_SCL I2C Clock line - connects to the Board Peripheral Bus I2C bus
12 AUX_INT Auxiliary interrupt signal - connects to EHC RD12.
OS81092 Evaluation Board User’s Guide
DS60001239A-page 18 2013 Microchip Technology Inc.
6.0 OS81092 INIC
The Eval92 Board utilizes an OS81092 MOST50 (INIC)
device [1] (U1) to communicate over the MOST50 Net-
work. By default, INIC powers up with the I2C Control
Port enabled and is ready for access by an I2C bus
master device (e.g. EHC). Alternatively, R284 can be
installed (and R285 removed) to configure INIC for
MediaLB access following power-up/reset. Refer to
Section 6.7 “MediaLB Port” and Section 8.4.1 “I2C
Communication” for more information on Eval92 Board
MediaLB and I2C communication interfaces.
When Stand-Alone mode is enabled (see Section 8.2
“Stand-Alone Mode”), the EHC sh ould disable its com-
munication interfaces, allowing the INIC to be controlled
remotely across the network or by an off-board device
through the MOST CONTROL header (J17) or the
DAUGHTERBOARD connector (J21).
As required by the MOST50 EVB, a 384×Fs (18.432
MHz) external crystal (Y3) is provided on the board,
supporting a 48 kHz MOST50 Network frame rate.
6.1 INIC Configuration String (OTP)
To support the MOST compliant power management
scheme as outlined in the MOST INIC Hardware Con-
cepts Technical Bulletin [8] a few changes the factory default INIC Configuration String (stored in One-Time Program-
mable (OTP) memory) are required. The Eval92 Board is shipped with the following settings (changes from default are
in bold):
• NBMIN.NodeAddress.NodeAddress = 0xFFFF
• NBMIN.GroupAddress.GroupAddress = 0x03C8
• NBMIN.PermissionToStart.StartStatus = On
• NBMIN.RetryParameters.RetryTime = 11
• NBMIN.RetryParameters.RetryNumbers = 6
• INIC.VersionInfo.ConfString = 0.0.0
• INIC.RMCK.Divider = 256Fs
• INIC.ClockMode.Frequency = 48000 Hz
• INIC.RemoteAccess.AccessMode = 0x1
• INIC.WatchdogMode.AutoShutDownDelay = 65535 ms
• INIC.Bandwidth.AssignBWInit = 16
• INIC.DeviceMode.DeviceMode = Slave
• INIC.RBDOptions.Options = 0x0
• INIC.PortConfiguration.MediaLBInterf aceMode = 3-pin
• INIC.PortConfiguration.MediaLBClockCfg = 1024Fs
• INIC.PortConfiguration.CPCfg.I2CSlaveAddress = 0x40
• INIC.PortConfiguration.DefPort = INT_Select
• INIC.AddressConfig.Mode = 0x0
• INIC.TimeBypass.Time = 1 ms
• INIC.PMIConfig.Config = 0x1C
• INIC.PMIConfig.TimePwrOff = 60 s
OTP memory may be progra mmed up to two times, as neede d for custom applications. As described in th e OS81092
MOST50 INIC Hardware Data Sheet [1], INIC’s internal OTP memory (used for configuration) can be written via the I2C
Control Port (either b y the EHC or by an external device through the MOST CONTROL header, J17). Updating the INIC
Configuration String via the Control Port is described in the OS81092 INIC Flash Programming Guide [10]. Additionally,
INIC OTP memory can be written through the Debug Port, as described in Section 6.2 “Debug Port Access”.
12
11
10
9
8
7
6
5
4
3
2
1
25
26
27
28
29
30
31
32
33
34
35
36
24
23
22
21
20
19
18
17
16
15
14
13
37
38
39
40
41
42
43
44
45
46
47
48 3
e
OS81092AM
lllrffyyww
tttttttttttt
cc
PS1
PS0
XTI
XTO
GNDU
VDDU
GNDA2
VDDA33
ERXP
ERXN
ERXCM
GNDE
SR0/MLBSI/SX1
SX0/MLBDI/SR1
FSY
SCK
VDDP3
VDDC3
GND3
RSOUT
ERR/BOOT
DINT/TDO
INT
SCL
PWROFF
TMS
DSCL/TCK
GND2
VDDC2
VDDP2
DSDA/TDI
TST1
MLBCLK
MLBSIG/MLBSO/SR1
MLBDAT/MLBDO/SX1
TST2
VDDE2
VDDA18
GNDA1
VDDE1
ETXN
ETXP
GND1
VDDC1
VDDP1
RMCK
RST
SDA
FIGURE 6-1: OS81092 INIC
2013 Microchip Technology Inc. DS60001239A-page 19
OS81092 Evaluation Board User’s Guide
6.2 Debug Port Access
The Eval92 Board provides the INIC DEBUG header (J31) for connecting the INIC Explorer Interface Tool [11]. In addition
to viewing and writing th e INIC Configura tion String in OTP memory, INIC Explorer provides debugging capabilities by
allowing users access to INIC (via PC software) for:
• Exploring internal INIC properties and states during norma l operation,
• Viewing internal INIC states and routing configurations (sockets and handles) graphically,
• Creating an INIC data memory snapshot as a file dump, and
• Viewing FBlock INIC and FBlock NetBlock status.
6.3 Network Port
The INIC Network Port includes both a transmitter and receiver connected to an a nalog front end circuit optimize d for
data transmission/reception in automotive environments using unshield ed twisted pair (UTP) wire. The Eval92 Board
connects to a MOST50 Netwo rk through the ePHY NETWORK connector (Tyco/AMP 131877 2-2) at J18. This connector
allows connection to other network nodes using a mating connector (Tyco/AMP 1318774-1) to UTP wire. Figure 6-2
shows the ePHY Front End Circuitry used on the Eval92 Board.
FIGURE 6-2: EPHY FRONT END CIRCUITRY
The ePHY NETWORK connecto r (J18), shown in Figure 6-3, is a 12-pin right-angle connector. Pins 5, 6, 11, and 12 are
used for ePHY network signals. The Eval92 Board is also powered through this connector, where pins 1 and 7 connect
to HARNESS_BATT_POS and pins 2 and 8 connect to HARNESS_BATT_NEG. Pins 4 and 10 are co nnected to ground.
Additionally, pins 3 and 9 are co nnected to th e PwrMgr and function as an ECL [6] for Sleep Mode wake up signaling,
as described in Section Section 10.5.1 “Wakeup due to ECL Activity”.
Chip Side Cable Side
100 differential
R293
64.9
R292
64.9 R48
182
R59
43.2
R53
43.2
C224
X7R
C89
22 pF
C0G
L11 140
L10 140
L12
100 nH
C85
22 pF
C0G
C79
X7R
C96
X7R
C91
68 pF
C0G
C94
68 pF
C0G
C93
22 pF
C0G
L14 140
L15 140
2
1
3
6
7
8
16
15
14
11
10
9
4
5
13
12
C81 1000 pF
C0G
C80 10 pF
C0G
C97 1000 pF
C0G
C98 10 pF
C0G
L16
L13
J18
T1
0.01 F
0.01 F
0.01 F
ERXN
ERXP
ERXCM
ETXN
ETXP
INIC
U1
D215
ESD7C5.0DT5G
D216
ESD7C5.0DT5G
TG100-MOST15N2LF
ACM2012-121-2P-T001
ACM2012-121-2P-T001
SP2E
SP3E
Mating C onn ec t or:
Tyco/AM P 1318774 -1
Board Connector:
Tyco/AM P 1318772 -2
1
7
2
8
3
9
4
10
5
11
6
12
HARNESS
LIN/ECL
HARNESS
BATT_NEG
HARNESS
BATT_POS
SP1E
SP4E
OS81092 Evaluation Board User’s Guide
DS60001239A-page 20 2013 Microchip Technology Inc.
FIGURE 6-3: BOARD HARNESS CONNECTOR
6.4 Control Port
The INIC Control Port operates as an I2C bus slave (address 40h/41h) and supports asynchronous packet and control
message exchange with th e EHC. The INIC hardware interrupt ( INT pin) is used to notify the external controller that
INIC requires service. By default, the INIC_INT signal (connected to EHC RD7) on the Eval92 Board is pulled-up
(through R285) to automatically enable the Control Port at power-up/reset. Alternatively, a pull-down resistor can be
installed at R284 (requires R285 removed) to enable the MediaLB Port at power-up/reset.
Typically, the EHC application code implements an I2C bus master and uses Port Message Protoco l to confi gure and
control the INIC. Refer to Section 8.4.1 “I2C Communication” for more informat ion on the I2C communication busses on
the Eval92 Board.
6.5 Power Management Interface
The PwrMgr uses its Power Management interface to convey board power information to INIC. Using PS0 and PS1, four
different power states can be conveyed (including over-voltage and under-voltage conditions), as defined in the
MOST Spe cifi cation 3.0 [5]. This specification defines the four general power states; however, the exact voltage levels
and thresholds for each state are configurable and typically defined by the OEM’s system integrator.
INIC recognizes
transitions between these power states and responds to the PwrMgr (using
PWROFF
) when it is ready to be powered
down.
For more information on the configuration and use of the pow er mana gement i nterfa ce, re fer to th e MPM85000
Automotive Power Management Device Data Sheet [3].
The Eval92 Board connects the power management interfaces of the PwrMgr and INIC with a hardware option that
allows the EHC to ho ld PWROFF low if the a pplication requires additional time before the board enters Sleep Mode.
The EHC application code may use the EHC_PWROFF (RB13) signal to override PWROFF and prevent board power-
down.
DIP switch 6 (S2) provides a hardware override option which disables power management. When the switch is closed,
board power-down is prevented by forcing the PwrMgr PWROFF pin low via PM_PWROFF.
Note: To be a ctive on the network, INIC requires PS[1:0] not be in the ULow state
(PS[1:0]=11b).
123456
789101112
ETXP
ERXN
GND
LIN / ECL
BATT_NEG
BATT_POS
ETXN
ERXP
J18
2013 Microchip Technology Inc. DS60001239A-page 21
OS81092 Evaluation Board User’s Guide
Figure 6-4 provides an overview of the Eval92 Board power manageme nt i nterface.
FIGURE 6-4: POWER MANAGEMENT INTERFACE
Refer to Chapter 10.0 for more information abo ut power management on the Eval92 Board.
6.6 INIC Streaming Port
The INIC S treaming Port is used by external devices (e.g. stereo audio CODEC) to source/sink streaming data with low
overhead. The Eval92 Board is designed to use two of the four availabl e St reami ng Port data pins (also referred to as
Partial S treaming Mode). In this mode, INIC supports one serial input (SR0) and one serial output (SX0) using the InOut
option. These two serial data pins are available for connection (with shunts) to the stereo audio CODEC at
CODEC CONFIG (J8). Refer to Section 9.1 “Stereo Audio CODEC” for more information on the stereo audio CODEC. The
INIC Streaming Port conne ction options on the Eval92 Board are shown in Figure 6-5.
FIGURE 6-5: INIC STREAMING PORT CONNECTION OPTIONS
EHC_PWROFF
(EHC RB13)
MAIN_3V3
47 k
R30
J12
PWR MGMT
PS0
PS1
PWROFF
INIC
U1
47 k
R260 47 k
R259
D8
U3
PS1
PWROFF
PS0
PwrMgr
47 k
R262
MAIN_3V3
ENABLE
GND
GND
ON_SW
PM_RST
PM_INT
PS1
PS0
NOACT
PM_PWROFF PM_PWROFF
* Driven low by:
- Board Reset Switch
-DIP Switch 6
D9
0
0
R28
R29
CAN_STAT
INIC
U1
RMCK
SCK
FSY
SX0/MLBDI/SR1
SR0/MLBSI/SX1
MLBCLK
MLBSIG/MLBSO/SR1
MLBDAT/MLBDO/SX1
22.1 R63
100 kR66 100 k
100 k
100 k
100 k
R238
R244
R240
R255
EHC_SDO
CODEC CONFIG
SCLK
BCK
WS
DATAO*
DATAI*
(to/from stereo
audio CODEC)
J10
LFST CONFIG
RXD
SDI
TXD
SDO
SX0
SX0
SR0
SR0
(to EHC RF2)
(to EHC RG7)
(from EHC RF8)
(from EHC SDO2) AUX CONFIG
J11
INIC SX0
EHC TXD
(from EHC RF8)
AUX DATA (to J33)
J5
J8
(from EHC SDO2)
* Signals are reversed from
silkscreen indication
OS81092 Evaluation Board User’s Guide
DS60001239A-page 22 2013 Microchip Technology Inc.
As shown above, INIC St reaming Port signals can be connected to the EHC using LFST CONFIG (J10). Additionally, the
INIC serial output pin can be routed to an external device conn ected to AUX (J33) by placing a shunt betwee n pins 1
and 2 of AUX CONFIG (J11). These al tern ative co nnection op ti ons can be used for low freque ncy sig nal tunnel ing appli-
cations, as described in Section 9.2 “Low Frequency Signal Tunneling”
6.7 MediaLB Port
The INIC MediaLB Port is a 3-wire hardware interface used to exchange MOST Network data types with other on-board
devices (e.g. EHC or IOC) using the protocol defined in the MediaLB Specification [12]. T he Eval92 Board provide s a
3-pin MediaLB interface between INIC and the IOC. When communication is enabled, the INIC MediaLB Port functions
as the MediaLB Controller, providing real-time access to all supported MOST50 data types. The IOC MediaLB Port func-
tions as a MediaLB Device and sup ports routing of Med iaLB data to other ports used by the application (e.g. SPI Port,
Streaming Port). The Media LB interface is used in higher perfo rmance applications, where the IOC is u sed to bridge
communication between INIC and the EHC and/or the expanded streaming audio capabilities of the IOC are required.
Figure 6-6 illustrates the MediaLB interface on the Eval92 Board.
FIGURE 6-6: MEDIALB 3-PIN CONNECTION DIAGRAM
MediaLB 3-pin debugging capabilities are provided on the Eval92 Board via the MediaLB DEBUG co nnector (J34). Inte-
grated circuitry on the Eval92 Board (referred to as the MediaLB Monitor Active Pod Circuitry) enables real-time analysis
and debugging of the MediaLB interface by the MediaLB Monitor Adapter tool [13]. Contact Microchip for more informa-
tion regarding MediaLB analysis and debugging tools.
For more information on the MediaLB physical layer and link layer, refer to the MediaLB Specification [12].
The MediaLB 3-pin interface is also routed to the DAUGHTER BOARD (J21) connector . This header allows communication
with an off-board MediaLB Device. Possible off-board implementations include daughterboards featuring the OS85621
Video I/O Companion device [9] or an FPGA implementation of the OS62420 MediaLB device [14]. Refer to Section 5.3
“Off-Board Applications” for more information on supplemental hardware connections (e.g. daughterboards) on the
Eval92 Board.
INIC
U1
MLBSIG
MLBCLK
MLBDAT
MLBSIG
MediaLB Monitor
Active Pod Circuitry MediaLB
DEBUG
IOC
U2
MLBDAT
MLBCLK
MLBSIG
J34
100
differential pairs
R306
0
R311
0
R298
0
R58 41.2
R62 41.2
R57 41.2
R61 22.1
R56 22.1
R55
100
NO POP
C92
27 pF
NO POP
R299
47 k
R302
47 k
R307
47 k
MLBCLK
MLBDAT
DaughterBoard
Connector
J21
DAUGHTER BOARD
2013 Microchip Technology Inc. DS60001239A-page 23
OS81092 Evaluation Board User’s Guide
7.0 OS85650 IOC
The Eval92 Board provides an OS85650 I/O Companion (IOC) device [2] (U2) to provide a high-speed link between the
EHC peripherals and the MOST Network. The IOC device can route both synchronous (e.g. audio/video) and asynchro-
nous (e.g. packet) data streams. An optional Digital Transmission Content Protection (DTCP) coprocessor is also avail-
able. When supported by the Eval92 Boar d application code, the IOC device is typically used to:
• Exchange data with INIC over the MediaLB 3-pin interface,
• Route between MediaLB 3-pin interface and SPI Port (interface to EHC),
• Route between MediaLB 3-pin interface and Streaming Port (inte r face to audio CODEC),
• Route between MediaLB 3-pin interface and TSI Port (interface to off-board device),
• Encrypt/Decrypt synchronous and/or isochronous data streams, and
• Support full Authentication and Key Exchange (AKE), as defined by the DTCP Specification [15].
7.1 Configuration and Debug
The OS85650 IOC contains two memory spaces used for configuration: One-Time Programmable (OTP) memory and
RAM-based Configuration Me mory (Cfg Memory). Neither the OTP memory nor the Cfg memory on the IOC is config-
ured (default). When EHC application code is available that utilizes the IOC, the Microchip IOC Configuration
Software [16] should be used to configure OTP and Cfg Memory appropriately for the desired functionality by:
• directly configuring OTP memory using the INIC Explorer tool via the IOC DEBUG header (J30), or
• generating a list of IOCMs for EHC applications to send to configure OTP memory and/or Cfg Memory.
The Eval92 Board provides a re sistor population option to set the default state of the IOC DBG pin. This pin sets the
initial mode of operation for the IOC Debug Port. By default, R344 is populated and the IOC Debug Port is set for JTAG
mode. Alternatively, R270 can be installed (and R344 removed) to configure the IOC Debug Port for I2C mode. Refer
to the OS85650/2 I/O Companion Data Sheet [2] and the Microchip IOC Configuration Software [16] for more informa-
tion on using and configuring the IOC.
7.2 Control Port
The IOC Control Port operates as an I 2C bus slave (address 48h/49h) and supports message-based communication
with the EHC. The IOC hardware interrupt (INT pin) is used to notify the external controller that the IOC requires service.
The IOC_INT signal is connected to EHC RD4 on the Eval92 Board.
Typically, the EHC application code implements an I2C bus master and uses Port Message Protoco l to confi gure and
control the IOC. Refer to Section 8.4.1 “I2C Communication” for more information on the I2C communication busses on
the Eval92 Board.
7.3 MediaLB Ports
The OS85650 IOC device in cludes two MediaLB Ports, namely a Me diaLB 3-pin Port and a MediaLB 6-pin Po rt. The
IOC MediaLB Ports are 3-wire (single-ended) and 6-wire (differential) hardware interfaces used to exchange MOST Net-
work data types with other on-board devices (e.g. INIC or EHC) using the protocol defined in the
MediaLB Specification [12].
The Eval92 Board provides a 3-pin MediaLB interface between INIC and the IOC with the IOC functioning as a MediaLB
Device that supports routing of MediaLB data to other ports used by the application (e.g. Streaming Port). See
Section 6.7 “MediaLB Port” for more information (including a connection diag ram) re garding the MediaLB 3 -pin imple-
mentation on the Eval92 Board.
The IOC MediaLB 6-pin Port is not used on the Eval92 Board.
7.4 HBI Port
The OS85650 IOC device includes a high speed parallel interface call the Host Bus Interface (HBI), but this interface is
not connected to the PIC32 EHC. The HBI Port is connected to a header at J19 so it is possible for some external device
to talk to the IOC device via HBI.
OS81092 Evaluation Board User’s Guide
DS60001239A-page 24 2013 Microchip Technology Inc.
7.5 Streaming Ports
The two IOC Streaming Ports are used to further extend the network stream ing source/sink capabilities of the Eval92
Board. The IOC’s integrated DTCP coprocessor can optionally be used by application code to encrypt/decrypt protected
synchronous data streams. The Eval92 Board is designed to utilize two o f the four available serial data pins on each
IOC Streaming Port. The serial data pins for Streaming Port A (SRA0 for receive and SXA2 for transmit) and clock pins
can be connected (with shunts) to the stereo audio CODEC at CODEC CONFIG (J8). IOC Streaming Port connection
options on the Eval92 Board are shown in Figure 7-1.
FIGURE 7-1: IOC STREAMING PORT CONNECTION OPTIONS
As shown above, the serial data pins for S treaming Port B (SRB0 for receive and SXB2 for transmit) and the associated
clock signals can be conn ected to the EHC (with shunts) at EHC I2S CONFIG (J9). Refer to Section 6.6 “INIC Streaming
Port” for more information.
The unused IOC Streaming Port serial data pins ( SRA1, SXA3, SRB1 and SXB3) are accessible via through-hole test-
points.
7.6 SPI Ports
The IOC offers up to two SPI Ports; however, the Eval92 Board connections are configured such that only SPI Port 0 is
available for use. SPI Port 1 is unavailable due to pin conflicts with TSI Port 1 (see Section 7.7 “TSI Ports”). In addition
to the 4 typical SPI protocol signals (clock, chip select, MOSI and MISO), IOC SPI Port 0 also includes a hardware inter-
rupt (SINT0 pin, connected to EHC RD11) that the EHC can monitor to check the IOC’s availability for an SPI transac-
tion.
100 kR337 100 k
100 k
100 k
100 k
R254
R336
R263
R246
J9
EHC I2S CONFIG
SDO
SDI
SCK
WS
SRB0
SXB2
SCKB
FSYB
(from EHC SDO2)
(to EHC RG7)
(to E HC RG6)
(to EHC U6RX)
J8
CODEC CONFIG
SCLK
BCK
WS
DATAO*
DATAI*
(to/from stereo
audio CODEC)
IOC
U2
RMCK
SCKA
FSYA
SRA0
SRA1
SXA2
SXA3
SCKB
FSYB
SRB0
SRB1
SXB2
SXB3
(Streaming Port A)
(Streaming Port B)
22.1 R368
TP30
TP29
SRA1
SXA3
100 k
R239 100 k
R236
TP32
TP31
SRB1
SXB3
100 kR335 100 k
100 k
100 k
100 k
R247
R334
R241
R264 100 k
R256
EHC_SDO
J5
from EHC SDO2)
* Signals are reversed from
silkscreen indication
2013 Microchip Technology Inc. DS60001239A-page 25
OS81092 Evaluation Board User’s Guide
When IOC SPI Port 0 is enabled, it operates as an SPI bu s slave that can exchange a synchronous data packets (i.e.
MDPs or MEPs) at a rate of up to 25 Mbps. T ypically , the EHC application code implements an SPI bus master for packet
data exchange with the IOC. Alternatively, an off-board SPI master can access the IOC via the IOC SPI (J15) header.
Refer to Section 8.4.5 “Serial Peripheral Interface (SPI) Ports” for more information (including a connection diagram) on
the EHC SPI implementation on the Eval92 Board.
7.7 TSI Ports
The IOC offers up to two TSI Ports; however, the Eval92 Board connections are configured such that only TSI Port 1 is
available for use. TSI Port 0 is unavailable due to pin conflicts with SPI Port 0 (see Section 7.6 “SPI Ports”). Althou gh
TSI Port 1 can operate in both serial and parallel mode, only serial mode operation is supported on the Eval92 Board.
TSI Port 1 can be confi gured for either TSI stream transmission (master mode) or TSI stream reception (slave mode ).
The Eval92 Board does not contain any integrated devices capable of TSI stream exchange with the IOC; therefore an
external device is required for all TSI implementations. The Eval92 Board provides the IOC TSI (J23) header (2 mm pitch)
to support connection to off-board devices. The IOC TSI Port 1 connections are shown below in Figure 7-2.
FIGURE 7-2: IOC TSI PORT HEADER CONNECTIONS
J23
IOC TSI
TCLK
TVAL
TSYN
TDAT
TERR
IOC
U2
TCLK
TVAL1/SINT1
TSYN1/CS1
TD0/TDAT1/SDOUT1
TERR1
TREQ1/SDIN1
100 k
100 k
100 k
100 k
R320
R319
R318
R317
TD1
TD2
TD3
TD4
TD5
TD6
TD7
47 R82
47 R84 47 R79 47 R81 47 R83
1 kR80
100 kR85
100 k
10 k
R316
R313
NO POP
MAIN_3V3
OS81092 Evaluation Board User’s Guide
DS60001239A-page 26 2013 Microchip Technology Inc.
8.0 PIC32 EHC
The on-board EHC (U42B-3C) is a 121-pin BGA PIC32MX795F512L [17] 32-bit microcontroller . This device provides 512
kbytes of on-chip Flash program memory and 128 kbytes of SRAM. The EHC is powered by the 3.3 V switched supply
(MAIN_3V3), while an internal regul ator generates the 1.8 V power required for co re logi c and in tegrated memory of the
PIC32. The main internal clock is derived from the 12 MHz external crystal (Y201), while a 32.768 kHz crystal (Y2) pro-
vides the clock source for an internal Real Time Counter (RTC).
8.1 PIC32 Configuration Bits
The PIC32 processor has several configuration settings to se lect options like which oscillator to use at startup, how to
set up the PLL to provide the desired CPU clock rate, how the watchdog timer behaves and other settings. The Config-
uration Bits are described in Section 28 of the PIC32MX5XX/6XX/7XX 32-Bit Microcontrollers Family Data Sheet [17].
The MPLAB X IDE from Microchip provides a built in wizard to help with setting the configuration bits. The wizard is
selected from the Tools -> PIC Memory Views -> Configuration Bits menu selection. The user selects the desired
options, and the wizard generates a configuration_bits.c file to include in the project. The configuration bits will then be
set according to the settings in the file each time the application is run.
The contents of the configuration_bits.c file are show below . Many settings are left at the default value. The main settings
configured are to select the 12 MHz external crystal as the clock source, and to scale the 12 MHz clock up to 80 MHz
for the CPU clock. Additionally, the peripheral clocks are set to 1/2 the CPU clock rate, an d the watchd og ti mer is dis-
abled.
EXAMPLE 8-1: CONFIGURATION_BITS.C
8.2 Stand-Alone Mode
A Stand-Alone mode should be provided in any EHC application code written for the Eval92 Board. When this mode is
enabled, the EHC sh ould not interact with INIC, the IOC, or any other on-board devices in any way. In Standard Appli-
cations, this entails disabling the I2C bus master functionality and tri-stating all I/O pins. When Stand-Alone mode is
enabled, an off-board EHC is permitted to access the INIC and IOC devices (typically as a external I 2C bus master)
through the MOST CONTROL (J17) header . Utilizing the Eval92 Board in this manner provides software developers a hard-
ware reference platform, which enables hardware development with the target EHC before a complete platform is avail-
able.
// PIC32MX795F512L Configuration Bit Settings
#include <p32xxxx.h>
// DEVCFG3
// USERID = No Setting
#pragma config FSRSSEL = PRIORITY_7 // SRS Select (SRS Priority 7)
#pragma config FMIIEN = ON // Ethernet RMII/MII Enable (MII Enabled)
#pragma config FETHIO = ON // Ethernet I/O Pin Select (Default Ethernet I/O)
#pragma config FCANIO = ON // CAN I/O Pin Select (Default CAN I/O)
#pragma config FUSBIDIO = ON // USB USID Selection (Controlled by the USB Module)
#pragma config FVBUSONIO = ON // USB VBUS ON Selection (Controlled by USB Module)
// DEVCFG2
#pragma config FPLLIDIV = DIV_3 // PLL Input Divider (3x Divider)
#pragma config FPLLMUL = MUL_20 // PLL Multiplier (20x Multiplier)
#pragma config UPLLIDIV = DIV_3 // USB PLL Input Divider (3x Divider)
#pragma config UPLLEN = ON // USB PLL Enable (Enabled)
#pragma config FPLLODIV = DIV_1 // System PLL Output Clock Divider (PLL Divide by 1)
// DEVCFG1
#pragma config FNOSC = PRIPLL // Oscillator Selection Bits (Primary Osc w/PLL (XT+,HS+,EC+PLL))
#pragma config FSOSCEN = ON // Secondary Oscillator Enable (Enabled)
#pragma config IESO = ON // Internal/External Switch Over (Enabled)
#pragma config POSCMOD = HS // Primary Oscillator Configuration (HS osc mode)
#pragma config OSCIOFNC = OFF // CLKO Output Signal Active on the OSCO Pin (Disabled)
#pragma config FPBDIV = DIV_2 // Peripheral Clock Divisor (Pb_Clk is Sys_Clk/2)
#pragma config FCKSM = CSDCMD //
Clock Switching and Monitor Selection (Clock Switch Disable, FSCM Disabled)
#pragma config WDTPS = PS1048576 // Watchdog Timer Postscaler (1:1048576)
#pragma config FWDTEN = OFF // Watchdog Timer Enable (WDT Disabled (SWDTEN Bit Controls))
// DEVCFG0
#pragma config DEBUG = ON // Background Debugger Enable (Debugger is enabled)
#pragma config ICESEL = ICS_PGx1 // ICE/ICD Comm Channel Select (ICE EMUC1/EMUD1 pins shared with PGC1/PGD1)
#pragma config PWP = OFF // Program Flash Write Protect (Disable)
#pragma config BWP = OFF // Boot Flash Write Protect bit (Protection Disabled)
#pragma config CP = OFF // Code Protect (Protection Disabled)
2013 Microchip Technology Inc. DS60001239A-page 27
OS81092 Evaluation Board User’s Guide
The Eval92 Board provides the BOARD OPTIONS (S2) 8-position dip switch for setting various firmware options. The EHC
typically reads the states of the DIP switches during initialization (i .e. immediately following power-up/reset). Microchip
application code typically uses one of the DIP switches to indicate whether or not the EHC should operate in Stand-
Alone mode. Refer to the MOST ToGo Basic Application Code Firmware Manual [4] for more information.
8.3 EHC Flash and Debug
The Eval92 Board supports several methods of updating and debug ging EHC application code. To simply update the
application in Flash memory, th e installed serial bootloader can be used alo ng with the Microchi p PIC32UBL program-
ming utility and a prebuilt HEX file. For deb ugging as well as loading new applications, the MPLAB X IDE can be u s ed
with one of the Microchip debug tools. The applications themselves provide a lot of debug text output via the on-board
CommBridge device (U11) which permits following the application execution with a terminal program on the PC through
a standard USB connection. Power management should be disabled (DIP Switch 6 closed) when programming the EHC
to prevent the board from powering-down inadvertently.
8.3.1 FLASHING FROM PC VIA USB
The Eval92 Board is shipped with the PIC32 Serial Bootloader in Flash memory . This bootloader is available from Micro-
chip and is described in AN1388 PIC32 Bootloader Application Note [18]. The bootloader permits application code
updates using the on-board CommBridge. A PC running the Microchip PIC32UBL Flasher Software [19] utility connects
to the Eval92 Board CB USB (J7) connector and tra nsmits the firmware image to the CommBrid ge over a virtual COM
port. Then the image is serially programmed into the EHC flas h through the UART2 interface.
To enter the bo otloader, th e EHC DFU (S10) button must be pressed while a n EHC reset is performed using either the
EHC RESET (S6) switch or the BOARD RESET (S9) switch. An orange LED (D206) next to the EHC DFU button flashes to
indicate the bootloader is waiting for commands. If this LED does not flash, either the switches were not pressed prop-
erly, or the bootloader is not present.
8.3.2 EHC HARDWARE DEBUG PORTS
FIGURE 8-1: EHC DEBUG AND JTAG HEADERS
The Eval92 Board supports all of the current Microchip debug tools including the PICKit3, ICD3, and ReaIICE. All three
emulators can use the standard ICSP programming and debug interface at J27, how ever, the ICD3 and RealICE will
require a cable adap ter to convert from the 6 pin RJ45 ph one jack on the tool to the straight 6 pin header at J27. The
PICKit3 ca n pl u g directly onto the J27 header.
For more sophisticated debugging, the Eval92 Board also supports the full JTAG and Trace Debug features of the
PIC32. These interfaces require the use of the RealICE debugger along with its JTAG interface board and I/O Port trace
cable. The JT AG header is at J24, and the T race Debug header is at J26. Using these interfaces along with the RealICE
debugger enables real time instruction trace collection, real time watch, stopwatch, and logic probe inputs and outputs.
Note: Flashing the EHC from the PC through the CommBridge allows Eval92
Board application code to be updated without the use of any Microchip hard-
ware tools.
J27
EHC ICSP
GND
3V3
MCLR
PGC
PGD
NC
(EHC_RST)
(MAIN_3V3)
(EHC_PGED1)
(EHC_PGEC1)
J24
EHC JTAG
GND
GND
GND
GND
GND
KEY
3V3
TRST
TDI
TDO
TMS
TCK
SRST
DINT (MAIN_3V3)
(EHC_TDI)
(EHC_TDO)
(EHC_TMS)
(EHC_TCK)
(EHC_RST)
(N/C TP38)
(N/C TP28)
(no pin)
J26
EHC TRAC E
GND
GND
GND
GND
GND
TRCLK
TRD0
TRD1
TRD2
TRD3
(EHC_TRD0)
(EHC_TRD1)
(EHC_TRD2)
(EHC_TRD3)
(EHC_TRCLK)
OS81092 Evaluation Board User’s Guide
DS60001239A-page 28 2013 Microchip Technology Inc.
8.3.3 DEBUG PRINT STATEMENTS VIA USB
The on-board CommBridge supports transmission of debug print information from the EHC to the PC via a USB con-
nection. Debug information can be viewed on the PC using a terminal application such as Hyperterminal, Tera Term or
the Microchip Port Message Viewer PC software [20]. The EHC uses the UART2 interface to send debug info rmation
to the CommBridge.
Some excerpts from the debug output of a typical application are shown b elow. Included in the d ebug output are mes-
sages from the application as it runs, the outpu t of the NetServices Trace Module, and the output of a virtual I2C spy
that shows all of the I2C traffic between the EHC and all of th e peripheral s includin g the port messa ges going to INIC.
The Port Message Viewer program can show this output as well as interpret the port messages into a more readab le
format as shown in Figure 8-2. An example of the raw debug output code is shown in Example 8-2.
FIGURE 8-2: PORT MESSAGE VIEWER INTERPRETED OUTPUT
Note: Caution: When the EHC is programmed using any of the emulators, the
EHC’s internal bootloader will be erased. This is not a p roblem as long as
the emulator is used for al l subsequent programming and debugging. The
original bootloader a pplication is available from Microchip and can be rein-
stalled to re-enable serial flashing through the CommBridge.
2013 Microchip Technology Inc. DS60001239A-page 29
OS81092 Evaluation Board User’s Guide
EXAMPLE 8-2: RAW DEBUG OUTPUT EXAMPLE
********************************************************************************
Microchip/SMSC
MOST ToGo Master
V1.2.3
********************************************************************************
000:00:00:017> s44.0C.FFp
000:00:00:019> s44.0C.FFp
...
***** Starting MSMM *****
000:00:00:239> 239 MNS: Init
000:00:00:241> 241 MNS: Init phase state machine goes into state [state 0x00].
000:00:00:245> 245 MNS: Reset phase state machine goes into state [state 0x00].
000:00:00:250> 249 MNS: Init of MOST NetServices V3.0.5Distrib PMS, MIS, MNS, wAMS, wMCS, wADS, vMSV,
wSCM, GAS
000:00:00:255> 255 MIS: Init
000:00:00:257> 257 MBM: Init
000:00:00:259> 259 PMS: Init
000:00:00:261> 261 AMS: Init
000:00:00:263> 263 MNS: Init phase state machine goes into state [state 0x08].
000:00:00:267> 267 WMCS: Init
000:00:00:269> 269 WADS: Init
000:00:00:271> 270 MNS: Init phase state machine goes into state [state 0x28].
000:00:00:275> 275 VMSV: Init
000:00:00:276> 276 WSCM: Init
000:00:00:278> 278 SCMPM: Init
***** MOST Task Init Finished *****
000:00:00:283> ECLSM: SSEQI wakeup started at 000:00:00:124.
000:00:00:286> s41.00.03.02.1A.80p
000:00:00:288> s40.00.03.02.18.80p
000:00:00:290> ECLSM: SSEQI tEWU pulse 1 ended at 000:00:00:204.
000:00:00:293> s41.00.03.02.1A.90p
...
000:00:00:639> s40.00.09.01.14.30.32.00.03.14. 02.03p
000:00:00:642> s41.00.07.01.14.41.0C.00.01.FFp
000:00:00:645> s41.00.03.02.12.44p
000:00:00:647> 647 MIS: RX of Local.INIC.00.SourceDrop.Status (len = 1 bytes)
000:00:00:651> s40.00.06.01.14.30.61.00.00p
000:00:00:654> s40.00.03.02.12.44p
000:00:00:656> s41.00.08.01.14.41.1C.00.02.FF. 00p
000:00:00:659> s41.00.03.02.12.44p
000:00:00:661> 661 MIS: RX of Local.INIC.00.SCError.Status (len = 2 bytes)
000:00:00:666> s40.00.03.02.12.44p
000:00:00:668> s41.00.07.01.14.20.6C.00.01.00p
000:00:00:671> 671 MIS: RX of Local.INIC.00.BIST.Status (len = 1 bytes)
000:00:00:675> s40.00.03.02.12.44p
000:00:00:678> s41.00.09.01.14.30.3C.00.03.14. 02.03p
000:00:00:680> 680 MIS: RX of Local.INIC.00.MidLevelRetry.Status (len = 3 bytes)
000:00:00:685> s40.00.03.02.12.44p
000:00:00:688> s41.00.07.01.14.30.6C.00.01.01p
000:00:00:690> 690 MIS: RX of Local.INIC.00.AbilityToSegment.Status (len = 1 bytes)
000:00:00:695> s40.00.03.02.12.44p
000:00:00:697> s41.00.08.01.14.30.BC.00.02.0B. 05p
000:00:00:700> 700 MIS: RX of Local.INIC.00.RetryOptions.Status (len = 2 bytes)
000:00:00:704> 704 AMS: TX of Local.NetBlock.00.RetryParameters.Get (len = 0 bytes)
...
000:00:00:846> s40.00.07.01.14.30.00.00.01.02p
000:00:00:849> s41.00.03.02.12.44p
000:00:00:851> s41.00.07.01.14.30.0C.00.01.02p
000:00:00:854> 853 MIS: RX of Local.INIC.00.EHCIState.Status (len = 1 bytes)
000:00:00:858> 858 MNS: EHCIState state machine goes into state Attached.
********************************************************************************
000:00:00:865> Most NetServices initialization complete
********************************************************************************
000:00:00:871> 871 AMS: TX of Local.INIC.00.RMCK.Set (len = 1 bytes)
000:00:00:875> 875 AMS: TX of Local.NetBlock.00.NodeAddress.Set (len = 2 bytes)
AvmStart.
...
AvmRequestCR - Local NWM
AvmState: AVM_REQUEST_SOURCE_SINK_LIST
000:00:01:306> 1306 AMS: TX of 0x0141.[unknown FBlock 0x22].02.[FktID 0x001].[OpType 0x0]. (len = 3 bytes)
AvmRequestSourceSinkList - NTF.Set sent.
000:00:01:313> 1313 AMS: TX of 0x0141.[unknown FBlock 0x24].02.[FktID 0x001].[OpType 0x0]. (len = 3 bytes)
AvmRequestSourceSinkList - NTF.Set sent.
000:00:01:321> 1320 AMS: TX of 0x0161.[unknown FBlock 0x24].01.[FktID 0x001].[OpType 0x0]. (len = 3 bytes)
AvmRequestSourceSinkList - NTF.Set sent.
000:00:01:328> 1328 AMS: TX of 0x0161.[unknown FBlock 0x25].01.[FktID 0x001].[OpType 0x0]. (len = 3 bytes)
AvmRequestSourceSinkList - NTF.Set sent.
AvmState: AVM_REQUEST_SOURCE_SINK_LIST_WAIT
AvmTimer AVM_WAITTIME_REQUEST_SOURCE_SINK_LIST started.
000:00:01:389> s40.00.03.02.02.44p
000:00:01:391> s40.00.0F.09.05.10.00.06.03.C8. 02.01.0 0.A0.0C. 00.01.01 p
000:00:01:395> s41.00.03.02.02.44p
000:00:01:397> s44.05.BFp
000:00:01:399> s51.74.51.10p
000:00:01:400> s50.74.50p
000:00:01:402> 1402 AMS: TX of 0x03C8.[unknown FBlock 0x02].01.[FktID 0xA00].[OpType 0xC]. (len = 5 bytes)
000:00:01:408> s40.00.0D.05.04.01.61.24.01.00. 10.00.0 3.00.01. 41p
000:00:01:412> s41.00.03.02.02.44p
000:00:01:414> s40.00.0D.05.04.01.61.25.01.00. 10.00.0 3.00.01. 41p
000:00:01:418> s41.00.03.02.02.44p
000:00:01:420> s40.00.0F.05.04.03.C8.02.01.A0. 0C.00.0 5.04.01. 52.22.03 p
000:00:01:425> s41.00.0A.01.14.50.AC.00.04.01. 00.01.0 0p
AvmRequestCR - Local NWM
AvmState: AVM_REQUEST_SOURCE_SINK_LIST
...
OS81092 Evaluation Board User’s Guide
DS60001239A-page 30 2013 Microchip Technology Inc.
8.4 EHC Peripherals
The PIC32 EHC includes numerous integrated peripherals available for use by the application code. The following sec-
tions provide an overview of the ava ilable hardware co nnectio ns on the Eval92 Board for each EHC peripheral. Refer
to the PIC32MX5XX/6XX/7XX 32-Bit Microcontrollers Fami ly Data Sheet [17] for more information on these peripheral
interfaces.
8.4.1 I2C COMMUNICATION
The Eval92 Board implements two separate I2C communicatio n buses [21]. The EHC acts as the bus master for both
buses. The MOST Control Bus includes the INIC and IOC as slave devices. In Standard App lication code, all commu-
nication between the EHC and INIC/IOC occurs via Port Message exchange with the INIC and IOC Control Ports. This
interface can be used to configure INIC and the IOC (at power-up or after reset) based on the EHC application code.
The Board Peripheral Bus is also mastered by the EHC and includes various peripheral slave devices used by the appli-
cation. Signals for both buses appear a t various he ade rs for co nnectio n to off-board devi ces. The fu ll device l isti ng for
each I2C bus is provided in Table 8-1.
TABLE 8-1: ON-BOARD I2C SLAVE DEVICES
Slave Device Address * Description
MOST Control Bus - I2C Port 2
Microchip
OS81092 INIC 40h/41h MOST50 network interface controller; the EHC can configure INIC throug h its I2C
Control Port using INIC Control Messages (ICMs).
Microchip
OS85650 IOC 48h/49h I/O port expansion for INIC; the EHC can configure the IOC through its I2C Control
Port using I/O Control Messages (IOCMs).
Board Peripheral Bus - I2C Port 4
Microchip
MPM85000 PwrMgr 10h/11h MOST-compliant power management device; manages and controls board power
while indicating power status and wakeup events to the EHC.
CODEC
NXP UDA1380 30h/31h Stereo audio CODEC; Provides an analog line and headphone output with software
volume control capability.
I/O Expander
TI TCA6424 44h/45h 24-bit GPIO port expansion for the EHC; supports reset and interrupt functionality.
Microchip
EEPROM 24LC32AT A0h/A1h
Connected to the IOC Debug Port for storing optional configuration information. The
EHC can program configuration data into this device. (Note: this device i s isolated
from the rest of the bus with a bus switch (U21) to avoid a multi-master conflict in
case a debug tool is plugged into the IOC debug header.)
* Addresses listed in this table are provided in 8-bit form at: the 7 most significant bits represent the actual slave
address and the least significant bit is the read/write bit.
2013 Microchip Technology Inc. DS60001239A-page 31
OS81092 Evaluation Board User’s Guide
8.4.1.1 I2C Port 2 - MOST Control Bus
Figure 8-3 shows the I2C connections for the MOST Control Bus on the Eval92 Board.
FIGURE 8-3: MOST CONTROL I2C BUS
8.4.1.2 I2C Port 1 - Board Peripheral Bus
Figure 8-4 shows the I2C connections for the Board Peripheral Bus on the Eval92 Board.
FIGURE 8-4: PERIPHERAL I2C BUS.
Note: When Stand-Alone mode (see Section 8.2 “Stand-Alone Mode”) is enabled,
the EHC should disable its I2C interfaces. This allows an external I2C master
to access slave devices on both buses.
EHC
U15
(I2C Port 2)
(RA3)
SCL
SDA
INT INIC
I2C Address 40/41h
U1
MAIN_3V3
2.21 k
R60
SDA
INT
SCL
IOC
I2C Address 48/49h
U2
MAIN_3V3
15 k
R272
to EHC RD4
J17
MOST CONTROL
(RA2)
MOST_SDA
MOST_SCL
2.21 k
R54
MAIN_3V3
to EHC RD7 15 k
R285
15 k
R284
NO POP
SCLSDA
IOC_INT
INT
INT
INIC_INT
EHC
U15
(I2C Port 2)
(RA15)
SCL
SDA
INT
PwrMgr
I2C Address 10/11h
U3
MAIN_3V3
2.21 k
R351
L3DATA/SDA
L3CLK/SCL
CODEC
I2C Address 30/31h
U6
(RA14)
PERIPH_SDA
PERIPH_SCL
2.21 k
R350
MAIN_3V3
to EHC RE8 15 k
R258
SCL
SDA
INT
I/O Expander
U200
MAIN_3V3
to EHC RE9 15 k
R217
I2C Address 44/45h
U21
I2C Bus
Switch
U20
EEPROM
SCL
SDA EN
EEPROM_I2C_EN
IOC
Debug Port
U2
DSCL
TDI/DSDA
4.7 k
R343
4.7 k
R366
MAIN_3V3 (EHC Controlled)
(DaughterBoard Connector)
to J21
(Auxiliary Connector)
to J33
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DS60001239A-page 32 2013 Microchip Technology Inc.
An external I2C slave device with a unique address can be connected to the Eval92 Board MOST Control Bus via the
MOST CONTROL header ( J17), or to the Board Peripheral Bus via the, DAUGHTER BOARD (J21) or AUX (J33) headers. In
these scenarios, EHC applications may be written to support commun ication with the device; however, the I2C clock
speed may need to be lowered as a result of the extra capacitance added by the off-board device.
8.4.2 CAN INTER FAC E
The Eval92 Board supports CAN bus gateway applications using the Freescale MC33897 Single Wire CAN
Transceiver [22] connected to the EHC’s CAN interface. Single Wire CAN is defined by the SAE J2411 Single Wire Can
Network [23]. The MC33897 device is also compatible with the General Motors GMW3089 Single Wi re CAN Physical
and Data Link Layers [24] (also known as GMLAN).
The CAN transceiver (U202) is powered directly from protected, unswitched battery power (12VP) and therefore remains
operational while the Eval9 2 Board is in Sleep Mode . This allows the Eval 92 Board to support CAN b us activity as an
external wakeup source when power management is enabled. Refer to Section 10.0 “Power Management” for more
information on power management.
The CAN transceiver is connected to the EHC’s CAN interface with two unidirectional data lines. Additionally, the EHC
uses two GPIO signals to select the CAN transceiver operationa l mode.
The CAN interface connection diagram is shown in Figure 8-5.
FIGURE 8-5: CAN INTERFACE
Note: Eval92 Board Sleep Mode current can be significantly reduced by disabling
the CAN bus transce iver. Th is is accomp lishe d by removing R212 from the
board.
CAN
Transceiver
MODE0
MODE1
TXD
RXD
CNTL
12VP
U202
0
R212
VBATT
R231
15 k
R232
15 k
MAIN_3V3
(to PwrMgr)
CAN_STATUS
CONT_3V3
(to I/O Expander)
CAN_STATUS_EHC
MAIN_3V3
R19
47 k
R278
47 k
Q1 Q2
BUS
LOAD
R8
6.49 k
HARNESS_CAN
(to J201)
TP1
CAN
L200
47 µH
MMBZ27VCLT1G
D1
12VP
C207
C0G
100 pF
1 k
R216
C203
C0G
33 pF
EHC
U15
(RD2)
(RD1)
(RF1)
(RF0)
CAN_MODE1
CAN_MODE0
CAN_TX
CAN_RX
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8.4.3 UART INTERFACES
8.4.3.1 UART Port 4 - LIN/ECL
The EHC’s UAR T Port 4 interface is connected to the MPM85000 PwrMgr device (U3) and may be used by the standard
application code to implement either Local Interconnect Netw ork (LI N) Specif icatio n [25] communication or MOST ECL
(MOST Electrical Control Line Specification [6]) communication. The LIN/ECL lin e can be controlled/monitored in the
following ways:
• Using the MPM85000 TXD and RXD hardware pins (connected to the EHC UART Port 4 interface), or
• Via the MPM85000 Control Port (LIN Control Register), accessible through the EHC I2C Board Peripheral Bus.
Refer to the MOST ToGo Basic Application Code Firmware Manual [4] and MOST Electrical Control Line
Specification [6] for more information on LIN/ECL communication between network nodes.
The connections for the EHC UART Port 4 interface are shown below in Figure 8-6.
FIGURE 8-6: UART PORT 4 INTERFACE
8.4.3.2 UART Port 2 - CommBr idge
The EHC’s UART Port 2 interface is connected to the CommBridge for flashing new application code and for debug print
functionality. See Section 8.3.3 “Debug Print Statements via USB” and Section 11.0 “MCP2200 CommBridge” for more
information.
8.4.3.3 UART Port 1 - Aux/Misc
The EHC’s UART Port 1 interface is connected to various headers on the Eval92 Board. Depending on the application
code, several different options exist for using this interface. The transmit signal (EHC_TXD, connected to EHC RF8) can
be used for Low Frequency Signal T unneling (LFST) applications by connecting it to an INIC streaming port via the LFST
CONFIG jumpers at J10. Alternatively, it can be routed an off-board device such as a display connected to the AUX
header (J33) via the AUX CONFIG jumper at J11. Refer to Section 9.0 “Audio and Low Frequency Signal Tunneling
(LFST)” for more information on LFST applications and the required hardware connections.
8.4.4 USB
The Eval92 Board provide s a type A USB receptacle connected to the EHC USB port. EHC application code ca n use
this connector to implement a USB host that has access to a variety of peripheral devices (e.g. mass storage applica-
tions) attached to the Eval92 Board. 5 V bus power (up to 125 mA) is provided for attached devices by an on-board
charge pump regulator (U14). The EHC USB port also includes a 3-wire ESD suppression device rated for ±15 kV.
Figure 8-7 illustrates the hardware interface between the EHC and the EHC USB connector (J20).
EHC PwrMgr
TXD
RXD
U3
U4
R24
15 k
R22
15 k
MAIN_3V3
(RD15)
(RD14)
PM_TXD
PM_RXD LIN HARNESS_LIN/ECL
(to J18/J202)
TP13
LIN/ECL
L202
300 @
100 MHz
C217
100 pF
C0G C218
100 pF
C0G
MMBZ27VCLT1G
D212
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DS60001239A-page 34 2013 Microchip Technology Inc.
FIGURE 8-7: USB INTERFACE
8.4.5 SERIAL PERIPHERAL INTERFACE (SPI) PORTS
SPI is a synchronous serial data communication protocol over which a controller (e.g. EHC) can e xchange data with
various slave devices. The controller generates a universal clock and communicates with slave devices using two uni-
directional data signals. Each slave device also has a dedicated chip select signal to prevent data collisions on the bus.
8.4.5.1 SPI Port 1
The EHC SPI Port 1 is co nnected to the IOC’s SPI Port 0. Using this communication interface, the EHC and the IOC
can exchange asynchronous data packets (i.e. MDPs, MEPs) at a rate of up to 25 Mbps. The IOC SPI he ader (J15) is
also provided to permit EHC connection to an off-board SPI slave device. Alternatively, an off-board SPI master device
can be connected to J15 for packet data exchange with the IOC. In th is scenario, the EHC ma y also be co nfigured as
an SPI slave.
The connections for the EHC SPI Port 1 are shown in Figure 8-8.
FIGURE 8-8: EHC SPI PORT 1 CONNECTIONS
EHC
DP (RG2)
DM (RG3)
VBUS
0
J20
U4
R49 0 R50 D-
VBUS
D+
GND
CASE
CASE
USB T ype-A
Receptacle
TP21
VBOF (RB5)
differential si gnal pair
(Zdiff = 90 Ohms)
ESD
Protection
Device
U204
USB_5V
USB Bus Supply
Charge Pump
(5V, 125mA)
EN
MAIN_3V3
U14
100K
R45
EHC
U4
MAIN_3V3
(RD10)
(RD0)
SCK1
SDO1
(SPI Port 1)
(RC4)
(RD9)
SDI1
SS1
IOC
SDIN0/TERR0
SCLK0/TCLK0
SDOUT/TDAT0
CS0/TSYN0
U2
R273
100 k
R274
100 k
R288
100 k
R289
100 k
R287
100 k
SINT0/TVAL0
J15
IOC SPI
3V3
SDIN0
SDOUT0
EHC_CS
SINT0
CS0
SCLK0
GND
MAIN_3V3
MAIN_3V3
R275
100 k
(CN12)
NPCS0/NSS
(RD11)IOC_SINT
(SPI Port 0)
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8.4.6 SPI PORT 2 STREAMING AUDIO
The PIC32 EHC SPI module incl udes an Audio Protocol Interface Mode (Section 2 3 in the PIC 32 Family Reference
Manual [26]) which provides a 4-wire, bidirectional, synchronous, digital audio link with external audio devices. The for-
mat of the digital data is compatib le with some of the I2S formats supported by INIC or the OS85650 I/O Companion
(IOC) on the Eval92 Board. The EHC application co de must run the port in slave mode operation whe re the serial bit
clock SCK2 (also known as BCLK) and the word select clock SS2 (also called LRCK or FSY) are driven by an external
master (i.e. the IOC), so that the audio data is synchronous to the MOST Network.
The EHC SPI Port 2 can optionally be connected to the IOC Streaming Port B (with jumper shunts) using the
EHC I2S CONFIG header (J9), as shown in Figure 7-1. This conn ection permits an audio source application o n the EHC
to exchange streaming audio data over the MOST Network. In this scenario, the IOC acts as an I2S-to-MediaLB bridge
between the EHC and the INIC. Refer to the MOST ToGo Basic Application Cod e Firmware Manual [4] for more infor-
mation.
Additionally, the EHC’s IISC interface may be used in Low Fr equency Signal Tunnelin g (LFST) applications. Refer to
Section 9.2 “Low Frequency Signal T unneling” for more information on configuring the Eval92 Board for LFST operation.
Use of the EHC IISC for Eval92 Board audio applications is further described in Section 9.0 “Audio and Low Frequency
Signal Tunneling (LFST) ”.
8.5 GPIO Reference
Table 8-2 provide s a list of all EHC GPIO connections on the Eval92 Board. The GPIO channels are divided into the
register groupings as defined by the PIC32 GPIO architecture. For exact hardware connections on each EHC GPIO pin,
refer to the Appendix D: “DB81092PCB5.A Silk Screens with Component Grid Placements” and Appendix E:
“DB81092PCB5.A Schematic Layout Files” .
TABLE 8-2: EHC GPIO REFERENCE
Pin
Name GPIO # Pin # Net Name EHC
Peripheral Description / Notes
Component
Register Bank A (s19)
RA0 GPIO00 G3 EHC_TMS JTAG EHC JTAG interface test mode select input U4-G
RA1 GPIO01 J6 EHC_TCK JTAG EHC JTAG interface test clock input U4-G
RA2 GPIO02 H11 MOST_SCL I2C 2 MOST I2C Bus cloc k signal U4-G
RA3 GPIO03 G10 MOST_SDA I2C 2 MOST I2C Bus serial data signal U4-G
RA4 GPIO04 G11 EHC_TD1 JTAG EHC JTAG interface test data input U4-G
RA5 GPIO05 G9 EHC_TDO JTAG EHC JTAG interface test data output U4-G
RA6 GPIO06 C5 EHC_TRCLK TRACE EHC Instruction Trace Clock U4-F
RA7 GPIO07 B5 EHC_TRD3 TRACE EHC Instructi on Trace Data 3 U4-E
RA9 GPIO09 L2 INIC_RST GPIO INIC reset signal U4-H
RA10 GPIO10 K3 PM_NOACT GPIO PwrMgr ePHY activity indicator signal:
0 - valid network activity detected at SP4E
1 - no network activity present at SP4E U4-H
RA14 GPIO14 E11 PERIPH_SCL I2C 4 Peripheral I2C Bus clock signal U4-F
RA15 GPIO15 E8 PERIPH_SDA I2C 4 Peripheral I2C Bus serial data signal U4-F
Register Bank B (s19)
RB0 GPIO16 K2 EHC_PGED1 PGED1 EHC Programming Data U4-H
RB1 GPIO17 K1 EHC_PGEC1 PGEC1 EHC Programming Clock U4-H
RB2 GPIO18 J2 EHC_DFU GPIO EHC Device Firmware Update indicator signal:
0 - Boot mode, bootloader expecting flash commands
1 - EHC bootloader jumps to application (default)
U4-G
RB3 GPIO19 J1 EHC_DFU_LED GPIO LED Flashing indicates DFU mode U4-G
RB4 GPIO20 H2 LED3 GPIO Orange LED - application LED U4-G
RB5 GPIO21 H1 USB_VBUS_EN VBUSON Control signal for USB 5 V charge pump (U14)U4-G
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DS60001239A-page 36 2013 Microchip Technology Inc.
RB6 GPIO22 L1 CODEC_RST GPIO Audio CODEC reset signal U4-H
RB7 GPIO23 J3 Open Pin U4-G
RB8 GPIO24 K4 IOC_DBG GPIO IOC debug configuration signal U4-H
RB9 GPIO25 L4 INIC_ERR/BOOT GPIO INIC error indicator; boot mode enable pin U4-H
RB10 GPIO26 L5 IOC_RST GPIO IOC reset signal U4-H
RB11 GPIO27 J5 Open Pin U4-G
RB12 GPIO28 J7 Open Pin U4-H
RB13 GPIO29 L7 EHC_PWROFF GPIO PwrMgr power-down signal:
0 - EHC is holding ECU power on
1 - EHC is not holding ECU power on U4-H
RB14 GPIO30 K7 CB_READY GPIO CommBridge ready: MCP2200 GP3 (not
implemented) U4-H
RB15 GPIO31 L8 EHC_NPCS0/NSS SPI 1 SPI chip select signa l for off-board device
(attached to J15); EHC SPI slave select signal
for external controller U4-H
Register Bank C (s19)
RC1 GPIO33 D1 Open Pin U4-F
RC2 GPIO34 E4 Open Pin U4-F
RC3 GPIO35 E2 Open Pin U4-F
RC4 GPIO36 E1 IOC_SDOUT0 SPI 1 SPI data output signal for IOC (EHC MISO) U4-F
RC12 GPIO44 F9 EHC_XIN0 OSC 12 MHz crystal input for EHC main clock U4-G
RC13 GPIO45 C10 EHX_XIN32 SOSC 32.768 kHz crystal input for EHC RTC clock U4-F
RC14 GPIO46 B11 EHC_XOUT32 SOSC 32.768 kHz cryst al output for EHC RTC clock U4-E
RC15 GPIO47 F11 EHC_XOUT0 OSC 12 MHz crystal output for EHC main clock U4-G
Register Bank D (s19)
RD0 GPIO48 D9 IOC_SDIN0 SPI 1 SPI data input signal for IOC (EHC MOSI) U4-F
RD1 GPIO49 A11 CAN_MODE0 GPIO CAN PHY mode configuration signal 0 U4-E
RD2 GPIO50 A10 CAN_MODE1 GPIO CAN PHY mode configuration signal 1 U4-E
RD3 GPIO51 B9 Open Pin U4-E
RD4 GPIO52 C8 IOC_INT GPIO IOC interrupt sig nal U4-F
RD5 GPIO53 B8 Open Pin U4-E
RD6 GPIO54 D7 DC_I/O_INT GPIO DaughterBoard I/O Expander interrupt signal U4-F
RD7 GPIO55 C7 INIC_INT GPIO INIC interrupt signal U4-F
RD8 GPIO56 E9 EHC_SWA GPIO Debounced output (from U210) of tactile
switch, SWA U4-F
RD9 GPIO57 E10 IOC_CS0 SPI 1 SPI chip select signa l for IOC U4-F
RD10 GPIO58 D11 IOC_SCLK0 SPI 1 SPI clock signal for IOC U4-F
RD11 GPIO59 C11 IOC_SINT0 GPIO IOC SPI Port interrup t sign al U4-F
RD12 GPIO60 A9 AUX_INT GPIO Interrupt signal for external device attached
to J33 U4-E
RD13 GPIO61 D8 DC_INT GPIO DaughterBoard interrupt signal U4-F
RD14 GPIO62 L9 PM_RXD UART 4 PwrMgr ECL/LIN receive data signal U4-H
RD15 GPIO63 K9 PM_TXD UART 4 PwrMgr ECL/LIN transmit data signal U4-H
Register Bank E (s19)
TABLE 8-2: EHC GPIO REFERENCE (CONTINUED)
Pin
Name GPIO # Pin # Net Name EHC
Peripheral Description / Notes
Component
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RE0 GPIO64 A4 DC_READY GPIO DaughterBoard ready signal:
0 - external device (at J21) is ready for access
1 - device (at J21) is not ready for access U4-E
RE1 GPIO65 B4 Open Pin U4-E
RE2 GPIO66 B3 Open Pin U4-E
RE3 GPIO67 A2 DC_RST GPIO DaughterBoard reset signal U4-E
RE4 GPIO68 A1 IOC_ERROR GPIO IOC error indicator (not locked) U4-E
RE5 GPIO69 D3 Ope n Pin U4-F
RE6 GPIO70 C1 EHC_SWB GPIO Debounced output (from U210) of tactile
switch, SWB U4-E
RE7 GPIO71 D2 Ope n Pin U4-F
RE8 GPIO72 G1 PM_INT GPIO / INT1 PwrMgr interrupt signal U4-G
RE9 GPIO73 G2 I/O_EXP_INT GPIO / INT2 I/O Expander interrup t si g nal U4-G
Register Bank F (s19)
RF0 GPIO80 B6 CAN_RX CAN 1 EHC CAN Interface channel 1 receive signal U4-E
RF1 GPIO81 A6 CAN_TX CAN 1 EHC CAN Interface channel 1 transmit signal U4-E
RF2 GPIO82 K11 EHC_RXD UART 1 EHC UART receive data signal (for LFST
and auxiliary appli cations) U4-H
RF3 GPIO83 K10 Open Pin U4-D
RF4 GPIO84 L10 CB_TXD UART 2 CommBridge UART transmit data signal
(EHC RXD) U4-H
RF5 GPIO85 L11 CB_RXD UART 2 CommBridge UART receive data signal
(EHC TXD) U4-H
RF8 GPIO88 J10 EHC_TXD UART 1 EHC UART transmit data signal (for LFST
and auxiliary appli cations) U4-H
RF12 GPIO92 K6 CB_RTS UART 2 CommBridge UART Request To Send U4-H
RF13 GPIO93 L6 CB_CTS UART 2 CommBridge UART Clear To Send U4-H
Register Bank G (s19)
RG0 GPIO96 Open Pin U4-E
RG1 GPIO97 Open Pin U4-F
RG2 GPIO98 USB_D+ USB USB Di fferential Data Pin U4-D
RG3 GPIO99 USB_D- USB USB Di fferential Data Pin U4-D
RG6 GPIO102 EHC_I2S_SCK SPI 2 EHC I2S Port serial data bit cloc k U4-F
RG7 GPIO103 EHC_I2S_SDI SPI 2 EHC I2S Port serial data input U4-G
RG8 GPIO104 EHC_I2S_SDO SPI 2 EHC I2S Port serial data output U4-G
RG9 GPIO105 EHC_I2S_WS IISC EHC I2S Port word select / TDM frame sync U4-G
RG12 GPIO108 EHC_TRD1 TRACE EHC Instruction Trace Data 1 U4-E
RG13 GPIO109 EHC_TRD0 TRACE EHC Instruction Trace Data 0 U4-E
RG14 GPIO110 EHC_TRD2 TRACE EHC Instruction Trace Data 2 U4-E
RG15 GPIO111 Open Pin U4-E
TABLE 8-2: EHC GPIO REFERENCE (CONTINUED)
Pin
Name GPIO # Pin # Net Name EHC
Peripheral Description / Notes
Component
OS81092 Evaluation Board User’s Guide
DS60001239A-page 38 2013 Microchip Technology Inc.
8.6 I/O Expander
The Eval92 Board includes a 24-bit TCA6424AR I2C Port Expander device (U200) that provides the EHC with additional
GPIO capabilities. The I/O expander resides at address 44/45h on the EHC’s peripheral I2C bus. The I/O expander
includes reset and interru pt functionality: the reset pi n is tied directly to the EHC_RST line and the device will alert the
EHC of a change on any of its input pins by asserting the I/O_EXP_INT signal (connected to EHC pin RE9). Table 8-3,
below, describes the 24 I/O channels on the I/O expander.
TABLE 8-3: I/O EXPANDER SIGNAL REFERENCE
Pin Name Pin # Net Name Description / Notes Component
Gate B: I/O Expander (U200) Bank 0 ( s21)
P00 1 8-position DIP switch (BOARD OPTIONS ), DIP switch 1 S2
P01 2 8-position DIP switch (BOARD OPTIONS ), DIP switch 2 S2
P02 3 8-position DIP switch (BOARD OPTIONS ), DIP switch 3 S2
P03 4 8-position DIP switch (BOARD OPTIONS ), DIP switch 4 S2
P04 5 8-position DIP switch (BOARD OPTIONS ), DIP switch 5 S2
P05 6 8-position DIP switch (BOARD OPTIONS ), DIP switch 6 S2
P06 7 8-position DIP switch (BOARD OPTIONS ), DIP switch 7 S2
P07 8 8-position DIP switch (BOARD OPTIONS ), DIP switch 8 S2
Gate C: I/O Expander (U200) Bank 1 ( s21)
P10 9 16-position coded rotary switch (ID), bit 0 S1
P11 10 16-position coded rotary switch (ID), bit 1 S1
P12 11 16-position coded rotary switch (ID), bit 2 S1
P13 12 16-position coded rotary switch (ID), bit 3 S1
P14 13 LED1 Control signal for EHC LED 1 (green) D203
P15 14 LED2 Control signal for EHC LED 2, (yellow) D202
P16 15 LED3 Control signal for EHC LED 3, (orange) D201
P17 16 LED4 Control signal for EHC LED 4, (red) D200
Gate D: I/O Expander (U200) Bank 2 ( s21)
P20 17 EEPROM_I2C_EN
Control signal for I2C bus switch:
• 0 - EHC peripheral I2C bus isolated from IOC Debug Port
(default)
• 1 - EHC peripheral I2C bus connected to IOC Debug Port
(allows EHC to program IOC configuration data into
EEPROM)
U21
P21 18 TP4 Spare pin
P22 19 CAN_STATUS_EHC
EHC sense signal for CAN PHY VCC regulator control line to
PwrMgr:
• 0 - high-voltage wakeup signal detected
• 1 - wakeup signal not detected (or tCNTLFDLY expired)
P23 20 AUX_ATT External device attached signal for AUX connector J33
P24 21 REM_PWR_EN Control signal for high-side switch for remote power:
• 0 - switch off (remote devices not powered)
• 1 - switch on (12VP_SW power connected to pin 1
U201
J200
P25 22 REM_PWR_STATUS Fault status output from remote power high-side switch U201
P26 23 TP3 Spare pin
P27 24 DC_ATT External device attached signal for DAUGHTERBOARD header U21
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9.0 AUDIO AND LOW FREQUENCY SIGNAL TUNNELING (LFST)
The Eval92 Board supports applications that route streaming audio data between the network and local audio jacks.
On-board jumper options permit a variety of network streaming source/sink implementations between the INIC/IOC and
the stereo audio CODEC for A/D and D/A conve rsi on.
The Eval92 Board also supports Low Frequency Signal T unneling (LFST) over the MOST Network’s synchronous chan-
nel. LFST can be used to transport UART data, IR data, and other low frequency digital signals over the network thereby
eliminating the need for additional dedicated wiring.
9.1 Stereo Aud io CODEC
The Eval92 Board implements network audio source/sink ca pabilities with NXP’s UDA130 Stereo Audi o CODEC [27].
The CODEC device (U6) includes an ADC which provides a network audio source by converting analog input (blue jack,
J2) to digital I2S format. The CODEC also includes a DAC which provides a network audio sink by converting streaming
network audio data (in digital I2S format) to analog output. The DAC is capable of driving headphones (lime green jack,
J3). The EHC application code can manage the CODEC over the peripheral I2C bus (address 30/31h), providing initial
configuration as well as volume, base, treble and mute control.
To support a MOST Network audio source channel, EHC application code can provide an FBlock AuxIn. Using this
FBlock, an audio channel between the INIC or IOC S treaming Port and the CODEC’s ADC (e.g. 16-bit, I2S format) could
be setup and managed over the network.
Similarly, to support a MOST Network audio sink channel, EHC application code can provide an FBlock AudioAmp.
Using this FBlock, an audio channel between the INIC or S treaming Port and the CODEC’s DAC (e.g. 16-bit, I2S format)
could be setup and managed over the network.
In MOST50 systems, audio data exchanged over the network must be synchronous to the MOST Network frame rate
(Fs). Therefore, the CODEC is operated in clock slave mode (i.e. the CODEC bit clock and word clock signals are
inputs). The INIC or IOC Streaming Port bit clock and frame sync signals should be configured as outputs. Additionally,
the CODEC system clock input should be connected to the recovered master clock synchronization signal (either
INIC_RMCK or IOC_RMCK).
9.1.1 DAC CONTROL
The DAC supports mute and volume control from 0 dB to -78 dB attenuation (in 0.25 dB steps). The ADC supports mute
and volume control from -63.5 dB to 24 dB attenuation (in 0.5 dB steps). Typically, application code uses 2 dB steps
from the network.
For DAC volume control, the 16 bit, Master Volume Control register (address 10h) is used, in which the upper byte
(MVCR[7:0]) controls the right channel and the lower byte (MVCL[7:0]) controls the left channel. For 2 dB steps, the byte
values change by 8 for each channel, as shown in Table 9-1.
For DAC mute control, application code typically uses the Master Mute bit in register address 13h. This bit (MTM) is set
when Mute is On and cleared when Mute is Off (Note: MT2 is always set when writing MTM).
Note: Once the audio clocks are properly configured and connected (via J8,
CODEC CONFIG), the EHC must ensure the CODEC reset line (CODEC_RST,
connected to EHC RB6) is high for proper operatio n.
TABLE 9-1: DAC VOLUME TRANSLATION
Volume Network Value MVCR/MVCL Comments
0 dB 20h 00h/00h Maximum value
-2 dB 1Fh 08h/08h
-4 dB 1Eh 10h/10h
-12 dB 1Ah 30h/30h Power-up default
-76 dB 02h F0h/F0h
-78 dB 01h F8h/F8h
Mute 00h FCh/FCh Minimum value; exception to algorithm
OS81092 Evaluation Board User’s Guide
DS60001239A-page 40 2013 Microchip Technology Inc.
For DAC Bass (boost) control, application code should use register address 12h, where BBL[3:0] controls the left chan-
nel and BBR[3:0] controls the right channel. The mappin g is directly proportio nal with o ne DAC Bass b it moveme nt for
every one network value, with a range of 0 to 9 (+18 dB). This range covers both DAC Bass sets.
For DAC T reble (boost) control, application code should use the same register address (12h); TRL[1:0] controls the left
channel and TRR[1:0] controls the right channel. The mapping is directly proportional with one DAC Treble bit movement
for every one network value, with a range of 0 to 3 (+6 dB).
9.1.2 ADC CONTROL
For ADC volume control (if supported), application code should use the 16 bit, Decimator Volume Control register
(address 20h), where the upper byte (ML_DEC[7:0]) controls the left channel and the lower byte (MR_DEC[7:0]) controls
the right channel. For 2 dB steps, the byte values change by 4 for each channel, as shown in Table 9-2.
For ADC mute control, appli cation cod e should use the Decimator Mute bi t in register a ddress 21h. This bit ( MT_ADC)
is set when Mute is On and cleared when Mute is Off.
For ADC InputGainOffset() (if supported), the a ppl ication cod e sh ould use the PGA Gain bits in register address
21h, where PGA_GAINCTRLR[3:0] controls the righ t chann el and PGA_GAINCTRLL[3:0] controls the left channel. Since
InputGainOffset() is specified in dB, and the CODEC step size is 3 dB, every increment of the CODEC gain value
from the network is multiplied by 3.
9.2 Low Frequency Signal Tunneling
The Eval92 Board supports Low Frequency Signal Tunneling (LFST) over the MOST Network’s synchronous channel.
LFST is used to transport low frequency digital signals (e.g. UART or IR data) over the network thereby eliminating the
need for additional dedicated wiring.
Figure 9-1 shows a typical LFST application running in a system with an Eval92 Boar d. A digital bitstream from an IR
receiver (at the remote sensor node) is oversampled at an INIC Streaming Port input pin. The data is transmitted over
the MOST Network synchronous channel using 1 byte of bandwidth and then regenerated locally at an INIC Streaming
Port output pin. The LFST CONFIG ju mp er (J10) is configured to connect the re gen erated bitstream to an EHC input p in
so the signal can be decoded by the app lication.
TABLE 9-2: ADC VOLUME TRANSLATION
Volume Network Value ML_DEC/MR_DEC Comments
24 dB 2Ch 30h/30h Maximum value
2 dB 21h 04h/04h
0 dB 20h 00h/00h Power-up default
-2 dB 19h FCh/FC h
-62 dB 01h 84h/84h
Mute 00h 80h/80h Minimum value
TABLE 9-3: ADC INPUTGAINOFFSET MAPPING
Volume Network Value PGA_GAINCTRLR/L Comments
0 dB 2 0h 00h/00h Maximum value
-2 dB 1Fh 08h/08h
-4 dB 1Eh 10h/10h
-12 dB 1Ah 30h/30h Power-up default
-76 dB 02h F0h/F0h
-78 dB 01h F8h/F8h
Mute 00h FCh/FCh Minimum value; exception to algorithm
2013 Microchip Technology Inc. DS60001239A-page 41
OS81092 Evaluation Board User’s Guide
FIGURE 9-1: LFST TYPICAL APPLICATION
Variou s connection options exist on the Eval92 Board to support both the sourcin g and sinking of LF ST data streams
to/from the network using serial data pins at the INIC Streamin g Port. LFST data streams can be exchanged with the
EHC using the LFST CONFIG header (J10), as shown in Figure 6-5. Also, the INIC serial data output pin can be connected
to an off-board device (connected to the AUX header , J33) by configuring jumper options at the AUX CONFIG header (J11).
Note that the AUX CONFIG header can also be used to connect an EHC UART transmit pin to an external device attached
to J33.
9.3 Hardware Connection Options
The Eval92 Board provides several of jumper options to support a variety of streaming audio and low frequency sign al
tunneling applications. A full overview of the hardware connection options is provided in Figure 9-2, below.
FIGURE 9-2: AUDIO AND LFST CONNEC TION OP TION S
Remote Sensor Node
Eval92 MOST ToGo Board
MOST
Network
OS81092
INIC
SR0 01100011
IR
Receiver
EHC I2C
LFST
CONFIG
J10
SDI
(RG7) OS81092 I N IC
SX0
J9
I2S CONFIG
SDO
SDI
SCK
WS
SRB0
SXB2
SCKB
FSYB
IOC_SRB0
IOC_SRB2
IOC_SCKB
IOC_FSYB
J10
RXD
SDI
TXD
SDO
SX0
SX0
SR0
SR0
LFST CONFIG
EHC ---|--- IOC
(SPB)
EHC_I2S_SDO
EHC_I2S_SDI
EHC_I2S_SCK
EHC_I2S_WS
To IOC
Streaming Port B
To EHC
IISC Port
EHC ---|--- INIC
EHC_RXD
EHC_TXD
To EHC
UART Port 4
J8
CODEC CONFIG
IOC -|- CODEC -|- INIC
(SPA)
INIC_RMCK
INIC_SCK
INIC_FSY
INIC_SX0
To INIC
Streaming Po rt
INIC_SR0
IOC_RMCK
IOC_SCKA
IOC_FSYA
IOC_SXA2
To IOC
Streaming Port A IOC_SRA0
SYSCLK
BCK
WA
DATAO*
DATAI*
CODEC_SYSCLK
CODEC_BCK
CODEC_WS
CODEC_DATAI To Audio CODEC
CODEC_DATAO
AUX CONFIG
J11
INIC SX0
AUX DATA
EHC TXD AUX_SX To J33
Auxiliary Header
J5
EHC_SDO
* Signals are rever se d f r om
silkscreen indic ation
OS81092 Evaluation Board User’s Guide
DS60001239A-page 42 2013 Microchip Technology Inc.
10.0 POWER MANAGEMENT
The Eval92 Board integrates MPM85000 Power Management [3] (PwrMgr) (U3), which is a MOST-compliant power
management device. On the Eval92 Board, the PwrMgr and external circuitry support:
• Status outputs connected to an external power management interface (EHC or INIC),
• Control signal for switching 12 V power to the applicatio n regulators,
• Reset generator output connected to the board reset circuitry,
• Wakeup signaling via Local Interco nnect Network (LIN) [25] or MOST Electrical Control Line (ECL) [6]
• ePHY Network activity detection at SP4E,
• Detection and qualification of local application wa keup events using ON_SW and STATUS inputs,
•I
2C slave port for status monitoring and configuration by the EHC,
• Temperature monitoring and reporting, and
• Low-power operation (Sleep Mode) - <100 A total quiescent current from main 12 V supply (VBATT).
Power management functionality is enabled by hardware when DIP switch 6 is OPEN (default). When enabled, the
PwrMgr controls 12 V protected and switched board power (12VP_SW). The PwrMgr po wers-down the board based on
the state of its PWROFF input pin, which can be infl uenced by the EHC, INIC, o r both. The Eval92 Board is d esigned
to support all three options; however , the INIC exclusively influences board power-down by default.
10.1 Sleep Mode
The Eval92 Board supports Sleep Mode (defined in the MOST Specification 3.0 [5]) in which the PwrMgr places the
board in a low power state. Thi s is accomplished when the PwrMgr releases the ENABLE signal (pulled high on the
board), disabling the 12 V input power (12VP_SW) to the 3.3 V and 1.8 V application regulators. Disabling these supplies
powers-down INIC, the EHC, and other board devices.
During normal operation, the PwrMgr attempts to enter Sleep Mode when wakeup/interrupt events are not present. On
the Eval92 Board, the EHC may optionally hold-off Sleep Mode by either driving the EHC_PWROFF signal low or setting
the PwrMgr HOLD bit (MPM85000 Voltage Control Register, 0x06).
As part of its monitoring and diagnostic functionality, the PwrMgr may also force the Eval92 Bo ard into Sleep Mode in
certain under-voltage conditions. See the MPM85000 Automotive Power Management Devi ce Data Sheet [3] for more
information.
When the PwrM gr enters Sleep Mode, current consumption is minimized with the switched supplies disabled; however,
the PwrMgr continues to monitor board power/status and output a 3.3 V continuous micro-regulated supply (VDDU). The
Eval92 Board remains in Sleep Mode until a wakeup event (de scri bed in Section 10.2 “Wake up and Interrup t Events”)
is recognized by the PwrMgr’s internal logic.
10.2 Wakeup and Interrupt Events
When the Eval92 Board is in Sleep Mode , the PwrMgr continues to monitor power/status on the board. The PwrMgr
exits Sleep Mode (e.g. drives ENABLE low to restore 12 V switched power) when the power supply is within the Power
On Volt age range and a qualified wakeup event is recognized, which includes:
•WAKE/SLEEP switch pressed (S5),
• ePHY Network activity detected at SP4E,
• ECL activity (MOST Electrical Control Line Specification [6]) is detected (low-level is detected on PM_ECL/LIN
from the ePHY NETWORK connector), or
• high-voltage wakeup signal recognized by the CAN transceiver (U202)
If one of the above wakeup events occurs during normal operation (not in Sleep Mode), it is considered an interrupt
event. The PwrMgr informs the EHC of an interrupt event by driving the PM_INT signal low (EHC RE8).
Note: To initially power the Eval92 Board, the main board power switch (S3) must
be ON and the main board power supply (e.g. supplied through the
ePHY NETWORK connector and measured at the PwrMgr VPRO pin) must be
above the minimu m Powe r On Voltage, as defined in Appendix A: “Operat-
ing Conditions” on page 49.
2013 Microchip Technology Inc. DS60001239A-page 43
OS81092 Evaluation Board User’s Guide
For EHC application code that supports power management, recognition of an interrupt event is likely to trigger a read
of the MPM85000 Initial Wake Event Register (0Fh), which indicates the reason the Eval92 Boa rd exited Sleep Mode.
Operation as either a Power Master or Power Slave determines how wakeup and interrupt events are handled b y the
application.
10.3 Other Circuitry
The Eval92 Board uses resistor installation optio ns to control the default state of MPM85000 WAKEHI configura tion
pin. By default, R35 is present (R27 not installed) and the pin is set high. If R35 is removed and R27 is installed, the pin
will be set low.
•If WAKEHI is sampled high at initial power-up, the board will not exit Sleep Mode in the UCritical region.
•If WAKEHI is sampled low at initial power-up, the board will exit Sleep Mode in UCritical.
Refer to the MPM85000 Automotive Power Management Device Data Sheet [3] for more information on the MPM85000
Allowed Wakeup Range and using the WAKEHI pin to set the default state of the CR.WAKECV bit.
The PM_RST reset signal (controlled by the PwrMgr RESET output pin) is used to reset the entire Eval92 Board. T his
signal, as well as the BOARD_RESET switch (S9), force the PM_PWROFF signal low, which prevents the Eval92 Board
from entering Sleep Mode during the reset period.
10.4 Disabling Power Management
The Eval92 Board uses a hardware override mechanism to allow th e power management circu itry to be disabled (via
DIP Switch 6) during EHC programming or debugging.
When DIP switch 6 is CLOSED, all shutdown capabilities of the power management circuitry are overridden by clamping
the PM_PWROFF signal to ground through D4. With power man agement disab led in this manner, the Eval92 Board is
prevented from entering Sleep Mode.
10.5 Typical Power Scenarios
When Eval92 Board
power management is enabled, the following figures provide typical power-up and power-down
sequencing of a timing-slave node from Sleep Mode. These figures are typical, in that some variances may be observed
with different EHC application code. These figures show Eval92 Board
power scenarios when standard EHC ap plication
code (provided by Microchip) is used. Refer to the
Eval92 Board MOST ToGo Basic Application Code Firmware
Manual [4]
for more information on specific firmware implementations.
Note: The EHC application code can disable PwrMgr detection of individual
wakeup and interrupt events via register settings, as needed.
OS81092 Evaluation Board User’s Guide
DS60001239A-page 44 2013 Microchip Technology Inc.
10.5.1 WAKEUP DUE TO ECL ACTIVITY
Figure 10-1 illustrates how the Eval92 Board
(configured as a timing-slave) wakes from
Sleep Mode
as a result of the
PM_ECL/LIN
line being pulled low via the
ePHY NETWORK
connector. In this scenario, INIC (not the EHC) controls the
PwrMgr
PWROFF
pin
FIGURE 10-1: POWER SLAVE - WAKEUP DUE TO ECL ACTIVITY
.
VDDP
(3.3V switched supply)
1.8VSW
(1.8V switched supply)
ETXP/ETXN
(INIC Network Transmitter)
~25 ms
(MOST tWaitNodes)
INIC_PWROFF
(PwrMgr PWROFF input pin;
controlled by INIC)
ERXP/ERXN
(INIC Network Receiver)
common-mode enabled
PLL locked to RX
ENABLE
(PwrMgr ENABLE output pin)
PM_RST
(PwrMgr RESET output pin)
ERR/BOOT
(INIC ERR/BOOT output pin)
~1 ms
~20 ms
~115 µs
PM_ECL/LIN
(PwrMgr LIN input pin) ~80 ms
(EHC controlled)
~3 ms
(tLIN_ACT + tLIN_D)
~1.2 ms
~10 µs
(tpal)
controlled by MPM85000
RD.DELAY[2:0]
~1.2 ms
controlled by hardware
RC circuit
(tinicinit)
INIC_RST
(Output of the on-board
MAIN_1.8VSW voltage monitor;
also influenced by PM_RST)
2013 Microchip Technology Inc. DS60001239A-page 45
OS81092 Evaluation Board User’s Guide
10.5.2 WAKEUP DUE TO NETWORK ACTIVITY
Figure 10-2 illustrates how the Eval92 Board
(configured as a timing-slave) wakes from
Sleep Mode
as a result of ePHY
network activity. In this scenario, INIC (not the EHC) controls the PwrMgr
PWROFF
pin.
FIGURE 10-2: POWER SLAVE - WAKE DUE TO NETWORK ACTIVITY
~31 ms
(MOST tWaitNodes & tWakeUp)
common-mode enabled
PLL locked to RX
~1 ms
~10 ms
~20 ms
~115 µs
ERXP/ERXN
(INIC Network Rec ei ver)
ENABLE
(PwrMgr ENABLE output pin)
VDDP
(3.3V switched supply)
PM_RST
(PwrMgr RESET output pin)
1.8VSW
(1.8V switched supply)
ERR/BOOT
(INIC ERR/BOOT output pin)
ETXP/ETXN
(INIC Network Tran s m i tt er)
(tePHY_ACT)
(tinicinit)
~10 µs
(tpal)
controlled by MPM85000
CR.EDELAY[2:0]
INIC_RST
(Output of the on-board
MAIN_1.8VSW voltage monitor;
also influenced by PM_RST)
INIC_PWROFF
(PwrMgr PWROFF input pin;
controlled by INIC )
OS81092 Evaluation Board User’s Guide
DS60001239A-page 46 2013 Microchip Technology Inc.
10.5.3 POWER DOWN
Figure 10-3 illustrates how the Eval92 Board
(configured as a timing-slave) returns to
Sleep Mode
. In this scenario, INIC
controls the PwrMgr
PWROFF
pin; however, (with
INIC.PMIConfig.Config = 0x02
in OTP memory) INIC do es not
release the
PWROFF
pin until there is no network activity (for
INIC.PMIConfig.TimePwrOff
time) and it enters
EHCI Protected Mode
.
By sending INIC.EHCIState.Set(EHCI_Protected), the EHC can control when INIC
enters EHCI Protected Mode. This allows the EHC to
keep the board from powering down (e.g. entering
Sleep Mode
)
until the application is ready.
Allowing INIC to control the PwrMgr PWROFF line, with the EHC managing INIC is a more robust architecture than
allowing the EHC to manage the PWROFF line directly. Refer to the MOST INIC Hardware Concepts Technical
Bulletin [8] for more information on this scenario.
FIGURE 10-3: POWER SLAVE - POWER DOWN SEQUENCE
NOACT
(PwrMgr NOACT output pin)
~115 µs
(tNtwShutdown)
~500 µs
EHC<-INIC.NIState.Status(NET_OFF)
EHC->INIC.PMIState.Set(PWROFF_HIGH)
ERXP/ERXN
(INIC Network Receiver)
ETXP/ETXN
(INIC Network Tran sm i tte r)
VDDP
(3.3V switched supply)
PM_ENABLE
(PwrMgr ENABLE output pin)
INIC_PWROFF
(to PwrMgr PWROFF in pu t pi n;
controlled by INIC)
ERR/BOOT
(INIC ERR/BOOT output pin)
(tePHY_INACT)
(EHC controlled)
~200 ms
(tPOFF_DEL)
(MOST tPwrSwitchOffDelay) typ 20 sec
2013 Microchip Technology Inc. DS60001239A-page 47
OS81092 Evaluation Board User’s Guide
11.0 MCP2200 COMMBRIDGE
The Eval92 Board includes an integrated communications bridge (CommBridge) to facilitate application firmware
updates and obtaining status and debug information from the EHC applicatio n. The CommBridge is used to interface
the board to a PC while preserving the USB port of the PIC32 for use as a mass storage devi ce.
The CommBridge device (U11) itself is a MCP2200 Microchip USB to UART Serial Converter, which enables USB con-
nectivity in applications that have a UART interface. The d evice runs from 3.3 V power (CB_3V3) which can be de rived
from the USB VBUS or from the board’s main 3.3 V supply. The main internal clock is derived from the 12 MHz external
crystal (Y1). The MCP2200 also has some GPIO pins and an internal EEPROM that can be accessed from PC appli-
cations across the USB interface. The MCP2200 implements a composite USB device with a CDC class device to carry
the UART traffic, and a HID device to ac cess the EEPROM and I/O pin s. The CDC class means that on the PC side,
the EHC UART traffic appears as a simple serial port. See the MCP2200 USB 2.0 to UART Protocol Converter with
GPIO Data Sheet [28] for full details
An overview of the Eval92 Board CommBri dge is shown in Figure 11-1.
FIGURE 11-1: COMMBRIDGE OVERVIEW
The Eval92 Board implemen ts an automatic po wer switch (U7) to control the CommBridge power source. If the board
is connected to a PC with a USB cable via J7, the CommBridge always runs from the external USB power (even when
the board is in Sleep Mode). If the external supply is removed, the CommBridge automatically switches over to the
MAIN_3V3 supply. The CB_STATUS signal conveys the state of the power switch to the CommBridge.
Since the CommBridge remains powered while the rest of the application is in Sleep Mode, i t must not be driving any
of its GPIOs if power is removed from the EHC to avoid inadvertent currents across power domains. To accomplish this,
the CB_STATUS signal from the power switch goes to a CommBridge GPIO which can be checked by a PC application
before driving any of the IO pins that go to the EHC.
The CommBridge USART2 interface is connected to the EHC. The CommBridge sends data using the CB_TXD signal.
The EHC transmits debug print information to the CommBridge (for transmission to the PC over USB) using the CB_RXD
signal.
The CommBridge is also capable of loading application code images into EHC flash memory. Refer to Section 8.3.1
“Flashing from PC via USB” for more information.
PIC32
PIC32MX795
Automatic
Power Switch
USB to UART Serial
Converter
CommBridge
MCP2200
CB_READY
MAIN_3V3
CB_3V3
USB Mini AB
Connector
J7
U11 U4
D-
VBUS
D+
GND
U7
CB_USB_5V
3.3 V
Regulator
MAIN_3V3
CB_USB_3V3
U9
ESD
Protection
Device
U8
CB_STATUS
12 MHz
Crystal
Y1
R249 D-
D+
0
0
R243
RB14
U2RX
U2TX
U2CTS
U2RTS
TX
RX
RTS
CTS
J14
CB UART
CTS
RX
TX
GND
RTS
(CB_TXD)
(CB_RXD)
(CB_CTS)
(CB_RTS)
CB_3V3 CB_3V3
475
475
TX_LED/
GP7 RX_LED/
GP6
USB_TX
(Yellow) USB_RX
(Green)
GP3
D205 D6
EHC_RST
EHC_DFU
INIC_RST
GP0GP2
GP5
GP4
Q218 Q3
OS81092 Evaluation Board User’s Guide
DS60001239A-page 48 2013 Microchip Technology Inc.
11.1 CommBridge GPIO Reference
Table 11-1 provides a list of all CommBridge GPIO connections on the Eval92 Board. As mentioned, the PC application
should not configure any of th e GPIO outputs until it is verifi ed that the MAIN_3V3 power is on by checking CB_STATUS
and/or MAIN_3V3 inputs.
TABLE 11-1: COMMBRIDGE GPIO REFERENCE
Pin Name Pin # Net Name Description / Notes
Component
MCP2200 CommBridge ((U11) GPIO ( s23)
GP0/SSPND 13 EHC_RST GPIO output the PC application can reset the EHC. Note: the
SSPND functionality is not used or enabled. U11
GP1/USBCFG 12 MAIN_3V3 GPIO input the PC appl ication can check for ma in 3.3 V power.
Note: the USBCFG functionality is not used or enabled. U11
GP2 11 EHC_DFU GPIO output the PC application can use to put the EHC into
bootloader mode fo r programming. U11
GP3 6 CB_READY Not used - should be left unconfigured U11
GP4 5 CB_STATUS GPIO input the PC applicati on can check to see if CommBridge
is powered by USB or MAIN_3V3. U11
GP5 4 INIC_RST GPIO output the PC appli cation can use to hold INIC in reset
during a firmware update. U11
GP6/RXLED 3 CB_USB_RXLED The RXLED functionality is enabled. This pin drives green USB
RX LED D6 U11
GP7/TXLED 2 CB_USB_TXLED The TXLED functiona lity is enabled. This pin drives yellow USB
TX LED D205 U11
2013 Microchip Technology Inc. DS60001239A-page 49
OS81092 Evaluation Board User’s Guide
APPENDIX A: OPERATING CONDITIONS
V alues specified below assume Fs = 48 kHz and PwrMgr default register values, unless otherwise noted. Voltages spec-
ified below are measured on the board edge at VBATT (TP2) and do not consider losses found in power supply cabling.
Values in this table are typical and measured at room temperature.
TABLE A-1: OPERATING SPECIFICATIONS
Description Min Typ Max Units Conditions
Network Harness (J18)
Continuous Operating Ra nge (Notes [1], [2], [3]) 6.55 14.05 26.00 V
Power On Voltage[3]9.15
6.65 V
VR27 removed; R35 installed (default)
R27 installed; R35 removed
Power Consumption 2.00 W
Normal Operating Current [4] 142 mA VBATT = 14.05 V; VPRO = 13.5 V
Sleep Mode Current 49 AVBATT = 13.65 V; VPRO = 13.5 V
CAN PHY disabled (R212 removed)
Voltage Drop due to Load Dump Circuitry [5]0.55
0.15 V
VNormal Operation
Sleep Mode
Audio Input Jack (J2)
CODEC Full-Scale Input 2.00 VRMS
Audio Output Jack (J3)
CODEC Full-Scale Outp ut 0.75 VRMS RL = 16
Miscellaneous Ambient Temperature 0 70 C
Note 1: Operation at DC voltages above the maximum value will result in increased power consumption due to
various protection diodes turning on.
2: The Contin uous Opera ting Range does not consider over-voltage tran sients and under-voltage dropouts
that may occur in automotive e nvironments. The Eval92 Board contains typical load-dump circuitry that
passes Test Level IV (max.) for all transient pulses defined for 12 V automotive systems in the
ISO 7637-2:2004 [29] test specification.
3: With typical EHC application code, if the operating voltage falls below 6.55 V after initial power-up, the
Eval92 Board enters Sleep Mode when power management is enabled. If power management is disabled,
Sleep Mode is not supported. W hile in Sleep Mode, the operating voltage must rise above the minimum
Power On V oltage before the Eval92 Board will exit Sleep Mode in response to a permitted wakeup event.
4: The Normal Operating Current specification is based on an Eval92 Board Standard Application, as defined
in Section 1.2.1 “S tandard Application”. The board is a MOST Network timing-master configured for audio
sourcing/sinking using standard EHC application code.
5: V oltage thresholds used to control board power-up and power-down are measured at the PwrMgr (VPRO).
Therefore, when considering programmable PwrMgr threshold values, the user must take VLoadDump into
consideration, which is defined as the difference between VPRO and VBATT due to various series compo-
nents.
OS81092 Evaluation Board User’s Guide
DS60001239A-page 50 2013 Microchip Technology Inc.
APPENDIX B: PCB DETAILS
Please see the Appendix D: “DB81092PCB5.A Silk Screens with Component Grid Placements” and Appendix E:
“DB81092PCB5.A Schematic Layout Files” for detailed information
The board layout plots utilize a grid system for locating components, jumpers and test points on the board. As illustrated
in Figure B-1, the top grid column begins the alphabet on the long edge of the board, and the bottom grid column stops
at the end of the alphabet. This allows user to immediately determine which side of the board a particular jumper is
located.
FIGURE B-1: SILKSCREEN GRID EXAMPLE WITH BOARD DIMENSIONS
Throughout this document, the following conventions are used to help locate components on the board:
• 1-5 are used on both sides of the board as the vertical locator,
• A-G are used as the top side horizontal locator, and
• T-Z are used as the bottom side horizontal locator.
Note: See Appendix D: “DB81092PCB5.A Schematics” for detailed silkscreen
images and for the placement of components on the board using the above
grid diagram.
12.70 cm
Top
19. 69 cm
AEBDC
3
4
5
F G
2
1
12.70 cm
Bottom
19 . 69 cm
WTVU X Y Z
3
4
5
2
1
Details found in
FIGURE D-1:
Silkscreen Top
Details found in
FIGURE D-2: Silkscreen
Bottom
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APPENDIX C: COMPONENT PLACEMENT
C.1 Jumpers & Test Points
Table C-1 provides assistance in locating headers, connectors, switches, and test points on the Eval92 Board.
Jumper and Test Point component types are defined as follows:
•C - Connector/Jack
Allows for specific connection by a mating device on external tool, equipment, or cable.
•H - Header
Allows connections via fly-wires and accommodates connections to osci lloscope or multimeter.
•J - Jumper
Uses shorting jumpers (shunts) to make connections. Uses 0.1 " spacing, unless noted otherwise.
•TP - Test Point
Allows connection to oscilloscope or multimeter. Can be differential, wire-loop or through-hole.
•SW - Switch
User-controllable mechanical switch (e.g. DIP, push-button).
TABLE C-1: JUMPERS AND TEST POINTS
Type Ref Des Silkscreen Description Sheet # *Board
Location †
TP DP 1 SP1E Differential Test Point for INIC ETXP and ETXN s5 2F
TP DP 2 SP2E Differential Test Point for TX+ and TX- at
ePHY connector s5 2G
TP DP 3 SP3E Differential Test Point for RX+ and RX- at
ePHY connector s5 5F
TP DP 4 SP4E Differential Test Point for INIC ERXP and ERXN s5 3F
TP J 1 GND Ground Loop s25 5G
C J 2 AUDIO IN CODEC Line In Jack (3.5 mm, light blue) s16 5D
C J 3 AUDIO OUT CODEC Headphone Jack (3.5 mm, lime green) s16 5D-5E
TP J 4 GND Ground Loop s25 5A
H J 5 EHC_SDO Serial Stream Data from EHC s17 3D-4D
C J 6 BOARD POWER Main Power Connector (Binder 09-3419-82-03) s1 4G-5G
C J 7 CB USB CommBridge USB Connector (USB Mini-AB Connector) s23 4A
H/J J 8 CODEC CONFIG CODEC Configuration Header s17 4D
H/J J 9 I2S CONFIG EHC I2S Configuration Header s17 4C
H/J J 10 LFST CONFIG LFST Configuration Header s17 4C
H/J J 11 AUX CONFIG AUX Configuration Header s17 4D
H J 12 PWR MGMT Power Management Header s3 4E
TP J 13 GND Ground Loop s25 4G
H J 14 CB UART CommBridge UART Header s23 4A
H J 15 IOC SPI IOC SPI Header s10 3C
TP J 16 GND Ground Loop s25 3C
H J 17 MOST CONTROL MOST Control Header s13 3D
C J 18 ePHY NETWORK Network Cable Harness (Tyco/AMP 1318772-2) s24 3G
H J 19 IOC HBI IOC HBI Header s11 2C-3C
C J 20 EHC USB EHC USB Connector (USB Type A Receptacle) s20 2A-3A
CJ21
DAUGHTER
BOARD High-Speed Connector for attaching secondary applica-
tion PCB (QSH-020-01-L-D-DP-A) s15 2E-3E
TP J 22 GND Ground Loop s25 2C
* Sheet # correspond to board schematic sheet files shown in Figure E-1 through Figure E-25.
† The Board Location coordinates refer to silkscreen Figure D-1 and Figure D-2.
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C J 23 IOC TSI IOC TSI Connector (5x2 position, 2mm pitc h) s10 1D
H J 24 EHC JTAG EHC JTAG Debug and Programming Port s18 1B
TP J 25 GND Ground Loop s25 1E
H J 26 EHC TRACE EHC Instruction Trace Header s18 1B-1C
H J 27 EHC ICSP EHC Programming and Debug ICSP header s18 1B
TP J 28 GND Ground Loop s25 1G
C J 30 IOC DEBUG IOC Debug Header (7x2 position, 2mm pitch , shrouded) s14 1D-1E
C J 31 I NIC DEB UG INIC Debug Header (7x2 position, 2mm pitch, shrouded) s14 1F
C J 33 AUX AUX Connector (Wuerth 68711214522) s15 1C
C J 34 MEDIALB DEBUG MediaLB Debug Connector
(Samtec HDMI HDMR-19-02-S-SM) s12 1E
TP J 35 GND Ground Loop s25 1A
C J 200 12VPSW OUT Switched Remote Power Connecto r (Molex 43650-0209) s24 5V
C J 201 CAN Single-Wire CAN Connector (Mol ex 43650-0209) s24 5C
C J 202 LIN/ECL LIN/ECL Connector (Molex 43650-0209) s24 4G
CJ203BATT PWR OUT
Continuous Remote Power Connector
(Molex 43650-0209) s24 5U
TP J 204 GND Ground Loop s25 3X
SW S 1 ID 16-position Rotary Switch s21 5B-5C
SW S 2 BOARD OPTIONS 8-position DIP Switch s21 5B
SW S 3 OFF/ON Toggle Swich for Main Board Power s1 5G
SW S 5 WAKE/SLEEP Push-Button Switch for PwrMgr ON_SW pin; controls
board power-up/power-down. s3 3F-4F
SW S 6 EHC RESET Push-Button Switch for EHC Re set s4 1F
SW S 7 IOC RESET Push-Button Switch for IOC Reset s4 1F
SW S 8 INIC RESET Push-Button Switch for INIC Reset s4 1G
SW S 9 BOARD RESET Push-Button Switch for Board Reset s4 1G
SW S 10 EHC DFU Push-Button Switch to EHC DFU Enable s20 1D
SW SWA SWA
General Purpose EHC Push-Button Switch (with hardware
debounce device)
s20 2A
SW SWB SWB
General Purpose EHC Push-Button Switch (with hardware
debounce device)
s20 2A
TP TP 1 CAN Single-Wire CAN Test Point (HARNESS_CAN)s24 5C
TP TP 2 VBATT Battery Voltage Test Point (HARNESS_BATT_POS)s1 5G
TP TP 3 TP3 Unused I/O Expander pin P2.6 s21 5C
TP TP 4 TP4 Unused I/O Expander pin P2.1 s21 5C
TP TP 5 CB_3V3 CommBridge 3.3 V Peripheral Supply s22 4A
TP TP 6 CB GPIO7 CommBridge USB Tx LED s23 4B
TP TP 7 12VP Continuous 12 V Protected Power s1 4F
TP TP 8 MAIN_3V3 Main Board 3.3 V Switched Power Supply s2 4F
TP TP 9 CB_USB_3V3 CommBridge USB Bus Power Regulated 3.3 V Supply s22 4A
TP TP 10 CB_USB_5V CommBridge USB 5 V Bus Power s23 4A
TP TP 11 CONT_3V3 PwrMgr Continuous 3.3 V Micropower Supply s3 4F
TP TP 12 EHC DFU EHC DFU Enable Signal (EHC_DFU)s20 2C
TABLE C-1: JUMPERS AND TEST POINTS (CONTINUED)
Type Ref Des Silkscreen Description Sheet # *Board
Location †
* Sheet # correspond to board schematic sheet files shown in Figure E-1 through Figure E-25.
† The Board Location coordinates refer to silkscreen Figure D-1 and Figure D-2.
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TP TP 13 LIN/ECL LIN/ECL Signal (HARNESS_LIN/ECL)s24 3G
TP TP 14 VPRO PwrMgr VPRO Signal s3 3F
TP TP 15 MAIN_1V8 Main Board 1.8 V Switched Power Supply s2 3E
TP TP 16 TST1 INIC TST1 Signal (unus ed) s8 3E
TP TP 17 TST2 INIC TST2 Signal (unus ed) s8 3E
TP TP 18 TP18 USBID/RF3 Unused EHC GPIO Pin s20 3B
TP TP 19 ERXCM INIC ERXCM Signal s5 3F
TP TP 20 GND Ground s12 3E
TP TP 21 USB_5V EHC USB 5 V Bus Power s20 3A
TP TP 22 SWA De bounced Output of EHC Push-Button Switch, SWA s20 2A
TP TP 23 IOC XTI IOC XTI Signal (unused) s9 2D
TP TP 24 TP24 Status Signal for Main Power High-Side Switch s1 4F
TP TP 25 12VP_SW Switched 12 V Protected Power s1 4F
TP TP 26 TP26 Unused Signal for DAUGHTER BOARD Connector (J21)s15 2D-2E
TP TP 27 SWB Debounced Output of EHC Push-Button Switch, SWB s20 2A
TP TP 28 TP28 Unused TRST signal on EHC JTAG Header (J24)s18 1B
TP TP 29 IOC SXA3 IOC Streaming Port A SXA3 Signal s10 3C
TP TP 30 IOC SRA1 IOC Streaming Port A SRA1 Signal s10 3C
TP TP 31 IOC SXB3 IOC Streaming Port B SXB3 Signal s10 3C
TP TP 32 IOC SRB1 IOC Streaming Port B SRB1 Signal s10 3C
TP TP 33 CB GPIO6 CommBridge USB Rx LED s23 4B
TP TP 34 TP34 Unused Signal for AUX Connector (J33)s15 1C
TP TP 35 MLBCLK MediaLB 3-pin Bus Clock (INIC_MLBCLK)s12 2E-3E
TP TP 36 MLBSIG MediaLB 3-pin Signal (INIC_MLBSIG)s12 2E
TP TP 37 MLBDAT MediaLB 3-pin Data (INIC_MLBDAT)s12 2E
TP TP 38 TP38 Unused DINT signal on EHC JTAG Header (J24)s12 1A
TABLE C-1: JUMPERS AND TEST POINTS (CONTINUED)
Type Ref Des Silkscreen Description Sheet # *Board
Location †
* Sheet # correspond to board schematic sheet files shown in Figure E-1 through Figure E-25.
† The Board Location coordinates refer to silkscreen Figure D-1 and Figure D-2.
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C.2 Reference Designators
Table C-2 provides assistance in locating integrated circuits, diodes, resistors and crystals on the Eval92 Board.
Circuit component types are defined as follows:
•D - Diodes
•R - Resistors
•U - Integrated Circuits
•Y - Crystals
Note: The following Table only references Circuit components mentioned within
this User’s Guide. For a complete listing, pl ease see the DB81092SCH5A1
Bill of Materials. All components are listed withi n the schematic files shown
in Figure E-1 through Figure E-25 and on the board silkscreen drawings
Figure D-1 and Figure D-2.
TABLE C-2: REFERENCE DESIGNATORS
Type Ref Des Description Sheet # *Board
Location †
D D 4 Schottky Diode - DIP SW6 Control of PM_PWROFF s21 5B
D D 6 LED - Yellow-Green - USB Rx s23 5A
D D 10 Schottky Diode - Connect RSOUT to EHC_RST s8 1E
D D 11 Schottky Diode - Connect RSOUT to IOC_RST s8 1E
D D 200 LED - Red - Application LED s25 5Y
D D 201 LED - Orange - Application LED s25 5Y
D D 202 LED - Yellow - Application LED s25 5Y
D D 203 LED - Yellow-Green - Application LED s25 5Y
D D 205 LED - Yellow - USB Tx s23 5A
D D 206 LED - Orange - EHC - Firmware Update s25 1W
D D 207 LED - Red - CommBridge Power s25 5Z
D D 209 LED - Red - Board Power s25 4T
D D 217 LED - Yellow-Green - Network Lock s25 2T
D D 218 LED - Yellow - INIC Reset s25 2T
D D 219 LED - Yellow - IOC Reset s25 2U
D D 220 LED - Yellow - EHC Reset s25 2U
D D 221 LED - Orange - IOC Error s25 1W
D D 223 Schottky Diode - Gang INI C Reset with Board Reset s4 1T
D D 224 Schottky Diode - Gang IOC Reset with Board Reset s4 1U
D D 225 Schottky Diode - Gang EHC Reset with Board Reset s4 1U
D D 227 Schottky Diode - Gang EHC Reset with Da ughter Card Reset s15 1V
R R 27 0 Ohm Resistor - WAKEHI Pull Down (no pop) s3 4F
R R 35 0 Ohm Resist or - WAKEHI Pull Up s3 4F
R R 212 0 Ohm Resistor - Disable CAN Transceive r s6 5X
R R 270 15K Resistor - IOC default to I2C Mode (no pop) s11 1V
R R 284 15K Resistor - INIC MediaLB at Power Up (no pop) s13 3W
R R 285 15K Resistor - INIC I2C at Power Up s13 3W
R R 309 0 Ohm Resistor - Daughterboard Reset s15 2V
R R 344 15K Resistor - IOC Default to JTAG Mode s11 1X
U U 1 OS81092 INIC MOST50 s5, s7, s8, s12, s13, s14 2E-3E
* Sheet # correspond to board schematic sheet files shown in Figure E-1 through Figure E-25.
† The Board Location coordinates refer to silkscreen Figure D-1 and Figure D-2.
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U U 2 OS85650 I/O Companion s9, s10, s11, s12, s13, s14 2D-3D
U U 3 MPM85000 MOST Power Management Device s3 3F
U U 4 PIC32MX795F512L_BGA s19 3B
U U 6 UDA1380 Audio Codec s18, s19, s20 4D
U U 7 TPS2112 Auto Switching Power Mux s22 4A
U U 11 MCP2200 Microcontroller s22 4B
U U 14 MAX5008 USB Charge Pump s20 3A
U U 21 PCA9517 I2C Repeater s14 1D
U U 200 TCA6424 I/O Expander s21 5X
U U 201 VN750 Hi gh Side Driver s24 5V
U U 202 MC33897 Si ngle Wire Can Transceiver s6 5X
U U 207 TPS3808 Voltage Supervisor s4 1T
U U 208 TPS3808 Voltage Supervisor s4 1U
U U 210 MAX6817 Dual Switch Debouncer s20 2Z
Y Y 1 12 MHz XTAL - CommBridge Oscillator s22 4B
Y Y 2 32.768 KHz Crystal Tuning Fork - EHC Secondary Oscillator s18 3B
Y Y 3 18.4320 MHz ABM8 Crystal - INIC Oscillator s7 3E
Y Y 201 12 MHz XTAL - EHC Primary Oscillator s18 3Y
TABLE C-2: REFERENCE DESIGNATORS (CONTINUED)
Type Ref Des Description Sheet # *Board
Location †
* Sheet # correspond to board schematic sheet files shown in Figure E-1 through Figure E-25.
† The Board Location coordinates refer to silkscreen Figure D-1 and Figure D-2.
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APPENDIX D: DB81092PCB5.A SILK SCREENS WITH COMPONENT GRID
PLACEMENTS
FIGURE D-1: SILKSCREEN TOP
Top Silk
19.69cm
AEBDC
3
4
5
F G
2
1
12.70 cm
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FIGURE D-2: SILKSCREEN BOTTOM
Bottom Silk
19.69cm
TXUWV
3
4
5
Y Z
2
1
12.70 cm
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FIGURE D-3: LAYER 1
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FIGURE D-4: LAYER 2
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FIGURE D-5: LAYER 3
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FIGURE D-6: LAYER 4
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FIGURE D-7: LAYER 5
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FIGURE D-8: LAYER 6
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FIGURE D-9: LAYER 7
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FIGURE D-10: LAYER 8
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APPENDIX E: DB81092PCB5.A SCHEMATIC LAYOUT FILES
FIGURE E-1: SHEET 1 - PWR_MAIN
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FIGURE E-2: SHEET 2 - PWR_REGULATORS
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FIGURE E-3: SHEET 3 - PWR_MGMT
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FIGURE E-4: SHEET 4 - BOARD_RESET
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FIGURE E-5: SHEET 5 - MOST_NTWK
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FIGURE E-6: SHEET 6 - CAN_LIN/ECL
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FIGURE E-7: SHEET 7 - INIC_PWR_XTAL
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FIGURE E-8: SHEET 8 - INIC_MSC
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FIGURE E-9: SHEET 9 - IOC_PWR_XTAL
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FIGURE E-10: SHEET 10 - IOC_TSI_SPI_SP
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FIGURE E-11: SHEET 11 - IOC_HBI_MISC
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FIGURE E-12: SHEET 12 - MLB_3PIN
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FIGURE E-13: SHEET 13 - MOST_CTRL_PORT
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FIGURE E-14: SHEET 14 - MOST_DEBUG_PORT
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FIGURE E-15: SHEET 15 - DAUGHTER_BOARD
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FIGURE E-16: SHEET 16 - AUDIO_CODEC
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FIGURE E-17: SHEET 17 - I2S_LFST_CONFIG
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FIGURE E-18: SHEET 18 - EHC_PWR_XTAL
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FIGURE E-19: SHEET 19 - EHC_PORTS
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FIGURE E-20: SHEET 20 - EHC_USB
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FIGURE E-21: SHEET 21 - I/O_EXPANDER
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FIGURE E-22: SHEET 22 - COMM_BRIDGE
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FIGURE E-23: SHEET 23 - COMM_BRIDGE_I/O
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FIGURE E-24: SHEET 24 - CABLE_HARNESS
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FIGURE E-25: SHEET 25 - BOARD_MISO
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APPENDIX F: REFERENCES
Documents listed below and referenced within this publication are current as of the release of this publication and may
have been reissued with more current information. To obtain the latest releases of Microchip documentation please visit
the Microchip web si te. Plea se note , some Mi croc hip do cumentation may require approval. Contact information can be
found at www.microchip.com.
All non-Microchip documentation should be retrieved from the applicable website locations listed below . Microchip is not
responsible for the update, maintenance or distribution of non-Microchip documentation.
Because the Internet is a constantly changing environment, all Internet links mentioned below and throughout this doc-
ument are subject to change without notice.
[1] OS81092 MOST50 INIC Hardware Data Sheet
DS81092AP3: Apr. 2011. Microchip. www.microchip.com.
[2] OS85650/2 I/O Companion Data Sheet
DS85650AP6: Apr. 2011. Microchip. www.microchip.com.
[3] MPM85000 Automotive Power Management Device Data Sheet
DS85000AP2: Nov. 2009. Microchip. www.microchip.com.
[4] MOST ToGo Basic Application Code Firmware Manual
Microchip. www.microchip.com.
[5] MOST Specification 3.0
Rev. 3.0 E2: Jul. 2010. MOST Cooperation. www.mostcooperation.com.
[6] MOST Electrical Control Line Specification
Revision 1.1.1. July 2011. MOST Coo peration. www.mostcooperation.com.
[7] OS81092 MOST50 INIC API User’s Manual
Rev 1.3.0-1: Dec. 2010. Microchip. www.microchip.com.
[8] MOST INIC Hardware Concepts Technical Bulletin
TB0520AN2: Nov. 2011 . Microchip. www.microchip.com.
[9] OS85620 V ideo I/O Companion Data Sheet
DS85620AP1: Aug. 2011 . Microchip . www.microchip.com.
[10] OS81092 INIC Flash Programming Guide
V01_00_XX-2: Jul. 2010. Microchip. www.microchip.com.
[11] INIC Explorer Interface Tool Specification
V1.6.x-1: Dec. 2009. Microchip. www.microchip.com.
[12] MediaLB Specification
TB0400AN4V2: Dec. 2010. Microchip. www.microchip.com.
[13] MediaLB Monitor Adapter User’s Manua l
V2.0.x-2: May 2005. Microchip. www.microchip.com.
[14] OS62420 MediaLB Device Interface Macro Data Sheet
DS60001215A: Jul. 2013. Microc hip. www.microchip.com.
[15] DTCP Specification
Available under license from the DTLA. www.dtcp.com.
[16] Microchip IOC Configuration Software
Microchip. www.microchip.com.
OS81092 Evaluation Board User’s Guide
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[17] PIC32MX5XX/6XX/7XX 32-Bit Microcontrollers Family Data Sheet
DS60001156H: Mar. 2013. Microchi p. www.microchip.com.
[18] AN1388 PIC32 Bootloader Application Note
DS01388B: Jan.2012. Microchip. www.microchip.com.
[19] PIC32UBL Flasher Software
Jul. 2009. Microchip. www.microchip.com.
[20] Port Message Viewer v6+ User’s Guide
DS60001219A. Jul. 2013. Microc hip. www.microchip.com.
[21] I2C-Bus Specification
Rev. 03: Jun. 2007. NXP (formerly a divi si on of Philips). www.nxp.com.
[22] MC33897 Single Wire CAN Transceiver
MC33897, Rev. 18.0: Apr. 2012. Freescale Semiconductor. www.freescale.com.
[23] SAE J2411 Single Wire Can Network
J2411: Feb. 2000 . SAE International. www.sae.org.
[24] GMW3089 Single Wire CAN Physical and Data Link Layers
V2.3. General Motors Corporation . www.gm.com.
[25] Local Interconnect Network (LIN) Specification
Revision 2.2: LIN Consortium. www.lin-subbus.de.
[26] PIC 32 Family Reference Manual
Microchip. www.microchip.com.
[27] UDA1380 Stereo Audio CODEC Data Sheet
Apr. 2004. NXP. www.ics.nxp.com.
[28] MCP2200 USB 2.0 to UART Protocol Converter with GPIO Da ta Sheet
DS22228B: Mar. 2011. Microchip. www.microchip.com.
[29] ISO 7637-2: Road vehicles - Electrical disturbances from co nd uc tio n an d co up ling
Part 2: Electrical transient conduction along supply lines only. ISO 7637-2, May 2004,
International Organization for Standardization. www.iso.org.
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APPENDIX G: USER’S GUIDE REVISION HISTORY
G.1 Current Document Revision
Revision A (DS60001239A – 10/2013),
• Initial release of the OS81092 Evaluation Board User’s Guide (DB81092PCB5.A)
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APPENDIX H: LIST OF FIGURES
DB81092PCB5.A Front Photo.....................................................................5
DB81092PCB5.A Back Photo.....................................................................6
FIGURE 1-1: Hardware Block Diagram ............................................................................7
FIGURE 1-2: Standard Application Diagram.....................................................................9
FIGURE 1-3: Expanded Application Diagram.................................................................10
FIGURE 3-1: Power Distribution.....................................................................................12
FIGURE 4-1: Board Reset Architecture..........................................................................14
FIGURE 6-1: OS81092 INIC...........................................................................................18
FIGURE 6-2: ePHY Front End Circuitry..........................................................................19
FIGURE 6-3: Board Harness Connector.........................................................................20
FIGURE 6-4: Power Management Interface...................................................................21
FIGURE 6-5: INIC Streaming Port Connection Options..................................................21
FIGURE 6-6: MediaLB 3-pin Connection Diagram .........................................................22
FIGURE 7-1: IOC Streaming Port Connection Options ..................................................24
FIGURE 7-2: IOC TSI Port Header Connections............................................................25
FIGURE 8-1: EHC Debug and JTAG Headers ...............................................................27
FIGURE 8-2: Port Message Viewer Interpreted Output..................................................28
FIGURE 8-3: MOST Control I2C Bus. ... ... ................ .... ................ ................ ... ................31
FIGURE 8-4: Peripheral I2C Bus.....................................................................................31
FIGURE 8-5: CAN Interface............................................................................................32
FIGURE 8-6: UART Port 4 Interface...............................................................................33
FIGURE 8-7: USB Interface............................................................................................34
FIGURE 8-8: EHC SPI Port 1 Connections ....................................................................34
FIGURE 9-1: LFST Typical Application...........................................................................41
FIGURE 9-2: Audio and LFST Connection Options........................................................41
FIGURE 10-1: Power Slave - Wakeup due to ECL Activity. .............................................44
FIGURE 10-2: Power Slave - Wake due to Network Activity............................................45
FIGURE 10-3: Power Slave - Power Down Sequence .....................................................46
FIGURE 11-1: CommBridge Overview .............................................................................47
FIGURE B-1: Silkscreen Grid Example with Board Dimensions.....................................50
FIGURE D-1: Silkscreen Top...........................................................................................56
FIGURE D-2: Silkscreen Bottom .....................................................................................57
FIGURE D-3: Layer 1 ......................................................................................................58
FIGURE D-4: Layer 2 ......................................................................................................59
FIGURE D-5: Layer 3 ......................................................................................................60
FIGURE D-6: Layer 4 ......................................................................................................61
FIGURE D-7: Layer 5 ......................................................................................................62
FIGURE D-8: Layer 6 ......................................................................................................63
FIGURE D-9: Layer 7 ......................................................................................................64
FIGURE D-10: Layer 8 ......................................................................................................65
FIGURE E-1: Sheet 1 - PWR_MAIN ...............................................................................66
FIGURE E-2: Sheet 2 - PWR_REGULATORS................................................................67
FIGURE E-3: Sheet 3 - PWR_MGMT .............................................................................68
FIGURE E-4: Sheet 4 - BOARD_RESET........................................................................69
FIGURE E-5: Sheet 5 - MOST_NTWK............................................................................70
FIGURE E-6: Sheet 6 - CAN_LIN/ECL............................................................................71
FIGURE E-7: Sheet 7 - INIC_PWR_XTAL......................................................................72
FIGURE E-8: Sheet 8 - INIC_MSC..................................................................................73
FIGURE E-9: Sheet 9 - IOC_PWR_XTAL.......................................................................74
FIGURE E-10: Sheet 10 - IOC_TSI_SPI_SP....................................................................75
FIGURE E-11: Sheet 11 - IOC_HBI_MISC .......................................................................76
FIGURE E-12: Sheet 12 - MLB_3PIN ...............................................................................77
FIGURE E-13: Sheet 13 - MOST_CTRL_PORT...............................................................78
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FIGURE E-14: Sheet 14 - MOST_DEBUG_PORT............................................................79
FIGURE E-15: Sheet 15 - DAUGHTER_BOARD..............................................................80
FIGURE E-16: Sheet 16 - AUDIO_CODEC ......................................................................81
FIGURE E-17: Sheet 17 - I2S_LFST_CONFIG.................................................................82
FIGURE E-18: Sheet 18 - EHC_PWR_XTAL....................................................................83
FIGURE E-19: Sheet 19 - EHC_PORTS...........................................................................84
FIGURE E-20: Sheet 20 - EHC_USB................................................................................85
FIGURE E-21: Sheet 21 - i/O_EXPANDER ......................................................................86
FIGURE E-22: Sheet 22 - COMM_BRIDGE......................................................................87
FIGURE E-23: Sheet 23 - COMM_BRIDGE_I/O...............................................................88
FIGURE E-24: Sheet 24 - CABLE_HARNESS..................................................................89
FIGURE E-25: Sheet 25 - BOARD_MISO.........................................................................90
OS81092 Evaluation Board User’s Guide
DS60001239A-page 96 2013 Microchip Technology Inc.
NOTES:
2013 Microchip Technology Inc. DS60001239A-page 97
OS81092 Evaluation Board User’s Guide
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to cus-
tomers. Accessible by using your favorite Internet
browser, the web site contains the following informa-
tion:
•Product Support – Data sheets and errata, appli-
cation notes and sample programs, desi gn
resources, user’s guides and hardware support
documents, latest software releases and archived
software
•General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip co nsultant
program member listin g
•Business of Micr oc hip – Product selector and
ordering guides, latest Microchip press relea se s ,
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chip sales offices, distributors and factory repre-
sentatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
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will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a spec-
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To register, access the Microchip web site at
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tomer Change Notification” and follow the registration
instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
Customers should contact their distributor, representa-
tive or Field Application Engineer (FAE) for support.
Local sales offices are also available to help custom-
ers. A listing of sales offices and locations is included in
the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
DS60001239A-page 98 2013 Microchip Technology Inc.
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Worldwide Sales and Service
10/28/13
