SY58051AU
Ultra-Precision CML AnyGate®
with Internal Input and Output Termination
Revision 1.0
AnyGate and Precision Edge are registered trademarks of Micrel, Inc.
San --http://www.micrel.com
January 28, 2014
Revision 1.0
hbwhelp@micrel.com or (408) 955-1690
General Description
The SY58051AU is an ultra-fast, low jitter universal logic
gate with a guaranteed maximum data or clock throughput
of 10.7Gbps or 8GHz, respectively. This AnyGate®
differential logic device will produce many logic functions
of two Boolean variables, such as AND, NAND, OR, NOR,
DELAY, or NEGATION.
The SY58051AU differential inputs include a unique
internal termination design that allows access to the
termination network throughout a VT pin. This feature
allows the device to easily interface to different logic
standards, both AC- and DC-coupled, without external
resistor-bias and termination networks. The result is a
clean, stub-free, low-jitter interface solution. The
differential CML output is optimized for environments with
internal 50Ω source termination and a 400mV output
swing.
The SY58051AU operates from a 2.5V or 3.3V supply and
is guaranteed over the full industrial temperature range of
–40°C to +85°C. The SY58051AU is part of Micrel’s
Precision Edge® product family.
Datasheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
Functional Block Diagram
Precision Edge®
Features
Three matched-delay input pairs provide any logic
function: AND, NAND, OR, NOR
Guaranteed AC performance over temperature and
voltage:
DC to >10.7Gbps data rate throughput
DC to >8GHz clock fMAX
<160ps Any In-to-Out tpd
20ps typical tr/tf
Ultra-low jitter design:
0.2psRMS typical random jitter (data)
2psPP typical deterministic jitter (data)
5psPP typical total jitter (clock)
46fsRMS typical additive phase jitter (clock)
Unique input termination and VT pin accepts AC- and
DC-coupled inputs (CML, PECL)
Internal 50Ω output source termination
Typical 400mV CML output swing (RL = 50Ω)
Internal 50Ω input termination
Power supply 2.5V ±5% or 3.3V ±10%
–40°C to +85°C industrial temperature range
Available in a 16-pin 3mm × 3mm QFN package
Applications
Data communciation systems
OC-192, OC-192+FEC data-to-clock
All SONETOC-3 – OC-768 applications
Fibre Channel
Gigabit Ethernet
ATE
Test and measurement
Micrel, Inc.
SY58051AU
January 28, 2014
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Ordering Information
Part Number
Package Type
Temperature Range
Package Marking
Lead Finish
SY58051AUMG(1)
Pb-Free QFN-16
Industrial
051A with
Pb-Free bar-line indicator
NiPdAu Pb-Free
SY58051AUMG TR(1, 2)
Pb-Free QFN-16
Industrial
051A with
Pb-Free bar-line indicator
NiPdAu Pb-Free
Notes:
1. Pb-Free package recommended for new designs.
2. Tape and Reel
Pin Configuration
16-Pin QFN
Pin Description
Pin Number
Pin Name
Pin Function
1
VTA
Input termination center tap: Each of the two inputs (A, /A) terminates to this pin through a 50Ω
resistor. The VTA pin provides a center-tap to a termination network for maximum interface
flexibility. See the Input Interface Applications section for more details.
15, 16
2, 3
A, /A
B, /B
Differential input: These input pairs are the two data inputs to the device. Each pin of a pair (A, /A)
and (B, /B) internally terminates to the VTA or VTB pin to 50Ω. Note that these inputs will default
to an indeterminate state if left open. See the Input Interface Applications section for more
details.
4
VTB
Input termination center tap: Each of the two inputs (B, /B) terminates to this pin through a 50Ω
resistor. The VTB pin provides a center-tap to a termination network for maximum interface
flexibility. See the Input Interface Applications section for more details.
5, 6
S, /S
Differential input: This input pair is the select input to the device. Each pin of this pair internally
terminates to the VTS pin to 50Ω. Note that this input will default to an indeterminate state if left
open. See the Input Interface Applications section for more details.
7
VTS
Input termination center tap: Each of the two inputs (S, /S) terminates to this pin. The VTS pin
provides a center-tap to a termination network for maximum interface flexibility.
8, 13
VCC
Positive power supply. Bypass with 0.1µF║0.01µF low ESR capacitors.
12, 9
Q, /Q
Differential output: This CML output pair is the output of the device. It is a logic function of the A,
B, and S inputs. See the Truth Tables for details.
10, 11, 14
GND
Ground. Exposed pad must be connected to the same potential as GND pin.
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SY58051AU
January 28, 2014
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Truth Tables
A
/A
B
/B
S
/S
Q
/Q
0
1
X
X
0
1
0
1
1
0
X
X
0
1
1
0
X
X
0
1
1
0
0
1
X
X
1
0
1
0
1
0
AND/NAND
A
B
S
Q
( )
/Q
L
L
L
L
L
H
L
H
L
L
H
H
L
L
L
H
H
H
H
L
OR/NOR
A
B
S
+
Q
βα
/Q
L
H
L
H
H
H
H
H
L
L
H
H
L
H
H
H
H
L
L
L
DELAY/NEGATION
A
B
S
Q
/Q
α
L
H
L
L
L
H
H
L
DELAY/NEGATION
A
B
S
Q
β
/Q
L
H
H
H
L
H
H
L
2:1 MUX
S
Q
/Q
L
H
A
B
B
A
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SY58051AU
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Absolute Maximum Ratings(3)
Supply Voltage (VCC) .................................... –0.5V to +4.0V
Input Voltage (VIN) ............................................ –0.5V to VCC
CML Output Voltage (VOUT) ...........VCC – 1.0V to VCC + 0.5V
Termination Current(5)
Source or Sink Current on VTA, VTB, VTS ................... ±60mA
Input Current
Source or Sink Current on A, /A, B, /B, S, /S ............ ±30mA
Lead Temperature (soldering, 20s) ............................ 260°C
Storage Temperature (Ts) ......................... –65°C to +150°C
Operating Ratings(4)
Supply Voltage (VCC) ............................ +2.375V to +2.625V
....................................................... or +2.97V to +3.63V
Ambient Temperature (TA) .......................... –40°C to +85°C
Junction Thermal Resistance(6)
QFN (JA) Still-Air ............................................... 61°C/W
QFN (ψJB) .......................................................... 38°C/W
DC Electrical Characteristics(7, 8)
TA = –40°C to +85°C.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
VCC
Power supply
2.375
2.97
2.5
3.3
2.625
3.63
V
ICC
Power supply current
With load for either 2.5V or 3.3V supply
42
60
mA
RDIFF_IN
Differential input resistance
(A-to-/A), (B-to-/B), or (S-to-/S)
90
100
110
Ω
RIN
Input resistance
(A-to-VTA, B-to-VTB, or S-to-VTS)
45
50
55
Ω
VIH
Input HIGH voltage
(A, /A), (B, /B), or (S, /S)
Note 9
1.2
VCC
V
VIL
Input LOW voltage
(A, /A), (B, /B), or (S, /S)
Note 9
0
VIH +
0.1
mV
VIN
Input voltage swing
(A, /A), (B, /B), or (S, /S)
Note 9
See Figure 3
100
mV
VDIFF_IN
Differential input voltage swing
(A, /A), (B, /B), or (S, /S)
Note 9
See Figure 4
200
mV
IIN
Input current
(A, /A), (B, /B), or (S, /S)
Note 9
21
mA
Notes:
3. Exceeding the absolute maximum ratings may damage the device.
4. The device is not guaranteed to function outside its operating ratings.
5. Due to the limited drive capability use for input of the same package only.
6. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. ΨJB uses 4-layer
JA in still-air, unless otherwise stated.
7. Specification for packaged product only.
8. The circuit is designed to meet the DC specifications shown in the table above after thermal equilibrium has been established.
9. Due to the internal termination (see “Input Structures” section), the input current depends upon the applied voltages at A, /A, and VTA inputs, the B,
/B, and VTB inputs, or the S, /S, and VTS inputs. Do not apply a combination of voltages that causes the input current to exceed the maximum limit.
Micrel, Inc.
SY58051AU
January 28, 2014
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CML Electrical Characteristics(10)
VCC = 2.5V ±5% or 3.3V ±10%; RL =100 across output pair or equivalent; TA = –40°C to +85°C.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
VOH
Output HIGH voltage
(Q, /Q)
RL = 50Ω to VCC
VCC-
0.020
VCC
V
VOUT
Output voltage swing
(Q, /Q)
See Figure 3
325
400
mV
VDIFF_OUT
Differential output voltage swing
(Q, /Q)
See Figure 4
650
800
mV
ROUT
Output source impedance
(Q, /Q)
45
50
55
Ω
AC Electrical Characteristics(10, 11)
VCC = 2.5V ±5% or 3.3V ±10%; RL =100 across output pair or equivalent; TA = –40°C to +85°C.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
fMAX
Maximum operating frequency
Clock
NRZ data
8
10.7
GHz
Gbps
tpd
Propagation delay any input
(A, B, S)-to-Q
70
160
ps
tSKEW
Part-to-part skew
Note 12
100
ps
tJITTER
Data
Random jitter (RJ)
Note 13
0.2
1
psRMS
Deterministic jitter (DJ)
Note 14
2
5
psPP
Clock
Cycle-to-cycle jitter (RJ)
Note 15
0.5
1
psRMS
Total jitter (TJ)
Note 16
5
10
psPP
Additive phase jitter
622MHz input integrated over 12kHz – 20MHz
46
fsRMS
tr/tf
Output rise/fall times
(20% to 80%)
At full output swing
20
50
ps
Notes:
10. Specification for packaged product only.
11. Measured with 100mV input swing. See the Timing Diagrams section for definition of parameters. High-frequency AC parameters are guaranteed by
design and characterization.
12. Skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs.
13. Random jitter is measured with a K28.7 comma detect character pattern, measured at 2.5Gbps/3.2Gbps.
14. Deterministic jitter is measured at 2.5Gbps/3.2Gbps with both K28.5 and 223–1 PRBS pattern.
15. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, Tn – Tn–1 where Tn is the time between rising edges of the output
signal.
16. Total jitter definition: with an ideal clock input of frequency ≤fMAX, no more than one output edge in 1012 output edges will deviate by more than the
specified peak-to-peak jitter value.
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SY58051AU
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Definition of Single-Ended and Differential Swings
Figure 3. Single-Ended Swing
Figure 4. Differential Swing
Typical Operating Characteristics
50
60
70
80
90
100
110
120
130
140
150
160
170
180
-50 -25 0 25 50 75 100
PROPAGATION DELAY (ps)
TEMPERATURE (C)
IN-to-Q Propagation Delay
vs. Temperature
VCC = 3.3V
VIN = 400mVP
Freq. = 2GHz
0
50
100
150
200
250
300
350
400
450
0246810
Q AMPLITUDE (mV)
FREQUENCY (GHz)
Single-Ended Output Swing
vs. Frequency
80
85
90
95
100
105
110
115
120
125
130
135
140
0 100 200 300 400 500 600
PROPAGATION DELAY (ps)
INPUT SWING (mVP)
IN-to-Q Propagation Delay vs.
Single-Ended Input Swing
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SY58051AU
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Phase Noise Plot
VCC = 3.0V, CML Input, Temperature = 25°C
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
0.001 0.01 0.1 1 10 100
Phase Noise (dBc/Hz)
Frequency (MHz)
Phase Noise at 622MHz over 12kHz to 20MHz
Additive RMS Phase Jitter: 46fsRMS
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SY58051AU
January 28, 2014
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Input Interface Applications
Figure 5. Static Input Level
Figure 6. LVDS Interface
(DC-Coupled)
Figure 7. LVDS Interface
(AC-Coupled)
Note: Be certain that the LVDS driver can be AC-coupled.
Figure 8. CML Interface
(DC-Coupled)
Figure 9. CML Interface
(AC-Coupled)
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SY58051AU
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Input Interface Applications (Continued)
Figure 10. PECL Interface
(DC-Coupled)
Figure 11. PECL Interface
(AC-Coupled)
Related Product and Support Docume ntation
Part Number
Function
Datasheet Link
SY58016L
3.3V 10Gbps Differential CML
Line Driver/Receiver with
Internal Termination
http://www.micrel.com/_PDF/HBW/sy58016l.pdf
SY58052AU
10.7Gbps Clock/Data Retimer
with 50Ώ Input Termination
http://www.micrel.com/_PDF/HBW/SY58052AU.pdf
TCG Solutions
New Products and
Applications
http://www.micrel.com/index.php/en/products/clock-
timing.html
Micrel, Inc.
SY58051AU
January 28, 2014
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