Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics R DS680 (v2.0) April 12, 2010 Product Specification Virtex-4QV FPGA Electrical Characteristics Space-grade, radiation-tolerant Virtex(R)-4QV FPGAs are available in the -10 speed grade and qualified for military (Tj = -55 C to +125 C) operational temperatures. Virtex-4QV FPGA DC and AC characteristics are specified for military temperatures only. Except the operating temperature range or unless otherwise noted, all the DC and AC electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -10 speed grade military device are the same as for a -10 speed grade industrial device). All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters included are common to popular designs and typical applications. This Virtex-4QV FPGA data sheet is part of an overall set of documentation on the Virtex-4 family of FPGAs available on the Xilinx website: * DS653, Space-Grade Virtex-4QV Family Overview * UG070, Virtex-4 FPGA User Guide * UG071, Virtex-4 FPGA Configuration Guide * UG073, XtremeDSP for Virtex-4 FPGAs * UG496, Virtex-4QV FPGA Ceramic Packaging and Pinout Specifications * UG072, Virtex-4 FPGA PCB Designer's Guide Virtex-4QV FPGA DC Characteristics Table 1: Absolute Maximum Ratings Symbol Description VCCINT Internal supply voltage relative to GND VCCAUX VCCO Units -0.5 to 1.32 V Auxiliary supply voltage relative to GND -0.5 to 3.0 V Output drivers supply voltage relative to GND -0.5 to 3.75 V VBATT Key memory battery backup supply -0.5 to 4.05 V VREF Input reference voltage -0.3 to 3.75 V -0.75 to 4.05 V -0.85 to 4.3 V -0.75 to VCCO +0.5 V I/O input voltage relative to GND (all user and dedicated I/Os) VIN I/O input voltage relative to GND(3) (restricted to maximum of 100 user I/Os) (4) 2.5V or below I/O input voltage relative to GND (user and dedicated I/Os) Voltage applied to 3-state 3.3V output (3) (all user and dedicated I/Os) Voltage applied to 3-state 3.3V output (3) (restricted to maximum of 100 user I/Os) (4) VTS 2.5V or below I/O input voltage relative to GND (user and dedicated I/Os) TSTG Storage temperature (ambient) TSOL Maximum soldering temperature(2) Maximum junction TJ temperature (2) -0.75 to 4.05 V -0.85 to 4.3 V -0.75 to VCCO +0.5 V -65 to 150 C +220 C +125 C Notes: 1. 2. 3. 4. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability. For soldering guidelines and thermal considerations, see the Virtex-4QV FPGA Ceramic Packaging and Pinout Specifications on the Xilinx website. For 3.3V I/O operation, refer to the Virtex-4 FPGA User Guide, Chapter 6, 3.3V I/O Design Guidelines, Table 6-38. For more flexibility in specific designs, a maximum of 100 user I/Os can be stressed beyond the normal spec for no more than 20% of a data period. There are no bank restrictions. (c) Copyright 2008-2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PowerPC is a trademark of IBM Corp. and is used under license. All other trademarks are the property of their respective owners. DS680 (v2.0) April 12, 2010 Product Specification www.xilinx.com 1 R Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics Table 2: Recommended Operating Conditions Symbol Description Min Max Units VCCINT Internal supply voltage relative to GND 1.14 1.26 V VCCAUX Auxiliary supply voltage relative to GND 2.375 2.625 V 1.14 3.45 V 3.3V supply voltage relative to GND GND - 0.20 3.45 V 2.5V and below supply voltage relative to GND GND - 0.20 VCCO + 0.2 V 1.0 3.6 V VCCO(1,2,3,4,5)) Supply voltage relative to GND VIN VBATT(2) Battery voltage relative to GND Notes: 1. 2. 3. 4. 5. Configuration data is retained even if VCCO drops to 0V. VBATT is required only when using bitstream encryption. If battery is not used, connect VBATT to either ground or VCCAUX. For 3.3V I/O operation, refer to the Virtex-4 FPGA User Guide. Includes VCCO of 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V. The configuration output supply voltage VCC_CONFIG is also known as VCCO_0. Table 3: DC Characteristics Over Recommended Operating Conditions Symbol Description Min Typ Max Units VDRINT Data retention VCCINT voltage (below which configuration data might be lost) 0.9 V VDRI Data retention VCCAUX voltage (below which configuration data might be lost) 2.0 V IREF VREF current per pin 10 A IL Input or output leakage current per pin (sample-tested) 10 A CIN Input capacitance (sample-tested) 10 pF IRPU(1) IRPD (1) Pad pull-up (when selected) @ VIN = 0V, VCCO = 3.3V 5 200 A Pad pull-up (when selected) @ VIN = 0V, VCCO = 3.0V 5 125 A Pad pull-up (when selected) @ VIN = 0V, VCCO = 2.5V 5 120 A Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.8V 5 60 A Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.5V 5 40 A Pad pull-down (when selected) @ VIN = VCCO 5 IBATT(1) Battery supply current PCPU 100 A 75 nA Power dissipation of PowerPC(R) 405 processor block 0.45 mW/ MHz n Temperature diode ideality factor 1.02 n r Series resistance 2 Notes: 1. Typical values are specified at nominal voltage, 25C. DS680 (v2.0) April 12, 2010 Product Specification www.xilinx.com 2 R Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics Table 4: Quiescent Supply Current Symbol ICCINTQ ICCOQ ICCAUXQ Device Typ (1) Max Units XQR4VSX55 488 Note (4) mA XQR4VFX60 365 Note (4) mA XQR4VFX140 796 Note (4) mA XQR4VLX200 880 Note (4) mA XQR4VSX55 3.00 Note (4) mA XQR4VFX60 3.00 Note (4) mA XQR4VFX140 5.00 Note (4) mA XQR4VLX200 5.00 Note (4) mA XQR4VSX55 137 Note (4) mA XQR4VFX60 120 Note (4) mA XQR4VFX140 215 Note (4) mA XQR4VLX200 225 Note (4) mA Description Quiescent VCCINT supply current Quiescent VCCO supply current Quiescent VCCAUX supply current Notes: 1. 2. 3. 4. Typical values are specified at nominal voltage, 25C. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and floating. If DCI or differential signaling is used, more accurate quiescent current estimates can be obtained by using the Power Estimator or XPOWER tool. Use the XPowerTM Estimator (XPE) tool to calculate maximum static power for specific process, voltage, and temperature conditions. Power-On Power Supply Requirements Xilinx(R) FPGAs require a certain amount of supply current during power-on to ensure proper device initialization. The actual current consumed depends on the power-on ramp rate of the power supply. VCCO. Xilinx does not specify the current for other power-on sequences. Table 5 shows the maximum current required by Virtex-4 devices for proper power-on and configuration. The power supplies can be turned on in any sequence, though the specifications shown in Table 5 are for the recommended power-on sequence of VCCINT, VCCAUX, Once initialized and configured, use the XPOWER tool to estimate current drain on these supplies. Table 5: Maximum Power-On Current for Virtex-4QV Devices Device ICCINT ICCAUX ICCO Units Typ (1) Max(2) Typ (1) Max(2) Typ (1) Max(2) XQR4VSX55 520 5355 225 930 150 450 mA XQR4VFX60 410 4680 220 1050 150 435 mA XQR4VFX140 860 9540 450 1313 250 563 mA XQR4VLX200 1020 8820 500 1313 250 600 mA Ramp Time Units Notes: 1. 2. Typical values are specified at nominal voltage, 25C. Maximum values are specified under worst-case process, voltage, and military temperature conditions. Table 6: Power Supply Ramp Time Symbol Description VCCINT Internal supply voltage relative to GND 0.20 to 50.0 ms VCCO Output drivers supply voltage relative to GND 0.20 to 50.0 ms VCCAUX Auxiliary supply voltage relative to GND 0.20 to 50.0 ms DS680 (v2.0) April 12, 2010 Product Specification www.xilinx.com 3 R Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics SelectIO DC Input and Output Levels Values for VIL and VIH are recommended input voltages. Unless otherwise noted, values for IOL and IOH are guaranteed over the recommended operating conditions at the VOL and VOH test points. Only selected standards are tested. These are chosen to ensure that all standards meet their specifications. The selected standards are tested at a minimum VCCO with the respective VOL and VOH voltage levels shown. Other standards are sample tested. Table 7: Select I/O DC Input and Output Levels IOSTANDARD Attribute VIH VIL VOL VOH IOL IOH V, Min V, Max V, Min V, Max V, Max V, Min mA mA LVTTL -0.2 0.8 2.0 3.45 0.4 2.4 Note(3) Note(3) LVCMOS33 -0.2 0.8 2.0 3.45 0.4 VCCO - 0.4 Note(3) Note(6) LVCMOS25 -0.3 0.7 1.7 VCCO + 0.3 0.4 VCCO - 0.4 Note(3) Note(3) LVCMOS18 -0.3 35% VCCO 65% VCCO VCCO + 0.3 0.4 VCCO - 0.45 Note(4) Note(4) LVCMOS15 -0.3 35% VCCO 65% VCCO VCCO + 0.3 0.4 VCCO - 0.45 Note(4) Note(6) PCI33_3(5) -0.2 30% VCCO 50% VCCO VCCO 10% VCCO 90% VCCO 1.5 -0.5 PCI66_3(5) -0.2 30% VCCO 50% VCCO VCCO 10% VCCO 90% VCCO 1.5 -0.5 PCI-X(5) -0.2 35% VCCO 50% VCCO VCCO 10% VCCO 90% VCCO 1.5 -0.5 GTLP -0.3 VREF - 0.1 VREF + 0.1 - 0.6 - 36 - GTL -0.3 VREF - 0.05 VREF + 0.05 - 0.4 - 32 - HSTL I(2) -0.3 VREF - 0.1 VREF + 0.1 VCCO + 0.3 0.4 VCCO - 0.4 8 -8 HSTL II(2) -0.3 VREF - 0.1 VREF + 0.1 VCCO + 0.3 0.4 VCCO - 0.4 16 -16 HSTL III(2) -0.3 VREF - 0.1 VREF + 0.1 VCCO + 0.3 0.4 VCCO - 0.4 24 -8 HSTL IV(2) -0.3 VREF - 0.1 VREF + 0.1 VCCO + 0.3 0.4 VCCO - 0.4 48 -8 -0.3 50% VCCO - 0.1 50% VCCO + 0.1 VCCO + 0.3 0.4 VCCO - 0.4 - - SSTL2 I -0.3 VREF - 0.15 VREF + 0.15 VCCO + 0.3 VTT - 0.61 VTT + 0.61 8.1 -8.1 SSTL2 II -0.3 VREF - 0.15 VREF + 0.15 VCCO + 0.3 VTT - 0.81 VTT + 0.81 16.2 -16.2 DIFF SSTL2 II -0.3 50% VCCO - 0.15 50% VCCO + 0.15 VCCO + 0.3 0.5 VCCO - 0.5 - - SSTL18 I -0.3 VREF - 0.125 VREF + 0.125 VCCO + 0.3 VTT - 0.47 VTT + 0.47 6.7 -6.7 SSTL18 II -0.3 VREF - 0.125 VREF + 0.125 VCCO + 0.3 VTT - 0.60 VTT + 0.60 13.4 -13.4 DIFF SSTL18 II -0.3 VCCO + 0.3 0.4 VCCO - 0.4 - - DIFF HSTL II(2) 50% VCCO - 0.125 50% VCCO + 0.125 Notes: 1. 2. 3. 4. 5. 6. Tested according to relevant specifications. Applies to both 1.5V and 1.8V HSTL. Using drive strengths of 2, 4, 6, 8, 12, 16, or 24 mA. Using drive strengths of 2, 4, 6, 8, 12, or 16 mA. For more information on PCI33_3, PCI66_3, and PCIX, refer to the Virtex-4 FPGA User Guide, SelectIO Resources, Chapter 6. LVCMOS15 4 mA, LVCMOS33 6 mA, LVCMOS33 8 mA have reduced drive strength (IOH) by 20%. DS680 (v2.0) April 12, 2010 Product Specification www.xilinx.com 4 R Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics LDT DC Specifications (LDT_25) Table 8: LDT DC Specifications Symbol VCCO VOD DC Parameter Conditions Supply Voltage Differential Output Voltage(1,2) RT = 100 across Q and Q signals VOD Change in VOD Magnitude VOCM Output Common Mode Voltage VOCM Min Typ Max Units 2.38 2.5 2.63 V 495 600 750 mV 15 mV 600 715 mV 15 mV 600 1000 mV 15 mV 780 mV 15 mV Max Units -15 RT = 100 across Q and Q signals 495 Change in VOCM Magnitude -15 VID Input Differential Voltage 200 VID Change in VID Magnitude -15 VICM Input Common Mode Voltage 440 Change in VICM Magnitude -15 VICM 600 Notes: 1. 2. Recommended input maximum voltage not to exceed VCC0 + 0.2V. Recommended input minimum voltage not to go below -0.5V. LVDS DC Specifications (LVDS_25) Table 9: LVDS DC Specifications Symbol VCCO DC Parameter Conditions Supply Voltage Min Typ 2.38 2.5 2.63 V 1.602 V VOH Output High Voltage for Q and Q RT = 100 across Q and Q signals VOL Output Low Voltage for Q and Q RT = 100 across Q and Q signals 0.898 RT = 100 across Q and Q signals 247 350 550 RT = 100 across Q and Q signals 1.100 1.250 1.375 Voltage(1,2) V VODIFF Differential Output Q = High (Q - Q), Q = High VOCM Output Common-Mode Voltage VIDIFF Differential Input Voltage (Q - Q), Q = High (Q - Q), Q = High 100 350 600 VICM Input Common-Mode Voltage 0.3 1.2 2.2 V Min Typ Max Units 2.38 2.5 2.63 V (Q - Q), mV V mV Notes: 1. 2. Recommended input maximum voltage not to exceed VCC0 + 0.2V. Recommended input minimum voltage not to go below -0.5V. Extended LVDS DC Specifications (LVDSEXT_25) Table 10: Extended LVDS DC Specifications Symbol VCCO DC Parameter Conditions Supply Voltage VOH Output High Voltage for Q and Q RT = 100 across Q and Q signals - - 1.785 V VOL Output Low Voltage for Q and Q RT = 100 across Q and Q signals 0.715 - - V VODIFF Differential Output Voltage (Q - Q), Q = High (Q - Q), Q = High RT = 100 across Q and Q signals 380 - 820 mV VOCM Output Common-Mode Voltage RT = 100 across Q and Q signals 1.000 1.250 1.375 V VIDIFF Differential Input Voltage(1,2) (Q - Q), Q = High (Q - Q), Q = High Common-mode input voltage = 1.25V 100 - 1000 mV VICM Input Common-Mode Voltage Differential input voltage = 350 mV 0.3 1.2 2.2 V Notes: 1. 2. Recommended input maximum voltage not to exceed VCC + 0.2V. Recommended input minimum voltage not to go below -0.5V. DS680 (v2.0) April 12, 2010 Product Specification www.xilinx.com 5 R Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics LVPECL DC Specifications (LVPECL_25) These values are valid when driving a 100 differential load only, for example, a 100 resistor between the two receiver pins. The VOH levels are 200 mV below standard LVPECL levels and are compatible with devices tolerant of lower common-mode ranges. Table 11 summarizes the DC output specifications of LVPECL. For more information on using LVPECL, see the Virtex-4 FPGA User Guide: Chapter 6, SelectIO Resources. Table 11: LVPECL DC Specifications Symbol DC Parameter Min Typ Max Units VOH Output High Voltage VCC - 1.025 1.545 VCC - 0.88 V VOL Output Low Voltage VCC - 1.81 0.795 VCC - 1.62 V VICM Input Common-Mode Voltage 0.6 2.2 V 0.100 1.5 V VIDIFF Differential Input Voltage(1,2) Notes: 1. 2. Recommended input maximum voltage not to exceed VCC0 + 0.2V. Recommended input minimum voltage not to go below -0.5V. Interface Performance Characteristics Table 12: Interface Performances Description Speed Grade -10 Networking Applications SFI-4.1 (SDR LVDS Interface)(5) 500 MHz SPI-4.2 (DDR LVDS Interface) 800 Mb/s Memory Interfaces DDR(1) 426 Mb/s DDR2(2) 510 Mb/s QDR II SRAM(3) RLDRAM 514 Mb/s II(4) 524 Mb/s Notes: 1. 2. 3. 4. 5. Performance defined using design implementation described in application note XAPP709: DDR SDRAM Controller Using Virtex-4 FPGA Devices. Performance defined using design implementation described in application note XAPP702: DDR2 Controller Using Virtex-4 Devices. Performance defined using design implementation described in application note XAPP703: QDR II SRAM Interface for Virtex-4 Devices. Performance defined using design implementation described in application note XAPP710: Synthesizable CIO DDR RLDRAM II Controller for Virtex-4 FPGAs. 644 MHz not supported for operating temperatures above 100C. DS680 (v2.0) April 12, 2010 Product Specification www.xilinx.com 6 R Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics Switching Characteristics Switching characteristics are specified on a per-speed- grade basis and can be designated as Advance, Preliminary, or Production. Each designation is defined as follows: Table 13: Virtex-4QV Device Speed Grade Designations Device Advance These specifications are based on simulations only and are typically available soon after device design specifications are frozen. Although speed grades with this designation are considered relatively stable and conservative, some underreporting might still occur. Preliminary These specifications are based on complete ES (engineering sample) silicon characterization. Devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. The probability of under-reporting delays is greatly reduced as compared to Advance data. Speed Grade Designations Advance Preliminary Production XQR4VSX55 -10 XQ4RVFX60 -10 XQR4VFX140 -10 XQR4VLX200 -10 Because individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. All specifications are always representative of worst-case supply voltage and junction temperature conditions. Production Testing of Switching Characteristics These specifications are released once enough production silicon of a particular device family member has been characterized to provide full correlation between specifications and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to Production before faster speed grades. All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotate to the simulation net list. Unless otherwise noted, values apply to all Virtex-4QV FPGAs. Table 13 correlates the current status of each Virtex-4QV device with a corresponding speed specification version 1.67 designation. DS680 (v2.0) April 12, 2010 Product Specification www.xilinx.com 7 R Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics PowerPC Processor Switching Characteristics Consult UG018, PowerPC 405 Processor Block Reference Guide for further information. Table 14: PowerPC 405 Processor Clocks Absolute AC Characteristics Speed Grade Description -10 Units Min Max CPMC405CLOCK frequency(1,4) 0 350 MHz CPMDCRCLK(3) 0 350 MHz CPMFCMCLK(3) - - MHz Characteristics when APU Not Used frequency (2) 0 175 MHz PLBCLK(3) 0 350 MHz BRAMDSOCMCLK(3) 0 350 MHz BRAMISOCMCLK(3) 0 350 MHz CPMC405CLOCK frequency(1,4) 0 233 MHz CPMDCRCLK(3) 0 233 MHz CPMFCMCLK(3) 0 233 MHz JTAGC405TCK frequency(2) 0 116.5 MHz PLBCLK(3) 0 233 MHz BRAMDSOCMCLK(3) 0 233 MHz BRAMISOCMCLK(3) 0 233 MHz JTAGC405TCK Characteristics when APU Used Notes: 1. 2. 3. 4. Worst-case DCM output clock jitter is included in these specifications. The theoretical maximum frequency of this clock is one-half the CPMC405CLOCK. However, the achievable maximum is system dependent, and will be much less. The theoretical maximum frequency of these clocks is equal to the CPMC405CLOCK. Integer clock ratios are required for the CPMC405CLOCK and BRAMDSOCMCLK, CPMC405CLOCK and BRAMISOCMCLK, CPMC405CLOCK and CPMDCRCLK, CPMC405CLOCK and CPMFCMCLK, and CPMC405CLOCK and PLBCLK. The integer ratios can be different for each interface. However, the achievable maximum is system dependent. Maximum operating frequency of CPMC405CLOCK is specified with the input pin TIEC405DISOPERANDFWD connected to a logic 1. DS680 (v2.0) April 12, 2010 Product Specification www.xilinx.com 8 R Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics Table 15: Processor Block Switching Characteristics Description Symbol Speed Grade Units -10 Setup and Hold Relative to Clock (CPMC405CLOCK) Clock and Power Management control inputs TPPCDCK_CORECKI TPPCCKD_CORECKI 0.74 0.23 ns Min Reset control inputs TPPCDCK_RSTCHIP TPPCCKD_RSTCHIP 0.74 0.23 ns Min Debug control inputs TPPCDCK_EXBUSHAK TPPCCKD_EXBUSHAK 0.74 0.23 ns Min Trace control inputs TPPCDCK_TRCDIS TPPCCKD_TRCDIS 0.74 0.23 ns Min External Interrupt Controller control inputs TPPCDCK_CINPIRQ TPPCCKD_CINPIRQ 1.40 0.23 ns Min TPPCCKO_CORESLP 1.74 ns Max Reset control outputs TPPCCKO_RSTCHIP 1.83 ns Max Debug control outputs TPPCCKO_DBGLDAPU 1.70 ns Max Trace control outputs TPPCCKO_TRCCYCLE 1.83 ns Max CPMC405CLOCK minimum pulse width, High TCPWH 1.43 ns Min CPMC405CLOCK minimum pulse width, Low TCPWL 1.43 ns Min Speed Grade Units Clock to Out Clock and Power Management control outputs Clock Table 16: Processor Block PLB Switching Characteristics Description Symbol -10 Setup and Hold Relative to Clock (PLBCLK) Processor Local Bus (ICU/DCU) control inputs TPPCDCK_ICUBUSY TPPCCKD_ICUBUSY 0.76 0.23 ns Min Processor Local Bus (ICU/DCU) data inputs TPPCDCK_ICURDDB TPPCCKD_ICURDDB 1.15 0.23 ns Min Processor Local Bus (ICU/DCU) control outputs TPPCCKO_DCUABORT 2.05 ns Max Processor Local Bus (ICU/DCU) address bus outputs TPPCCKO_ICUABUS 2.13 ns Max Processor Local Bus (ICU/DCU) data bus outputs TPPCCKO_DCUWRDBUS 2.57 ns Max Speed Grade Units Clock to Out Table 17: Processor Block JTAG Switching Characteristics Description Symbol -10 Setup and Hold Relative to Clock (JTAGC405TCK) JTAG control inputs TPPCDCK_JTGTDI TPPCCKD_JTGTDI 1.48 0.23 ns Min JTAG reset input TPPCDCK_JTGTRSTN TPPCCKD_JTGTRSTN 0.74 0.23 ns Min TPPCCKO_JTGTDO 2.14 ns Max Clock to Out JTAG control outputs DS680 (v2.0) April 12, 2010 Product Specification www.xilinx.com 9 R Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics Table 18: PowerPC 405 Data-Side On-Chip Memory Switching Characteristics Description Symbol Speed Grade Units -10 Setup and Hold Relative to Clock (BRAMDSOCMCLK) TPPCDCK_DSOCMRDDB TPPCCKD_DSOCMRDDB 0.74 0.23 ns Min Data-Side On-Chip Memory control outputs TPPCCKO_BRAMBWR 2.65 ns Max Data-Side On-Chip Memory address bus outputs TPPCCKO_BRAMABUS 2.65 ns Max Data-Side On-Chip Memory data bus outputs TPPCCKO_IBRAMWRDBUS01 2.06 ns Max Speed Grade Units Data-Side On-Chip Memory data bus inputs Clock to Out Table 19: PowerPC 405 Instruction-Side On-Chip Memory Switching Characteristics Description Symbol -10 Setup and Hold Relative to Clock (BRAMISOCMCLK) TPPCDCK_ISOCMRDDB TPPCCKD_ISOCMRDDB 0.94 0.23 ns Min Instruction-Side On-Chip Memory control outputs TPPCCKO_IBRAMEN 3.88 ns Max Instruction-Side On-Chip Memory address bus outputs TPPCCKO_IBRAMRDABUS 2.13 ns Max Instruction-Side On-Chip Memory data bus outputs TPPCCKO_IBRAMWRDBUS 2.14 ns Max Speed Grade Units Instruction-Side On-Chip Memory data bus inputs Clock to Out Table 20: Processor Block DCR Bus Switching Characteristics Description Symbol -10 Setup and Hold Relative to Clock (CPMDCRCLOCK) Device Control Register Bus control inputs TPPCDCK_EXDCRACK TPPCCKD_EXDCRACK 0.15 0.19 ns Min Device Control Register Bus data inputs TPPCDCK_EXDCRDBUSI TPPCCKD_EXDCRDBUSI 1.02 0.27 ns Min Device Control Register Bus control outputs TPPCCKO_EXDCRRD 1.54 ns Max Device Control Register Bus address bus outputs TPPCCKO_EXDCRABUS 1.66 ns Max Device Control Register Bus data bus outputs TPPCCKO_EXDCRDBUSO 1.67 ns Max Speed Grade Units Clock to Out Table 21: Processor Block APU Interface Switching Characteristics Description Symbol -10 Setup and Hold Relative to Clock (CPMDFCMCLOCK) APU bus control inputs TPPCDCK_DCDCREN TPPCCKD_DCDCREN 0.42 0.23 ns Min APU bus data inputs TPPCDCK_RESULT TPPCCKD_RESULT 0.78 0.23 ns Min APU bus control outputs TPPCCKO_APUFCMDEC 2.00 ns Max APU bus data outputs TPPCCKO_RADATA 2.00 ns Max Clock to Out DS680 (v2.0) April 12, 2010 Product Specification www.xilinx.com 10 R Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics IOB Pad Input/Output/3-State Switching Characteristics Table 22 summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard and 3-state delays. TIOPI is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies depending on the capability of the SelectIOTM input buffer technology. TIOOP is described as the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies depending on the capability of the SelectIO output buffer. TIOTP is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is disabled. The delay varies depending on the SelectIO capability of the output buffer. Table 24, page 16 summarizes the value of TIOTPHZ. TIOTPHZ is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is enabled (for example, a high-impedance state). Table 22: IOB Switching Characteristics(1,2) Speed Grade IOSTANDARD Attribute(1) -10 Units TIOPI TIOOP TIOTP LVDS_25 1.28 1.85 1.85 ns RSDS_25 1.28 1.85 1.85 ns LVDSEXT_25 1.30 1.91 1.91 ns LDT_25 1.28 1.82 1.82 ns BLVDS_25 1.28 2.34 2.34 ns ULVDS_25 1.28 1.83 1.83 ns PCI33_3 (PCI, 33 MHz, 3.3V) 0.97 3.02 3.02 ns PCI66_3 (PCI, 66 MHz, 3.3V) 0.97 2.72 2.72 ns PCI-X 0.97 2.25 2.25 ns GTL 1.63 2.03 2.03 ns GTLP 1.68 2.03 2.03 ns HSTL_I 1.64 2.35 2.35 ns HSTL_II 1.64 2.13 2.13 ns HSTL_III 1.64 2.22 2.22 ns HSTL_IV 1.64 2.03 2.03 ns HSTL_I _18 1.60 2.21 2.21 ns HSTL_II _18 1.60 2.16 2.16 ns HSTL_III _18 1.60 2.09 2.09 ns HSTL_IV_18 1.60 2.06 2.06 ns SSTL2_I 1.68 2.43 2.43 ns SSTL2_II 1.68 2.16 2.16 ns LVTTL, Slow, 2 mA 0.97 7.03 7.03 ns LVTTL, Slow, 4 mA 0.97 5.04 5.04 ns LVTTL, Slow, 6 mA 0.97 4.91 4.91 ns LVTTL, Slow, 8 mA 0.97 4.91 4.91 ns LVTTL, Slow, 12 mA 0.97 3.96 3.96 ns LVTTL, Slow, 16 mA 0.97 3.46 3.46 ns LVTTL, Slow, 24 mA 0.97 3.12 3.12 ns LVTTL, Fast, 2 mA 0.97 4.86 4.86 ns LVTTL, Fast, 4 mA 0.97 3.46 3.46 ns LVTTL, Fast, 6 mA 0.97 3.00 3.00 ns DS680 (v2.0) April 12, 2010 Product Specification www.xilinx.com 11 R Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics Table 22: IOB Switching Characteristics(1,2) (Cont'd) Speed Grade IOSTANDARD Attribute(1) -10 Units TIOPI TIOOP TIOTP LVTTL, Fast, 8 mA 0.97 2.79 2.79 ns LVTTL, Fast, 12 mA 0.97 2.47 2.47 ns LVTTL, Fast, 16 mA 0.97 2.47 2.47 ns LVTTL, Fast, 24 mA 0.97 2.20 2.20 ns LVCMOS33, Slow, 2 mA 0.97 8.73 8.73 ns LVCMOS33, Slow, 4 mA 0.97 6.09 6.09 ns LVCMOS33, Slow, 6 mA 0.97 5.00 5.00 ns LVCMOS33, Slow, 8 mA 0.97 3.95 3.95 ns LVCMOS33, Slow, 12 mA 0.97 3.42 3.42 ns LVCMOS33, Slow, 16 mA 0.97 2.49 2.49 ns LVCMOS33, Slow, 24 mA 0.97 2.49 2.49 ns LVCMOS33, Fast, 2 mA 0.97 7.44 7.44 ns LVCMOS33, Fast, 4 mA 0.97 4.33 4.33 ns LVCMOS33, Fast, 6 mA 0.97 3.55 3.55 ns LVCMOS33, Fast, 8 mA 0.97 2.46 2.46 ns LVCMOS33, Fast, 12 mA 0.97 2.27 2.27 ns LVCMOS33, Fast, 16 mA 0.97 2.08 2.08 ns LVCMOS33, Fast, 24 mA 0.97 2.08 2.08 ns LVCMOS25, Slow, 2 mA 0.88 5.89 5.89 ns LVCMOS25, Slow, 4 mA 0.88 5.02 5.02 ns LVCMOS25, Slow, 6 mA 0.88 4.31 4.31 ns LVCMOS25, Slow, 8 mA 0.88 4.31 4.31 ns LVCMOS25, Slow, 12 mA 0.88 3.50 3.50 ns LVCMOS25, Slow, 16 mA 0.88 3.31 3.31 ns LVCMOS25, Slow, 24 mA 0.88 2.77 2.77 ns LVCMOS25, Fast, 2 mA 0.88 3.89 3.89 ns LVCMOS25, Fast, 4 mA 0.88 3.19 3.19 ns LVCMOS25, Fast, 6 mA 0.88 2.81 2.81 ns LVCMOS25, Fast, 8 mA 0.88 2.52 2.52 ns LVCMOS25, Fast, 12 mA 0.88 2.43 2.43 ns LVCMOS25, Fast, 16 mA 0.88 2.21 2.21 ns LVCMOS25, Fast, 24 mA 0.88 2.13 2.13 ns LVCMOS18, Slow, 2 mA 1.25 5.89 5.89 ns LVCMOS18, Slow, 4 mA 1.25 4.35 4.35 ns LVCMOS18, Slow, 6 mA 1.25 4.00 4.00 ns LVCMOS18, Slow, 8 mA 1.25 3.76 3.76 ns LVCMOS18, Slow, 12 mA 1.25 3.74 3.74 ns LVCMOS18, Slow, 16 mA 1.25 3.55 3.55 ns LVCMOS18, Fast, 2 mA 1.25 3.89 3.89 ns LVCMOS18, Fast, 4 mA 1.25 3.02 3.02 ns LVCMOS18, Fast, 6 mA 1.25 2.72 2.72 ns DS680 (v2.0) April 12, 2010 Product Specification www.xilinx.com 12 R Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics Table 22: IOB Switching Characteristics(1,2) (Cont'd) Speed Grade IOSTANDARD Attribute(1) -10 Units TIOPI TIOOP TIOTP LVCMOS18, Fast, 8 mA 1.25 2.52 2.52 ns LVCMOS18, Fast, 12 mA 1.25 2.36 2.36 ns LVCMOS18, Fast, 16 mA 1.25 2.27 2.27 ns LVCMOS15, Slow, 2 mA 1.34 6.61 6.61 ns LVCMOS15, Slow, 4 mA 1.34 4.88 4.88 ns LVCMOS15, Slow, 6 mA 1.34 4.26 4.26 ns LVCMOS15, Slow, 8 mA 1.34 4.26 4.26 ns LVCMOS15, Slow, 12 mA 1.34 3.77 3.77 ns LVCMOS15, Slow, 16 mA 1.34 3.53 3.53 ns LVCMOS15, Fast, 2 mA 1.34 4.17 4.17 ns LVCMOS15, Fast, 4 mA 1.34 3.32 3.32 ns LVCMOS15, Fast, 6 mA 1.34 2.94 2.94 ns LVCMOS15, Fast, 8 mA 1.34 2.71 2.71 ns LVCMOS15, Fast, 12 mA 1.34 2.50 2.50 ns LVCMOS15, Fast, 16 mA 1.34 2.43 2.43 ns LVDCI_33 0.97 3.13 3.13 ns LVDCI_25 0.88 3.02 3.02 ns LVDCI_18 1.25 2.95 2.95 ns LVDCI_15 1.34 2.93 2.93 ns LVDCI_DV2_25 0.88 2.27 2.27 ns LVDCI_DV2_18 1.25 2.28 2.28 ns LVDCI_DV2_15 1.34 2.58 2.58 ns GTL_DCI 1.51 2.03 2.03 ns GTLP_DCI 1.23 2.03 2.03 ns HSTL_I_DCI 1.64 2.35 2.35 ns HSTL_II_DCI 1.64 2.13 2.13 ns HSTL_III_DCI 1.64 2.22 2.22 ns HSTL_IV_DCI 1.64 2.03 2.03 ns HSTL_I_DCI_18 1.60 2.21 2.21 ns HSTL_II_DCI_18 1.60 2.16 2.16 ns HSTL_III_DCI_18 1.60 2.09 2.09 ns HSTL_IV_DCI_18 1.60 2.06 2.06 ns SSTL2_I_DCI 1.68 2.46 2.46 ns SSTL2_II_DCI 1.68 2.45 2.45 ns LVPECL_25 1.77 1.74 1.74 ns SSTL18_I 1.68 2.54 2.54 ns SSTL18_II 1.68 2.24 2.24 ns SSTL18_I_DCI 1.68 2.32 2.32 ns SSTL18_II_DCI 1.68 2.18 2.18 ns Notes: 1. The I/O standard is selected in the Xilinx ISE(R) software tool using the IOSTANDARD attribute. 2. All I/O timing specifications are measured with VCCO at -5% from nominal. DS680 (v2.0) April 12, 2010 Product Specification www.xilinx.com 13 R Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics Table 23: TIOOP and TIOTP Offset for 125C Operation Speed Grade IOSTANDARD Attribute -10 I Grade V Grade Units Delta LVDS 1.85 2.23 0.38 ns RSDS 1.85 2.23 0.38 ns LVDSEXT 1.91 2.25 0.34 ns LDT 1.82 2.23 0.41 ns PCI33_3 3.02 3.26 0.24 ns PCI66_3 2.72 3.26 0.54 ns PCIX 2.25 2.49 0.24 ns GTL 2.03 2.27 0.24 ns GTLP 2.03 2.25 0.22 ns HSTL_I 2.35 2.54 0.19 ns HSTL_II 2.13 2.47 0.34 ns HSTL_III 2.22 2.55 0.33 ns HSTL_IV 2.03 2.43 0.40 ns HSTL_I_18 2.21 2.43 0.22 ns HSTL_II_18 2.16 2.39 0.23 ns HSTL_III_18 2.09 2.40 0.31 ns HSTL_IV_18 2.06 2.38 0.32 ns SSTL2_I 2.43 2.46 0.03 ns SSTL2_II 2.16 2.27 0.11 ns LVTTL_S2 7.03 9.95 2.92 ns LVTTL_S4 5.04 7.84 2.80 ns LVTTL_S6 4.91 6.67 1.76 ns LVTTL_S8 4.91 6.40 1.49 ns LVTTL_S12 3.96 4.87 0.91 ns LVTTL_S16 3.46 4.42 0.96 ns LVTTL_S24 3.12 3.24 0.12 ns LVTTL_F2 4.86 8.44 3.58 ns LVTTL_F4 3.46 6.41 2.95 ns LVTTL_F6 3.00 4.76 1.76 ns LVTTL_F8 2.79 3.97 1.18 ns LVTTL_F12 2.47 2.92 0.45 ns LVTTL_F16 2.47 2.93 0.46 ns LVTTL_F24 2.20 2.87 0.67 ns LVCMOS33_S2 8.73 11.43 2.70 ns LVCMOS33_S4 6.09 8.56 2.47 ns LVCMOS33_S6 5.00 7.27 2.27 ns LVCMOS33_S8 3.95 6.35 2.40 ns LVCMOS33_S12 3.42 4.74 1.32 ns DS680 (v2.0) April 12, 2010 Product Specification www.xilinx.com 14 R Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics Table 23: TIOOP and TIOTP Offset for 125C Operation (Cont'd) Speed Grade IOSTANDARD Attribute -10 I Grade V Grade Units Delta LVCMOS33_S16 2.49 4.56 2.07 ns LVCMOS33_S24 2.49 3.06 0.57 ns LVCMOS33_F2 7.44 10.18 2.74 ns LVCMOS33_F4 4.33 6.18 1.85 ns LVCMOS33_F6 3.55 5.53 1.98 ns LVCMOS33_F8 2.46 4.47 2.01 ns LVCMOS33_F12 2.27 3.22 0.95 ns LVCMOS33_F16 2.08 2.74 0.66 ns LVCMOS33_F24 2.08 2.61 0.53 ns LVCMOS25_S2 5.89 8.57 2.68 ns LVCMOS25_S4 5.02 6.44 1.42 ns LVCMOS25_S6 4.31 6.00 1.69 ns LVCMOS25_S8 4.31 5.24 0.93 ns LVCMOS25_S12 3.50 4.30 0.80 ns LVCMOS25_S16 3.31 3.95 0.64 ns LVCMOS25_S24 2.77 2.64 -0.13 ns LVCMOS25_F2 3.89 7.97 4.08 ns LVCMOS25_F4 3.19 4.99 1.80 ns LVCMOS25_F6 2.81 3.92 1.11 ns LVCMOS25_F8 2.52 3.29 0.77 ns LVCMOS25_F12 2.43 2.43 0.00 ns LVCMOS25_F16 2.21 2.39 0.18 ns LVCMOS25_F24 2.13 2.39 0.26 ns LVCMOS18_S2 5.89 8.68 2.79 ns LVCMOS18_S4 4.35 7.31 2.96 ns LVCMOS18_S6 4.00 5.66 1.66 ns LVCMOS18_S8 3.76 5.11 1.35 ns LVCMOS18_S12 3.74 4.59 0.85 ns LVCMOS18_S16 3.55 3.89 0.34 ns LVCMOS18_F2 3.89 8.34 4.45 ns LVCMOS18_F4 3.02 5.99 2.97 ns LVCMOS18_F6 2.72 4.35 1.63 ns LVCMOS18_F8 2.52 3.66 1.14 ns LVCMOS18_F12 2.36 2.80 0.44 ns LVCMOS18_F16 2.27 2.70 0.43 ns LVCMOS15_S2 6.61 9.21 2.60 ns LVCMOS15_S4 4.88 7.75 2.87 ns LVCMOS15_S6 4.26 6.14 1.88 ns DS680 (v2.0) April 12, 2010 Product Specification www.xilinx.com 15 R Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics Table 23: TIOOP and TIOTP Offset for 125C Operation (Cont'd) Speed Grade IOSTANDARD Attribute -10 Units I Grade V Grade Delta LVCMOS15_S8 4.26 6.18 1.92 ns LVCMOS15_S12 3.77 4.77 1.00 ns LVCMOS15_S16 3.53 4.07 0.54 ns LVCMOS15_F2 4.17 8.32 4.15 ns LVCMOS15_F4 3.32 6.53 3.21 ns LVCMOS15_F6 2.94 4.69 1.75 ns LVCMOS15_F8 2.71 3.90 1.19 ns LVCMOS15_F12 2.50 2.92 0.42 ns LVCMOS15_F16 2.43 2.84 0.41 ns SSTL18_I 2.54 2.44 -0.10 ns SSTL18_II 2.24 2.42 0.18 ns Table 24: IOB 3-State On Output Switching Characteristics (TIOTPHZ) Symbol TIOTPHZ Description T input to Pad high-impedance Speed Grade -10 1.12 Units ns Ethernet MAC Switching Characteristics Consult UG074,Virtex-4 Embedded Tri-Mode Ethernet MAC User Guide for further information. Table 25: Maximum Ethernet MAC Performance Description Speed Grade Units -10 Ethernet MAC Maximum Performance DS680 (v2.0) April 12, 2010 Product Specification 10/100/1000 Mb/s www.xilinx.com 16 R Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics Input/Output Logic Switching Characteristics Table 26: ILOGIC Switching Characteristics Symbol Description Speed Grade -10 Units Setup/Hold TICE1CK / TICKCE1 CE1 pin setup/hold with respect to CLK 0.79/-0.23 ns TICECK / TICKCE DLYCE pin setup/hold with respect to CLKDIV 0.23/0.16 ns TIRSTCK / TICKRST DLYRST pin setup/hold with respect to CLKDIV -0.02/0.54 ns TIINCCK / TICKINC DLYINC pin setup/hold with respect to CLKDIV 0.01/0.51 ns TISRCK / TICKSR SR/REV pin setup/hold with respect to CLK 1.59/-0.56 ns TIDOCK / TIOCKD D pin setup/hold with respect to CLK without Delay 0.34/-0.10 ns D pin setup/hold with respect to CLK (IOBDELAY_TYPE = DEFAULT) 8.84/-5.99 ns D pin setup/hold with respect to CLK (IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0) 1.09/-0.63 ns D pin to O pin propagation delay, no Delay 0.24 ns D pin to O pin propagation delay (IOBDELAY_TYPE = DEFAULT) 7.96 ns D pin to O pin propagation delay (IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0) 0.99 ns D pin to Q1 pin using flip-flop as a latch without Delay 0.71 ns D pin to Q1 pin using flip-flop as a latch (IOBDELAY_TYPE = DEFAULT) 9.21 ns D pin to Q1 pin using flip-flop as a latch (IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0) 1.45 ns TICKQ CLK to Q outputs 0.72 ns TICE1Q CE1 pin to Q1 using flip-flop as a latch, propagation delay 1.27 ns TRQ SR/REV pin to OQ/TQ out 2.44 ns TGSRQ Global set/reset to Q outputs 2.03 ns Minimum pulse width, SR/REV inputs 0.70 ns, Min TIDOCKD / TIOCKDD Combinatorial TIDI TIDID Sequential Delays TIDLO TIDLOD Set/Reset TRPW DS680 (v2.0) April 12, 2010 Product Specification www.xilinx.com 17 R Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics Table 27: OLOGIC Switching Characteristics Symbol Description Speed Grade -10 Units Setup/Hold TODCK / TOCKD D1/D2 pins setup/hold with respect to CLK 0.75/-0.22 ns TOOCECK / TOCKOCE OCE pin setup/hold with respect to CLK 0.77/-0.33 ns TOSRCK / TOCKSR SR/REV pin setup/hold with respect to CLK 1.42/-0.55 ns TOTCK / TOCKT T1/T2 pins setup/hold with respect to CLK 0.75/-0.22 ns TOTCECK / TOCKTCE TCE pin setup/hold with respect to CLK 0.77/-0.33 ns Combinatorial TODQ D1 to OQ out 0.76 ns TOTQ T1 to TQ out 0.76 ns TIOSRON REV pin to TQ out 1.64 ns TOCKQ CLK to OQ/TQ out 0.59 ns TRQ SR/REV pin to OQ/TQ out 1.64 ns TGSRQ Global Set/Reset to Q outputs 2.03 ns Minimum Pulse Width, SR/REV inputs 0.70 ns Min Sequential Delays Set/Reset TRPW DS680 (v2.0) April 12, 2010 Product Specification www.xilinx.com 18 R Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics Input Serializer/Deserializer Switching Characteristics Table 28: ISERDES Switching Characteristics Symbol Description Speed Grade -10 Units Setup/Hold for Control Lines TISCCK_BITSLIP / TISCKC_BITSLIP BITSLIP pin setup/hold with respect to CLKDIV 0.40/-0.13 ns TISCCK_CE / TISCKC_CE(2) CE pin setup/hold with respect to CLK (for CE1) 0.69/-0.25 ns CE pin setup/hold with respect to CLKDIV (for CE2) 0.16/-0.02 ns TISCCK_DLYCE / TISCKC_DLYCE DLYCE pin setup/hold with respect to CLKDIV 0.23/0.16 ns TISCCK_DLYINC / TISCKC_DLYINC DLYINC pin setup/hold with respect to CLKDIV 0.01/0.51 ns TISCCK_DLYRST / TISCKC_DLYRST DLYRST pin setup/hold with respect to CLKDIV -0.02/0.54 ns TISCCK_REV REV pin setup with respect to CLK 1.23 ns TISCCK_SR SR pin setup with respect to CLKDIV 0.92 ns D pin setup/hold with respect to CLK (IOBDELAY = IBUF or NONE) 0.34/-0.11 ns D pin setup/hold with respect to CLK (IOBDELAY = IFD or BOTH, IOBDELAY_TYPE = DEFAULT) 8.84/-6.51 ns D pin setup/hold with respect to CLK(1) (IOBDELAY = IFD or BOTH, IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0) 1.08/-0.68 ns D pin setup/hold with respect to CLK at DDR mode (IOBDELAY = IBUF or NONE) 0.34/-0.11 ns D pin setup/hold with respect to CLK at DDR mode (IOBDELAY = IFD or BOTH, IOBDELAY_TYPE = DEFAULT) 8.84/-6.51 ns D pin setup/hold with respect to CLK at DDR mode(1) (IOBDELAY = IFD or BOTH, IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0) 1.08/-0.68 ns CLKDIV to out at Q pin 0.85 ns TISDO_DO_IOBDELAY_IFD D input to DO output pin (IOBDELAY = IFD) 0.24 ns TISDO_DO_IOBDELAY_NONE D input to DO output pin (IOBDELAY = NONE) 0.24 ns D input to DO output pin (IOBDELAY = BOTH, IOBDELAY_TYPE = DEFAULT) 7.96 ns D input to DO output pin(1) (IOBDELAY = BOTH, IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0) 0.99 ns D input to DO output pin (IOBDELAY = IBUF, IOBDELAY_TYPE = DEFAULT) 7.96 ns D input to DO output pin(1) (IOBDELAY = IBUF, IOBDELAY_TYPE = FIXED, IOBDELAY_VALUE = 0) 0.99 ns TISCCK_CE2 / TISCKC_CE2 (2) Setup/Hold for Data Lines TISDCK_D / TISCKD_D TISDCK_DDR / TISCKD_DDR Sequential Delays TISCKO_Q Propagation Delays TISDO_DO_IOBDELAY_BOTH TISDO_DO_IOBDELAY_IBUF Notes: 1. 2. Recorded at 0 tap value. TISCCK_CE2 and TISCKC_CE2 are reported as TISCCK_CE / TISCKC_CE in TRCE report. DS680 (v2.0) April 12, 2010 Product Specification www.xilinx.com 19 R Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics Input Delay Switching Characteristics Table 29: Input Delay Switching Characteristics Symbol Description TIDELAYRESOLUTION IDELAY Chain Delay Resolution TIDELAYTOTAL_ERR Cumulative delay at a given tap (3) TIDELAYCTRLCO_RDY Speed Grade -10 Units 75 ps [(tap -1) x 75 +34] 0.07[(tap -1) x 75 +34] ps Reset to Ready for IDELAYCTRL (Maximum) 3.00 s FIDELAYCTRL_REF REFCLK frequency 200 MHz IDELAYCTRL_REF_PRECISION (2) REFCLK precision 10 MHz TIDELAYCTRL_RPW Minimum Reset pulse width 50.0 ns 0 Note (1) 10 2 Note (1) Pattern dependent period jitter in delay chain for clock pattern TIDELAYPAT_JIT Pattern dependent period jitter in delay chain for random data pattern (PRBS 23) Notes: 1. 2. 3. Units in ps peak-to-peak per tap. See the "REFCLK - Reference Clock" section (specific to IDELAYCTRL) in the Virtex-4 FPGA User Guide: Chapter 7, "SelectIO Logic Resources." This value accounts for tap 0, an anomaly in the tap chain with an average value of 34 ps. Output Serializer/Deserializer Switching Characteristics Table 30: OSERDES Switching Characteristics Symbol Description Speed Grade -10 Units Setup/Hold TOSDCK_D / TOSCKD_D D input setup/hold with respect to CLKDIV 0.50/-0.03 ns TOSDCK_T / TOSCKD_T(1) T input setup/hold with respect to CLK 0.62/-0.16 ns TOSDCK_T2 / TOSCKD_T2(1) T input setup/hold with respect to CLKDIV 0.50/-0.03 ns TOSCCK_OCE / TOSCKC_OCE OCE input setup/hold with respect to CLK 0.64/0.03 ns TOSCCK_S SR (Reset) input setup with respect to CLKDIV 0.96 ns TOSCCK_TCE / TOSCKC_TCE TCE input setup/hold with respect to CLK 0.64/0.03 ns Sequential Delays TOSCKO_OQ Clock to out from CLK to OQ 0.59 ns TOSCKO_TQ Clock to out from CLK to TQ 0.59 ns TOSDO_TTQ T input to TQ out 0.76 ns TOSCO_OQ Asynchronous reset to OQ 1.64 ns TOSCO_TQ Asynchronous reset to TQ 1.64 ns Combinatorial Notes: 1. TOSDCK_T2 and TOSCKD_T2 are reported as TOSDCK_T / TOSCKD_T in TRCE report. DS680 (v2.0) April 12, 2010 Product Specification www.xilinx.com 20 R Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics CLB Switching Characteristics Table 31: CLB Switching Characteristics Symbol Speed Grade Description -10 Units Combinatorial Delays TILO 4-input function: F/G inputs to X/Y outputs 0.20 ns, max TIF5 5-input function: F/G inputs to F5 output 0.46 ns, max TIF5X 5-input function: F/G inputs to X output 0.57 ns, max TIF6Y FXINA or FXINB inputs to YMUX output 0.39 ns, max TINAFX FXINA input to FX output via MUXFX 0.27 ns, max TINBFX FXINB input to FX output via MUXFX 0.26 ns, max TBXX BX input to XMUX output 0.76 ns, max TBYY BY input to YMUX output TBXCY TBYCY TBYP TOPCYF TOPCYG 0.56 ns, max BX input to COUT output - Getting into carry chain(2) 0.78 ns, max BY input to COUT output - Getting into carry chain(2) 0.63 ns, max CIN input to COUT output - Carry chain delay(2) 0.09 ns, max F input to COUT output - Getting out from carry chain(2) 0.58 ns, max G input to COUT output - Getting out from carry chain(2) 0.57 ns, max Sequential Delays TCKO FF Clock CLK to XQ/YQ outputs 0.36 ns, max TCKLO Latch Clock CLK to XQ/YQ outputs 0.48 ns, max Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK TDICK / TCKDI BX/BY inputs 0.47/-0.09 ns, min TCECK / TCKCE CE input 0.75/-0.16 ns, min TFXCK / TCKFX FXINA/FXINB inputs 0.54/-0.14 ns, min TSRCK / TCKSR SR/BY inputs (synchronous) 1.35/-0.73 ns, min 0.67/-0.23 ns, min TCINCK / TCKCIN CIN Data Inputs (DI) - Getting out from carry chain(2) Set/Reset TRPW Minimum Pulse Width, SR/BY inputs 0.70 ns, min TRQ Delay from SR/BY inputs to XQ/YQ outputs (asynchronous) 1.35 ns, max FTOG Toggle Frequency (MHz) (for export control) 1028 MHz Notes: 1. 2. A zero "0" hold time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed "best-case," but if a "0" is listed, there is no positive hold time. These items are of interest for carry chain applications. DS680 (v2.0) April 12, 2010 Product Specification www.xilinx.com 21 R Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics CLB Distributed RAM Switching Characteristics (SLICEM Only) ) Table 32: CLB Distributed RAM Switching Characteristics Symbol Description Speed Grade -10 Units Sequential Delays TSHCKO Clock CLK to X outputs (WE active) 2.08 ns, max TSHCKOF5 Clock CLK to F5 output (WE active) 1.98 ns, max Setup and Hold Times Before/After Clock CLK TDS / TDH BX/BY data inputs (DI) 1.80/-0.88 ns, min TAS / TAH F/G address inputs 1.13/-0.29 ns, min TWS / TWH WE input (SR) 1.42/-0.47 ns, min Clock CLK TWPH Minimum Pulse Width, High 0.69 ns, min TWPL Minimum Pulse Width, Low 0.70 ns, min TWC Minimum clock period to meet address write cycle time 0.98 ns, min Notes: 1. 2. A zero "0" hold time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed "best-case," but if a "0" is listed, there is no positive hold time. TSHCKO also represents the CLK to XMUX output. Refer to TRCE report for the CLK to XMUX path. CLB Shift Register Switching Characteristics (SLICEM Only) ) Table 33: CLB Shift Register Switching Characteristics Symbol Description Speed Grade -10 Units Sequential Delays TREG Clock CLK to X/Y outputs 2.57 ns, max TREGXB Clock CLK to XB output via MC15 LUT output 2.04 ns, max TREGYB Clock CLK to YB output via MC15 LUT output 2.17 ns, max TCKSH Clock CLK to Shiftout 1.99 ns, max TREGF5 Clock CLK to F5 output 2.47 ns, max Setup and Hold Times Before/After Clock CLK TWS / TWH WE input (SR) 1.12/-0.62 ns, min TDS / TDH BX/BY data inputs (DI) 1.75/-1.11 ns, min Clock CLK TWPH Minimum pulse width, High 0.69 ns, min TWPL Minimum pulse width, Low 0.70 ns, min Notes: 1. A zero "0" hold time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed "best-case," but if a "0" is listed, there is no positive hold time. DS680 (v2.0) April 12, 2010 Product Specification www.xilinx.com 22 R Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics Block RAM and FIFO Switching Characteristics Table 34: Block RAM Switching Characteristics Symbol Speed Grade Description -10 Units Sequential Delays Clock CLK to DOUT output (without output register)(2) TRCKO_DORA TRCKO_DOA 2.10 ns, max 0.92 ns, min ADDR inputs 0.43/0.33 ns, min inputs(4) 0.23/0.33 ns, min 0.52/0.33 ns, min Clock CLK to DOUT output (with output register)(3) Setup and Hold Times Before Clock CLK TRCCK_ADDR / TRCKC_ADDR TRDCK_DI / TRCKD_DI DIN TRCCK_EN / TRCKC_EN EN input(5) TRCCK_REGCE / TRCKC_REGCE CE input of output register 0.32/0.33 ns, min TRCCK_SSR / TRCKC_SSR RST input 0.32/0.33 ns, min TRCCK_WE / TRCKC_WE WEN input 0.75/0.33 ns, min Maximum Frequency FMAX Write first and no change mode 400.00 MHz FMAX Read first mode 400.00 MHz Notes: 1. 2. 3. 4. 5. A zero "0" hold time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed "best-case," but if a "0" is listed, there is no positive hold time. TRCKO_DORA includes TRCKO_DOWA, TRCKO_DOPAR, and TRCKO_DOPAW as well as the B port equivalent timing parameters. TRCKO_DOA includes TRCKO_DOPA as well as the B port equivalent timing parameters. TRCKO_DI includes both A and B inputs as well as the parity inputs of A and B. Xilinx block RAMs do not have asynchronous inputs on an enabled port address. During the time that a port is enabled, its addresses must be stable during the specified set-up time. Do not create an asynchronous input on an enabled port address. Table 35: FIFO Switching Characteristics Symbol Description Speed Grade -10 Units Sequential Delays TFCKO_DO Clock CLK to DO output(2) outputs(3) TFCKO_FLAGS Clock CLK to FIFO flags TFCKO_POINTERS Clock CLK to FIFO pointer outputs(4) 0.92 ns, max 1.19 ns, max 1.48 ns, max Setup and Hold Times Before Clock CLK TFDCK_DI / TFCKD_DI TFCCK_EN / TFCKC_EN DI input(5) 0.23/0.33 ns, min inputs(6) 0.84/0.33 ns, min Reset RST to FLAGS(7) 1.68 ns, max 400.00 MHz Enable Reset Delays TFCO_FLAGS Maximum Frequency FMAX FIFO in all modes Notes: 1. 2. 3. 4. 5. 6. 7. A zero "0" hold time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed "best-case," but if a "0" is listed, there is no positive hold time. TFCKO_DO includes parity output (TFCKO_DOP). TFCKO_FLAGS includes these parameters: TFCKO_AEMPTY, TFCKO_AFULL, TFCKO_EMPTY, TFCKO_FULL, TFCKO_RDERR, TFCKO_WRERR. TFCKO_POINTERS includes both TFCKO_RDCOUNT and TFCKO_WRCOUNT. TFDCK_DI includes parity inputs (TFDCK_DIP). TFCCK_EN includes both WRITE and READ enable. TFCO_FLAGS includes these flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT and WRCOUNT. DS680 (v2.0) April 12, 2010 Product Specification www.xilinx.com 23 R Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics XtremeDSP Switching Characteristics Table 36: XtremeDSPTM Switching Characteristics Symbol Description Speed Grade -10 Units Setup and Hold of CE Pins TDSPCCK_CE / TDSPCKC_CE Setup/hold of all CE inputs of the DSP48 slice 0.49/0.12 ns TDSPCCK_RST / TDSPCKC_RST Setup/hold of all RST inputs of the DSP48 slice 0.40/0.12 ns TDSPDCK_{AA, BB, CC} / TDSPCKD_{AA, BB, CC} Setup/hold of {A, B, C} input to {A, B, C} register 0.32/0.29 TDSPDCK_{AM, BM} / TDSPCKD_{AM, BM} Setup/hold of {A, B} input to M register 2.28/0.00 TDSPCKO_PP Clock to out from P register to P output 0.79 ns TDSPCKO_PM Clock to out from M register to P output 2.98 ns From {A, B} input to P output (LEGACY_MODE = MULT18X18) 4.41 From {A, B} register to P register (LEGACY_MODE = MULT18X18) 253.94 Fully Pipelined 400.00 Setup and Hold Times of Data ns ns Sequential Delays Combinatorial TDSPDO_{AP, BP}L ns Maximum Frequency FMAX DS680 (v2.0) April 12, 2010 Product Specification MHz MHz www.xilinx.com 24 R Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics Configuration Switching Characteristics Table 37: Configuration Switching Characteristics Symbol Description Speed Grade -10 Units Power-up Timing Characteristics TPL Program latency 0.5 s/fram e, max TPOR Power-on-reset TPL + 10 ms, max TICCK CCLK (output) delay 500 ns, min TPROGRAM Program pulse width 400 ns, min Master/Slave Serial Mode Programming Switching TDCC / TCCD DIN setup/hold, slave mode 1.0/1.0 ns, min TDSCK / TSCKD DIN setup/hold, master mode 1.0/1.0 ns, min TCCO DOUT 8.0 ns, max TCCH High time 2.0 ns, min TCCL Low time 2.0 ns, min FCC_SERIAL Maximum frequency, master mode with respect to nominal CCLK. 80 MHz, max FMCCTOL Frequency tolerance, master mode with respect to nominal CCLK. 50 % FMAX_SLAVE Slave mode external CCLK 80 MHz SelectMAP Mode Programming Switching TSMDCC / TSMCCD SelectMAP setup/hold 3.0/0.0 ns, min TSMCSCC / TSMCCCS CS_B setup/hold 2.0/0.5 ns, min TSMCCW / TSMWCC RDWR_B setup/hold 8.0/1.0 ns, min TSMCKBY BUSY propagation delay 8.0 ns, max FCC_SELECTMAP Maximum frequency, master mode with respect to nominal CCLK. 80 MHz, max FMCCTOL Frequency tolerance, master mode with respect to nominal CCLK. 50 % Boundary-Scan Port Timing Specifications TTAPTCK TMS and TDI setup time before TCK 1.5 ns, min TTCKTAP TMS and TDI hold time after TCK 2.0 ns, min TTCKTDO TCK falling edge to TDO output valid 8.0 ns, max FTCK Maximum configuration TCK clock frequency 66 MHz, max FTCKB Maximum Boundary-Scan TCK clock frequency 50 MHz, max DS680 (v2.0) April 12, 2010 Product Specification www.xilinx.com 25 R Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics Table 37: Configuration Switching Characteristics (Cont'd) Symbol Speed Grade Description Units -10 Dynamic Reconfiguration Port (DRP) for DCM 400 MHz, max D_DCMADV_DADDR_DCLK_SETUP/ DADDR setup/hold D_DCMADV_DADDR_DCLK_HOLD 0.72/0.00 ns, max D_DCMADV_DI_DCLK_SETUP/ D_DCMADV_DI_DCLK_HOLD DI setup/hold 0.72/0.00 ns, max D_DCMADV_DEN_DCLK_SETUP/ D_DCMADV_DEN_DCLK_HOLD DEN setup/hold time 0.58/0.00 ns, max D_DCMADV_DWE_DCLK_SETUP/ D_DCMADV_DWE_DCLK_HOLD DWE setup/hold time 0.58/0.00 ns, max D_DCMADV_DCLK_DO CLK to out of DO(1) 0 ns, max D_DCMADV_DCLK_DRDY CLK to out of DRDY 0.92 ns, max CLKIN_FREQ_DLL_HF_MS_MAX Maximum frequency for DCLK Notes: 1. DO holds until next DRP operation. Master/Slave SelectMAP Parameters Figure 1 is a generic timing diagram for data loading using SelectMAP. For other data loading diagrams, refer to the Virtex-4 FPGA User Guide. X-Ref Target - Figure 1 CCLK CS_B RDWR_B TSMCCCS TSMCSCC TSMWCC TSMCCW TSMCCD TSMDCC DATA[0:7] TSMCKBY BUSY No Write Write No Write Write DS680_01_032608 Figure 1: SelectMAP Mode Data Loading Sequence (Generic) DS680 (v2.0) April 12, 2010 Product Specification www.xilinx.com 26 R Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics Clock Buffers and Networks Table 38: Global Clock Switching Characteristics (Including BUFGCTRL) Symbol Description Speed Grade -10 Units TBCCCK_CE / TBCCKC_CE(1) CE pins setup/hold 0.35/0.00 ns TBCCCK_S / TBCCKC_S(1) S pins setup/hold 0.35/0.00 ns TBCCKO_O BUFGCTRL delay 0.90 ns Global clock tree 400 MHz Maximum Frequency FMAX Notes: 1. TBCCCK_CE and TBCCKC_CE must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These parameters do not apply to the BUFGMUX_VIRTEX4 primitive that assures glitch-free operation. The other global clock setup and hold times are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between clocks. DCM and PMCD Switching Characteristics DCM in Maximum Range (MR) Mode is not supported for operation beyond industrial temperature range. Table 39: Operating Frequency Ranges for DCM in Maximum Speed (MS) Mode Symbol Description Speed Grade -10 Units Outputs Clocks (Low Frequency Mode) CLKOUT_FREQ_1X_LF_MS_MIN CLKOUT_FREQ_1X_LF_MS_MAX CLKOUT_FREQ_2X_LF_MS_MIN CLKOUT_FREQ_2X_LF_MS_MAX CLKOUT_FREQ_DV_LF_MS_MIN CLKOUT_FREQ_DV_LF_MS_MAX CLKOUT_FREQ_FX_LF_MS_MIN CLKOUT_FREQ_FX_LF_MS_MAX CLK0, CLK90, CLK180, CLK270 CLK2X, CLK2X180 CLKDV CLKFX, CLKFX180 32 MHz 150 MHz 64 MHz 300 MHz 2 MHz 100 MHz 32 MHz 210 MHz Input Clocks (Low Frequency Mode) CLKIN_FREQ_DLL_LF_MS_MIN CLKIN_FREQ_DLL_LF_MS_MAX CLKIN_FREQ_FX_LF_MS_MIN CLKIN_FREQ_FX_LF_MS_MAX PSCLK_FREQ_LF_MS_MIN PSCLK_FREQ_LF_MS_MAX CLKIN (using DLL outputs)(1,3,4,5) CLKIN (using DFS outputs only)(2,3,4) PSCLK 32 MHz 150 MHz 1 MHz 210 MHz 1 KHz 400 MHz 150 MHz 400 MHz 300 MHz 400 MHz 9.4 MHz 267 MHz 210 MHz 300 MHz Outputs Clocks (High Frequency Mode) CLKOUT_FREQ_1X_HF_MS_MIN CLKOUT_FREQ_1X_HF_MS_MAX CLKOUT_FREQ_2X_HF_MS_MIN CLKOUT_FREQ_2X_HF_MS_MAX CLKOUT_FREQ_DV_HF_MS_MIN CLKOUT_FREQ_DV_HF_MS_MAX CLKOUT_FREQ_FX_HF_MS_MIN CLKOUT_FREQ_FX_HF_MS_MAX DS680 (v2.0) April 12, 2010 Product Specification CLK0, CLK90, CLK180, CLK270 CLK2X, CLK2X180 CLKDV CLKFX, CLKFX180 www.xilinx.com 27 R Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics Table 39: Operating Frequency Ranges for DCM in Maximum Speed (MS) Mode (Cont'd) Symbol Speed Grade Description -10 Units Input Clocks (High Frequency Mode) CLKIN_FREQ_DLL_HF_MS_MIN CLKIN_FREQ_DLL_HF_MS_MAX CLKIN_FREQ_FX_HF_MS_MIN CLKIN_FREQ_FX_HF_MS_MAX PSCLK_FREQ_HF_MS_MIN PSCLK_FREQ_HF_MS_MAX CLKIN (using DLL outputs)(1,3,4) CLKIN (using DFS outputs only)(2,3,4) PSCLK 150 MHz 400 MHz 50 MHz 300 MHz 1 KHz 400 MHz Notes: 1. 2. 3. 4. 5. DLL outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. DFS outputs are used in these instances to describe the outputs: CLKFX and CLKFX180. When using the DCMs CLKIN_DIVIDE_BY_2 attribute these values should be doubled. When using a CLKIN frequency > 400 MHz and the DCMs CLKIN_DIVIDE_BY_2 attribute, the CLKIN duty cycle must be within 5% (45/55 to 55/45). The DCM must be reset if the clock input clock stops for more than 100 ms. Table 40: Input Clock Duty Cycle Input Tolerance Symbol CLKIN_PSCLK_PULSE_RANGE_1 Description Frequency Range Value Units < 1 MHz 25 - 75 % PSCLK only CLKIN_PSCLK_PULSE_RANGE_1_50 CLKIN_PSCLK_PULSE_RANGE_50_100 CLKIN_PSCLK_PULSE_RANGE_100_200 PSCLK and CLKIN CLKIN_PSCLK_PULSE_RANGE_200_400 1 - 50 MHz 25 - 75 % 50 - 100 MHz 30 - 70 % 100 - 200 MHz 40 - 60 % 200 - 400 MHz 45 - 55 % Table 41: Input Clock Tolerances Symbol Description Speed Grade -10 Units Input Clock Cycle-Cycle Jitter (Low Frequency Mode) CLKIN (using DLL outputs)(1) 300 ps outputs)(2) 300 ps CLKIN (using DLL outputs)(1) 150 ps outputs)(2) 150 ps CLKIN (using DLL outputs)(1) 1.0 ns outputs)(2) 1.0 ns CLKIN_PER_JITT_DLL_HF CLKIN (using DLL outputs)(1) 1.0 ns CLKIN_PER_JITT_FX_HF CLKIN (using DFS outputs)(2) 1.0 ns CLKFB off-chip feedback 1.0 ns CLKIN_CYC_JITT_DLL_LF CLKIN_CYC_JITT_FX_LF CLKIN (using DFS Input Clock Cycle-Cycle Jitter (High Frequency Mode) CLKIN_CYC_JITT_DLL_HF CLKIN_CYC_JITT_FX_HF CLKIN (using DFS Input Clock Period Jitter (Low Frequency Mode) CLKIN_PER_JITT_DLL_LF CLKIN_PER_JITT_FX_LF CLKIN (using DFS Input Clock Period Jitter (High Frequency Mode) Feedback Clock Path Delay Variation CLKFB_DELAY_VAR_EXT Notes: 1. 2. 3. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180. If both DLL and DFS outputs are used, follow the more restrictive specifications. DS680 (v2.0) April 12, 2010 Product Specification www.xilinx.com 28 R Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics Output Clock Jitter Table 42: Output Clock Jitter Description Symbol Speed Grade -10 Units Clock Synthesis Period Jitter CLK0 CLKOUT_PER_JITT_0 100 ps CLK90 CLKOUT_PER_JITT_90 150 ps CLK180 CLKOUT_PER_JITT_180 150 ps CLK270 CLKOUT_PER_JITT_270 150 ps CLK2X, CLK2X180 CLKOUT_PER_JITT_2X 200 ps CLKDV (integer division) CLKOUT_PER_JITT_DV1 150 ps CLKDV (non-integer division) CLKOUT_PER_JITT_DV2 300 ps CLKFX, CLKFX180 CLKOUT_PER_JITT_FX Note 1 ps Notes: 1. Values for this parameter are available at www.xilinx.com. DS680 (v2.0) April 12, 2010 Product Specification www.xilinx.com 29 R Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics Output Clock Phase Alignment Table 43: Output Clock Phase Alignment Description Symbol Speed Grade -10 Units Phase Offset Between CLKIN and CLKFB CLKIN / CLKFB CLKIN_CLKFB_PHASE 120 ps CLKOUT_PHASE 200 ps CLKOUT_DUTY_CYCLE_DLL(3,4) 150 ps CLKOUT_DUTY_CYCLE_FX(4) 250 ps Phase Offset Between Any DCM Outputs All CLK outputs Duty Cycle Precision DLL outputs(1) DFS outputs(2) Notes: 1. 2. 3. 4. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180. CLKOUT_DUTY_CYCLE_DLL applies to the 1X clock outputs (CLK0, CLK90, CLK180, and CLK270) only if DUTY_CYCLE_CORRECTION=TRUE. The measured value includes the duty cycle distortion of the global clock tree. Table 44: Miscellaneous Timing Parameters Symbol Description Speed Grade -10 Units Time Required to Achieve LOCK T_LOCK_DLL_240 DLL output - Frequency range > 240 MHz(1) 20 s T_LOCK_DLL_120_240 DLL output - Frequency range 120 - 240 MHz(1) 63 s T_LOCK_DLL_60_120 DLL output - Frequency range 60 - 120 MHz(1) 225 s T_LOCK_DLL_50_60 DLL output - Frequency range 50 - 60 MHz(1) 325 s T_LOCK_DLL_40_50 DLL output - Frequency range 40 - 50 MHz(1) 500 s T_LOCK_DLL_30_40 DLL output - Frequency range 30 - 40 MHz(1) 900 s T_LOCK_DLL_24_30 DLL output - Frequency range 24 - 30 MHz(1) 1250 s T_LOCK_DLL_30 DLL output - Frequency range < 30 MHz(1) 1250 s 10 ms 10 ms Multiplication factor for DLL lock time with Fine Shift 2 - Absolute shifting range in maximum speed mode 7 ns DCM_TAP_MS_MIN Tap delay resolution (Min) in maximum speed mode 5 ps DCM_TAP_MS_MAX Tap delay resolution (Max) in maximum speed mode 40 ps T_LOCK_FX_MIN T_LOCK_FX_MAX T_LOCK_DLL_FINE_SHIFT DFS outputs(2) Fine Phase Shifting FINE_SHIFT_RANGE_MS Delay Lines DS680 (v2.0) April 12, 2010 Product Specification www.xilinx.com 30 R Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics Table 44: Miscellaneous Timing Parameters (Cont'd) Symbol Speed Grade Description -10 Units Input Signal Requirements Minimum duration that RST must be held asserted DCM_RESET(3) Maximum duration that RST can be held DCM_INPUT_CLOCK_STOP asserted(4) Maximum duration that CLKIN and CLKFB can be stopped(5,6) 200 ms 10 sec 100 ms Notes: 1. 2. 3. 4. 5. 6. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180. CLKIN must be present and stable during the DCM_RESET. This only applies to production step 1 LX and SX devices. For these devices, use the design solutions described in answer record 21127 for support of longer reset durations. Production step 2 LX and SX devices and all production FX devices do not have this requirement. For production step 1 LX and SX devices, use the design solutions described in answer record 21127 for support of longer durations of stopped clocks. For production step 2 LX and SX devices and all production FX devices, the ISE software automatically inserts a small macro to support longer durations of stopped clocks. For all stepping levels, once the input clock is toggling again and stable after being stopped, DCM must be reset. Table 45: Frequency Synthesis Attribute Min Max CLKFX_MULTIPLY 2 32 CLKFX_DIVIDE 1 32 Table 46: DCM Switching Characteristics Symbol Description Speed Grade -10 Units TDMCCK_PSEN / TDMCKC_PSEN PSEN setup/hold 1.07/0.00 ns TDMCCK_PSINCDEC / TDMCKC_PSINCDEC PSINCDEC setup/hold 1.07/0.00 ns TDMCKO_PSDONE Clock to out of PSDONE 0.69 ns Table 47: PMCD Switching Characteristic Symbol Description TPMCCCK_REL / TPMCCKC_REL REL setup/hold for all outputs Speed Grade -10 0.60/0.00 Units ns TPMCCO_CLK{A1,B,C,D} RST assertion to clock output deassertion 4.50 ns TPMCCKO_CLK{A1,B,C,D} Max clock propagation delay of PMCD for all outputs 5.20 ns PMCD_CLK_SKEW Max phase between all outputs assuming all inputs 150 ps CLKIN_FREQ_PMCD_CLKA_MAX Max input/output frequency 400 MHz Note(1) CLKIN_PSCLK_PULSE_RANGE Max duty-cycle input tolerance (same as DCM) PMCD_REL_HIGH_PULSE_MIN Min pulse width for REL 1.25 ns PMCD_RST_HIGH_PULSE_MIN Min pulse width for RST 1.25 ns Notes: 1. Refer to Table 40, page 28 parameter: CLKIN_PSCLK_PULSE_RANGE. DS680 (v2.0) April 12, 2010 Product Specification www.xilinx.com 31 R Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics System-Synchronous Switching Characteristics Virtex-4QV FPGA Pin-to-Pin Output Parameter Guidelines All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are listed in Table 48. Values are expressed in nanoseconds unless otherwise noted. Table 48: Global Clock Input-to-Output Delay for LVCMOS25, 12 mA, Fast Slew Rate, With DCM Symbol Description Device Speed Grade -10 Units LVCMOS25 Global Clock Input-to-Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM.(3) TICKOFDCM Global Clock and OFF with DCM XQR4VSX55 4.14 ns XQR4VFX60 3.96 ns XQR4VFX140 4.59 ns XQR4VLX200 4.46 ns Notes: 1. 2. 3. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. DCM output jitter is already included in the timing calculation. Clock to out has +320 ps offset for operation above 100 C. Table 49: Global Clock Input-to-Output Delay for LVCMOS25, 12 mA, Fast Slew Rate, Without DCM Symbol Description Device Speed Grade -10 Units LVCMOS25 Global Clock Input-to-Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, without DCM.(2) TICKOF Global Clock and OFF without DCM XQR4VSX55 9.54 ns XQR4VFX60 9.11 ns XQR4VFX140 10.02 ns XQR4VLX200 10.14 ns Notes: 1. 2. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net. Clock to out has +250 ps offset for operation above 100 C DS680 (v2.0) April 12, 2010 Product Specification www.xilinx.com 32 R Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics Virtex-4QV FPGA Pin-to-Pin Input Parameter Guidelines All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are listed in Table 50. Values are expressed in nanoseconds unless otherwise noted. Table 50: Global Clock Setup and Hold for LVCMOS25 Standard, With DCM Symbol Description Device Speed Grade -10 Units Input Setup-and-Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1,4) TPSDCM / TPHDCM No Delay Global Clock and IFF with DCM(2) XQR4VSX55 1.73/-0.13 ns XQR4VFX60 1.53/0.12 ns XQR4VFX140 1.52/0.82 ns XQR4VLX200 1.76/0.41 ns Notes: 1. 2. 3. 4. Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the Global Clock input signal with the slowest route and heaviest load. These measurements include: CLK0 DCM jitter IFF = input flip-flop or latch Use IBIS to determine any duty-cycle distortion incurred using various standards. Hold time has +200 ps offset for operation above 100 C. Table 51: Global Clock Setup and Hold for LVCMOS25 Standard, With DCM in Source-Synchronous Mode Symbol Description Device Speed Grade -10 Units Example Data Input Setup-and-hold Times Relative to a Forwarded Clock Input Pin, Using DCM and Global Clock Buffer.(1,3,4) TPSDCM_0 /TPHDCM_0 No Delay Global Clock and IFF with DCM in Source-Synchronous Mode(2) XQR4VSX55 -0.09/1.52 ns XQR4VFX60 -0.25/1.77 ns XQR4VFX140 -0.32/2.56 ns XQR4VLX200 0.00/2.06 ns Notes: 1. 2. 3. 4. The timing values were measured using the fine-phase adjustment feature of the DCM. These measurements include CLK0 DCM jitter. Package skew is not included in these measurements. IFF = input flip-flop For situations where clock and data inputs conform to different standards, adjust the setup and hold values accordingly using the values shown in "IOB Switching Characteristics(1,2)," page 11. Setup time has +100 ps offset for operation above 100 C. Table 52: Global Clock Setup and Hold for LVCMOS25 Standard, Without DCM Symbol Description Device Speed Grade -10 Units Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.(1) TPSFD /TPHFD Full Delay Global Clock and IFF without DCM(2) XQR4VSX55 3.02/0.98 ns XQR4VFX60 3.58/0.62 ns XQR4VFX140 3.51/1.71 ns XQR4VLX200 4.32/0.82 ns Notes: 1. 2. 3. Setup time is measured relative to the global clock input signal with the fastest route and the lightest load. Hold time is measured relative to the global clock input signal with the slowest route and heaviest load. IFF = input flip-flop or latch A zero "0" hold time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed best-case, but if a "0" is listed, there is no positive hold time. DS680 (v2.0) April 12, 2010 Product Specification www.xilinx.com 33 R Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics ChipSync Source-Synchronous Technology Switching Characteristics The parameters in this section provide the necessary values for calculating timing budgets for Virtex-4QV FPGA source-synchronous transmitter and receiver data-valid windows. Table 53: Duty Cycle Distortion and Clock-Tree Skew Symbol Description Device Global Clock Tree Duty Cycle Distortion(1) TDCD_CLK Speed Grade -10 Units All 150 ps XQR4VSX55 190 ps XQR4VFX60 190 ps XQR4VFX140 350 ps XQR4VLX200 350 ps I/O clock tree duty cycle distortion All 100 ps I/O clock tree skew across one clock region All 50 ps TBUFIOSKEW I/O clock tree skew across multiple clock regions All 50 ps TDCD_BUFR Regional clock tree duty cycle distortion All 250 ps TBUFIO_MAX_FREQ I/O clock tree MAX frequency All 500 MHz TBUFR_MAX_FREQ Regional clock tree MAX frequency All 250 MHz Global Clock Tree Skew(2) TCKSKEW TDCD_BUFIO Notes: 1. 2. These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For cases where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times. The TCKSKEW value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor and Timing Analyzer tools to evaluate clock skew specific to the application. Table 54: Sample Window Symbol Description Device Speed Grade -10 Units TSAMP Sampling Error at Receiver Pins(1) All 550 ps TSAMP_BUFIO Sampling Error at Receiver Pins using BUFIO(2) All 450 ps Notes: 1. 2. This parameter indicates the total sampling error of Virtex-4 FPGA DDR input registers across voltage, temperature, and process. The characterization methodology uses the DCM to capture the DDR input registers' edges of operation. These measurements include: - CLK0 DCM jitter - DCM accuracy (phase offset) - DCM phase shift resolution These measurements do not include package or clock tree skew. This parameter indicates the total sampling error of Virtex-4 FPGA DDR input registers across voltage, temperature, and process. The characterization methodology uses the BUFIO clock network and IDELAY to capture the DDR input registers' edges of operation. These measurements do not include package or clock tree skew. Table 55: ChipSyncTM Technology Pin-to-Pin Setup/Hold and Clock to Out Symbol Description Speed Grade -10 Units Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO TPSCS / TPHCS Setup/hold of I/O clock across multiple clock regions -0.44/1.17 ns 5.02 ns Pin-to-Pin Clock to Out Using BUFIO TICKOFCS DS680 (v2.0) April 12, 2010 Product Specification Clock-to-Out of I/O clock across multiple clock regions www.xilinx.com 34 R Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics Production Stepping The Virtex-4 FPGA stepping identification system denotes the capability improvement of production released devices. By definition, devices from one stepping are functional supersets of previous devices. Bitstreams compiled for a device with an earlier stepping are guaranteed to operate correctly in subsequent device steppings. New device steppings can be shipped in place of earlier device steppings. Existing production designs are guaranteed on new device steppings. To take advantage of the capabilities of a newer device stepping, customers are able to order a new stepping version and compile a new bitstream. This parameter is set in the UCF file: CONFIG STEPPING = "#"; Where # = the stepping version Table 56 shows the JTAG ID code by step. Table 56: JTAG ID Code by Step Production devices are marked with a stepping version, with the exception of some step 1 devices. Designs should be compiled with a CONFIG STEPPING parameter set to a specific stepping version. Device ID Code Stepping XQR4VSX55 4 2 XQ4RVFX60 8 1 XQR4VFX140 4 1 XQR4VLX200 2 or 5 0 or 3 Current Production Virtex-4 FPGA Devices Table 57 summarizes the current production device stepping. Table 57: Current Production Devices Device Stepping Step 2 Example Ordering Code XQR4VFX60-CF1144V Device steppings shipped when ordered per Example Ordering Code Step 1 or 2 only (see Table 56) Capability Improvements * TCONFIG requirement is removed * DCM_RESET requirement is removed * DCM_INPUT_CLOCK_STOP requirement is removed by a macro (automatically inserted by ISE software) CONFIG STEPPING parameter (must be set in UCF file) "1" Minimum Software Required ISE 7.1i SP4 Minimum Speed Specification Required 1.58 DS680 (v2.0) April 12, 2010 Product Specification www.xilinx.com 35 R Space-Grade Virtex-4QV FPGAs: DC and Switching Characteristics Revision History The following table shows the revision history for this document. Date Version Revisions 03/28/08 1.0 Initial Xilinx release. 12/16/08 1.1 Changed occurrences of "hardened" to "tolerant". 04/12/10 2.0 Changed document classification from Preliminary Product Specification to Product Specification. Changed product title to "Space-Grade Virtex-4QV FPGAs" and changed product name to "Virtex-4QV FPGA" throughout document. In the first paragraph of "Virtex-4QV FPGA Electrical Characteristics," added "radiation-tolerant" to the description of the Virtex-4QV FPGA. In Table 12, removed table notes referring to obsolete application notes. Added values for XQR4VFX140 device to Table 13, Table 48, Table 49, Table 50, Table 51, Table 52, Table 53, and Table 56. Added Critical Applications disclaimer. Notice of Disclaimer THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS") ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. 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TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW, CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN CRITICAL APPLICATIONS. DS680 (v2.0) April 12, 2010 Product Specification www.xilinx.com 36