1. General description
The 74HC595-Q100 ; 74HCT595-Q100 are high-speed Si-gate CM OS devices and are pin
compatible with Low- power Schottky TT L (L STTL). They are specified in compliance with
JEDEC standard No. 7A.
The 74HC595-Q100; 74HCT595-Q100 are 8-stage serial shift registers with a storage
register and 3-state outputs. The register s have separate clocks. Data is shifted on the
positive-going transitions of the shift register clock input (SHCP). The data in each register
is transferred to the storage register on a positive-going transition of the storage register
clock input (STCP). If both clocks are connected together, the shift register is always one
clock pulse ahead of the storage register.
The shift register has a serial input (DS) and a serial standard output (Q7S) for cascading.
It is also provided with asynchronou s reset (acti ve LOW) for all 8 shif t register st ages. The
storage register has 8 parallel 3-state bus driver o utputs. Data in the storage register
appears at the output whenever the output enable input (OE) is LOW.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
8-bit serial input
8-bit serial or parallel output
Storage register with 3-state outputs
Shift register with direct clear
100 MHz (typical) shift out frequency
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
3. Applications
Serial-to-parallel data conversion
Remote control holding register
74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output
latches; 3-state
Rev. 2 — 10 April 2013 Product data sheet
74HC_HCT595_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 10 April 2013 2 of 23
NXP Semiconductors 74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
4. Ordering information
5. Functional diagram
Table 1. Ordering information
Type number Package
Tempe rature range Name Description Version
74HC595D-Q100 40 C to +125 C SO16 plastic small outline package; 16 leads;
body width 3.9 mm SOT109-1
74HCT595D-Q100
74HC595DB-Q100 40 C to +125 C SSOP16 plastic shrink small out li n e package; 16 lead s;
body width 5.3 mm SOT338-1
74HCT595DB-Q100
74HC595PW-Q100 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads;
body wid th 4.4 mm SOT403-1
74HCT595PW-Q100
74HC595BQ-Q100 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads;
16 terminals; body 2.5 3.5 0.85 mm
SOT763-1
74HCT595BQ-Q100
Fig 1. Functional di agram
mna554
3-STATE OUTPUTS
8-BIT STORAGE REGISTER
8-STAGE SHIFT REGISTER
Q0Q1Q2Q3Q4Q5Q6Q7
Q7S
14
151234567
9
DS
SHCP
STCP
OE
11
10
12
13
MR
74HC_HCT595_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 10 April 2013 3 of 23
NXP Semiconductors 74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
Fig 2. Logic symbol Fig 3. IEC logic symbol
OEMR
9
15
1
2
3
4
5
6
7
1310
14
11 12
mna552
Q1
Q0
Q2
Q3
Q4
Q5
Q6
Q7
Q7S
DS
STCP
SHCP
mna553
15
9
1
2
3
4
5
6
7
1D 2D
C1/
10
11
14
C2
12
13 EN3
SRG8
R
3
Fig 4. Logic diagram
STAGE 0 STAGES 1 TO 6 STAGE 7
FF0
D
CP
Q
R
LATCH
D
CP
Q
FF7
D
CP
Q
R
LATCH
D
CP
Q
mna555
DQ
Q1Q2Q3Q4Q5Q6Q7
Q7S
Q0
DS
STCP
SHCP
OE
MR
74HC_HCT595_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 10 April 2013 4 of 23
NXP Semiconductors 74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
6. Pinning information
6.1 Pinning
Fig 5. Pin configuration SO16 Fig 6. Pin configuration (T)SSOP16
+&4
+&74
4
9
&
&
4
4
4
'
6
4
2
(
4
67&3
4
6+&3
4
0
5
*1' 46
DDD







+&4
+&74
49
&&
44
4'6
42(
4 67&3
4 6+&3
405
*1' 46
DDD







(1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or
mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to
GND.
Fig 7. Pin configuration for DHVQFN16

+&4
+&74
4 05
4 6+&3
4 67&3
4 2(
4 '6
4 4
*1'
46
4
9&&
7UDQVSDUHQWWRSYLHZ







WHUPLQDO
LQGH[DUHD
*1'
74HC_HCT595_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 10 April 2013 5 of 23
NXP Semiconductors 74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
6.2 Pin description
7. Functional description
[1] H = HIGH voltage state;
L = LOW voltage state;
= LOW-to-HIGH transition;
X = don’t care;
NC = no change;
Z = high-impedance OFF-state.
Table 2. Pin description
Symbol Pin Description
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 15, 1, 2, 3, 4, 5, 6, 7 parallel data output
GND 8 ground (0 V)
Q7S 9 serial data output
MR 10 master reset (active LOW)
SHCP 11 shift register clock input
STCP 12 storage regist er cl ock input
OE 13 output enable input (acti v e LOW)
DS 14 serial data input
VCC 16 supply voltage
Table 3. Function table[1]
Control Input Output Function
SHCP STCP OE MR DS Q7S Qn
X X L L X L NC a LOW-level on MR only affects the shift registers
XL L X L L empty shift register loaded into storage register
X X H L X L Z shift register clear; parallel outputs in high-impedance OFF-state
X L H H Q6S NC logic HIGH-level shifted into shift register stage 0. Contents of all
shift register stages shifted through, e.g. previous state of stage 6
(internal Q6S) appears on the serial output (Q7S).
XL H X NC QnS contents of shift register stages (internal QnS) are transferred to
the storage register and parallel output stages
L H X Q6S QnS contents of shift re gi st er sh ifted through; previous content s of the
shift register is transferred to the storage register and the parallel
output stages
74HC_HCT595_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 10 April 2013 6 of 23
NXP Semiconductors 74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
8. Limiting values
[1] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
[2] For (T)SSOP16 package: Ptot derates linearly with 5.5 mW/K above 60 C.
[3] For DHVQFN16 package: Ptot derates linearly with 4.5 mW/K above 60 C.
Fig 8. Timing diagram
SHCP
DS
STCP
MR
OE
Q0
Q1
Q6
Q7
Q7S
Z-state
Z-state
Z-state
Z-state
mna556
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI>V
CC + 0.5 V - 20 mA
IOK output clamping current VO<0.5 V or VO > VCC + 0.5 V - 20 mA
IOoutput current VO=0.5 V to (VCC +0.5V)
pin Q7S - 25 mA
pins Qn - 35 mA
ICC supply current - 70 mA
IGND ground current 70 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation
SO16 package [1] - 500 mW
(T)SSOP16 package [2] - 500 mW
DHVQFN16 package [3] - 500 mW
74HC_HCT595_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 10 April 2013 7 of 23
NXP Semiconductors 74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
9. Recommended operating conditions
10. Static characteristics
Table 5. Recommended operating con ditions
Symbol Parameter Conditions 74HC595-Q100 74HCT595-Q100 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VIinput voltage 0 - VCC 0-V
CC V
VOoutput voltage 0 - VCC 0-V
CC V
t/V input transition rise and
fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V
VCC = 6.0 V - - 83 - - - ns/V
Tamb ambient temperature 40 +25 +125 40 +25 +125 C
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max
74HC595-Q100
VIH HIGH-level
input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - V
VCC = 4.5 V 3.15 2.4 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - V
VIL LOW-level
input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 V
VCC = 4.5 V - 2.1 1.35 - 1.35 V
VCC = 6.0 V - 2.8 1.8 - 1.8 V
VOH HIGH-level
output voltage VI=V
IH or VIL
all outputs
IO=20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - V
IO=20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - V
IO=20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - V
Q7S output
IO=4mA; V
CC = 4.5 V 3.84 4.32 - 3.7 - V
IO=5.2 mA; VCC = 6.0 V 5.34 5.81 - 5.2 - V
Qn bus driver outputs
IO=6mA; V
CC = 4.5 V 3.84 4.32 - 3.7 - V
IO=7.8 mA; VCC = 6.0 V 5.34 5.81 - 5.2 - V
74HC_HCT595_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 10 April 2013 8 of 23
NXP Semiconductors 74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
VOL LOW-level
output voltage VI=V
IH or VIL
all outputs
IO=20A; VCC = 2.0 V - 0 0.1 - 0.1 V
IO=20A; VCC = 4.5 V - 0 0.1 - 0.1 V
IO=20A; VCC = 6.0 V - 0 0.1 - 0.1 V
Q7S output
IO=4mA; V
CC = 4.5 V - 0.15 0.33 - 0.4 V
IO=5.2mA; V
CC = 6.0 V - 0.16 0.33 - 0.4 V
Qn bus driver outputs
IO=6mA; V
CC = 4.5 V - 0.15 0.33 - 0.4 V
IO=7.8mA; V
CC = 6.0 V - 0.16 0.33 - 0.4 V
IIinput leakage
current VI=V
CC or GND; VCC =6.0V - - 1.0 - 1.0 A
IOZ OFF-state
output current VI=V
IH or VIL; VCC =6.0V;
VO=V
CC or GND --5.0 - 10 A
ICC supply current VI=V
CC or GND; IO=0A;
VCC =6.0V - - 80 - 160 A
CIinput
capacitance -3.5- - -pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max
74HC_HCT595_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 10 April 2013 9 of 23
NXP Semiconductors 74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
74HCT595-Q100
VIH HIGH-level
input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - V
VIL LOW-level
input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 V
VOH HIGH-level
output voltage VI=V
IH or VIL; VCC =4.5V
all outputs
IO=20 A 4.4 4.5 - 4.4 - V
Q7S output
IO=4 mA 3.84 4.32 - 3.7 - V
Qn bus driver outputs
IO=6 mA 3.7 4.32 - 3.7 - V
VOL LOW-level
output voltage VI=V
IH or VIL; VCC =4.5V
all outputs
IO=20A - 0 0.1 - 0.1 V
Q7S output
IO= 4.0 mA - 0.15 0.33 - 0.4 V
Qn bus driver outputs
IO= 6.0 mA - 0.16 0.33 - 0.4 V
IIinput leakage
current VI=V
CC or GND; VCC =5.5V - - 1.0 - 1.0 A
IOZ OFF-state
output current VI=V
IH or VIL; VCC =5.5 V;
VO=V
CC or GND --5.0 - 10 A
ICC supply current VI=V
CC or GND; IO=0A;
VCC =5.5V - - 80 - 160 A
ICC additional
supply current per input pin; IO=0A; V
I=V
CC
2.1 V; other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
pins MR, SHCP, STCP, OE - 150 675 - 735 A
pin DS - 25 113 - 1 23 A
CIinput
capacitance -3.5- - -pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ Max Min Max
74HC_HCT595_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 10 April 2013 10 of 23
NXP Semiconductors 74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
11. Dynamic characteristics
Table 7. Dy namic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 14.
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max Min Max
74HC595-Q100
tpd propagation
delay SHCP to Q7S; see Figure 9 [2]
VCC = 2 V - 52 160 - 200 - 240 ns
VCC = 4.5 V - 19 32 - 40 - 48 ns
VCC = 6 V - 15 27 - 34 - 41 ns
STCP to Qn; see Figure 10 [2]
VCC = 2 V - 55 175 - 220 - 265 ns
VCC = 4.5 V - 20 35 - 44 - 53 ns
VCC = 6 V - 16 30 - 37 - 45 ns
MR to Q7S; see Figure 12 [3]
VCC = 2 V - 47 175 - 220 - 265 ns
VCC = 4.5 V - 17 35 - 44 - 53 ns
VCC = 6 V - 14 30 - 37 - 45 ns
ten enable time OE to Qn; see Figure 13 [4]
VCC = 2 V - 47 150 - 190 - 225 ns
VCC = 4.5 V - 17 30 - 38 - 45 ns
VCC = 6 V - 14 26 - 33 - 38 ns
tdis disable time OE to Qn; see Figure 13 [5]
VCC = 2 V - 41 150 - 190 - 225 ns
VCC = 4.5 V - 15 30 - 38 - 45 ns
VCC = 6 V - 12 27 - 33 - 38 ns
tWpulse width SHCP HIGH or LOW;
see Figure 9
VCC = 2 V 75 17 - 95 - 110 - ns
VCC = 4.5 V 15 6 - 19 - 22 - ns
VCC = 6 V 13 5 - 16 - 19 - ns
STCP HIGH or LOW;
see Figure 10
VCC = 2 V 75 11 - 95 - 110 - ns
VCC = 4.5 V 15 4 - 19 - 22 - ns
VCC = 6 V 13 3 - 16 - 19 - ns
MR LOW; see Figure 12
VCC = 2 V 75 17 - 95 - 110 - ns
VCC = 4.5 V 15 6 - 19 - 22 - ns
VCC = 6 V 13 5 - 16 - 19 - ns
74HC_HCT595_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 10 April 2013 11 of 23
NXP Semiconductors 74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
tsu set-up time DS to SHCP; see Figure 10
VCC = 2 V 50 11 - 65 - 75 - ns
VCC = 4.5 V 10 4 - 13 - 15 - ns
VCC = 6 V 9 3 - 11 - 13 - ns
SHCP to STCP;
see Figure 11
VCC = 2 V 75 22 - 95 - 110 - ns
VCC = 4.5 V 15 8 - 19 - 22 - ns
VCC = 6 V 13 7 - 16 - 19 - ns
thhold time DS to SHCP; see Figure 11
VCC = 2 V 3 6- 3 - 3 - ns
VCC = 4.5 V 3 2- 3 - 3 - ns
VCC = 6 V 3 2- 3 - 3 - ns
trec recovery
time MR to SHCP; see Figure 12
VCC = 2 V 50 19 - 65 - 75 - ns
VCC = 4.5 V 10 7- 13 - 15 - ns
VCC = 6 V 9 6- 11 - 13 - ns
fmax maximum
frequency SHCP or STCP;
see Figure 9 and Figure 10
VCC = 2 V 9 30 - 4.8 - 4 - MHz
VCC = 4.5 V 30 91 - 24 - 20 - MHz
VCC = 6 V 35 108 - 28 - 24 - MHz
CPD power
dissipation
capacitance
fi = 1 MHz; VI=GNDtoV
CC [6][7] -115- - - - - pF
74HCT595-Q100; VCC = 4.5 V to 5.5 V
tpd propagation
delay SHCP to Q7S; see Figure 9 [2] -2542- 53 - 63ns
STCP to Qn; see Figure 10 [2] -2440- 50 - 60ns
MR to Q7S; see Figure 12 [3] -2340- 50 - 60ns
ten enable time OE to Qn; see Figure 13 [4] -2135- 44 - 53ns
tdis disable time OE to Qn; see Figure 13 [5] -1830- 38 - 45ns
tWpulse width SHCP HIGH or LOW;
see Figure 9 16 6 - 20 - 24 - ns
STCP HIGH or LOW;
see Figure 10 16 5 - 20 - 24 - ns
MR LOW; see Figure 12 20 8 - 25 - 30 - ns
tsu set-up time DS to SHCP; see Figure 10 16 5 - 20 - 24 - ns
SHCP to STCP;
see Figure 11 16 8 - 20 - 24 - ns
thhold time DS to SHCP; see Figure 11 32- 3 - 3 - ns
Table 7. Dy namic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 14.
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max Min Max
74HC_HCT595_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 10 April 2013 12 of 23
NXP Semiconductors 74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
[1] Typical values are measured at nominal supply voltage.
[2] tpd is the same as tPHL and tPLH.
[3] tpd is the same as tPHL only.
[4] ten is the same as tPZL and tPZH.
[5] tdis is the same as tPLZ and tPHZ.
[6] CPD is used to determine the dynamic power dissipation (PDin W).
PD=C
PD VCC2fi+(CLVCC2fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
(CLVCC2fo) = sum of outputs;
CL= output load capacitance in pF;
VCC = supply voltage in V.
[7] All 9 out puts switching.
12. Waveforms
trec recovery
time MR to SHCP; see Figure 12 10 7- 13 - 15 - ns
fmax maximum
frequency SHCP and STCP;
see Figure 9 and Figure 10 30 52 - 24 - 20 - MHz
CPD power
dissipation
capacitance
fi = 1 MHz; VI=GNDtoV
CC [6][7] - 130 - - - - - pF
Table 7. Dy namic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 14.
Symbol Parameter Conditions 25 C40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max Min Max
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 9. Shift clock pulse, maximum frequency and input to output propagation delays
74HC_HCT595_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 10 April 2013 13 of 23
NXP Semiconductors 74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 10. Storage clock to output propagation delays
mna558
STCP input
Qn output
tPLH tPHL
tW
tsu 1/fmax
VM
VOH
VI
GND
VOL
VM
SHCP input
VI
GND
VM
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 11. Data set-up and hold times
mna560
GND
GND
t
h
t
su
t
h
t
su
V
M
V
M
V
M
V
I
V
OH
V
OL
V
I
Q7S output
SHCP input
DS input
74HC_HCT595_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 10 April 2013 14 of 23
NXP Semiconductors 74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 12. Master reset to output propagation delays
mna561
MR input
SHCP input
Q7S output
t
PHL
t
W
t
rec
V
M
V
OH
V
OL
V
I
GND
V
I
GND
V
M
V
M
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 13. Enable and disa ble times
msa697
tPLZ
tPHZ
outputs
disabled outputs
enabled
90 %
10 %
outputs
enabled
OE input VM
tPZL
tPZH
VM
VM
Qn output
LOW-to-OFF
OFF-to-LOW
Qn output
HIGH-to-OFF
OFF-to-HIGH
trtf
90 %
10 %
Table 8. Measurement points
Type Input Output
VMVM
74HC595-Q100 0.5VCC 0.5VCC
74HCT595-Q100 1.3 V 1.3 V
74HC_HCT595_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 10 April 2013 15 of 23
NXP Semiconductors 74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
Test data is given in Table 9.
Definitions for test circuit:
CL = load capacitance including jig and probe capacitance.
RL = load resistance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
S1 = test selection switch.
Fig 14. Test circuit for measuring switching times
V
M
V
M
t
W
t
W
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
t
f
t
r
t
r
t
f
001aad983
DUT
V
CC
V
CC
VIVO
RT
RLS1
CL
open
G
Table 9. Test data
Type Input Load S1 position
VItr, tfCLRLtPHL, tPLH tPZH, tPHZ tPZL, tPLZ
74HC595-Q100 VCC 6 ns 50 pF 1 kopen GND VCC
74HCT595-Q100 3 V 6 ns 50 pF 1 kopen GND VCC
74HC_HCT595_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 10 April 2013 16 of 23
NXP Semiconductors 74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
13. Package outline
Fig 15. Package outline SOT109-1 (SO16)
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
8
9
1
16
y
pin 1 index
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 10.0
9.8 4.0
3.8 1.27 6.2
5.8 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT109-1 99-12-27
03-02-19
076E07 MS-012
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.39
0.38 0.16
0.15 0.05
1.05
0.041
0.244
0.228 0.028
0.020 0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
0 2.5 5 mm
scale
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
74HC_HCT595_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 10 April 2013 17 of 23
NXP Semiconductors 74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
Fig 16. Package outline SOT338-1 (SSOP16)
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.25 0.38
0.25 0.20
0.09 6.4
6.0 5.4
5.2 0.65 1.25
7.9
7.6 1.03
0.63 0.9
0.7 1.00
0.55 8
0
o
o
0.130.2 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT338-1 99-12-27
03-02-19
(1)
wM
bp
D
HE
E
Z
e
c
vMA
X
A
y
18
16 9
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
MO-150
pin 1 index
0 2.5 5 mm
scale
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
A
max.
2
74HC_HCT595_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 10 April 2013 18 of 23
NXP Semiconductors 74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
Fig 17. Package outline SOT403-1 (TSSOP16)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 5.1
4.9 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.40
0.06 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT403-1 MO-153 99-12-27
03-02-18
wM
bp
D
Z
e
0.25
18
16 9
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
A
max.
1.1
pin 1 index
74HC_HCT595_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 10 April 2013 19 of 23
NXP Semiconductors 74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
Fig 18. Package outline SOT763-1 (DHVQFN16)
terminal 1
index area
0.51
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 3.6
3.4
Dh
2.15
1.85
y1
2.6
2.4 1.15
0.85
e1
2.5
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT763-1 MO-241 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT763-1
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
16 terminals; body 2.5 x 3.5 x 0.85 mm
A(1)
max.
AA1c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
27
15 10
9
8
1
16
X
D
E
C
BA
terminal 1
index area
AC
CB
vM
wM
E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)
02-10-17
03-01-27
74HC_HCT595_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 10 April 2013 20 of 23
NXP Semiconductors 74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
14. Abbreviations
15. Revision history
Table 10. Abbreviations
Acronym Abbreviation
CMOS Complementary Metal Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
LSTTL Low-power Schottky Transistor-T ransistor Logic
MM Machine Model
MIL Military
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT595_Q10 0 v.2 20130410 Product data sheet - 74HC_HCT595_Q10 0 v.1
Modifications: •74HC595DB-Q100 and 74HCT595DB-Q100 added.
74HC_HCT595_Q10 0 v.1 20120802 Product data sheet - -
74HC_HCT595_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 10 April 2013 21 of 23
NXP Semiconductors 74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
16. Legal information
16.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device (s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specificatio n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond tho se described in the
Product data sheet.
16.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ ag gregate and cumulative l iability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless ot herwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, lif e-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications an d ther efo re su ch inclusi on a nd/or use is at the cu stome r's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applicati ons or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly object s to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet D evelopment This document contains data from the objective specification for product develop ment.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
74HC_HCT595_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 10 April 2013 22 of 23
NXP Semiconductors 74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
No offer to sell or license — Nothing in this document may be interpreted or
construed as an of fer to sell product s that is op en for accept ance or the grant ,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a docume nt is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
16.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
© NXP B.V. 2013. All rights re served.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 10 April 2013
Document identi fier: 74HC_HCT595_Q100
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
18. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
7 Functional description . . . . . . . . . . . . . . . . . . . 5
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
9 Recommended operating conditions. . . . . . . . 7
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
11 Dynamic characteristics . . . . . . . . . . . . . . . . . 10
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 20
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 20
16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 21
16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21
16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22
17 Contact information. . . . . . . . . . . . . . . . . . . . . 22
18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23