DS90LV110T
DS90LV110T 1 to 10 LVDS Data/Clock Distributor
Literature Number: SNOS522H
DS90LV110T
June 7, 2011
1 to 10 LVDS Data/Clock Distributor
General Description
DS90LV110 is a 1 to 10 data/clock distributor utilizing LVDS
(Low Voltage Differential Signaling) technology for low power,
high speed operation. Data paths are fully differential from
input to output for low noise generation and low pulse width
distortion. The design allows connection of 1 input to all 10
outputs. LVDS I/O enable high speed data transmission for
point-to-point interconnects. This device can be used as a
high speed differential 1 to 10 signal distribution / fanout re-
placing multi-drop bus applications for higher speed links with
improved signal quality. It can also be used for clock distribu-
tion up to 400MHz.
The DS90LV110 accepts LVDS signal levels, LVPECL levels
directly or PECL with attenuation networks.
The LVDS outputs can be put into TRI-STATE® by use of the
enable pin.
For more details, please refer to the Application Information
section of this datasheet.
Features
■Low jitter 800 Mbps fully differential data path
■145 ps (typ) of pk-pk jitter with PRBS = 223−1 data pattern
at 800 Mbps
■Single +3.3 V Supply
■Less than 413 mW (typ) total power dissipation
■Balanced output impedance
■Output channel-to-channel skew is 35ps (typ)
■Differential output voltage (VOD) is 320mV (typ) with
100Ω termination load.
■LVDS receiver inputs accept LVPECL signals
■Fast propagation delay of 2.8 ns (typ)
■Receiver input threshold < ±100 mV
■28 lead TSSOP package
■Conforms to ANSI/TIA/EIA-644 LVDS standard
Connection Diagram
10133705
Order Number DS90LV110TMTC
See NS Package Number MTC28
Block Diagram
10133701
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2011 National Semiconductor Corporation 101337 www.national.com
DS90LV110T 1 to 10 LVDS Data/Clock Distributor
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VDD-VSS)−0.3V to +4V
LVCMOS/LVTTL Input Voltage
(EN) −0.3V to (VCC + 0.3V)
LVDS Receiver Input Voltage (IN
+, IN−) −0.3V to +4V
LVDS Driver Output Voltage (OUT
+, OUT−) −0.3V to +4V
Junction Temperature +150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature
(Soldering, 4 sec.) +260°C
Maximum Package Power Dissipation at 25°C
28L TSSOP 2.115 W
Package Derating
28L TSSOP 16.9 mW/°C above +25°C
θJA (4-Layer, 2 oz. Cu, JEDEC)
28L TSSOP 59.1 °C/Watt
ESD Rating:
(HBM, 1.5kΩ, 100pF) > 4 kV
(EIAJ, 0Ω, 200pF) > 250 V
Recommended Operating
Conditions
Min Typ Max Units
Supply Voltage (VDD - VSS) 3.0 3.3 3.6 V
Receiver Input Voltage 0 VDD V
Operating Free Air Temperature -40 +25 +85 °C
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol Parameter Conditions Min Typ Max Units
LVCMOS/LVTTL DC SPECIFICATIONS (EN)
VIH High Level Input Voltage 2.0 VDD V
VIL Low Level Input Voltage VSS 0.8 V
IIH High Level Input Current VIN = 3.6V or 2.0V; VDD = 3.6V ±7 ±20 μA
IIL Low Level Input Current VIN = 0V or 0.8V; VDD = 3.6V ±7 ±20 μA
VCL Input Clamp Voltage ICL = −18 mA −0.8 −1.5 V
LVDS OUTPUT DC SPECIFICATIONS (OUT1, OUT2, OUT3, OUT4, OUT5, OUT6, OUT7, OUT8, OUT9, OUT10)
VOD Differential Output Voltage RL = 100Ω 250 320 450 mV
RL = 100Ω, VDD = 3.3V, TA = 25°C 260 320 425 mV
ΔVOD Change in VOD between Complimentary Output States 35 |mV|
VOS Offset Voltage (Note 3) 1.125 1.25 1.375 V
ΔVOS Change in VOS between Complimentary Output States 35 |mV|
IOZ Output TRI-STATE Current EN = 0V, ±1 ±10 μA
VOUT = VDD or GND
IOFF Power-Off Leakage Current VDD = 0V; VOUT = 3.6V or GND ±1 ±10 μA
ISA,ISB Output Short Circuit Current VOUT+ OR VOUT− = 0V or VDD 12 24 |mA|
ISAB Both Outputs Shorted (Note 4) VOUT+ = VOUT− 6 12 |mA|
LVDS RECEIVER DC SPECIFICATIONS (IN)
VTH Differential Input High Threshold VCM = +0.05V or +1.2V or +3.25V, 0 +100 mV
VTL Differential Input Low Threshold VDD = 3.3V −100 0 mV
VCMR Common Mode Voltage Range VID = 100mV, VDD = 3.3V 0.05 3.25 V
IIN Input Current VIN = +3.0V, VDD = 3.6V or 0V ±1 ±10 μA
VIN = 0V, VDD = 3.6V or 0V ±1 ±10 μA
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DS90LV110T
Symbol Parameter Conditions Min Typ Max Units
SUPPLY CURRENT
ICCD Total Supply Current RL = 100Ω, CL = 5 pF, 400 MHz, 125 195 mA
EN = High
No Load, 400 MHz, EN = High 80 125 mA
ICCZ TRI-STATE Supply Current EN = Low 15 29 mA
Note 1: “Absolute Maximum Ratings” are these beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should
be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation.
Note 2: All typical are given for VCC = +3.3V and TA = +25°C, unless otherwise stated.
Note 3: VOS is defined as (VOH + VOL) / 2.
Note 4: Only one output can be shorted at a time. Don't exceed the package absolute maximum rating.
AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
TLHT Output Low-to-High Transition Time, 20% to 80%, Figure 4
(Note 5)
390 550 ps
THLT Output High-to-Low Transition Time, 80% to 20%, Figure 4
(Note 5)
390 550 ps
TDJ LVDS Data Jitter, Deterministic (Peak-to-
Peak)(Note 6)
VID = 300mV; PRBS=223-1 data; VCM
= 1.2V at 800 Mbps (NRZ)
145 ps
TRJ LVDS Clock Jitter, Random (Note 6) VID = 300mV; VCM = 1.2V
at 400 MHz clock
2.8 ps
TPLHD Propagation Low to High Delay, Figure 5 2.2 2.8 3.6 ns
TPHLD Propagation High to Low Delay, Figure 5 2.2 2.8 3.6 ns
TSKEW Pulse Skew |TPLHD - TPHLD| (Note 5) 20 340 ps
TCCS Output Channel-to-Channel Skew, Figure 6 (Note 5) 35 91 ps
TPHZ Disable Time (Active to TRI-STATE) High to Z, Figure 1 3.0 6.0 ns
TPLZ Disable Time (Active to TRI-STATE) Low to Z, Figure 1 1.8 6.0 ns
TPZH Enable Time (TRI-STATE to Active) Z to High, Figure 1 10.0 23.0 ns
TPZL Enable Time (TRI-STATE to Active) Z to Low, Figure 1 7.0 23.0 ns
Note 5: The parameters are guaranteed by design. The limits are based on statistical analysis of the device performance over PVT (process, voltage and
temperature) range.
Note 6: The measurement used the following equipment and test setup: HP8133A pattern/pulse generator), 5 feet of RG-142 cable with DUT test board and
HP83480A (digital scope mainframe) with HP83484A (50GHz scope module). The HP8133A with the RG-142 cable exhibit a TDJ = 26ps and TRJ = 1.3 ps
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DS90LV110T
AC Timing Diagrams
10133704
FIGURE 1. Output active to TRI-STATE and TRI-STATE to active output time
10133715
FIGURE 2. LVDS Driver TRI-STATE Circuit
10133706
FIGURE 3. LVDS Output Load
10133709
FIGURE 4. LVDS Output Transition Time
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DS90LV110T
10133707
FIGURE 5. Propagation Delay Low-to-High and High-to-Low
10133708
FIGURE 6. Output 1 to 10 Channel-to-Channel Skew
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DS90LV110T
DS90LV110 Pin Descriptions
Pin Name # of Pin Input/Output Description
IN+ 1 I Non-inverting LVDS input
IN - 1 I Inverting LVDS input
OUT+ 10 O Non-inverting LVDS Output
OUT - 10 O Inverting LVDS Output
EN 1 I This pin has an internal pull-down when left open. A logic
low on the Enable puts all the LVDS outputs into TRI-
STATE and reduces the supply current.
VSS 3 P Ground (all ground pins must be tied to the same supply)
VDD 2 P Power Supply (all power pins must be tied to the same
supply)
Application Information
INPUT FAIL-SAFE
The receiver inputs of the DS90LV110 do not have internal
fail-safe biasing. For point-to-point and multi-drop applica-
tions with a single source, fail-safe biasing may not be re-
quired. When the driver is off, the link is in-active. If fail-safe
biasing is required, this can be accomplished with external
high value resistors. The IN+ should be pull to Vcc with
10kΩ and the IN− should be pull to Gnd with 10kΩ. This pro-
vides a slight positive differential bias, and sets a known HIGH
state on the link with a minimum amount of distortion. See
AN-1194 for additional informations.
LVDS INPUTS TERMINATION
The LVDS Receiver input must have a 100Ω termination re-
sistor placed as close as possible across the input pins.
UNUSED CONTROL INPUTS
The EN control input pin has internal pull down device. If left
open, the 10 outputs will default to TRI-STATE.
EXPANDING THE NUMBER OF OUTPUT PORTS
To expand the number of output ports, more than one
DS90LV110 can be used. Total propagation delay through
the devices should be considered to determine the maximum
expansion. Adding more devices will increase the output jitter
due to each pass.
PCB LAYOUT AND POWER SYSTEM BYPASS
Circuit board layout and stack-up for the DS90LV110 should
be designed to provide noise-free power to the device. Good
layout practice also will separate high frequency or high level
inputs and outputs to minimize unwanted stray noise pickup,
feedback and interference. Power system performance may
be greatly improved by using thin dielectrics (4 to 10 mils) for
power/ground sandwiches. This increases the intrinsic ca-
pacitance of the PCB power system which improves power
supply filtering, especially at high frequencies, and makes the
value and placement of external bypass capacitors less criti-
cal. External bypass capacitors should include both RF ce-
ramic and tantalum electrolytic types. RF capacitors may use
values in the range 0.01 µF to 0.1 µF. Tantalum capacitors
may be in the range 2.2 µF to 10 µF. Voltage rating for tan-
talum capacitors should be at least 5X the power supply
voltage being used. It is recommended practice to use two
vias at each power pin of the DS90LV110 as well as all RF
bypass capacitor terminals. Dual vias reduce the interconnect
inductance by up to half, thereby reducing interconnect in-
ductance and extending the effective frequency range of the
bypass components.
The outer layers of the PCB may be flooded with additional
ground plane. These planes will improve shielding and isola-
tion as well as increase the intrinsic capacitance of the power
supply plane system. Naturally, to be effective, these planes
must be tied to the ground supply plane at frequent intervals
with vias. Frequent via placement also improves signal in-
tegrity on signal transmission lines by providing short paths
for image currents which reduces signal distortion. The
planes should be pulled back from all transmission lines and
component mounting pads a distance equal to the width of
the widest transmission line or the thickness of the dielectric
separating the transmission line from the internal power or
ground plane(s) whichever is greater. Doing so minimizes ef-
fects on transmission line impedances and reduces unwanted
parasitic capacitances at component mounting pads.
There are more common practices which should be followed
when designing PCBs for LVDS signaling. Please see Appli-
cation Note: AN-1108 for additional information.
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DS90LV110T
MULTI-DROP APPLICATIONS
10133702
POINT-TO-POINT DISTRIBUTION APPLICATIONS
10133703
For applications operating at data rate greater than 400Mbps,
a point-to-point distribution application should be used. This
improves signal quality compared to multi-drop applications
due to no stub PCB trace loading. The only load is a receiver
at the far end of the transmission line. Point-to-point distribu-
tion applications will have a wider LVDS bus lines, but data
rate can increase well above 400Mbps due to the improved
signal quality.
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DS90LV110T
Input Interfacing
The DS90LV110 accepts differential signals and allow simple
AC or DC coupling. With a wide common mode range, the
DS90LV110 can be DC-coupled with all common differential
drivers (i.e. LVPECL, LVDS, CML). The following three fig-
ures illustrate typical DC-coupled interface to common differ-
ential drivers.
10133741
Typical LVDS Driver DC-Coupled Interface to DS90LV110 Input
10133742
Typical CML Driver DC-Coupled Interface to DS90LV110 Input
10133743
Typical LVPECL Driver DC-Coupled Interface to DS90LV110 Input
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DS90LV110T
Output Interfacing
The DS90LV110 outputs signals that are compliant to the
LVDS standard. Their outputs can be DC-coupled to most
common differential receivers. The following figure illustrates
typical DC-coupled interface to common differential receivers
and assumes that the receivers have high impedance inputs.
While most differential receivers have a common mode input
range that can accomodate LVDS compliant signals, it is rec-
ommended to check respective receiver's data sheet prior to
implementing the suggested interface implementation.
10133744
Typical DS90LV110 Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver
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DS90LV110T
Typical Performance Characteristics
Output Voltage (VOD) vs. Resistive Load (RL)
10133711
Peak-to-Peak Output Jitter at VCM = +0.4V vs. VID
10133712
Peak-to-Peak Output Jitter at VCM = +1.2V vs. VID
10133713
Peak-to-Peak Output Jitter at VCM = +2.9V vs. VID
10133714
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DS90LV110T
Physical Dimensions inches (millimeters) unless otherwise noted
Order Number DS90LV110TMTC
See NS Package Number MTC28
11 www.national.com
DS90LV110T
Notes
DS90LV110T 1 to 10 LVDS Data/Clock Distributor
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