2013-2015 Microchip Technology Inc. DS40001723D-page 1
PIC12(L)F1571/2
Description:
PIC12(L)F1571/2 microcontrollers combine the capabilities of 16-bit PWMs with Analog to suit a variety of applications.
These devices deliver three 16-bit PWMs with independent timers for applications where high resolution is needed, such
as LED lighting, stepper motors, power supplies and other general purpose applications. The core independent
peripherals (16-bit PWMs, Complementary Waveform Generator), Enhanced Universal Synchronous Asynchronous
Receiver Transceiver (EUSART) and Analog (ADCs, Comparator and DAC) enable closed-loop feedback and
communication for use in multiple market segments. The EUSART peripheral enables the communication for
applications such as LIN.
Core Features:
• C Compiler Optimized RISC Architecture
• Only 49 Instructions
• Operating Speed:
- DC – 32 MHz clock input
- 125 ns minimum instruction cycle
• Interrupt Capability
• 16-Level Deep Hardware Stack
• Two 8-Bit Timers
• One 16-Bit Timer
• Three Additional 16-Bit Timers available using the
16-Bit PWMs
• Power-on Reset (POR)
• Power-up Timer (PWRT)
• Low-Power Brown-out Reset (LPBOR)
• Programmable Watchdog Timer (WDT) up to 256s
• Programmable Code Protection
Memory:
• Up to 3.5 Kbytes Flash Program Memory
• Up to 256 Bytes Data SRAM Memory
• Direct, Indirect and Relative Addressing modes
• High-Endurance Flash Data Memory (HEF)
- 128 bytes if nonvolatile data storage
- 100k erase/write cycles
Operating Characteristics:
• Operating Voltage Range:
- 1.8V to 3.6V (PIC12LF1571/2)
- 2.3V to 5.5V (PIC12F1571/2)
• Temperature Range:
- Industrial: -40°C to +85°C
- Extended: -40°C to +125°C
• Internal Voltage Reference module
• In-Circuit Serial Programming™ (ICSP™) via
Two Pins
eXtreme Low-Power (XLP) Features:
• Sleep mode: 20 nA @ 1.8V, Typical
• Watchdog Timer: 260 nA @ 1.8V, Typical
• Operating Current:
-30 A/MHz @ 1.8V, typical
Digital Peripherals:
• 16-Bit PWM:
- Three 16-bit PWMs with independent timers
- Multiple Output modes (Edge-Aligned,
Center-Aligned, Set and Toggle on
Register Match)
- User settings for phase, duty cycle, period,
offset and polarity
- 16-bit timer capability
- Interrupts generated based on timer matches
with Offset, Duty Cycle, Period and Phase
registers
• Complementary Waveform Generator (CWG):
- Rising and falling edge dead-band control
- Multiple signal sources
• Enhanced Universal Synchronous Asynchronous
Receiver Transceiver (EUSART):
- Supports LIN applications
Device I/O Port Features:
• Six I/Os
• Individually Selectable Weak Pull-ups
• Interrupt-On-Change Pins Option with
Edge-Selectable Option
8-Pin MCU with High-Pr ecision 16-Bit PWMs
PIC12(L)F1571/2
DS40001723D-page 2 2013-2015 Microchip Technology Inc.
Analog Peripherals:
• 10-Bit Analog-to-Digital Converter (ADC):
- Up to four external channels
- Conversion available during Sleep
• Comparator:
- Low-Power/High-Speed modes
- Fixed Voltage Reference at (non)inverting
input(s)
- Comparator outputs externally accessible
- Synchronization with Timer1 clock source
- Software hysteresis enable
• 5-Bit Digital-to-Analog Converter (DAC):
- 5-bit resolution, rail-to-rail
- Positive reference selection
- Unbuffered I/O pin output
- Internal connections to ADCs and
comparators
• Voltage Reference:
- Fixed voltage reference with 1.024V, 2.048V
and 4.096V output levels
Clocking Structure:
• Precision Internal Oscillator:
- Factory calibrated ±1%, typical
- Software-selectable clock speeds from
31 kHz to 32 MHz
• External Oscillator Block with:
- Resonator modes up to 20 MHz
- Two External Clock modes up to 32 MHz
• Fail-Safe Clock Monitor
• Digital Oscillator Input Available
PIC12(L)F1571/2 FAMILY TYPES
Device
Data Sheet Index
Program Memory Flash
(K words)
Data SRAM (bytes)
High-Endurance
Flash (bytes)
I/O Pins
8-Bit/16-Bit Timers
Comparators
16-Bit PWM
10-Bit ADC (ch)
5-Bit DAC
CWG
EUSART
Debug(1)
XLP
PIC12(L)F1571 A1 128 128 6 2/4(2) 134110 IY
PIC12(L)F1572 A2256 128 62/4(2) 1 3 4 1 1 1 I Y
Note 1: I – Debugging integrated on chip.
2: Three additional 16-bit timers available when not using the 16-bit PWM outputs.
Data Sheet Index: (Unshaded devices are described in this document.)
ADS40001723 PIC12(L)F1571/2 Data Sheet, 8-Pin Flash, 8-Bit MCU with High-Precision 16-Bit PWM.
2013-2015 Microchip Technology Inc. DS40001723D-page 3
PIC12(L)F1571/2
PIN DIAGRAMS
Pin Diagram – 8-Pin PDIP, SOIC, DFN, MSOP, UDFN
Note: See Table 1 for location of all peripheral functions.
1
2
3
4
8
7
6
5
VDD
RA5
RA3/MCLR/VPP
VSS
RA0/ICSPDAT
RA1/ICSPCLK
RA2
RA4
PIC12(L)F1571
PIC12(L)F1572
TABLE 1: 8-PIN ALLOCATION TABLE (PIC12(L)F1571/2)
I/O
8-Pin PDIP/SOIC/MSOP/DFN/UDFN
ADC
Reference
Comparator
Timers
PWM
EUSART(2)
CWG
Interrupt
Pull-up
Basic
RA0 7AN0 DAC1OUT C1IN+ —PWM2 TX(2)
CK(2) CWG1B IOC YICSPDAT
ICDDAT
RA1 6AN1 VREF+C1IN0- —PWM1 RX(2)
DT(2) —IOC YICSPCLK
ICDCLK
RA2 5AN2 —C1OUT T0CKI PWM3 —CWG1FLT
CWG1A
IOC
INT
Y —
RA3 4 — — — T1G(1) — — — IOC YMCLR
VPP
RA4 3AN3 —C1IN1- T1G PWM2(1) TX(1,2)
CK(1,2) CWG1B(1) IOC YCLKOUT
RA5 2 — — — T1CKI PWM1(1) RX(1,2)
DT(1,2) CWG1A(1) IOC YCLKIN
VDD 1 — — — — — — — — — VDD
Vss 8 — — — — — — — — — VSS
Note 1: Alternate pin function selected with the APFCON (Register 11-1) register.
2: PIC12(L)F1572 only.
PIC12(L)F1571/2
DS40001723D-page 4 2013-2015 Microchip Technology Inc.
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 13
3.0 Memory Organization ................................................................................................................................................................. 15
4.0 Device Configuration .................................................................................................................................................................. 41
5.0 Oscillator Module........................................................................................................................................................................ 47
6.0 Resets ........................................................................................................................................................................................ 59
7.0 Interrupts .................................................................................................................................................................................... 69
8.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 83
9.0 Watchdog Timer (WDT) ............................................................................................................................................................. 87
10.0 Flash Program Memory Control ................................................................................................................................................. 91
11.0 I/O Ports ................................................................................................................................................................................... 109
12.0 Interrupt-On-Change ................................................................................................................................................................ 119
13.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 123
14.0 Temperature Indicator Module ................................................................................................................................................. 127
15.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 129
16.0 5-Bit Digital-to-Analog Converter (DAC) Module...................................................................................................................... 143
17.0 Comparator Module.................................................................................................................................................................. 147
18.0 Timer0 Module ......................................................................................................................................................................... 155
19.0 Timer1 Module with Gate Control............................................................................................................................................. 159
20.0 Timer2 Module ......................................................................................................................................................................... 171
21.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 175
22.0 16-Bit Pulse-Width Modulation (PWM) Module ........................................................................................................................ 203
23.0 Complementary Waveform Generator (CWG) Module ............................................................................................................ 231
24.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 243
25.0 Instruction Set Summary .......................................................................................................................................................... 245
26.0 Electrical Specifications............................................................................................................................................................ 259
27.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 283
28.0 Development Support............................................................................................................................................................... 305
29.0 Packaging Information.............................................................................................................................................................. 309
Appendix A: Data Sheet Revision History.......................................................................................................................................... 327
The Microchip Web Site ..................................................................................................................................................................... 329
Customer Change Notification Service .............................................................................................................................................. 329
Customer Support .............................................................................................................................................................................. 329
Product Identification System............................................................................................................................................................. 331
2013-2015 Microchip Technology Inc. DS40001723D-page 5
PIC12(L)F1571/2
TO OUR VALUED CUSTOMERS
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The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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PIC12(L)F1571/2
DS40001723D-page 6 2013-2015 Microchip Technology Inc.
NOTES:
2013-2015 Microchip Technology Inc. DS40001723D-page 7
PIC12(L)F1571/2
1.0 DEVICE OVERVIEW
The PIC12(L)F1571/2 devices are described within this
data sheet. The block diagram of these devices is shown
in Figure 1-1, the available peripherals are shown in
Table 1-1 and the pinout descriptions are shown in
Table 1-2.
1.1 Register and Bit Naming
Conventions
1.1.1 REGISTER NAMES
When there are multiple instances of the same
peripheral in a device, the peripheral control registers
will be depicted as the concatenation of a peripheral
identifier, peripheral instance and control identifier. The
control registers section will show just one instance of
all the register names with an ‘x’ in the place of the
peripheral instance number. This naming convention
may also be applied to peripherals when there is only
one instance of that peripheral in the device to maintain
compatibility with other devices in the family that
contain more than one.
1.1.2 BIT NAMES
There are two variants for bit names:
• Short name: Bit function abbreviation
• Long name: Peripheral abbreviation + short name
1.1.2.1 Short Bit Names
Short bit names are an abbreviation for the bit function.
For example, some peripherals are enabled with the
EN bit. The bit names shown in the registers are the
short name variant.
Short bit names are useful when accessing bits in C
programs. The general format for accessing bits by the
short name is RegisterNamebits.ShortName. For
example, the enable bit, EN, in the COG1CON0 regis-
ter can be set in C programs with the instruction,
COG1CON0bits.EN = 1.
Short names are generally not useful in assembly
programs because the same name may be used by
different peripherals in different bit positions. When this
occurs, during the include file generation, all instances
of that short bit name are appended with an
underscore, plus the name of the register in which the
bit resides, to avoid naming contentions.
TABLE 1-1: DEVICE PERIPHERAL
SUMMARY
Peripheral
PIC12(L)F1571
PIC12(L)F1572
Analog-to-Digital Converter (ADC) ●●
Complementary Wave Generator
(CWG)
●●
Digital-to-Analog Converter (DAC) ●●
Enhanced Universal
Synchronous/Asynchronous
Receiver/Transmitter (EUSART)
●
Fixed Voltage Reference (FVR) ●●
Temperature Indicator ●●
Comparators
C1 ● ●
PWM Modules
PWM1 ●●
PWM2 ●●
PWM3 ●●
Timers
Timer0 ●●
Timer1 ●●
Timer2 ●●
PIC12(L)F1571/2
DS40001723D-page 8 2013-2015 Microchip Technology Inc.
1.1.2.2 Long Bit Names
Long bit names are constructed by adding a peripheral
abbreviation prefix to the short name. The prefix is
unique to the peripheral, thereby making every long bit
name unique. The long bit name for the COG1 enable bit
is the COG1 prefix, G1, appended with the enable bit
short name, EN, resulting in the unique bit name G1EN.
Long bit names are useful in both C and assembly pro-
grams. For example, in C, the COG1CON0 enable bit
can be set with the G1EN = 1 instruction. In assembly,
this bit can be set with the BSF COG1CON0,G1EN
instruction.
1.1.2.3 Bit Fields
Bit fields are two or more adjacent bits in the same
register. Bit fields adhere only to the short bit naming
convention. For example, the three Least Significant
bits of the COG1CON0 register contain the mode
control bits. The short name for this field is MD. There
is no long bit name variant. Bit field access is only
possible in C programs. The following example
demonstrates a C program instruction for setting the
COG1 to the Push-Pull mode:
COG1CON0bits.MD = 0x5;
Individual bits in a bit field can also be accessed with
long and short bit names. Each bit is the field name
appended with the number of the bit position within the
field. For example, the Most Significant mode bit has
the short bit name, MD2, and the long bit name is
G1MD2. The following two examples demonstrate
assembly program sequences for setting the COG1 to
Push-Pull mode:
Example 1:
MOVLW ~(1<<G1MD1)
ANDWF COG1CON0,F
MOVLW 1<<G1MD2 | 1<<G1MD0
IORWF COG1CON0,F
Example 2:
BSF COG1CON0,G1MD2
BCF COG1CON0,G1MD1
BSF COG1CON0,G1MD0
1.1.3 REGISTER AND BIT NAMING
EXCEPTIONS
1.1.3.1 Status, Interrupt and Mirror Bits
Status, interrupt enables, interrupt flags and mirror bits
are contained in registers that span more than one
peripheral. In these cases, the bit name shown is
unique so there is no prefix or short name variant.
1.1.3.2 Legacy Peripherals
There are some peripherals that do not strictly adhere
to these naming conventions. Peripherals that have
existed for many years and are present in almost every
device are the exceptions. These exceptions were
necessary to limit the adverse impact of the new
conventions on legacy code. Peripherals that do
adhere to the new convention will include a table in the
registers section indicating the long name prefix for
each peripheral instance. Peripherals that fall into the
exception category will not have this table. These
peripherals include, but are not limited to, the following:
• EUSART
• MSSP
2013-2015 Microchip Technology Inc. DS40001723D-page 9
PIC12(L)F1571/2
FIGURE 1-1: PIC12(L)F1571/2 BLOCK DIAGRAM
Note 1: See applicable chapters for more information on peripherals.
2: See Table 1-1 for peripherals available on specific devices.
3: See Figure 2-1.
4: PIC12(L)F1572 only.
CLKOUT
CLKIN
RAM
CPU
(Note 3)
Timing
Generation
INTRC
Oscillator
MCLR
Program
Flash Memory
FVR
ADC
10-bit
Temp
Indicator
TMR0TMR1TMR2
PWM1PWM2PWM3CWG1
PORTA
Rev. 10-000039E
9/12/2013
DACC1
EUSART(4)
PIC12(L)F1571/2
DS40001723D-page 10 2013-2015 Microchip Technology Inc.
TABLE 1-2: PIC12(L)F1571/2 PINOUT DESCRIPTION
Name Function Input
Type
Output
Type Description
RA0/AN0/C1IN+/DACOUT/
TX(2)/CK(2)/CWG1B/PWM2/
ICSPDAT/ICDDAT
RA0
(3) (4)
General purpose I/O.
AN0 ADC channel input.
C1IN+ Comparator positive input.
DACOUT Digital-to-Analog Converter output.
TX USART asynchronous transmit.
CK USART synchronous clock.
CWG1B CWG complementary output.
PWM2 PWM output.
ICSPDAT ICSP™ data I/O.
ICDDAT In-circuit debug data.
RA1/AN1/VREF+/C1IN0-/RX(2)/
DT(2)/PWM1/ICSPCLK/ICDCLK
RA1
(3) (4)
General purpose I/O.
AN1 ADC channel input.
VREF+ ADC Voltage Reference input.
C1IN0- Comparator negative input.
RX USART asynchronous input.
DT USART synchronous data.
PWM1 PWM output.
ICSPCLK ICSP programming clock.
ICDCLK In-circuit debug clock.
RA2/AN2/C1OUT/T0CKI/
CWG1FLT/CWG1A/PWM3/INT
RA2
(3) (4)
General purpose I/O.
AN2 ADC channel input.
C1OUT Comparator output.
T0CKI Timer0 clock input.
CWG1FLT Complementary Waveform Generator Fault input.
CWG1A CWG complementary output.
PWM3 PWM output.
INT External interrupt.
RA3/VPP/T1G(1)/MCLR RA3
(3) (4)
General purpose input with IOC and WPU.
VPP Programming voltage.
T1G Timer1 gate input.
MCLR Master Clear with internal pull-up.
RA4/AN3/C1IN1-/T1G/TX(1,2)/
CK(1,2)/CWG1B(1)/PWM2(1)/
CLKOUT
RA4
(3) (4)
General purpose I/O.
AN3 ADC channel input.
C1IN1- Comparator negative input.
T1G Timer1 gate input.
TX USART asynchronous transmit.
CK USART synchronous clock.
CWG1B CWG complementary output.
PWM2 PWM output.
CLKOUT FOSC/4 output.
Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: Alternate pin function selected with the APFCON (Register 11-1) register.
2: PIC12(L)F1572 only.
3: Input type is selected by the port.
4: Output type is selected by the port.
2013-2015 Microchip Technology Inc. DS40001723D-page 11
PIC12(L)F1571/2
RA5/T1CKI/RX(1,2)/DT(1,2)/
CWG1A(1)/PWM1(1)/CLKIN
RA5
(3) (4)
General purpose I/O.
T1CKI Timer1 clock input.
RX USART asynchronous input.
DT USART synchronous data.
CWG1A CWG complementary output.
PWM1 PWM output.
CLKIN External Clock input (EC mode).
VDD VDD Power — Positive supply.
VSS VSS Power — Ground reference.
TABLE 1-2: PIC12(L)F1571/2 PINOUT DESCRIPTION (CONTINUED)
Name Function Input
Type
Output
Type Description
Legend: AN = Analog input or output CMOS= CMOS compatible input or output OD = Open-Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C
HV = High Voltage XTAL = Crystal levels
Note 1: Alternate pin function selected with the APFCON (Register 11-1) register.
2: PIC12(L)F1572 only.
3: Input type is selected by the port.
4: Output type is selected by the port.
PIC12(L)F1571/2
DS40001723D-page 12 2013-2015 Microchip Technology Inc.
NOTES:
2013-2015 Microchip Technology Inc. DS40001723D-page 13
PIC12(L)F1571/2
2.0 ENHANCED MID-RANGE CPU
This family of devices contains an enhanced mid-range
8-bit CPU core. The CPU has 49 instructions. Interrupt
capability includes automatic context saving. The
hardware stack is 16 levels deep and has Overflow and
Underflow Reset capability. Direct, Indirect and
Relative Addressing modes are available. Two File
Select Registers (FSRs) provide the ability to read
program and data memory.
• Automatic Interrupt Context Saving
• 16-Level Stack with Overflow and Underflow
• File Select Registers
• Instruction Set
FIGURE 2-1: CORE BLOCK DIAGRAM
15
15
15
15
8
8
8
12
14
7
5
3
Program Counter
MUX
Addr MUX
16-Level Stack
(15-bit)
Program Memory
Read (PMR)
Instruction Reg
Configuration
FSR0 Reg
FSR1 Reg
BSR Reg
STATUS Reg
RAM
WReg
Power-up
Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Instruction
Decode and
Control
Timing
Generation
Internal
Oscillator
Block
ALU
Flash
Program
Memory
MUX
Data Bus
Program
Bus
Direct Addr
Indirect
Addr
RAM Addr
CLKIN
CLKOUT
VDD VSS
Rev. 10-000055A
7/30/2013
12
12
PIC12(L)F1571/2
DS40001723D-page 14 2013-2015 Microchip Technology Inc.
2.1 Automatic Interrupt Context
Saving
During interrupts, certain registers are automatically
saved in shadow registers and restored when returning
from the interrupt. This saves stack space and user
code. See Section 7.5 “Automatic Context Saving”,
for more information.
2.2 16-Level Stack with Overflow and
Underflow
These devices have a hardware stack memory, 15 bits
wide and 16 words deep. A Stack Overflow or Underflow
will set the appropriate bit (STKOVF or STKUNF) in the
PCON register, and if enabled, will cause a Software
Reset. See Section 3.5 “Stack” for more details.
2.3 File Select Registers
There are two 16-bit File Select Registers (FSR). FSRs
can access all file registers and program memory,
which allows one Data Pointer for all memory. When an
FSR points to program memory, there is one additional
instruction cycle in instructions using INDF to allow the
data to be fetched. General purpose memory can now
also be addressed linearly, providing the ability to
access contiguous data larger than 80 bytes. There
are also new instructions to support the FSRs. See
Section 3.6 “Indirect Addressing” for more details.
2.4 Instruction Set
There are 49 instructions for the enhanced mid-
range CPU to support the features of the CPU. See
Section 25.0 “Instruction Set Summary” for more
details.
2013-2015 Microchip Technology Inc. DS40001723D-page 15
PIC12(L)F1571/2
3.0 MEMORY ORGANIZATION
These devices contain the following types of memory:
• Program Memory:
- Configuration Words
- Device ID
-User ID
- Flash Program Memory
• Data Memory:
- Core Registers
- Special Function Registers
- General Purpose RAM
- Common RAM
The following features are associated with access and
control of program memory and data memory:
• PCL and PCLATH
•Stack
• Indirect Addressing
3.1 Program Memory Organization
The enhanced mid-range core has a 15-bit Program
Counter (PC) capable of addressing a 32K x 14 program
memory space. Table 3-1 shows the memory sizes
implemented. Accessing a location above these bound-
aries will cause a wraparound within the implemented
memory space. The Reset vector is at 0000h and the
interrupt vector is at 0004h (see Figure 3-1).
3.2 High-Endurance Flash
This device has a 128-byte section of high-endurance
Program Flash Memory (PFM) in lieu of data
EEPROM. This area is especially well-suited for non-
volatile data storage that is expected to be updated
frequently over the life of the end product. See
Section 10.2 “Flash Program Memory Overview”
for more information on writing data to PFM. See
Section 3.2.1.2 “Indirect Read with FSR” for more
information about using the FSR registers to read byte
data stored in PFM.
TABLE 3-1: DEVICE SIZES AND ADDRESSES
Device Program Memory
Space (Words)
Last Program Memory
Address
High-Endurance Flash
Memory Address Range(1)
PIC12(L)F1571 1,024 03FFh 0380h-03FFh
PIC12(L)F1572 2,048 07FFh 0780h-07FFh
Note 1: High-endurance Flash applies to the low byte of each address in the range.
PIC12(L)F1571/2
DS40001723D-page 16 2013-2015 Microchip Technology Inc.
FIGURE 3-1: PROGRAM MEMORY MAP
AND STACK FOR
PIC12(L)F1571
FIGURE 3-2: PROGRAM MEMORY MAP
AND STACK FOR
PIC12(L)F1572
Stack Level 0
Stack Level 15
Stack Level 1
Reset Vector
PC<14:0>
Interrupt Vector
Page 0
Rollover to Page 0
Rollover to Page 0
0000h
0004h
0005h
03FFh
0400h
7FFFh
CALL, CALLW
RETURN, RETLW
Interrupt, RETFIE
On-chip
Program
Memory
15
Rev. 10-000040D
7/30/2013
Stack Level 0
Stack Level 15
Stack Level 1
Reset Vector
PC<14:0>
Interrupt Vector
Page 0
Rollover to Page 0
Rollover to Page 0
0000h
0004h
0005h
07FFh
0800h
7FFFh
CALL, CALLW
RETURN, RETLW
Interrupt, RETFIE
On-chip
Program
Memory
15
Rev. 10-000040C
7/30/2013
2013-2015 Microchip Technology Inc. DS40001723D-page 17
PIC12(L)F1571/2
3.2.1 READING PROGRAM MEMORY AS
DATA
There are two methods of accessing constants in pro-
gram memory. The first method is to use tables of
RETLW instructions. The second method is to set an
FSR to point to the program memory.
3.2.1.1 RETLW Instruction
The RETLW instruction can be used to provide access
to tables of constants. The recommended way to create
such a table is shown in Example 3-1.
EXAMPLE 3-1: RETLW INSTRUCTION
The BRW instruction makes this type of table very
simple to implement. If your code must remain portable
with previous generations of microcontrollers, then the
BRW instruction is not available, so the older table read
method must be used.
3.2.1.2 Indirect Read with FSR
The program memory can be accessed as data by
setting bit 7 of the FSRnH register and reading the
matching INDFn register. The MOVIW instruction will
place the lower eight bits of the addressed word in the
W register. Writes to the program memory cannot be
performed via the INDFn registers. Instructions that
access the program memory via the FSR require one
extra instruction cycle to complete. Example 3-2
demonstrates accessing the program memory via an
FSR.
The HIGH operator will set bit<7> if a label points to a
location in program memory.
EXAMPLE 3-2: ACCESSING PROGRAM
MEMORY VIA FSR
constants
BRW ;Add Index in W to
;program counter to
;select data
RETLW DATA0 ;Index0 data
RETLW DATA1 ;Index1 data
RETLW DATA2
RETLW DATA3
my_function
;… LOTS OF CODE…
MOVLW DATA_INDEX
call constants
;… THE CONSTANT IS IN W
constants
DW DATA0 ;First constant
DW DATA1 ;Second constant
DW DATA2
DW DATA3
my_function
;… LOTS OF CODE…
MOVLW DATA_INDEX
ADDLW LOW constants
MOVWF FSR1L
MOVLW
HIGH c ons ta nts
;MSb is set
automatically
MOVWF FSR1H
BTFSC STATUS,C ;carry from ADDLW?
INCF FSR1H,f ;yes
MOVIW 0[FSR1]
;THE PROGRAM MEMORY IS IN W
PIC12(L)F1571/2
DS40001723D-page 18 2013-2015 Microchip Technology Inc.
3.3 Data Memory Organization
The data memory is partitioned in 32 memory banks
with 128 bytes in a bank. Each bank consists of
(Figure 3-3):
• 12 Core Registers
• 20 Special Function Registers (SFR)
• Up to 80 bytes of General Purpose RAM (GPR)
• 16 bytes of Common RAM
The active bank is selected by writing the bank number
into the Bank Select Register (BSR). Unimplemented
memory will read as ‘0’. All data memory can be
accessed either directly (via instructions that use the file
registers) or indirectly via the two File Select Registers
(FSR). See Section 3.6 “Indirect Addressing” for
more information.
Data memory uses a 12-bit address. The upper five bits
of the address define the bank address and the lower
seven bits select the registers/RAM in that bank.
3.3.1 CORE REGISTERS
The core registers contain the registers that directly
affect the basic operation. The core registers occupy
the first 12 addresses of every data memory bank
(addresses: x00h/x08h through x0Bh/x8Bh). These
registers are listed below in Ta b l e 3 - 2 . For detailed
information, see Tab le 3- 9.
TABLE 3-2: CORE REGISTERS
Addresses BANKx
x00h or x80h INDF0
x01h or x81h INDF1
x02h or x82h PCL
x03h or x83h STATUS
x04h or x84h FSR0L
x05h or x85h FSR0H
x06h or x86h FSR1L
x07h or x87h FSR1H
x08h or x88h BSR
x09h or x89h WREG
x0Ah or x8Ah PCLATH
x0Bh or x8Bh INTCON
2013-2015 Microchip Technology Inc. DS40001723D-page 19
PIC12(L)F1571/2
3.3.1.1 STATUS Register
The STATUS register, shown in Register 3-1, contains:
• The arithmetic status of the ALU
• The Reset status
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not affecting
any Status bits, refer to Section 25.0 “Instruction Set
Summary”).
Note 1: The C and DC bits operate as Borrow
and Digit Borrow out bits, respectively, in
subtraction.
REGISTER 3-1: STATUS: STATUS REGISTER
U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u
— — —TOPD ZDC
(1) C(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7-5 Unimplemented: Read as ‘0’
bit 4 TO: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-Down bit
1 = After power-down or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.
PIC12(L)F1571/2
DS40001723D-page 20 2013-2015 Microchip Technology Inc.
3.3.2 SPECIAL FUNCTION REGISTER
The Special Function Registers are registers used by
the application to control the desired operation of
peripheral functions in the device. The Special Function
Registers occupy the 20 bytes after the core registers of
every data memory bank (addresses: x0Ch/x8Ch
through x1Fh/x9Fh). The registers associated with the
operation of the peripherals are described in the
appropriate peripheral chapter of this data sheet.
3.3.3 GENERAL PURPOSE RAM
There are up to 80 bytes of GPR in each data memory
bank. The Special Function Registers occupy the
20 bytes after the core registers of every data memory
bank (addresses: x0Ch/x8Ch through x1Fh/x9Fh).
3.3.3.1 Linear Access to GPR
The general purpose RAM can be accessed in
a non-banked method via the FSRs. This can
simplify access to large memory structures. See
Section 3.6.2 “Linear Data Memory” for more
information.
3.3.4 COMMON RAM
There are 16 bytes of common RAM accessible from all
banks.
3.3.5 DEVICE MEMORY MAPS
The memory maps for PIC12(L)F1571/2 are as shown
in Table 3-3 through Tabl e 3 - 8 .
FIGURE 3-3: BANKED MEMORY
PARTITIONING
Memory Region7-bit Bank Offset
00h
0Bh
0Ch
1Fh
20h
6Fh
7Fh
70h
Core Registers
(12 bytes)
Special Function Registers
(20 bytes maximum)
General Purpose RAM
(80 bytes maximum)
Common RAM
(16 bytes)
Rev. 10-000041A
7/30/2013
2013-2015 Microchip Technology Inc. DS40001723D-page 21
PIC12(L)F1571/2
TABLE 3-3: PIC12(L)F1571 MEMORY MAP, BANK 0-7
BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7
000h
Core Registers
(Ta b l e 3 - 2 )
080h
Core Registers
(Ta b l e 3 - 2 )
100h
Core Registers
(Ta b l e 3 - 2 )
180h
Core Registers
(Ta b l e 3 - 2 )
200h
Core Registers
(Ta b l e 3 - 2 )
280h
Core Registers
(Ta b l e 3 - 2 )
300h
Core Registers
(Ta b l e 3 - 2 )
380h
Core Registers
(Ta b l e 3 - 2 )
00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh
00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch ODCONA 30Ch SLRCONA 38Ch INLVLA
00Dh —08Dh—10Dh—18Dh—20Dh—28Dh—30Dh—38Dh—
00Eh —08Eh—10Eh—18Eh—20Eh—28Eh—30Eh—38Eh—
00Fh —08Fh—10Fh—18Fh— 20Fh — 28Fh — 30Fh — 38Fh —
010h —090h—110h—190h— 210h — 290h — 310h — 390h —
011h PIR1 091h PIE1 111h CM1CON0 191h PMADRL 211h — 291h — 311h — 391h IOCAP
012h PIR2 092h PIE2 112h CM1CON1 192h PMADRH 212h — 292h — 312h — 392h IOCAN
013h PIR3 093h PIE3 113h — 193h PMDATL 213h — 293h — 313h — 393h IOCAF
014h —094h—114h— 194h PMDATH 214h — 294h — 314h — 394h —
015h TMR0 095h OPTION_REG 115h CMOUT 195h PMCON1 215h — 295h — 315h — 395h —
016h TMR1L 096h PCON 116h BORCON 196h PMCON2 216h — 296h — 316h — 396h —
017h TMR1H 097h WDTCON 117h FVRCON 197h VREGCON(1) 217h — 297h — 317h — 397h —
018h T1CON 098h OSCTUN E 118h DACxCON0 198h — 218h — 298h — 318h — 398h —
019h T1GCON 099h OSCCON 119h DACxCON1 199h — 219h — 299h — 319h — 399h —
01Ah TMR2 09Ah OSCSTAT 11Ah —19Ah—21Ah—29Ah—31Ah—39Ah—
01Bh PR2 09Bh ADRESL 11Bh —19Bh—21Bh—29Bh—31Bh—39Bh—
01Ch T2CON 09Ch ADRESH 11Ch —19Ch—21Ch—29Ch—31Ch—39Ch—
01Dh — 09Dh ADCON0 11Dh APFCON 19Dh —21Dh—29Dh—31Dh—39Dh—
01Eh — 09Eh ADCON1 11Eh —19Eh—21Eh—29Eh—31Eh—39Eh—
01Fh — 09Fh ADCON2 11Fh —19Fh— 21Fh — 29Fh — 31Fh — 39Fh —
020h
General
Purpose
Register
80 Bytes
0A0h General Purpose
Register
48 Bytes
120h
Unimplemented
Read as ‘0’
1A0h
Unimplemented
Read as ‘0’
220h
Unimplemented
Read as ‘0’
2A0h
Unimplemented
Read as ‘0’
320h
Unimplemented
Read as ‘0’
3A0h
Unimplemented
Read as ‘0’
0BFh
0C0h Unimplemented
Read as ‘0’
06Fh 0EFh 16Fh 1EFh 26Fh 2EFh 36Fh 3EFh
070h
Common RAM
0F0h
Common RAM
(Accesses
70h-7Fh)
170h
Common RAM
(Accesses
70h-7Fh)
1F0h
Common RAM
(Accesses
70h-7Fh)
270h
Common RAM
(Accesses
70h-7Fh)
2F0h
Common RAM
(Accesses
70h-7Fh)
370h
Common RAM
(Accesses
70h-7Fh)
3F0h
Common RAM
(Accesses
70h-7Fh)
07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh
Legend: = Unimplemented data memory locations, read as ‘0’.
Note 1: PIC12F1571 only.
PIC12(L)F1571/2
DS40001723D-page 22 2013-2015 Microchip Technology Inc.
TABLE 3-4: PIC12(L)F1572 MEMORY MAP, BANK 0-7
BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7
000h
Core Registers
(Ta b l e 3 - 2 )
080h
Core Registers
(Ta b l e 3 - 2 )
100h
Core Registers
(Ta b l e 3 - 2 )
180h
Core Registers
(Ta b l e 3 - 2 )
200h
Core Registers
(Ta b l e 3 - 2 )
280h
Core Registers
(Ta b l e 3 - 2 )
300h
Core Registers
(Ta b l e 3 - 2 )
380h
Core Registers
(Ta b l e 3 - 2 )
00Bh 08Bh 10Bh 18Bh 20Bh 28Bh 30Bh 38Bh
00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch WPUA 28Ch ODCONA 30Ch SLRCONA 38Ch INLVLA
00Dh —08Dh—10Dh—18Dh—20Dh—28Dh—30Dh—38Dh—
00Eh —08Eh—10Eh—18Eh—20Eh—28Eh—30Eh—38Eh—
00Fh —08Fh—10Fh—18Fh— 20Fh — 28Fh — 30Fh — 38Fh —
010h —090h—110h—190h— 210h — 290h — 310h — 390h —
011h PIR1 091h PIE1 111h CM1CON0 191h PMADRL 211h — 291h — 311h — 391h IOCAP
012h PIR2 092h PIE2 112h CM1CON1 192h PMADRH 212h — 292h — 312h — 392h IOCAN
013h PIR3 093h PIE3 113h — 193h PMDATL 213h — 293h — 313h — 393h IOCAF
014h —094h—114h— 194h PMDATH 214h — 294h — 314h — 394h —
015h TMR0 095h OPTION_REG 115h CMOUT 195h PMCON1 215h — 295h — 315h — 395h —
016h TMR1L 096h PCON 116h BORCON 196h PMCON2 216h — 296h — 316h — 396h —
017h TMR1H 097h WDTCON 117h FVRCON 197h VREGCON(1) 217h — 297h — 317h — 397h —
018h T1CON 098h OSCTUNE 118h DAC1CON0 198h — 218h — 298h — 318h — 398h —
019h T1GCON 099h OSCCON 119h DAC1CON1 199h RCREG 219h — 299h — 319h — 399h —
01Ah TMR2 09Ah OSCSTAT 11Ah — 19Ah TXREG 21Ah —29Ah—31Ah—39Ah—
01Bh PR2 09Bh ADRESL 11Bh — 19Bh SPBRG 21Bh —29Bh—31Bh—39Bh—
01Ch T2CON 09Ch ADRESH 11Ch — 19Ch SPBRGH 21Ch —29Ch—31Ch—39Ch—
01Dh — 09Dh ADCON0 11Dh APFCON 19Dh RCSTA 21Dh —29Dh—31Dh—39Dh—
01Eh — 09Eh ADCON1 11Eh — 19Eh TXSTA 21Eh —29Eh—31Eh—39Eh—
01Fh — 09Fh ADCON2 11Fh — 19Fh BAUDCON 21Fh — 29Fh — 31Fh — 39Fh —
020h
General
Purpose
Register
80 Bytes
0A0h
General
Purpose
Register
80 Bytes
120h
General
Purpose
Register
80 Bytes
1A0h
Unimplemented
Read as ‘0’
220h
Unimplemented
Read as ‘0’
2A0h
Unimplemented
Read as ‘0’
320h
Unimplemented
Read as ‘0’
3A0h
Unimplemented
Read as ‘0’
0EFh
06Fh 16Fh 1EFh 26Fh 2EFh 36Fh 3EFh
070h
Common RAM
0F0h
Accesses
70h-7Fh
170h
Accesses
70h-7Fh
1F0h
Accesses
70h-7Fh
270h
Accesses
70h-7Fh
2F0h
Accesses
70h-7Fh
370h
Accesses
70h-7Fh
3F0h
Accesses
70h-7Fh
07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh
Legend: = Unimplemented data memory locations, read as ‘0’.
Note 1: PIC12F1572 only.
2013-2015 Microchip Technology Inc. DS40001723D-page 23
PIC12(L)F1571/2
TABLE 3-5: PIC12(L)F1571/2 MEMORY MAP, BANK 8-23
BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15
400h
40Bh
Core Registers
(Ta b l e 3 - 2 )
480h
48Bh
Core Registers
(Ta b l e 3 - 2 )
500h
50Bh
Core Registers
(Ta b l e 3 - 2 )
580h
58Bh
Core Registers
(Ta b l e 3 - 2 )
600h
60Bh
Core Registers
(Ta b l e 3 - 2 )
680h
68Bh
Core Registers
(Ta b l e 3 - 2 )
700h
70Bh
Core Registers
(Ta b l e 3 - 2 )
780h
78Bh
Core Registers
(Ta b l e 3 - 2 )
40Ch —48Ch—50Ch—58Ch—60Ch—68Ch—70Ch—78Ch—
40Dh —48Dh—50Dh—58Dh—60Dh—68Dh—70Dh—78Dh—
40Eh —48Eh—50Eh—58Eh—60Eh—68Eh—70Eh—78Eh—
40Fh —48Fh—50Fh—58Fh— 60Fh — 68Fh — 70Fh — 78Fh —
410h —490h—510h—590h— 610h — 690h — 710h — 790h —
411h —491h—511h—591h—611h— 691h CWG1DBR 711h — 791h —
412h —492h—512h—592h— 612h — 692h CWG1DBF 712h — 792h —
413h —493h—513h—593h— 613h — 693h CWG1CON0 713h — 793h —
414h —494h—514h—594h— 614h — 694h CWG1CON1 714h — 794h —
415h —495h—515h—595h— 615h — 695h CWG1CON2 715h — 795h —
416h —496h—516h—596h— 616h — 696h — 716h — 796h —
417h —497h—517h—597h— 617h — 697h — 717h — 797h —
418h —498h—518h—598h— 618h — 698h — 718h — 798h —
419h —499h—519h—599h— 619h — 699h — 719h — 799h —
41Ah —49Ah—51Ah—59Ah—61Ah—69Ah—71Ah—79Ah—
41Bh —49Bh—51Bh—59Bh—61Bh—69Bh—71Bh—79Bh—
41Ch —49Ch—51Ch—59Ch—61Ch—69Ch—71Ch—79Ch—
41Dh —49Dh—51Dh—59Dh—61Dh—69Dh—71Dh—79Dh—
41Eh —49Eh—51Eh—59Eh—61Eh—69Eh—71Eh—79Eh—
41Fh —49Fh—51Fh—59Fh— 61Fh — 69Fh — 71Fh — 79Fh —
420h
Unimplemented
Read as ‘0’
4A0h
Unimplemented
Read as ‘0’
520h
Unimplemented
Read as ‘0’
5A0h
Unimplemented
Read as ‘0’
620h
Unimplemented
Read as ‘0’
6A0h
Unimplemented
Read as ‘0’
720h
Unimplemented
Read as ‘0’
7A0h
Unimplemented
Read as ‘0’
46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh
470h
Accesses
70h-7Fh
4F0h
Accesses
70h-7Fh
570h
Accesses
70h-7Fh
5F0h
Accesses
70h-7Fh
670h
Accesses
70h-7Fh
6F0h
Accesses
70h-7Fh
770h
Accesses
70h-7Fh
7F0h
Accesses
70h-7Fh
47Fh 4FFh 57Fh 5FFh 67Fh 6FFh 77Fh 7FFh
BANK 16 BANK 17 BANK 18 BANK 19 BANK 20 BANK 21 BANK 22 BANK 23
800h
80Bh
Core Registers
(Table 3-2 )
880h
88Bh
Core Registers
(Ta b l e 3 - 2 )
900h
90Bh
Core Registers
(Ta b l e 3 - 2 )
980h
98Bh
Core Registers
(Ta b l e 3 - 2 )
A00h
A0Bh
Core Registers
(Ta b l e 3 - 2 )
A80h
A8Bh
Core Registers
(Ta b l e 3 - 2 )
B00h
B0Bh
Core Registers
(Ta b l e 3 - 2 )
B80h
B8Bh
Core Registers
(Ta b l e 3 - 2 )
80Ch
Unimplemented
Read as ‘0’
88Ch
Unimplemented
Read as ‘0’
90Ch
Unimplemented
Read as ‘0’
98Ch
Unimplemented
Read as ‘0’
A0Ch
Unimplemented
Read as ‘0’
A8Ch
Unimplemented
Read as ‘0’
B0Ch
Unimplemented
Read as ‘0’
B8Ch
Unimplemented
Read as ‘0’
86Fh 8EFh 96Fh 9EFh A6Fh AEFh B6Fh BEFh
870h
Accesses
70h-7Fh
8F0h
Accesses
70h-7Fh
970h
Accesses
70h-7Fh
9F0h
Accesses
70h-7Fh
A70h
Accesses
70h-7Fh
AF0h
Accesses
70h-7Fh
B70h
Accesses
70h-7Fh
BF0h
Accesses
70h-7Fh
87Fh 8FFh 97Fh 9FFh A7Fh AFFh B7Fh BFFh
Legend: = Unimplemented data memory locations, read as ‘0’.
PIC12(L)F1571/2
DS40001723D-page 24 2013-2015 Microchip Technology Inc.
TABLE 3-6: PIC12(L)F1571/2 MEMORY MAP, BANK 24-31
BANK 24 BANK 25 BANK 26 BANK 27 BANK 28 BANK 29 BANK 30 BANK 31
C00h
C0Bh
Core Registers
(Ta b l e 3 - 2 )
C80h
C8Bh
Core Registers
(Ta b l e 3 - 2 )
D00h
D0Bh
Core Registers
(Ta b l e 3 - 2 )
D80h
D8Bh
Core Registers
(Ta b l e 3 - 2 )
E00h
E0Bh
Core Registers
(Ta b l e 3 - 2 )
E80h
E8Bh
Core Registers
(Ta b l e 3 - 2 )
F00h
F0Bh
Core Registers
(Ta b l e 3 - 2 )
F80h
F8Bh
Core Registers
(Ta b l e 3 - 2 )
C0Ch —C8Ch—D0Ch—D8Ch
See Table 3-7 for
Register Mapping
Details
E0Ch —E8Ch—F0Ch—F8Ch
See Table 3-7 for
Register Mapping
Details
C0Dh —C8Dh—D0Dh—E0Dh—E8Dh—F0Dh—
C0Eh —C8Eh—D0Eh—E0Eh—E8Eh—F0Eh—
C0Fh —C8Fh—D0Fh—E0Fh—E8Fh—F0Fh—
C10h —C90h—D10h—E10h—E90h—F10h—
C11h —C91h—D11h—E11h—E91h—F11h—
C12h —C92h—D12h—E12h—E92h—F12h—
C13h —C93h—D13h—E13h—E93h—F13h—
C14h —C94h—D14h—E14h—E94h—F14h—
C15h —C95h—D15h—E15h—E95h—F15h—
C16h —C96h—D16h—E16h—E96h—F16h—
C17h —C97h—D17h—E17h—E97h—F17h—
C18h —C98h—D18h—E18h—E98h—F18h—
C19h —C99h—D19h—E19h—E99h—F19h—
C1Ah —C9Ah—D1Ah—E1Ah—E9Ah—F1Ah—
C1Bh —C9Bh—D1Bh—E1Bh—E9Bh—F1Bh—
C1Ch —C9Ch—D1Ch—E1Ch—E9Ch—F1Ch—
C1Dh —C9Dh—D1Dh—E1Dh—E9Dh—F1Dh—
C1Eh —C9Eh—D1Eh—E1Eh—E9Eh—F1Eh—
C1Fh —C9Fh—D1Fh—E1Fh—E9Fh—F1Fh—
C20h
Unimplemented
Read as ‘0’
CA0h
Unimplemented
Read as ‘0’
D20h
Unimplemented
Read as ‘0’
E20h
Unimplemented
Read as ‘0’
EA0h
Unimplemented
Read as ‘0’
F20h
Unimplemented
Read as ‘0’
C6Fh CEFh D6Fh DEFh E6Fh EEFh F6Fh FEFh
C70h
Accesses
70h-7Fh
CF0h
Accesses
70h-7Fh
D70h
Accesses
70h-7Fh
DF0h
Accesses
70h-7Fh
E70h
Accesses
70h-7Fh
EF0h
Accesses
70h-7Fh
F70h
Accesses
70h-7Fh
FF0h
Accesses
70h-7Fh
CFFh CFFh D7Fh DFFh E7Fh EFFh F7Fh FFFh
Legend: = Unimplemented data memory locations, read as ‘0’.
2013-2015 Microchip Technology Inc. DS40001723D-page 25
PIC12(L)F1571/2
TABLE 3-7: PIC12(L)F1571/2 MEMORY
MAP, BANK 27
TABLE 3-8: PIC12(L)F1571/2 MEMORY
MAP, BANK 31
Bank 31
D8Ch —
D8Dh —
D8Eh PWMEN
D8Fh PWMLD
D90h PWMOUT
D91h PWM1PHL
D92h PWM1PHH
D93h PWM1DCL
D94h PWM1DCH
D95h PWM1PRL
D96h PWM1PRH
D97h PWM1OFL
D98h PWM1OFH
D99h PWM1TMRL
D9Ah PWM1TMRH
D9Bh PWM1CON
D9Ch PWM1INTE
D9Dh PWM1INTF
D9Eh PWM1CLKCON
D9Fh PWM1LDCON
DA0h PWM1OFCON
DA1h PWM2PHL
DA2h PWM2PHH
DA3h PWM2DCL
DA4h PWM2DCH
DA5h PWM2PRL
DA6h PWM2PRH
DA7h PWM2OFL
DA8h PWM2OFH
DA9h PWM2TMRL
DAAh PWM2TMRH
DABh PWM2CON
DACh PWM2INTE
DADh PWM2INTF
DAEh PWM2CLKCON
DAFh PWM2LDCON
DB0h PWM2OFCON
DB1h PWM3PHL
DB2h PWM3PHH
DB3h PWM3DCL
DB4h PWM3DCH
DB5h PWM2PRL
DB6h PWM3PRH
DB7h PWM3OFL
DB8h PWM3OFH
DB9h PWM3TMRL
DBAh PWM3TMRH
DBBh PWM3CON
DBCh PWM3INTE
DBDh PWM3INTF
DBEh PWM3CLKCON
DBFh PWM3LDCON
DC0h PWM3OFCON
DC1h
—
DEFh
Legend: = Unimplemented data memory locations,
read as ‘0’.
Bank 31
F8Ch
FE3h
Unimplemented
Read as ‘0’
FE4h STATUS_SHAD
FE5h WREG_SHAD
FE6h BSR_SHAD
FE7h PCLATH_SHAD
FE8h FSR0L_SHAD
FE9h FSR0H_SHAD
FEAh FSR1L_SHAD
FEBh FSR1H_SHAD
FECh —
FEDh STKPTR
FEEh TOSL
FEFh TOSH
Legend: = Unimplemented data memory locations,
read as ‘0’.
PIC12(L)F1571/2
DS40001723D-page 26 2013-2015 Microchip Technology Inc.
3.3.6 CORE FUNCTION REGISTERS
SUMMARY
The Core Function registers listed in Tabl e 3-9 can be
addressed from any bank.
TABLE 3-9: CORE FUNCTION REGISTERS SUMMARY
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on All
Other Resets
Bank 0-31
x00h or
x80h INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register) xxxx xxxx uuuu uuuu
x01h or
x81h INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register) xxxx xxxx uuuu uuuu
x02h or
x82h PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000
x03h or
x83h STATUS — — —TOPD ZDCC---1 1000 ---q quuu
x04h or
x84h FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu
x05h or
x85h FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000
x06h or
x86h FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu
x07h or
x87h FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000
x08h or
x88h BSR — — —BSR<4:0>---0 0000 ---0 0000
x09h or
x89h WREG Working Register 0000 0000 uuuu uuuu
x0Ah or
x8Ah PCLATH — Write Buffer for the Upper 7 bits of the Program Counter -000 0000 -000 0000
x0Bh or
x8Bh INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000
Legend: x = unknown; u = unchanged; q = value depends on condition; — = unimplemented, read as ‘0’; r = reserved.
Shaded locations are unimplemented, read as ‘0’.
2013-2015 Microchip Technology Inc. DS40001723D-page 27
PIC12(L)F1571/2
TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
All Other
Resets
Bank 0
00Ch PORTA —— RA<5:0>
--xx xxxx --xx xxxx
00Dh —Unimplemented — —
00Eh —Unimplemented — —
00Fh —Unimplemented — —
010h —Unimplemented — —
011h PIR1 TMR1GIF ADIF RCIF
(2)
TXIF
(2)
—— TMR2IF TMR1IF
0000 --00 0000 --00
012h PIR2 ——C1IF — — — — —
--0- ---- --0- ----
013h PIR3 — PWM3IF PWM2IF PWM1IF — — — —
-000 ---- -000 ----
014h —Unimplemented — —
015h TMR0 Holding Register for the 8-Bit Timer0 Count
xxxx xxxx uuuu uuuu
016h TMR1L Holding Register for the Least Significant Byte of the 16-Bit TMR1 Count
xxxx xxxx uuuu uuuu
017h TMR1H Holding Register for the Most Significant Byte of the 16-Bit TMR1 Count
xxxx xxxx uuuu uuuu
018h T1CON TMR1CS<1:0> T1CKPS<1:0> —T1SYNC —TMR1ON
0000 -0-0 uuuu -u-u
019h T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/
DONE
T1GVAL T1GSS<1:0>
0000 0x00 uuuu uxuu
01Ah TMR2 Timer2 Module Register
0000 0000 0000 0000
01Bh PR2 Timer2 Period Register
1111 1111 1111 1111
01Ch T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0>
-000 0000 -000 0000
01Dh —Unimplemented — —
01Eh —Unimplemented — —
01Fh —Unimplemented — —
Bank 1
08Ch TRISA —— TRISA<5:4> —
(2)
TRISA<2:0>
--11 1111 --11 1111
08Dh —Unimplemented — —
08Eh —Unimplemented — —
08Fh —Unimplemented — —
090h —Unimplemented — —
091h PIE1 TMR1GIE ADIE RCIE
(2)
TXIE
(2)
—— TMR2IE TMR1IE
0000 --00 0000 --00
092h PIE2 ——C1IE— — — — —
--0- ---- --0- ----
093h PIE3 — PWM3IE PWM2IE PWM1IE — — — —
-000 ---- -000 ----
094h —Unimplemented — —
095h OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0>
1111 1111 1111 1111
096h PCON STKOVF STKUNF —RWDTRMCLR RI POR BOR
00-1 11qq qq-q qquu
097h WDTCON ——WDTPS<4:0>SWDTEN
--01 0110 --01 0110
098h OSCTUNE ——TUN<5:0>
--00 0000 --00 0000
099h OSCCON SPLLEN IRCF<3:0> —SCS<1:0>
0011 1-00 0011 1-00
09Ah OSCSTAT — PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS
-0q0 0q00 -qqq qqqq
09Bh ADRESL ADC Result Register Low
xxxx xxxx uuuu uuuu
09Ch ADRESH ADC Result Register High
xxxx xxxx uuuu uuuu
09Dh ADCON0 — CHS<4:0> GO/DONE ADON
-000 0000 -000 0000
09Eh ADCON1 ADFM ADCS<2:0> —— ADPREF<1:0>
0000 --00 0000 --00
09Fh ADCON2 TRIGSEL<3:0> — — — —
0000 ---- 0000 ----
Legend:
x
= unknown;
u
= unchanged;
q
= value depends on condition; — = unimplemented;
r
= reserved. Shaded locations are unimplemented, read as ‘
0
’.
Note 1:
PIC12F1571/2 only.
2:
PIC12(L)F1572 only.
3:
Unimplemented, read as ‘
1
’.
PIC12(L)F1571/2
DS40001723D-page 28 2013-2015 Microchip Technology Inc.
Bank 2
10Ch LATA —— LATA<5:4> — LATA<2:0>
--xx -xxx --uu -uuu
10Dh —Unimplemented — —
10Eh —Unimplemented — —
10Fh —Unimplemented — —
110h —Unimplemented — —
111h CM1CON0 C1ON C1OUT C1OE C1POL — C1SP C1HYS C1SYNC
0000 -100 0000 -100
112h CM1CON1 C1INTP C1INTN C1PCH<1:0> —C1NCH<2:0>
0000 -000 0000 -000
113h —Unimplemented — —
114h —Unimplemented — —
115h CMOUT — — — — — — —MC1OUT
---- ---0 ---- ---0
116h BORCON SBOREN BORFS — — — — — BORRDY
10-- ---q uu-- ---u
117h FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0>
0q00 0000 0q00 0000
118h DAC1CON0 DACEN —DACOE — DACPSS<1:0> — —
0-0- 00-- 0-0- 00--
119h DAC1CON1 — — — DACR<4:0>
---0 0000 ---0 0000
11Ah
to
11Ch
—Unimplemented — —
11Dh APFCON RXDTSEL CWGASEL CWGBSEL — T1GSEL TXCKSEL P2SEL P1SEL
000- 0000 000- 0000
11Eh —Unimplemented — —
11Fh —Unimplemented — —
Bank 3
18Ch ANSELA — — —ANSA4— ANSA<2:0>
---1 -111 ---1 -111
18Dh —Unimplemented — —
18Eh —Unimplemented — —
18Fh —Unimplemented — —
190h —Unimplemented — —
191h PMADRL Flash Program Memory Address Register Low Byte
0000 0000 0000 0000
192h PMADRH —
(3)
Flash Program Memory Address Register High Byte
1000 0000 1000 0000
193h PMDATL Flash Program Memory Read Data Register Low Byte
xxxx xxxx uuuu uuuu
194h PMDATH —— Flash Program Memory Read Data Register High Byte
--xx xxxx --uu uuuu
195h PMCON1 —
(3)
CFGS LWLO FREE WRERR WREN WR RD
1000 x000 1000 q000
196h PMCON2 Flash Program Memory Control Register 2
0000 0000 0000 0000
197h VREGCON
(1)
— — — — — —VREGPMReserved
---- --01 ---- --01
198h —Unimplemented — —
199h RCREG USART Receive Data Register
0000 0000 0000 0000
19Ah TXREG USART Transmit Data Register
0000 0000 0000 0000
19Bh SPBRGL Baud Rate Generator Data Register Low
0000 0000 0000 0000
19Ch SPBRGH Baud Rate Generator Data Register High
0000 0000 0000 0000
19Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
0000 000x 0000 000x
19Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D
0000 0010 0000 0010
19Fh BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN
01-0 0-00 01-0 0-00
TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
All Other
Resets
Legend:
x
= unknown;
u
= unchanged;
q
= value depends on condition; — = unimplemented;
r
= reserved. Shaded locations are unimplemented, read as ‘
0
’.
Note 1:
PIC12F1571/2 only.
2:
PIC12(L)F1572 only.
3:
Unimplemented, read as ‘
1
’.
2013-2015 Microchip Technology Inc. DS40001723D-page 29
PIC12(L)F1571/2
Bank 4
20Ch WPUA —— WPUA<5:0>
--11 1111 --11 1111
20Dh —Unimplemented — —
20Eh
to
21Fh
—Unimplemented — —
Bank 5
28Ch ODCONA ——ODA<5:4> —ODA<2:0>
--11 -111 --11 -111
28Dh
to
29Fh
—Unimplemented — —
Bank 6
30Ch SLRCONA —— SLRA<5:4> — SLRA<2:0>
--11 -111 --11 -111
30Dh
to
31Fh
—Unimplemented — —
Bank 7
38Ch INLVLA —— INLVLA<5:0>
--11 1111 --11 1111
38Dh
to
390h
—Unimplemented — —
391h IOCAP ——IOCAP<5:0>
--00 0000 --00 0000
392h IOCAN ——IOCAN<5:0>
--00 0000 --00 0000
393h IOCAF ——IOCAF<5:0>
--00 0000 --00 0000
394h
to
39Fh
—Unimplemented — —
Bank 8
40Ch
to
41Fh
—Unimplemented — —
Bank 9
48Ch
to
49Fh
—Unimplemented — —
TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
All Other
Resets
Legend:
x
= unknown;
u
= unchanged;
q
= value depends on condition; — = unimplemented;
r
= reserved. Shaded locations are unimplemented, read as ‘
0
’.
Note 1:
PIC12F1571/2 only.
2:
PIC12(L)F1572 only.
3:
Unimplemented, read as ‘
1
’.
PIC12(L)F1571/2
DS40001723D-page 30 2013-2015 Microchip Technology Inc.
Bank 10
50Ch
to
51Fh
—Unimplemented — —
Bank 11
58Ch
to
59Fh
—Unimplemented — —
Bank 12
60Ch
to
61Fh
—Unimplemented — —
Bank 13
68Ch
to
690h
—Unimplemented — —
691h CWG1DBR ——CWG1DBR<5:0>
--00 0000 --00 0000
692h CWG1DBF ——CWG1DBF<5:0>
--xx xxxx --xx xxxx
693h CWG1CON0 G1EN G1OEB G1OEA G1POLB G1POLA ——G1CS0
0000 0--0 0000 0--0
694h CWG1CON1 G1ASDLB<1:0> G1ASDLA<1:0> — G1IS<2:0>
0000 -000 0000 -000
695h CWG1CON2 G1ASE G1ARSEN — — — G1ASDSC1 G1ASDSFLT —
00-- -00- 00-- -00-
696h
to
69Fh
—Unimplemented — —
Banks 14-26
x0Ch/
x8Ch
—
x1Fh/
x9Fh
—Unimplemented — —
TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
All Other
Resets
Legend:
x
= unknown;
u
= unchanged;
q
= value depends on condition; — = unimplemented;
r
= reserved. Shaded locations are unimplemented, read as ‘
0
’.
Note 1:
PIC12F1571/2 only.
2:
PIC12(L)F1572 only.
3:
Unimplemented, read as ‘
1
’.
2013-2015 Microchip Technology Inc. DS40001723D-page 31
PIC12(L)F1571/2
Bank 27
D8Ch —Unimplemented — —
D8Dh —Unimplemented — —
D8Eh PWMEN — — — — — PWM3EN_A PWM2EN_A PWM1EN_A
---- -000 ---- -000
D8Fh PWMLD — — — — — PWM3LDA_A PWM2LDA_A PWM1LDA_A
---- -000 ---- -000
D90h PWMOUT — — — — — PWM3OUT_A PWM2OUT_A PWM1OUT_A
---- -000 ---- -000
D91h PWM1PHL PH<7:0>
xxxx xxxx uuuu uuuu
D92h PWM1PHH PH<15:8>
xxxx xxxx uuuu uuuu
D93h PWM1DCL DC<7:0>
xxxx xxxx uuuu uuuu
D94h PWM1DCH DC<15:8>
xxxx xxxx uuuu uuuu
D95h PWM1PRL PR<7:0>
xxxx xxxx uuuu uuuu
D96h PWM1PRH PR<15:8>
xxxx xxxx uuuu uuuu
D97h PWM1OFL OF<7:0>
xxxx xxxx uuuu uuuu
D98h PWM1OFH OF<15:8>
xxxx xxxx uuuu uuuu
D99h PWM1TMRL TMR<7:0>
xxxx xxxx uuuu uuuu
D9Ah PWM1TMRH TMR<15:8>
xxxx xxxx uuuu uuuu
D9Bh PWM1CON PWM1EN PWM1OE PWM1OUT PWM1POL PWM1MODE<1:0> — —
0000 00-- 0000 00--
D9Ch PWM1INTE — — — — PWM1OFIE PWM1PHIE PWM1DCIE PWM1PRIE
---- 000 ---- 000
D9Dh PWM1INTF — — — — PWM1OFIF PWM1PHIF PWM1DCIF PWM1PRIF
---- 000 ---- 000
D9Eh PWM1CLKCON — PWM1PS<2:0> —— PWM1CS<1:0>
-000 -000 -000 --00
D9Fh PWM1LDCON PWM1LDA PWM1LDT — — — —PWM1LDS<1:0>
00-- -000 00-- --00
DA0h PWM1OFCON — PWM1OFM<1:0> PWM1OFO ——PWM1OFS<1:0>
-000 -000 -000 --00
DA1h PWM2PHL PH<7:0>
xxxx xxxx uuuu uuuu
DA2h PWM2PHH PH<15:8>
xxxx xxxx uuuu uuuu
DA3h PWM2DCL DC<7:0>
xxxx xxxx uuuu uuuu
DA4h PWM2DCH DC<15:8>
xxxx xxxx uuuu uuuu
DA5h PWM2PRL PR<7:0>
xxxx xxxx uuuu uuuu
DA6h PWM2PRH PR<15:8>
xxxx xxxx uuuu uuuu
DA7h PWM2OFL OF<7:0>
xxxx xxxx uuuu uuuu
DA8h PWM2OFH OF<15:8>
xxxx xxxx uuuu uuuu
DA9h PWM2TMRL TMR<7:0>
xxxx xxxx uuuu uuuu
DAAh PWM2TMRH TMR<15:8>
xxxx xxxx uuuu uuuu
DABh PWM2CON PWM2EN PWM2OE PWM2OUT PWM2POL PWM2MODE<1:0> — —
0000 00-- 0000 00--
DACh PWM2INTE — — — — PWM2OFIE PWM2PHIE PWM2DCIE PWM2PRIE
---- 000 ---- 000
DADh PWM2INTF — — — — PWM2OFIF PWM2PHIF PWM2DCIF PWM2PRIF
---- 000 ---- 000
DAEh PWM2CLKCON — PWM2PS<2:0> —— PWM2CS<1:0>
-000 -000 -000 --00
DAFh PWM2LDCON PWM2LDA PWM2LDT — — — —PWM2LDS<1:0>
00-- -000 00-- --00
TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
All Other
Resets
Legend:
x
= unknown;
u
= unchanged;
q
= value depends on condition; — = unimplemented;
r
= reserved. Shaded locations are unimplemented, read as ‘
0
’.
Note 1:
PIC12F1571/2 only.
2:
PIC12(L)F1572 only.
3:
Unimplemented, read as ‘
1
’.
PIC12(L)F1571/2
DS40001723D-page 32 2013-2015 Microchip Technology Inc.
Bank 27 (Continued)
DB0h PWM2OFCON — PWM2OFM<1:0> PWM2OFO ——PWM2OFS<1:0>
-000 -000 -000 --00
DB1h PWM3PHL PH<7:0>
xxxx xxxx uuuu uuuu
DB2h PWM3PHH PH<15:8>
xxxx xxxx uuuu uuuu
DB3h PWM3DCL DC<7:0>
xxxx xxxx uuuu uuuu
DB4h PWM3DCH DC<15:8>
xxxx xxxx uuuu uuuu
DB5h PWM3PRL PR<7:0>
xxxx xxxx uuuu uuuu
DB6h PWM3PRH PR<15:8>
xxxx xxxx uuuu uuuu
DB7h PWM3OFL OF<7:0>
xxxx xxxx uuuu uuuu
DA8h PWM3OFH OF<15:8>
xxxx xxxx uuuu uuuu
DA9h PWM3TMRL TMR<7:0>
xxxx xxxx uuuu uuuu
DBAh PWM3TMRH TMR<15:8>
xxxx xxxx uuuu uuuu
DBBh PWM3CON PWM3EN PWM3OE PWM3OUT PWM3POL PWM3MODE<1:0> — —
0000 00-- 0000 00--
DBCh PWM3INTE — — — — PWM3OFIE PWM3PHIE PWM3DCIE PWM3PRIE
---- 000 ---- 000
DBDh PWM3INTF — — — — PWM3OFIF PWM3PHIF PWM3DCIF PWM3PRIF
---- 000 ---- 000
DBEh PWM3CLKCON — PWM3PS<2:0> —— PWM3CS<1:0>
-000 -000 -000 --00
DBFh PWM3LDCON PWM3LDA PWM3LDT — — — —PWM3LDS<1:0>
00-- -000 00-- --00
DC0h PWM3OFCON — PWM3OFM<1:0> PWM3OFO ——PWM3OFS<1:0>
-000 -000 -000 --00
Bank 28-30
58Ch
to
59Fh
—Unimplemented — —
TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
All Other
Resets
Legend:
x
= unknown;
u
= unchanged;
q
= value depends on condition; — = unimplemented;
r
= reserved. Shaded locations are unimplemented, read as ‘
0
’.
Note 1:
PIC12F1571/2 only.
2:
PIC12(L)F1572 only.
3:
Unimplemented, read as ‘
1
’.
2013-2015 Microchip Technology Inc. DS40001723D-page 33
PIC12(L)F1571/2
Bank 31
F8Ch
—
FE3h
—Unimplemented — —
FE4h STATUS_
SHAD — — — — — Z_SHAD DC_SHAD C_SHAD
---- -xxx ---- -uuu
FE5h WREG_
SHAD Working Register Shadow
xxxx xxxx uuuu uuuu
FE6h BSR_
SHAD — — — Bank Select Register Shadow
---x xxxx ---u uuuu
FE7h PCLATH_
SHAD — Program Counter Latch High Register Shadow
-xxx xxxx uuuu uuuu
FE8h FSR0L_
SHAD Indirect Data Memory Address 0 Low Pointer Shadow
xxxx xxxx uuuu uuuu
FE9h FSR0H_
SHAD Indirect Data Memory Address 0 High Pointer Shadow
xxxx xxxx uuuu uuuu
FEAh FSR1L_
SHAD Indirect Data Memory Address 1 Low Pointer Shadow
xxxx xxxx uuuu uuuu
FEBh FSR1H_
SHAD Indirect Data Memory Address 1 High Pointer Shadow
xxxx xxxx uuuu uuuu
FECh —Unimplemented — —
FEDh STKPTR — — — Current Stack Pointer
---1 1111 ---1 1111
FEEh TOSL Top-of-Stack Low Byte
xxxx xxxx uuuu uuuu
FEFh TOSH — Top-of-Stack High Byte
-xxx xxxx -uuu uuuu
TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on
POR, BOR
Value on
All Other
Resets
Legend:
x
= unknown;
u
= unchanged;
q
= value depends on condition; — = unimplemented;
r
= reserved. Shaded locations are unimplemented, read as ‘
0
’.
Note 1:
PIC12F1571/2 only.
2:
PIC12(L)F1572 only.
3:
Unimplemented, read as ‘
1
’.
PIC12(L)F1571/2
DS40001723D-page 34 2013-2015 Microchip Technology Inc.
3.4 PCL and PCLATH
The Program Counter (PC) is 15 bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<14:8>) is not directly
readable or writable and comes from PCLATH. On any
Reset, the PC is cleared. Figure 3-4 shows the five
situations for the loading of the PC.
FIGURE 3-4: LOADING OF PC IN
DIFFERENT SITUATIONS
3.4.1 MODIFYING PCL
Executing any instruction with the PCL register as the
destination simultaneously causes the Program
Counter PC<14:8> bits (PCH) to be replaced by the
contents of the PCLATH register. This allows the entire
contents of the Program Counter to be changed by
writing the desired upper seven bits to the PCLATH
register. When the lower eight bits are written to the
PCL register, all 15 bits of the Program Counter will
change to the values contained in the PCLATH register
and those being written to the PCL register.
3.4.2 COMPUTED GOTO
A computed GOTO is accomplished by adding an offset to
the Program Counter (ADDWF PCL). When performing a
table read using a computed GOTO method, care should
be exercised if the table location crosses a PCL memory
boundary (each 256-byte block). Refer to Application
Note AN556, “Implementing a Table Read” (DS00556).
3.4.3 COMPUTED FUNCTION CALLs
A computed function CALL allows programs to maintain
tables of functions and provides another way to
execute state machines or look-up tables. When per-
forming a table read using a computed function CALL,
care should be exercised if the table location crosses a
PCL memory boundary (each 256-byte block).
If using the CALL instruction, the PCH<2:0> and PCL
registers are loaded with the operand of the CALL
instruction. PCH<6:3> is loaded with PCLATH<6:3>.
The CALLW instruction enables computed CALLs by
combining PCLATH and W to form the destination
address. A computed CALLW is accomplished by
loading the W register with the desired address and
executing CALLW. The PCL register is loaded with the
value of W and PCH is loaded with PCLATH.
3.4.4 BRANCHING
The branching instructions add an offset to the PC.
This allows relocatable code and code that crosses
page boundaries. There are two forms of branching,
BRW and BRA. The PC will have incremented to fetch
the next instruction in both cases. When using either
branching instruction, a PCL memory boundary may be
crossed.
If using BRW, load the W register with the desired
unsigned address and execute BRW. The entire PC will
be loaded with the address, PC + 1 + W.
If using BRA, the entire PC will be loaded with PC + 1 +,
the signed value of the operand of the BRA instruction.
78
6
14
0
0
411
0
60
14
78
60
014
15
014
15
014
PCL
PCL
PCL
PCL
PCL
PCH
PCH
PCH
PCH
PCH
PC
PC
PC
PC
PC
PCLATH
PCLATH
PCLATH
Instruction
with PCL as
Destination
GOTO,
CALL
CALLW
BRW
BRA
ALU result
OPCODE <10:0>
W
PC + W
PC + OPCODE <8:0>
Rev. 10-000042A
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2013-2015 Microchip Technology Inc. DS40001723D-page 35
PIC12(L)F1571/2
3.5 Stack
All devices have a 16-level x 15-bit wide hardware
stack (refer to Figures 3-5 through 3-8). The stack
space is not part of either program or data space. The
PC is PUSHed onto the stack when CALL or CALLW
instructions are executed, or an interrupt causes a
branch. The stack is POPed in the event of a RETURN,
RETLW or RETFIE instruction execution. PCLATH is
not affected by a PUSH or POP operation.
The stack operates as a circular buffer if the STVREN
bit is programmed to ‘0’ (Configuration Words). This
means that after the stack has been PUSHed sixteen
times, the seventeenth PUSH overwrites the value that
was stored from the first PUSH. The eighteenth PUSH
overwrites the second PUSH (and so on). The
STKOVF and STKUNF flag bits will be set on an
overflow/underflow, regardless of whether the Reset is
enabled.
3.5.1 ACCESSING THE STACK
The stack is available through the TOSH, TOSL and
STKPTR registers. STKPTR is the current value of the
Stack Pointer. The TOSH:TOSL register pair points to
the top of the stack. Both registers are read/writable.
TOS is split into TOSH and TOSL due to the 15-bit size
of the PC. To access the stack, adjust the value of
STKPTR, which will position TOSH:TOSL, then
read/write to TOSH:TOSL. The STKPTR is 5 bits to
allow detection of overflow and underflow.
During normal program operation, CALL, CALLW and
interrupts will increment STKPTR while RETLW,
RETURN and RETFIE will decrement STKPTR. At any
time, the STKPTR can be inspected to see how much
stack is left. The STKPTR always points at the currently
used place on the stack. Therefore, a CALL or CALLW
will increment the STKPTR and then write the PC, and
a return will unload the PC and then decrement the
STKPTR.
Reference Figure 3-5 through Figure 3-8 for examples
of accessing the stack.
FIGURE 3-5: ACCESSING THE STACK EXAMPLE 1
Note 1: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, CALLW, RETURN, RETLW and
RETFIE instructions or the vectoring to
an interrupt address.
Note: Care should be taken when modifying the
STKPTR while interrupts are enabled.
STKPTR = 0x1F Stack Reset Disabled
(STVREN = 0)
Stack Reset Enabled
(STVREN = 1)
Initial Stack Configuration:
After Reset, the stack is empty. The
empty stack is initialized so the Stack
Pointer is pointing at 0x1F. If the Stack
Overflow/Underflow Reset is enabled, the
TOSH/TOSL register will return ‘0’.Ifthe
Stack Overflow/Underflow Reset is
disabled, the TOSH/TOSL register will
return the contents of stack address
0x0F.
0x0000 STKPTR = 0x1F
TOSH:TOSL 0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x04
0x05
0x03
0x02
0x01
0x00
0x1F
TOSH:TOSL
Rev. 10-000043A
7/30/2013
PIC12(L)F1571/2
DS40001723D-page 36 2013-2015 Microchip Technology Inc.
FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2
FIGURE 3-7: ACCESSING THE STACK EXAMPLE 3
STKPTR = 0x00
Return Address
This figure shows the stack configuration
after the first CALL or a single interrupt.
If a RETURN instruction is executed, the
return address will be placed in the
Program Counter and the Stack Pointer
decremented to the empty state (0x1F).
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x04
0x05
0x03
0x02
0x01
0x00
TOSH:TOSL
Rev. 10-000043B
7/30/2013
STKPTR = 0x06
After seven CALLsorsixCALLs and an
interrupt, the stack looks like the figure on
the left. A series of RETURN instructions will
repeatedly place the return addresses into
the Program Counter and pop the stack.
Return Address
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x04
0x05
0x03
0x02
0x01
0x00
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
TOSH:TOSL
Rev. 10-000043C
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2013-2015 Microchip Technology Inc. DS40001723D-page 37
PIC12(L)F1571/2
FIGURE 3-8: ACCESSING THE STACK EXAMPLE 4
3.5.2 OVERFLOW/UNDERFLOW RESET
If the STVREN bit in the Configuration Words is
programmed to ‘1’, the device will be reset if the stack
is PUSHed beyond the sixteenth level or POPed
beyond the first level, setting the appropriate bits
(STKOVF or STKUNF, respectively) in the PCON
register.
3.6 Indirect Addressing
The INDFn registers are not physical registers. Any
instruction that accesses an INDFn register actually
accesses the register at the address specified by the
File Select Registers (FSR). If the FSRn address
specifies one of the two INDFn registers, the read will
return ‘0’ and the write will not occur (though Status bits
may be affected). The FSRn register value is created
by the pair, FSRnH and FSRnL.
The FSR registers form a 16-bit address that allows an
addressing space with 65536 locations. These locations
are divided into three memory regions:
• Traditional Data Memory
• Linear Data Memory
• Program Flash Memory
STKPTR = 0x10
When the stack is full, the next CALL or
an interrupt will set the Stack Pointer to
0x10. This is identical to address 0x00 so
the stack will wrap and overwrite the
return address at 0x00. If the Stack
Overflow/Underflow Reset is enabled, a
Reset will occur and location 0x00 will
not be overwritten.
Return Address0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x04
0x05
0x03
0x02
0x01
0x00
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
TOSH:TOSL
Rev. 10-000043D
7/30/2013
PIC12(L)F1571/2
DS40001723D-page 38 2013-2015 Microchip Technology Inc.
FIGURE 3-9: INDIRECT ADDRESSING
0x0000
0x0FFF
0x0000
0x7FFF0xFFFF
0x0000
0x0FFF
0x1000
0x1FFF
0x2000
0x29AF
0x29B0
0x7FFF
0x8000
Reserved
Reserved
Traditional
Data Memory
Linear
Data Memory
Program
Flash Memory
FSR
Address
Range
Note: Not all memory regions are completely implemented. Consult device memory tables for memory limits.
Rev. 10-000044A
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PIC12(L)F1571/2
3.6.1 TRADITIONAL DATA MEMORY
The traditional data memory is a region from FSR
address, 0x000, to FSR address, 0xFFF. The
addresses correspond to the absolute addresses of all
SFR, GPR and common registers.
FIGURE 3-10: TRADITIONAL DATA MEMORY MAP
Direct Addressing
40BSR 60
From Opcode
0
07FSRxH
000
07FSRxL
Indirect Addressing
00000 00001 00010 11111
Bank Select Location Select
0x00
0x7F
Bank Select Location Select
Bank 0 Bank 1 Bank 2 Bank 31
Rev. 10-000056A
7/31/2013
PIC12(L)F1571/2
DS40001723D-page 40 2013-2015 Microchip Technology Inc.
3.6.2 LINEAR DATA MEMORY
The linear data memory is the region from FSR
address, 0x2000, to FSR address, 0x29AF. This region
is a virtual region that points back to the 80-byte blocks
of GPR memory in all the banks.
Unimplemented memory reads as 0x00. Use of the
linear data memory region allows buffers to be larger
than 80 bytes because incrementing the FSR beyond
one bank will go directly to the GPR memory of the next
bank.
The 16 bytes of common memory are not included in
the linear data memory region.
FIGURE 3-11: LINEAR DATA MEMORY
MAP
3.6.3 PROGRAM FLASH MEMORY
To make constant data access easier, the entire
Program Flash Memory is mapped to the upper half of
the FSR address space. When the MSb of FSRnH is
set, the lower 15 bits are the address in program
memory which will be accessed through INDF. Only the
lower eight bits of each memory location are accessible
via INDF. Writing to the Program Flash Memory cannot
be accomplished via the FSR/INDF interface. All
instructions that access Program Flash Memory via the
FSR/INDF interface will require one additional
instruction cycle to complete.
FIGURE 3-12: PROGRAM FLASH
MEMORY MAP
0x020
Bank 0
0x06F
0x0A0
Bank 1
0x0EF
0x120
Bank 2
0x16F
0xF20
Bank 30
0xF6F
001
0077FSRnH FSRnL
Location Select 0x2000
0x29AF
Rev. 10-000057A
7/31/2013
0x0000
Program
Flash
Memory
(low 8 bits)
0x7FFF
1
0077FSRnH FSRnL
Location Select 0x8000
0xFFFF
Rev. 10-000058A
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PIC12(L)F1571/2
4.0 DEVICE CONFIGURATION
Device configuration consists of Configuration Words,
code protection and Device ID.
4.1 Configuration Words
There are several Configuration Word bits that allow
different oscillator and memory protection options.
These are implemented as Configuration Word 1 at
8007h and Configuration Word 2 at 8008h.
Note: The DEBUG bit in the Configuration Words
is managed automatically by device
development tools, including debuggers
and programmers. For normal device
operation, this bit should be maintained as
a ‘1’.
PIC12(L)F1571/2
DS40001723D-page 42 2013-2015 Microchip Technology Inc.
4.2 Register Definitions: Configuration Words
REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1
U-1 U-1 R/P-1 R/P-1 R/P-1 U-1
——CLKOUTEN BOREN<1:0>(1) —
bit 13 bit 8
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-1 R/P-1 R/P-1
CP(2) MCLRE PWRTE(1) WDTE<1:0> —FOSC<1:0>
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared ‘1’ = Bit is set n = Value when blank or after bulk erase
bit 13-12 Unimplemented: Read as ‘1’
bit 11 CLKOUTEN: Clock Out Enable bit
1 = Off – CLKOUT function is disabled; I/O or oscillator function on CLKOUT pin
0 =
On
– CLKOUT function is enabled on CLKOUT pin
bit 10-9 BOREN<1:0>: Brown-out Reset Enable bits(1)
11 =
On
– Brown-out Reset is enabled; the SBOREN bit is ignored
10 = Sleep – Brown-out Reset is enabled while running and disabled in Sleep; the SBOREN bit is ignored
01 =
SBODEN
– Brown-out Reset is controlled by the SBOREN bit in the BORCON register
00 = Off – Brown-out Reset is disabled; the SBOREN bit is ignored
bit 8 Unimplemented: Read as ‘1’
bit 7 CP: Flash Program Memory Code Protection bit(2)
1 = Off – Code protection is off; program memory can be read and written
0 =
On
– Code protection is on; program memory cannot be read or written externally
bit 6 MCLRE: MCLR/VPP Pin Function Select bit
If LVP bit = 1 (
On
):
This bit is ignored. MCLR/VPP pin function is MCLR; weak pull-up is enabled.
If LVP bit = 0 (Off):
1 =
On
– MCLR/VPP pin function is MCLR; weak pull-up is enabled
0 = Off – MCLR/VPP pin function is a digital input, MCLR is internally disabled; weak pull-up is under control
of pin’s WPU control bit
bit 5 PWRTE: Power-up Timer Enable bit(1)
1 = Off – PWRT is disabled
0 =
On
– PWRT is enabled
bit 4-3 WDTE<1:0>: Watchdog Timer Enable bits
11 =
On
– WDT is enabled; SWDTEN is ignored
10 = Sleep – WDT is enabled while running and disabled in Sleep; SWDTEN is ignored
01 =
SWDTEN
– WDT is controlled by the SWDTEN bit in the WDTCON register
00 = Off – WDT is disabled; SWDTEN is ignored
bit 2 Unimplemented: Read as ‘1’
bit 1-0 FOSC<1:0>: Oscillator Selection bits
11 = ECH – External Clock, High-Power mode: CLKI on CLKI
10 = ECM – External Clock, Medium Power mode: CLKI on CLKI
01 =
ECL
– External Clock, Low-Power mode: CLKI on CLKI
00 =
INTOSC
– I/O function on CLKI
Note 1: Enabling Brown-out Reset does not automatically enable the Power-up Timer.
2: Once enabled, code-protect can only be disabled by bulk erasing the device.
2013-2015 Microchip Technology Inc. DS40001723D-page 43
PIC12(L)F1571/2
REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1
LVP(1) DEBUG(2) LPBOREN BORV(3) STVREN PLLEN
bit 13 bit 8
U-1 U-1 U-1 U-1 U-1 U-1 R/P-1 R/P-1
——————WRT<1:0>
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared ‘1’ = Bit is set n = Value when blank or after bulk erase
bit 13 LVP: Low-Voltage Programming Enable bit(1)
1 = On – Low-voltage programming is enabled, MCLR/VPP pin function is MCLR; MCLRE
Configuration bit is ignored
0 = Off – High voltage on MCLR/VPP must be used for programming
bit 12 DEBUG: Debugger Mode bit(2)
1 = Off – In-Circuit Debugger is disabled; ICSPCLK and ICSPDAT are general purpose I/O pins
0 = On – In-Circuit Debugger is enabled; ICSPCLK and ICSPDAT are dedicated to the debugger
bit 11 LPBOREN: Low-Power Brown-out Reset Enable bit
1 = Off – Low-power Brown-out Reset is disabled
0 = On – Low-power Brown-out Reset is enabled
bit 10 BORV: Brown-out Reset Voltage Selection bit(3)
1 = Low – Brown-out Reset voltage (VBOR), low trip point selected
0 = High – Brown-out Reset voltage (VBOR), high trip point selected
bit 9 STVREN: Stack Overflow/Underflow Reset Enable bit
1 = On – Stack overflow or underflow will cause a Reset
0 = Off – Stack overflow or underflow will not cause a Reset
bit 8 PLLEN: PLL Enable bit
1 = On – 4xPLL is enabled
0 = Off – 4xPLL is disabled
bit 7-2 Unimplemented: Read as ‘1’
bit 1-0 WRT<1:0>: Flash Memory Self-Write Protection bits
2 kW Flash Memory (PIC12F1572):
11 = Off – Write protection is off
10 = Boot – 000h to 1FFh is write-protected, 200h to 7FFh may be modified by PMCON control
01 = Half – 000h to 3FFh is write-protected, 400h to 7FFh may be modified by PMCON control
00 = All – 000h to 7FFh is write-protected, no addresses may be modified by PMCON control
1 kW Flash Memory (PIC12(L)F1571):
11 = Off – Write protection is off
10 = Boot – 000h to 0FFh is write-protected, 100h to 3FFh may be modified by PMCON control
01 = Half – 000h to 1FFh is write-protected, 200h to 3FFh may be modified by PMCON control
00 = All – 000h to 3FFh is write-protected, no addresses may be modified by PMCON control
Note 1: This bit cannot be programmed to ‘0’ when programming mode is entered via LVP.
2: The DEBUG bit in Configuration Words is managed automatically by device development tools, including
debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’.
3: See VBOR parameter for specific trip point voltages.
PIC12(L)F1571/2
DS40001723D-page 44 2013-2015 Microchip Technology Inc.
4.3 Code Protection
Code protection allows the device to be protected from
unauthorized access. Internal access to the program
memory is unaffected by any code protection setting.
4.3.1 PROGRAM MEMORY PROTECTION
The entire program memory space is protected from
external reads and writes by the CP bit in the
Configuration Words. When CP = 0, external reads and
writes of program memory are inhibited and a read will
return all ‘0’s. The CPU can continue to read program
memory, regardless of the protection bit settings.
Writing the program memory is dependent upon the
write protection setting. See Section 4.4 “Write
Protection” for more information.
4.4 Write Protection
Write protection allows the device to be protected from
unintended self-writes. Applications, such as boot-
loader software, can be protected while allowing other
regions of the program memory to be modified.
The WRT<1:0> bits in the Configuration Words define
the size of the program memory block that is protected.
4.5 User ID
Four memory locations (8000h-8003h) are designated as
ID locations where the user can store checksum or other
code identification numbers. These locations are
readable and writable during normal execution. See
Section 10.4 “User ID, Device ID and Configuration
Word Access” for more information on accessing
these memory locations. For more information on
checksum calculation, see the “PIC12(L)F1571/2
Memory Programming Specification” (DS40001713).
4.6 Device ID and Revision ID
The 14-bit Device ID word is located at 8006h and the
14-bit Revision ID is located at 8005h. These locations
are read-only and cannot be erased or modified. See
Section 10.4 “User ID, Device ID and Configuration
Word Access” for more information on accessing
these memory locations.
Development tools, such as device programmers and
debuggers, may be used to read the Device ID and
Revision ID.
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PIC12(L)F1571/2
4.7 Register Definitions: Device ID
REGISTER 4-3: DEVICEID: DEVICE ID REGISTER(1)
RRRRRR
DEV<13:8>
bit 13 bit 8
RRRRRRRR
DEV<7:0>
bit 7 bit 0
Legend:
x = Bit is unknown
R = Readable bit
‘0’ = Bit is cleared ‘1’ = Bit is set
bit 13-0 DEV<13:0>: Device ID bits
Refer to Tabl e 4-1 to determine what these bits will read on which device. A value of 3FFFh is invalid.
Note 1: This location cannot be written.
REGISTER 4-4: REVISIONID: REVISION ID REGISTER(1)
RRRRRR
REV<13:8>
bit 13 bit 8
RRRRRRRR
REV<7:0>
bit 7 bit 0
Legend:
x = Bit is unknown
R = Readable bit
‘0’ = Bit is cleared ‘1’ = Bit is set
bit 13-0 REV<13:0>: Revision ID bits
These bits are used to identify the device revision.
Note 1: This location cannot be written.
TABLE 4-1: DEVICE ID VALUES
DEVICE Device ID Revision ID
PIC12F1571 3051h 2xxxh
PIC12LF1571 3053h 2xxxh
PIC12F1572 3050h 2xxxh
PIC12LF1572 3052h 2xxxh
PIC12(L)F1571/2
DS40001723D-page 46 2013-2015 Microchip Technology Inc.
NOTES:
2013-2015 Microchip Technology Inc. DS40001723D-page 47
PIC12(L)F1571/2
5.0 OSCILLATOR MODULE
5.1 Overview
The oscillator module has a wide variety of clock
sources and selection features that allow it to be used in
a wide range of applications, while maximizing perfor-
mance and minimizing power consumption. Figure 5-1
illustrates a block diagram of the oscillator module.
Clock sources can be supplied from external oscillators,
quartz crystal resonators, ceramic resonators and
Resistor-Capacitor (RC) circuits. In addition, the system
clock source can be supplied from one of two internal
oscillators and PLL circuits, with a choice of speeds
selectable via software. Additional clock features
include:
• Selectable system clock source between external
or internal sources via software
• Oscillator Start-up Timer (OST) ensures stability
of crystal oscillator sources
The oscillator module can be configured in one of the
following clock modes:
1. ECL – External Clock Low-Power mode
(0 MHz to 0.5 MHz)
2. ECM – External Clock Medium Power mode
(0.5 MHz to 4 MHz)
3. ECH – External Clock High-Power mode
(4 MHz to 32 MHz)
4. INTOSC – Internal Oscillator (31 kHz to 32 MHz)
Clock Source modes are selected by the FOSC<1:0>
bits in the Configuration Words. The FOSC bits deter-
mine the type of oscillator that will be used when the
device is first powered.
The ECH, ECM, and ECL Clock modes rely on an
external logic level signal as the device clock source.
The INTOSC internal oscillator block produces low,
medium and high-frequency clock sources, designated
as LFINTOSC, MFINTOSC and HFINTOSC (see
Internal Oscillator Block, Figure 5-1). A wide selection
of device clock frequencies may be derived from these
three clock sources.
PIC12(L)F1571/2
DS40001723D-page 48 2013-2015 Microchip Technology Inc.
FIGURE 5-1: SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM
Rev. 10-000155A
10/11/2013
31 kHz
Oscillator
Prescaler
HFINTOSC(1)
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
*500 kHz
*250 kHz
*125 kHz
62.5 kHz
*31.25 kHz
*31 kHz
IRCF<3:0>
4
INTOSC
to CPU and
Peripherals
Sleep
F
OSC
(1)
LFINTOSC(1)
to WDT, PWRT, and
other Peripherals
* Available with more than one IRCF selection
SCS<1:0>
2
600 kHz
Oscillator
FRC(1) to ADC and
other Peripherals
CLKIN
1
0
4x PLL(2)
HFPLL
16 MHz
500 kHz
Oscillator
MFINTOSC(1)
Internal Oscillator
Block
to Peripherals
PLLEN
SPLLEN
FOSC<1:0>
2
00
1x
01Reserved
Note 1: See Section 5.2 “Clock Source Types”.
2: ST Buffer is high-speed type when using T1CKI.
3: If FOSC<1:0> = 00, 4x PLL can only be used if IRCF<3:0> = 1110.
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5.2 Clock Source Types
Clock sources can be classified as external or internal.
External clock sources rely on external circuitry for the
clock source to function.
Internal clock sources are contained within the
oscillator module. The internal oscillator block has two
internal oscillators and a dedicated Phase-Locked
Loop (HFPLL) that are used to generate three internal
system clock sources: the 16 MHz High-Frequency
Internal Oscillator (HFINTOSC), 500 kHz Medium
Frequency Internal Oscillator (MFINTOSC) and the
31 kHz Low-Frequency Internal Oscillator (LFINTOSC).
The system clock can be selected between external or
internal clock sources via the System Clock Select
(SCS<1:0>) bits in the OSCCON register. See
Section 5.3 “Clock Switching” for additional
information.
5.2.1 EXTERNAL CLOCK SOURCES
An external clock source can be used as the device
system clock by performing one of the following
actions:
• Program the FOSC<1:0> bits in the Configuration
Words to select an external clock source that will
be used as the default system clock upon a
device Reset.
• Write the SCS<1:0> bits in the OSCCON register
to switch the system clock source to:
- Timer1 oscillator during run time, or
- An external clock source determined by the
value of the FOSCx bits.
See Section 5.3 “Clock Switching” for more
information.
5.2.1.1 EC Mode
The External Clock (EC) mode allows an externally
generated logic level signal to be the system clock
source. When operating in this mode, an external clock
source is connected to the CLKIN input. CLKOUT is
available for general purpose I/Os or CLKOUT.
Figure 5-2 shows the pin connections for EC mode.
EC mode has three power modes to select from through
the FOSCx bits in the Configuration Words:
• ECH – High power, 4-20 MHz
• ECM – Medium power, 0.5-4 MHz
• ECL – Low power, 0-0.5 MHz
The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
operation after a Power-on Reset (POR) or wake-up
from Sleep. Because the PIC® MCU design is fully
static, stopping the external clock input will have the
effect of halting the device while leaving all data intact.
Upon restarting the external clock, the device will
resume operation as if no time had elapsed.
FIGURE 5-2: EXTERNAL CLOCK (EC)
MODE OPERATION
CLKIN
CLKOUT
Clock from
Ext. System
PIC® MCU
FOSC/4 or
Note 1: Output depends upon CLKOUTEN bit of
the Configuration Words.
I/O(1)
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5.2.2 INTERNAL CLOCK SOURCES
The device may be configured to use the internal oscil-
lator block as the system clock by performing one of the
following actions:
• Program the FOSC<1:0> bits in the Configuration
Words to select the INTOSC clock source, which
will be used as the default system clock upon a
device Reset.
• Write the SCS<1:0> bits in the OSCCON register
to switch the system clock source to the internal
oscillator during run time. See
Section 5.3 “Clock Switching”for more
information.
In INTOSC mode, CLKIN is available for general
purpose I/O. CLKOUT is available for general purpose
I/O or CLKOUT.
The function of the OSC2/CLKOUT pin is determined
by the CLKOUTEN bit in the Configuration Words.
The internal oscillator block has two independent
oscillators and a dedicated Phase-Locked Loop,
HFPLL, that can produce one of three internal system
clock sources.
1. The HFINTOSC (High-Frequency Internal
Oscillator) is factory calibrated and operates at
16 MHz. The HFINTOSC source is generated
from the 500 kHz MFINTOSC source and the
dedicated Phase-Locked Loop, HFPLL. The
frequency of the HFINTOSC can be
user-adjusted via software using the OSCTUNE
register (Register 5-3).
2. The MFINTOSC (Medium Frequency Internal
Oscillator) is factory calibrated and operates at
500 kHz. The frequency of the MFINTOSC can
be user-adjusted via software using the
OSCTUNE register (Register 5-3).
3. The LFINTOSC (Low-Frequency Internal
Oscillator) is uncalibrated and operates at
31 kHz.
5.2.2.1 HFINTOSC
The High-Frequency Internal Oscillator (HFINTOSC) is
a factory calibrated 16 MHz internal clock source. The
frequency of the HFINTOSC can be altered via
software using the OSCTUNE register (Register 5-3).
The output of the HFINTOSC connects to a postscaler
and multiplexer (see Figure 5-1). One of multiple
frequencies derived from the HFINTOSC can be
selected via software using the IRCF<3:0> bits of the
OSCCON register. See Section 5.2.2.8 “Internal
Oscillator Clock Switch Timing” for more information.
The HFINTOSC is enabled by:
• Configuring the IRCF<3:0> bits of the OSCCON
register for the desired HF frequency, and
• Setting FOSC<1:0> = 00, or
• Setting the System Clock Source x (SCSx) bits of
the OSCCON register to ‘1x’.
A fast start-up oscillator allows internal circuits to power
up and stabilize before switching to HFINTOSC.
The High-Frequency Internal Oscillator Ready bit
(HFIOFR) of the OSCSTAT register indicates when the
HFINTOSC is running.
The High-Frequency Internal Oscillator Status Locked
bit (HFIOFL) of the OSCSTAT register indicates when
the HFINTOSC is running within 2% of its final value.
The High-Frequency Internal Oscillator Stable bit
(HFIOFS) of the OSCSTAT register indicates when the
HFINTOSC is running within 0.5% of its final value.
5.2.2.2 MFINTOSC
The Medium Frequency Internal Oscillator (MFINTOSC)
is a factory calibrated 500 kHz internal clock source.
The frequency of the MFINTOSC can be altered via
software using the OSCTUNE register (Register 5-3).
The output of the MFINTOSC connects to a postscaler
and multiplexer (see Figure 5-1). One of nine
frequencies derived from the MFINTOSC can be
selected via software using the IRCF<3:0> bits of the
OSCCON register. See Section 5.2.2.8 “Internal
Oscillator Clock Switch Timing” for more information.
The MFINTOSC is enabled by:
• Configuring the IRCF<3:0> bits of the OSCCON
register for the desired HF frequency, and
• Setting FOSC<1:0> = 00, or
• Setting the System Clock Source x (SCSx) bits of
the OSCCON register to ‘1x’
The Medium Frequency Internal Oscillator Ready bit
(MFIOFR) of the OSCSTAT register indicates when the
MFINTOSC is running.
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5.2.2.3 Internal Oscillator Frequency
Adjustment
The 500 kHz internal oscillator is factory calibrated.
This internal oscillator can be adjusted in software by
writing to the OSCTUNE register (Register 5-3). Since
the HFINTOSC and MFINTOSC clock sources are
derived from the 500 kHz internal oscillator, a change
in the OSCTUNE register value will apply to both.
The default value of the OSCTUNE register is ‘0’. The
value is a 6-bit two’s complement number. A value of
1Fh will provide an adjustment to the maximum
frequency. A value of 20h will provide an adjustment to
the minimum frequency.
When the OSCTUNE register is modified, the oscillator
frequency will begin shifting to the new frequency. Code
execution continues during this shift. There is no
indication that the shift has occurred.
OSCTUNE does not affect the LFINTOSC frequency.
Operation of features that depends on the LFINTOSC
clock source frequency, such as the Power-up Timer
(PWRT), Watchdog Timer (WDT) and peripherals, are
not affected by the change in frequency.
5.2.2.4 LFINTOSC
The Low-Frequency Internal Oscillator (LFINTOSC) is
an uncalibrated 31 kHz internal clock source.
The output of the LFINTOSC connects to a multiplexer
(see Figure 5-1). Select 31 kHz, via software, using
the IRCF<3:0> bits of the OSCCON register. See
Section 5.2.2.8 “Internal Oscillator Clock Switch
Timing” for more information. The LFINTOSC is also
the frequency for the Power-up Timer (PWRT),
Watchdog Timer (WDT) and Fail-Safe Clock Monitor
(FSCM).
The LFINTOSC is enabled by selecting 31 kHz
(IRCF<3:0> (OSCCON<6:3>) = 0000) as the system
clock source (SCS<1:0> (OSCCON<1:0>) = 1x) or
when any of the following are enabled:
• Configure the IRCF<3:0> bits of the OSCCON
register for the desired LF frequency, and
• Set FOSC<1:0> = 00, or
• Set the System Clock Source x (SCSx) bits of the
OSCCON register to ‘1x’
Peripherals that use the LFINTOSC are:
• Power-up Timer (PWRT)
• Watchdog Timer (WDT)
The Low-Frequency Internal Oscillator Ready bit
(LFIOFR) of the OSCSTAT register indicates when the
LFINTOSC is running.
5.2.2.5 FRC
The FRC clock is an uncalibrated, nominal 600 kHz
peripheral clock source.
The FRC is automatically turned on by the peripherals
requesting the FRC clock.
The FRC clock will continue to run during Sleep.
5.2.2.6 Internal Oscillator Frequency
Selection
The system clock speed can be selected via software
using the Internal Oscillator Frequency Select bits
IRCF<3:0> of the OSCCON register.
The postscaler outputs of the 16 MHz HFINTOSC,
500 kHz MFINTOSC and 31 kHz LFINTOSC output
connect to a multiplexer (see Figure 5-1). The Internal
Oscillator Frequency Select bits, IRCF<3:0> of the
OSCCON register, select the frequency output of the
internal oscillators. One of the following frequencies
can be selected via software:
• 32 MHz (requires 4x PLL)
•16 MHz
•8 MHz
•4 MHz
•2 MHz
•1 MHz
• 500 kHz (default after Reset)
•250 kHz
•125 kHz
•62.5 kHz
•31.25 kHz
• 31 kHz (LFINTOSC)
The IRCF<3:0> bits of the OSCCON register allow
duplicate selections for some frequencies. These dupli-
cate choices can offer system design trade-offs. Lower
power consumption can be obtained when changing
oscillator sources for a given frequency. Faster transi-
tion times can be obtained between frequency changes
that use the same oscillator source.
Note: Following any Reset, the IRCF<3:0> bits
of the OSCCON register are set to ‘0111’
and the frequency selection is set to
500 kHz. The user can modify the IRCFx
bits to select a different frequency.
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5.2.2.7 32 MHz Internal Oscillator
Frequency Selection
The internal oscillator block can be used with the
4x PLL associated with the external oscillator block to
produce a 32 MHz internal system clock source. The
following settings are required to use the 32 MHz
internal clock source:
• The FOSCx bits in the Configuration Words must
be set to use the INTOSC source as the device
system clock (FOSC<1:0> = 00).
• The SCSx bits in the OSCCON register must be
cleared to use the clock determined by
FOSC<1:0> in the Configuration Words
(SCS<1:0> = 00).
• The IRCFx bits in the OSCCON register must be
set to the 8 MHz HFINTOSC to use
(IRCF<3:0> = 1110).
• The SPLLEN bit in the OSCCON register must be
set to enable the 4x PLL or the PLLEN bit of the
Configuration Words must be programmed to a
‘1’.
The 4x PLL is not available for use with the internal
oscillator when the SCSx bits of the OSCCON register
are set to ‘1x’. The SCSx bits must be set to ‘00’ to use
the 4x PLL with the internal oscillator.
5.2.2.8 Internal Oscillator Clock Switch
Timing
When switching between the HFINTOSC, MFINTOSC
and the LFINTOSC, the new oscillator may already be
shut down to save power (see Figure 5-3). If this is the
case, there is a delay after the IRCF<3:0> bits of the
OSCCON register are modified before the frequency
selection takes place. The OSCSTAT register will
reflect the current active status of the HFINTOSC,
MFINTOSC and LFINTOSC oscillators. The sequence
of a frequency selection is as follows:
1. IRCF<3:0> bits of the OSCCON register are
modified.
2. If the new clock is shut down, a clock start-up
delay is started.
3. Clock switch circuitry waits for a falling edge of
the current clock.
4. The current clock is held low and the clock
switch circuitry waits for a rising edge in the new
clock.
5. The new clock is now active.
6. The OSCSTAT register is updated as required.
7. Clock switch is complete.
See Figure 5-3 for more details.
If the internal oscillator speed is switched between two
clocks of the same source, there is no start-up delay
before the new frequency is selected. Clock switching
time delays are shown in Table 5-1.
Start-up delay specifications are located in the
oscillator tables of Section 26.0 “Electrical
Specifications”.
Note: When using the PLLEN bit of the
Configuration Words, the 4x PLL cannot
be disabled by software and the 8 MHz
HFINTOSC option will no longer be
available.
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FIGURE 5-3: INTERNAL OSCILLATOR SWITCH TIMING
HFINTOSC/
LFINTOSC
IRCF<3:0>
System Clock
HFINTOSC/
LFINTOSC
IRCF <3:0>
System Clock
0= 0
0= 0
Oscillator Delay(1) 2-Cycle Sync Running
2-Cycle Sync Running
HFINTOSC/ LFINTOSC (WDT disabled)
HFINTOSC/ LFINTOSC (WDT enabled)
LFINTOSC
HFINTOSC/
IRCF <3:0>
System Clock
= 0 0
2-Cycle Sync
Running
LFINTOSC HFINTOSC/MFINTOSC
LFINTOSC Turns Off unless WDT is Enabled
MFINTOSC
MFINTOSC
MFINTOSC
MFINTOSC
MFINTOSC
Oscillator
Note 1: See Table 5 -1 (Oscillator Switching Delays) for more information.
Delay
(1)
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5.3 Clock Switching
The system clock source can be switched between
external and internal clock sources via software using
the System Clock Select (SCSx) bits of the OSCCON
register. The following clock sources can be selected
using the SCSx bits:
• Default system oscillator determined by FOSCx
bits in the Configuration Words
• Timer1 32 kHz crystal oscillator
• Internal Oscillator Block (INTOSC)
5.3.1 SYSTEM CLOCK SELECT (SCSx)
BITS
The System Clock Select (SCSx) bits of the OSCCON
register select the system clock source that is used for
the CPU and peripherals.
• When the SCSx bits of the OSCCON register = 00,
the system clock source is determined by the value
of the FOSC<1:0> bits in the Configuration Words.
• When the SCSx bits of the OSCCON register = 01,
the system clock source is the Timer1 oscillator.
• When the SCSx bits of the OSCCON register = 1x,
the system clock source is chosen by the internal
oscillator frequency selected by the IRCF<3:0> bits
of the OSCCON register. After a Reset, the SCSx
bits of the OSCCON register are always cleared.
When switching between clock sources, a delay is
required to allow the new clock to stabilize. These
oscillator delays are shown in Table 5-1.
5.4 Clock Switching Before Sleep
When clock switching from an old clock to a new clock
is requested, just prior to entering Sleep mode, it is
necessary to confirm that the switch is complete before
the SLEEP instruction is executed. Failure to do so may
result in an incomplete switch and consequential loss of
the system clock altogether. Clock switching is
confirmed by monitoring the clock status bits in the
OSCSTAT register. Switch confirmation can be accom-
plished by sensing that the ready bit for the new clock is
set or the ready bit for the old clock is cleared. For
example, when switching between the internal oscillator
with the PLL and the internal oscillator without the PLL,
monitor the PLLR bit. When PLLR is set, the switch to
32 MHz operation is complete. Conversely, when PLLR
is cleared, the switch from 32 MHz operation to the
selected internal clock is complete.
TABLE 5-1: OSCILLATOR SWITCHING DELAYS
Note: Any automatic clock switch does not
update the SCSx bits of the OSCCON
register. The user can monitor the OSTS
bit of the OSCSTAT register to determine
the current system clock source.
Switch From Switch To Frequency Oscillator Delay
Sleep/POR
LFINTOSC(1)
MFINTOSC(1)
HFINTOSC(1)
31 kHz
31.25 kHz-500 kHz
31.25kHz-16MHz
Oscillator Warm-up Delay (TWARM)(2)
Sleep/POR EC(1) DC – 32 MHz 2 cycles
LFINTOSC EC(1) DC – 32 MHz 1 cycle of each
Any Clock Source MFINTOSC(1)
HFINTOSC(1)
31.25 kHz-500 kHz
31.25kHz-16MHz 2s (approx.)
Any Clock Source LFINTOSC(1) 31 kHz 1 cycle of each
PLL Inactive PLL Active 16-32 MHz 2 ms (approx.)
Note 1: PLL inactive.
2: See Section 26.0 “Electrical Specifications”.
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5.5 Register Definitions: Oscillator Control
REGISTER 5-1: OSCCON: OSCILLATOR CONTROL REGISTER
R/W-0/0 R/W-0/0 R/W-1/1 R/W-1/1 R/W-1/1 U-0 R/W-0/0 R/W-0/0
SPLLEN IRCF<3:0> —SCS<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7 SPLLEN: Software PLL Enable bit
If PLLEN in Configuration Words = 1:
SPLLEN bit is ignored. 4x PLL is always enabled (subject to oscillator requirements).
If PLLEN in Configuration Words = 0:
1 = 4x PLL Is enabled
0 = 4x PLL is disabled
bit 6-3 IRCF<3:0>: Internal Oscillator Frequency Select bits
1111 = 16 MHz HF
1110 = 8 MHz or 32 MHz HF (see Section 5.2.2.1 “HFINTOSC”)
1101 = 4 MHz HF
1100 = 2 MHz HF
1011 = 1 MHz HF
1010 = 500 kHz HF(1)
1001 = 250 kHz HF(1)
1000 = 125 kHz HF(1)
0111 = 500 kHz MF (default upon Reset)
0110 = 250 kHz MF
0101 = 125 kHz MF
0100 = 62.5 kHz MF
0011 = 31.25 kHz HF(1)
0010 = 31.25 kHz MF
000x = 31 kHz LF
bit 2 Unimplemented: Read as ‘0’
bit 1-0 SCS<1:0>: System Clock Select bits
1x = Internal oscillator block
01 = Timer1 oscillator
00 = Clock determined by FOSC<1:0> in Configuration Words
Note 1: Duplicate frequency derived from HFINTOSC.
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REGISTER 5-2: OSCSTAT: OSCILLATOR STATUS REGISTER
U-0 R-0/q R-q/q R-0/q R-0/q R-q/q R-0/q R-0/q
— PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit q = Conditional bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7 Unimplemented: Read as ‘0’
bit 6 PLLR 4x PLL Ready bit
1 = 4x PLL is ready
0 = 4x PLL is not ready
bit 5 OSTS: Oscillator Start-up Timer Status bit
1 = Running from the clock defined by the FOSC<1:0> bits of the Configuration Words
0 = Running from an internal oscillator (FOSC<1:0> = 00)
bit 4 HFIOFR: High-Frequency Internal Oscillator Ready bit
1 = HFINTOSC is ready
0 = HFINTOSC is not ready
bit 3 HFIOFL: High-Frequency Internal Oscillator Locked bit
1 = HFINTOSC is at least 2% accurate
0 = HFINTOSC is not 2% accurate
bit 2 MFIOFR: Medium Frequency Internal Oscillator Ready bit
1 = MFINTOSC is ready
0 = MFINTOSC is not ready
bit 1 LFIOFR: Low-Frequency Internal Oscillator Ready bit
1 = LFINTOSC is ready
0 = LFINTOSC is not ready
bit 0 HFIOFS: High-Frequency Internal Oscillator Stable bit
1 = HFINTOSC is at least 0.5% accurate
0 = HFINTOSC is not 0.5% accurate
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TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
TABLE 5-3: SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES
REGISTER 5-3: OSCTUNE: OSCILLATOR TUNING REGISTER
U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
—— TUN<5:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 TUN<5:0>: Frequency Tuning bits
100000 = Minimum frequency
•
•
•
111111 =
000000 = Oscillator module is running at the factory-calibrated frequency
000001 =
•
•
•
011110 =
011111 = Maximum frequency
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
OSCCON SPLLEN IRCF<3:0> —SCS<1:0>55
OSCSTAT — PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 56
OSCTUNE —— TUN<5:0> 57
T1CON TMR1CS<1:0> T1CKPS<1:0> —T1SYNC —TMR1ON 167
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 Register
on Page
CONFIG1 13:8 — — — —CLKOUTENBOREN<1:0> —42
7:0 CP MCLRE PWRTE WDTE<1:0> — FOSC<1:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.
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NOTES:
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6.0 RESETS
There are multiple ways to reset this device:
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• Low-Power Brown-out Reset (LPBOR)
•MCLR Reset
•WDT Reset
•RESET instruction
• Stack Overflow
• Stack Underflow
• Programming mode exit
To allow VDD to stabilize, an optional Power-up Timer
can be enabled to extend the Reset time after a BOR
or POR event.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 6-1.
FIGURE 6-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Note 1: See Table 6-1 for BOR active conditions.
Device
Reset
Power-on
Reset
WDT
Time-out
Brown-out
Reset
LPBOR
Reset
RESET Instruction
MCLRE
Sleep
BOR
Active(1)
PWRTE
LFINTOSC
VDD
ICSP™ Programming Mode Exit
Stack Underflow
Stack Overlfow
VPP/MCLR
RPower-up
Timer
Rev. 10-000006A
8/14/2013
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6.1 Power-on Reset (POR)
The POR circuit holds the device in Reset until VDD has
reached an acceptable level for minimum operation.
Slow rising VDD, fast operating speeds or analog
performance may require greater than minimum VDD.
The PWRT, BOR or MCLR features can be used to
extend the start-up period until all device operation
conditions have been met.
6.1.1 POWER-UP TIMER (PWRT)
The Power-up Timer provides a nominal 64 ms
time-out on a POR or Brown-out Reset.
The device is held in Reset as long as PWRT is active.
The PWRT delay allows additional time for the VDD to
rise to an acceptable level. The Power-up Timer is
enabled by clearing the PWRTE bit in the Configuration
Words.
The Power-up Timer starts after the release of the POR
and BOR.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting” (DS00000607).
6.2 Brown-out Reset (BOR)
The BOR circuit holds the device in Reset when VDD
reaches a selectable minimum level. Between the
POR and BOR, complete voltage range coverage for
execution protection can be implemented.
The Brown-out Reset module has four operating
modes controlled by the BOREN<1:0> bits in the
Configuration Words. The four operating modes are:
• BOR is always on
• BOR is off when in Sleep
• BOR is controlled by software
• BOR is always off
Refer to Table 6 -1 for more information.
The Brown-out Reset voltage level is selectable by
configuring the BORV bit in the Configuration Words.
A VDD noise rejection filter prevents the BOR from trig-
gering on small events. If VDD falls below VBOR for a
duration greater than parameter, TBORDC, the device
will reset. See Figure 6-2 for more information.
TABLE 6-1: BOR OPERATING MODES
BOREN<1:0> SBOREN Device Mode BOR Mode Instruction Execution upon:
Release of POR or Wake-up from Sleep
11 X XActive Waits for BOR ready(1)
(BORRDY = 1)
10 X Awake Active Waits for BOR ready
(BORRDY = 1)
Sleep Disabled
01 1XActive Waits for BOR ready(1)
(BORRDY = 1)
0X Disabled Begins immediately
(BORRDY = x)
00 X X Disabled
Note 1: In these specific cases, “release of POR” and “wake-up from Sleep”, there is no delay in start-up. The BOR
ready flag (BORRDY = 1) will be set before the CPU is ready to execute instructions because the BOR
circuit is forced on by the BOREN<1:0> bits.
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6.2.1 BOR IS ALWAYS ON
When the BORENx bits of the Configuration Words are
programmed to ‘11’, the BOR is always on. The device
start-up will be delayed until the BOR is ready and VDD
is higher than the BOR threshold.
BOR protection is active during Sleep. The BOR does
not delay wake-up from Sleep.
6.2.2 BOR IS OFF IN SLEEP
When the BORENx bits of the Configuration Words are
programmed to ‘10’, the BOR is on, except in Sleep.
The device start-up will be delayed until the BOR is
ready and VDD is higher than the BOR threshold.
BOR protection is not active during Sleep. The device
wake-up will be delayed until the BOR is ready.
6.2.3 BOR CONTROLLED BY SOFTWARE
When the BORENx bits of the Configuration Words
are programmed to ‘01’, the BOR is controlled by the
SBOREN bit of the BORCON register. The device
start-up is not delayed by the BOR ready condition or
the VDD level.
BOR protection begins as soon as the BOR circuit is
ready. The status of the BOR circuit is reflected in the
BORRDY bit of the BORCON register.
BOR protection is unchanged by Sleep.
FIGURE 6-2: BROWN-OUT SITUATIONS
TPWRT(1)
VBOR
VDD
Internal
Reset
VBOR
VDD
Internal
Reset TPWRT(1)
< TPWRT
TPWRT(1)
VBOR
VDD
Internal
Reset
Note 1: TPWRT delay only if PWRTE bit is programmed to ‘0’.
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6.3 Register Definitions: BOR Control
REGISTER 6-1: BORCON: BROWN-OUT RESET CONTROL REGISTER
R/W-1/u R/W-0/u U-0 U-0 U-0 U-0 U-0 R-q/u
SBOREN BORFS(1) — — — — — BORRDY
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7 SBOREN: Software Brown-out Reset Enable bit
If BOREN<1:0> in Configuration Words = 01:
1 = BOR is enabled
0 = BOR is disabled
If BOREN <1:0> in Configuration Words 01:
SBOREN is read/write, but has no effect on the BOR.
bit 6 BORFS: Brown-out Reset Fast Start bit(1)
If BOREN <1:0> = 10 (Disabled in Sleep) or BOREN<1:0> = 01 (Under software control):
1 = Band gap is forced on always (covers Sleep/wake-up/operating cases)
0 = Band gap operates normally and may turn off
If BOREN<1:0> = 11 (Always On) or BOREN<1:0> = 00 (Always Off):
BORFS is read/write, but has no effect on the BOR.
bit 5-1 Unimplemented: Read as ‘0’
bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit
1 = The Brown-out Reset circuit is active
0 = The Brown-out Reset circuit is inactive
Note 1: BOREN<1:0> bits are located in the Configuration Words.
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6.4 Low-Power Brown-out Reset
(LPBOR)
The Low-Power Brown-out Reset (LPBOR) operates
like the BOR to detect low-voltage conditions on the
VDD pin. When too low of a voltage is detected, the
device is held in Reset. When this occurs, a register bit
(BOR) is changed to indicate that a BOR Reset has
occurred. The BOR bit in PCON is used for both BOR
and the LPBOR. Refer to Register 6-2.
The LPBOR Voltage Threshold (VLPBOR) has a wider
tolerance than the BOR (VBOR), but requires much
less current (LPBOR current) to operate. The LPBOR
is intended for use when the BOR is configured as dis-
abled (BOREN<1:0> = 00) or disabled in Sleep mode
(BOREN<1:0> = 10).
Refer to Figure 6-1 to see how the LPBOR interacts
with other modules.
6.4.1 ENABLING LPBOR
The LPBOR is controlled by the LPBOR bit of the
Configuration Words. When the device is erased, the
LPBOR module defaults to disabled.
6.5 MCLR
The MCLR is an optional external input that can reset
the device. The MCLR function is controlled by the
MCLRE and LVP bits of the Configuration Words
(Table 6-2).
6.5.1 MCLR ENABLED
When MCLR is enabled and the pin is held low, the
device is held in Reset. The MCLR pin is connected to
VDD through an internal weak pull-up.
The device has a noise filter in the MCLR Reset path.
The filter will detect and ignore small pulses.
6.5.2 MCLR DISABLED
When MCLR is disabled, the pin functions as a general
purpose input and the internal weak pull-up is under soft-
ware control. See Section 11.3 “PORTA Registers” for
more information.
6.6 Watchdog Timer (WDT) Reset
The Watchdog Timer generates a Reset if the firmware
does not issue a CLRWDT instruction within the
time-out period. The TO and PD bits in the STATUS
register are changed to indicate the WDT Reset. See
Section 9.0 “Watchdog Timer (WDT)” for more
information.
6.7 RESET Instruction
A RESET instruction will cause a device Reset. The RI
bit in the PCON register will be set to ‘0’. See Ta ble 6 - 4
for default conditions after a RESET instruction has
occurred.
6.8 Stack Overflow/Underflow Reset
The device can reset when the Stack overflows or
underflows. The STKOVF or STKUNF bits of the PCON
register indicate the Reset condition. These Resets are
enabled by setting the STVREN bit in the Configuration
Words. See Section 3.5.2 “Overflow/Underflow
Reset” for more information.
6.9 Programming Mode Exit
Upon exit of Programming mode, the device will
behave as if a POR had just occurred.
6.10 Power-up Timer
The Power-up Timer optionally delays device execution
after a BOR or POR event. This timer is typically used to
allow VDD to stabilize before allowing the device to start
running.
The Power-up Timer is controlled by the PWRTE bit of
the Configuration Words.
6.11 Start-up Sequence
Upon the release of a POR or BOR, the following must
occur before the device will begin executing:
1. Power-up Timer runs to completion (if enabled).
2. MCLR must be released (if enabled).
The total time-out will vary based on oscillator
configuration and Power-up Timer configuration. See
Section 5.0 “Oscillator Module” for more information.
The Power-up Timer runs independently of a MCLR
Reset. If MCLR is kept low long enough, the Power-up
Timer will expire. Upon bringing MCLR high, the device
will begin execution after 10 FOSC cycles (see
Figure 6-3). This is useful for testing purposes or to
synchronize more than one device operating in parallel.
TABLE 6-2: MCLR CONFIGURATION
MCLRE LVP MCLR
00Disabled
10Enabled
x1Enabled
Note: A Reset does not drive the MCLR pin low.
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FIGURE 6-3: RESET START-UP SEQUENCE
Note 1: Code execution begins 10 FOSC cycles after the FOSC clock is released.
External Oscillators , PWRTEN = 1, IESO = 1
code execution (1)
External Oscillators , PWRTEN = 0, IESO = 1
Ext. Oscillator
Osc Start-Up Timer TOST
TPWRT
TOST
VDD
Internal POR
Internal RESET
MCLR
FOSC
Begin Execution
Power-up Timer
Int. Oscillator
code execution (1)
External Oscillators , PWRTEN = 1, IESO = 0
code
execution (1)
External Oscillators , PWRTEN = 0, IESO = 0
Ext. Oscillator
Osc Start-Up Timer
code
execution (1)
TOST
TPWRT
TOST
VDD
Internal POR
Internal RESET
MCLR
FOSC
Begin Execution
Power-up Timer
VDD
Internal POR
External Clock (EC modes), PWRTEN = 0
Internal RESET
MCLR
FOSC
Begin Execution
Ext. Clock (EC)
Power-up Timer
External Clock (EC modes), PWRTEN = 1
code execution (1)
code execution (1)
TPWRT
Int. Oscillator
code execution (1)
Internal Oscillator, PWRTEN = 0Internal Oscillator, PWRTEN = 1
code execution (1)
TPWRT
VDD
Internal POR
Internal RESET
MCLR
FOSC
Begin Execution
Power-up Timer
Rev. 10-000032A
7/30/2013
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6.12 Determining the Cause of a Reset
Upon any Reset, multiple bits in the STATUS and
PCON registers are updated to indicate the cause of
the Reset. Tabl e 6 - 3 and Table 6- 4 show the Reset
conditions of these registers.
TABLE 6-3: RESET STATUS BITS AND THEIR SIGNIFICANCE
TABLE 6-4: RESET CONDITION FOR SPECIAL REGISTERS
STKOVF STKUNF RWDT RMCLR RI POR BOR TO PD Condition
001110x11Power-on Reset
001110x0xIllegal, TO is Set on POR
001110xx0Illegal, PD is Set on POR
00u11u011Brown-out Reset
uu0uuuu0uWDT Reset
uuuuuuu00WDT Wake-up from Sleep
uuuuuuu10Interrupt Wake-up from Sleep
uuu0uuuuuMCLR Reset during Normal Operation
uuu0uuu10MCLR Reset during Sleep
u u u u 0 u u u u RESET Instruction Executed
1uuuuuuuuStack Overflow Reset (STVREN = 1)
u1uuuuuuuStack Underflow Reset (STVREN = 1)
Condition Program
Counter
STATUS
Register
PCON
Register
Power-on Reset 0000h ---1 1000 00-- 110x
MCLR Reset during normal operation 0000h ---u uuuu uu-- 0uuu
MCLR Reset during Sleep 0000h ---1 0uuu uu-- 0uuu
WDT Reset 0000h ---0 uuuu uu-- uuuu
WDT Wake-up from Sleep PC + 1 ---0 0uuu uu-- uuuu
Brown-out Reset 0000h ---1 1uuu 00-- 11u0
Interrupt Wake-up from Sleep PC + 1(1) ---1 0uuu uu-- uuuu
RESET Instruction Executed 0000h ---u uuuu uu-- u0uu
Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1u-- uuuu
Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1-- uuuu
Legend: u = unchanged; x = unknown; - = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and the Global Interrupt Enable bit (GIE) is set, the return address
is pushed on the stack and the PC is loaded with the interrupt vector (0004h) after execution of PC + 1.
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6.13 Power Control (PCON) Register
The Power Control (PCON) register contains flag bits
to differentiate between a:
• Power-on Reset (POR)
• Brown-out Reset (BOR)
•RESET Instruction Reset (RI)
•MCLR Reset (RMCLR)
• Watchdog Timer Reset (RWDT)
• Stack Underflow Reset (STKUNF)
• Stack Overflow Reset (STKOVF)
The PCON register bits are shown in Register 6-2.
6.14 Register Definitions: Power Control
REGISTER 6-2: PCON: POWER CONTROL REGISTER
R/W/HS-0/q R/W/HS-0/q U-0 R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u
STKOVF STKUNF —RWDTRMCLR RI POR BOR
bit 7 bit 0
Legend: HC = Hardware Clearable bit HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7 STKOVF: Stack Overflow Reset Flag bit
1 = A Stack Overflow Reset occurred
0 = A Stack Overflow Reset has not occurred or is cleared by firmware
bit 6 STKUNF: Stack Underflow Reset Flag bit
1 = A Stack Underflow Reset occurred
0 = A Stack Underflow Reset has not occurred or is cleared by firmware
bit 5 Unimplemented: Read as ‘0’
bit 4 RWDT: Watchdog Timer Reset Flag bit
1 = A Watchdog Timer Reset has not occurred or is set by firmware
0 = A Watchdog Timer Reset has occurred (cleared by hardware)
bit 3 RMCLR: MCLR Reset Flag bit
1 = A MCLR Reset has not occurred or is set by firmware
0 = A MCLR Reset has occurred (cleared by hardware)
bit 2 RI: RESET Instruction Flag bit
1 = A RESET instruction has not been executed or set by firmware
0 = A RESET instruction has been executed (cleared by hardware)
bit 1 POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs)
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TABLE 6-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS
TABLE 6-6: SUMMARY OF CONFIGURATION WORD WITH RESETS
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
BORCON SBOREN BORFS ————— BORRDY 62
PCON STKOVF STKUNF —RWDTRMCLR RI POR BOR 66
STATUS — — —TOPD ZDC C19
WDTCON —— WDTPS<4:0> SWDTEN 89
Legend: — = unimplemented bit, reads as ‘0’. Shaded cells are not used by Resets.
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 Register
on Page
CONFIG1 13:8 — — — — CLKOUTEN BOREN<1:0> —42
7:0 CP MCLRE PWRTE WDTE<1:0> —FOSC<1:0>
CONFIG2 13:8 — — LVP DEBUG LPBOR BORV STVREN PLLEN 43
7:0 — — — — — — WRT<1:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets.
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NOTES:
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7.0 INTERRUPTS
The interrupt feature allows certain events to preempt
normal program flow. Firmware is used to determine
the source of the interrupt and act accordingly. Some
interrupts can be configured to wake the MCU from
Sleep mode.
This chapter contains the following information for
interrupts:
• Operation
• Interrupt Latency
• Interrupts during Sleep
•INT Pin
• Automatic Context Saving
Many peripherals produce interrupts. Refer to the
corresponding chapters for details.
A block diagram of the interrupt logic is shown in
Figure 7-1.
FIGURE 7-1: INTERRUPT LOGIC
TMR0IF
TMR0IE
INTF
INTE
IOCIF
IOCIE Interrupt
to CPU
Wake-up
(If in Sleep mode)
GIE
(TMR1IF) PIR1<0>
PIRn<7>
PEIE
(TMR1IE) PIE1<0>
Peripheral Interrupts
PIEn<7>
Rev. 10-000010A
1/13/2014
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7.1 Operation
Interrupts are disabled upon any device Reset. They
are enabled by setting the following bits:
• GIE bit of the INTCON register
• Interrupt enable bit(s) for the specific interrupt
event(s)
• PEIE bit of the INTCON register (if the interrupt
enable bit of the interrupt event is contained in the
PIE1, PIE2 and PIE3 registers)
The INTCON, PIR1, PIR2 and PIR3 registers record
individual interrupts via interrupt flag bits. Interrupt flag
bits will be set, regardless of the status of the GIE, PEIE
and individual interrupt enable bits.
The following events happen when an interrupt event
occurs while the GIE bit is set:
• Current prefetched instruction is flushed
• GIE bit is cleared
• Current Program Counter (PC) is pushed onto the
stack
• Critical registers are automatically saved to the
shadow registers (See “Section 7.5 “Automatic
Context Saving”.”)
• PC is loaded with the interrupt vector, 0004h
The firmware within the Interrupt Service Routine (ISR)
should determine the source of the interrupt by polling
the interrupt flag bits. The interrupt flag bits must be
cleared before exiting the ISR to avoid repeated
interrupts. Because the GIE bit is cleared, any interrupt
that occurs while executing the ISR will be recorded
through its interrupt flag, but will not cause the
processor to redirect to the interrupt vector.
The RETFIE instruction exits the ISR by popping the
previous address from the stack, restoring the saved
context from the shadow registers and setting the GIE
bit.
For additional information on a specific interrupt’s
operation, refer to its peripheral chapter.
7.2 Interrupt Latency
Interrupt latency is defined as the time from when the
interrupt event occurs to the time code execution at the
interrupt vector begins. The latency for synchronous
interrupts is three or four instruction cycles. For
asynchronous interrupts, the latency is three to five
instruction cycles, depending on when the interrupt
occurs. See Figure 7-2 and Figure 7-3 for more details.
Note 1: Individual interrupt flag bits are set,
regardless of the state of any other
enable bits.
2: All interrupts will be ignored while the GIE
bit is cleared. Any interrupt occurring
while the GIE bit is clear will be serviced
when the GIE bit is set again.
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FIGURE 7-2: INTERRUPT LATENCY
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Fosc
CLKR
PC 0004h 0005h
PC
Inst(0004h)NOP
GIE
Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4
1-Cycle Instruction at PC
PC
Inst(0004h)NOP
2-Cycle Instruction at PC
FSR ADDR PC+1 PC+2 0004h 0005h
PC
Inst(0004h)NOP
GIE
PCPC-1
3-Cycle Instruction at PC
Execute
Interrupt
Inst(PC)
Interrupt Sampled
during Q1
Inst(PC)
PC-1 PC+1
NOP
PC New PC/
PC+1 0005hPC-1 PC+1/FSR
ADDR 0004h
NOP
Interrupt
GIE
Interrupt
INST(PC) NOPNOP
FSR ADDR PC+1 PC+2 0004h 0005h
PC
Inst(0004h)NOP
GIE
PCPC-1
3-Cycle Instruction at PC
Interrupt
INST(PC) NOPNOP NOP
Inst(0005h)
Execute
Execute
Execute
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FIGURE 7-3: INT PIN INTERRUPT TIMING
Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4
FOSC
CLKOUT
INT Pin
INTF
GIE
PC
Instruction
Fetched
Instruction
Executed
Interrupt Latency(2)
PC PC + 1 PC + 1 0004h 0005h
Inst (0004h) Inst (0005h)
Forced NOP
Inst (PC) Inst (PC + 1)
Inst (PC – 1) Inst (0004h)
Forced NOP
Inst (PC)
—
Note 1: INTF flag is sampled here (every Q1).
2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: For minimum width of INT pulse, refer to AC specifications in Section 26.0 “Electrical Specifications”.
4: INTF is enabled to be set any time during the Q4-Q1 cycles.
(1)
(3)
(4)
(1)
INSTRUCTION FLOW
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7.3 Interrupts During Sleep
Some interrupts can be used to wake from Sleep. To
wake from Sleep, the peripheral must be able to
operate without the system clock. The interrupt source
must have the appropriate Interrupt Enable bit(s) set
prior to entering Sleep.
On waking from Sleep, if the GIE bit is also set, the
processor will branch to the interrupt vector. Otherwise,
the processor will continue executing instructions after the
SLEEP instruction. The instruction directly after the SLEEP
instruction will always be executed before branching to
the ISR. Refer to Section 8.0 “Power-Down Mode
(Sleep)” for more details.
7.4 INT Pin
The INT pin can be used to generate an asynchronous
edge-triggered interrupt. This interrupt is enabled by
setting the INTE bit of the INTCON register. The
INTEDG bit of the OPTION_REG register determines on
which edge the interrupt will occur. When the INTEDG
bit is set, the rising edge will cause the interrupt. When
the INTEDG bit is clear, the falling edge will cause the
interrupt. The INTF bit of the INTCON register will be set
when a valid edge appears on the INT pin. If the GIE and
INTE bits are also set, the processor will redirect
program execution to the interrupt vector.
7.5 Automatic Context Saving
Upon entering an interrupt, the return PC address is
saved on the stack. Additionally, the following registers
are automatically saved in the shadow registers:
• W register
• STATUS register (except for TO and PD)
• BSR register
• FSR registers
• PCLATH register
Upon exiting the Interrupt Service Routine, these
registers are automatically restored. Any modifications
to these registers during the ISR will be lost. If modifi-
cations to any of these registers are desired, the
corresponding shadow register should be modified and
the value will be restored when exiting the ISR. The
shadow registers are available in Bank 31 and are
readable and writable. Depending on the user’s
application, other registers may also need to be saved.
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7.6 Register Definitions: Interrupt Control
REGISTER 7-1: INTCON: INTERRUPT CONTROL REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0
GIE(1) PEIE(2) TMR0IE INTE IOCIE TMR0IF INTF IOCIF(3)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7 GIE: Global Interrupt Enable bit(1)
1 = Enables all active interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit(2)
1 = Enables all active peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 TMR0IE: Timer0 Overflow Interrupt Enable bit
1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt
bit 4 INTE: INT External Interrupt Enable bit
1 = Enables the INT external interrupt
0 = Disables the INT external interrupt
bit 3 IOCIE: Interrupt-On-Change Enable bit
1 = Enables the Interrupt-On-Change
0 = Disables the Interrupt-On-Change
bit 2 TMR0IF: Timer0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed
0 = TMR0 register has not overflow
bit 1 INTF: INT External Interrupt Flag bit
1 = The INT external interrupt occurred
0 = The INT external interrupt did not occur
bit 0 IOCIF: Interrupt-On-Change Interrupt Flag bit(3)
1 = When at least one of the Interrupt-On-Change pins changed state
0 = None of the Interrupt-On-Change pins have changed state
Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding
enable bit or the Global Interrupt Enable bit, GIE, of the INTCON register. User software should ensure the
appropriate interrupt flag bits are clear prior to enabling an interrupt.
2: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
3: The IOCIF Flag bit is read-only and cleared when all the Interrupt-On-Change flags in the IOCxF registers
have been cleared by software.
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REGISTER 7-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0
TMR1GIE ADIE RCIE(1) TXIE(1) —— TMR2IE TMR1IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit
1 = Enables the Timer1 gate acquisition interrupt
0 = Disables the Timer1 gate acquisition interrupt
bit 6 ADIE: Analog-to-Digital Converter (ADC) Interrupt Enable bit
1 = Enables the ADC interrupt
0 = Disables the ADC interrupt
bit 5 RCIE: USART Receive Interrupt Enable bit(1)
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4 TXIE: USART Transmit Interrupt Enable bit(1)
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3-2 Unimplemented: Read as ‘0’
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the Timer2 to PR2 match interrupt
0 = Disables the Timer2 to PR2 match interrupt
bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit
1 = Enables the Timer1 overflow interrupt
0 = Disables the Timer1 overflow interrupt
Note 1: PIC12(L)F1572 only.
2: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
Note: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
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REGISTER 7-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
U-0 U-0 R/W-0/0 U-0 U-0 U-0 U-0 U-0
——C1IE— — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-6 Unimplemented: Read as ‘0’
bit 5 C1IE: Comparator C1 Interrupt Enable bit
1 = Enables the Comparator C1 interrupt
0 = Disables the Comparator C1 interrupt
bit 4-0 Unimplemented: Read as ‘0’
Note: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
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REGISTER 7-4: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0
— PWM3IE PWM2IE PWM1IE — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7 Unimplemented: Read as ‘0’
bit 6 PWM3IE: PWM3 Interrupt Enable bit
1 = Enables the PWM3 interrupt
0 = Disables the PWM3 interrupt
bit 5 PWM2IE: PWM2 Interrupt Enable bit
1 = Enables the PWM2 interrupt
0 = Disables the PWM2 interrupt
bit 4 PWM1IE: PWM1 Interrupt Enable bit
1 = Enables the PWM1 interrupt
0 = Disables the PWM1 interrupt
bit 3-0 Unimplemented: Read as ‘0’
Note: Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
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REGISTER 7-5: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
R/W-0/0 R/W-0/0 R-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0
TMR1GIF ADIF RCIF(1) TXIF(1) —— TMR2IF TMR1IF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 6 ADIF: ADC Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 5 RCIF: USART Receive Interrupt Flag bit(1)
1 = Interrupt is pending
0 = Interrupt is not pending
bit 4 TXIF: USART Transmit Interrupt Flag bit(1)
1 = Interrupt is pending
0 = Interrupt is not pending
bit 3-2 Unimplemented: Read as ‘0’
bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
Note 1: PIC12(L)F1572 only.
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE, of the INTCON
register. User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
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REGISTER 7-6: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
U-0 U-0 R/W-0/0 U-0 U-0 U-0 U-0 U-0
——C1IF— — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-6 Unimplemented: Read as ‘0’
bit 5 C1IF: Numerically Controlled Oscillator Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
bit 4-0 Unimplemented: Read as ‘0’
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE, of the INTCON
register. User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
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REGISTER 7-7: PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3
U-0 R-0/0 R-0/0 R-0/0 U-0 U-0 U-0 U-0
—PWM3IF
(1) PWM2IF(1) PWM1IF(1) — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7 Unimplemented: Read as ‘0’
bit 6 PWM3IF: PWM3 Interrupt Flag bit(1)
1 = Interrupt is pending
0 = Interrupt is not pending
bit 5 PWM2IF: PWM2 Interrupt Flag bit(1)
1 = Interrupt is pending
0 = Interrupt is not pending
bit 4 PWM1IF: PWM1 Interrupt Flag bit(1)
1 = Interrupt is pending
0 = Interrupt is not pending
bit 3-0 Unimplemented: Read as ‘0’
Note 1: These bits are read-only. They must be cleared by addressing the Flag registers inside the module.
2: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding
enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the
appropriate interrupt flag bits are clear prior to enabling an interrupt.
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TABLE 7-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 74
OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 157
PIE1 TMR1GIE ADIE RCIE(1) TXIE(1) —— TMR2IE TMR1IE 75
PIE2 ——C1IE— — — — — 76
PIE3 — PWM3IE PWM2IE PWM1IE — — — — 77
PIR1 TMR1GIF ADIF RCIF(1) TXIF(1) —— TMR2IF TMR1IF 78
PIR2 ——C1IF— — — — — 79
PIR3 — PWM3IF PWM2IF PWM1IF — — — — 80
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupts.
Note 1: PIC12(L)F1572 only.
PIC12(L)F1571/2
DS40001723D-page 82 2013-2015 Microchip Technology Inc.
NOTES:
2013-2015 Microchip Technology Inc. DS40001723D-page 83
PIC12(L)F1571/2
8.0 POWER-DOWN MODE (SLEEP)
The Power-Down mode is entered by executing a
SLEEP instruction.
Upon entering Sleep mode, the following conditions exist:
1. WDT will be cleared but keeps running if
enabled for operation during Sleep.
2. PD bit of the STATUS register is cleared.
3. TO bit of the STATUS register is set.
4. CPU clock is disabled.
5. 31 kHz LFINTOSC is unaffected and peripherals
that operate from it may continue operation in
Sleep.
6. Timer1 and peripherals that operate from
Timer1 continue operation in Sleep when the
Timer1 clock source selected is:
•LFINTOSC
•T1CKI
• Timer1 oscillator
7. ADC is unaffected if the dedicated FRC oscillator
is selected.
8. I/O ports maintain the status they had before
SLEEP was executed (driving high, low or
high-impedance).
9. Resets other than WDT are not affected by
Sleep mode.
Refer to individual chapters for more details on
peripheral operation during Sleep.
To minimize current consumption, the following
conditions should be considered:
• I/O pins should not be floating
• External circuitry sinking current from I/O pins
• Internal circuitry sourcing current from I/O pins
• Current draw from pins with internal weak pull-ups
• Modules using 31 kHz LFINTOSC
• CWG module using HFINTOSC
I/O pins that are high-impedance inputs should be
pulled to VDD or VSS externally to avoid switching
currents caused by floating inputs.
Examples of internal circuitry that might be
sourcing current include the FVR module. See
Section 13.0 “Fixed Voltage Reference (FVR)”
for more information on this module.
8.1 Wake-up from Sleep
The device can wake-up from Sleep through one of the
following events:
1. External Reset input on MCLR pin if enabled.
2. BOR Reset if enabled.
3. POR Reset.
4. Watchdog Timer if enabled.
5. Any external interrupt.
6. Interrupts by peripherals capable of running
during Sleep (see individual peripheral for more
information)
The first three events will cause a device Reset. The last
three events are considered a continuation of program
execution. To determine whether a device Reset or wake-
up event occurred, refer to Section 6.12 “Determining
the Cause of a Reset”.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be enabled. Wake-up will
occur regardless of the state of the GIE bit. If the GIE
bit is disabled, the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
enabled, the device executes the instruction after the
SLEEP instruction, the device will then call the Interrupt
Service Routine. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOP after the SLEEP instruction.
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
8.1.1 WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
SLEEP instruction:
-SLEEP instruction will execute as a NOP.
- WDT and WDT prescaler will not be cleared
-TO
bit of the STATUS register will not be set
-PD bit of the STATUS register will not be
cleared.
• If the interrupt occurs during or after the
execution of a SLEEP instruction:
-SLEEP instruction will be completely
executed
- Device will immediately wake-up from Sleep
- WDT and WDT prescaler will be cleared
-TO
bit of the STATUS register will be set
-PD bit of the STATUS register will be cleared
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
PIC12(L)F1571/2
DS40001723D-page 84 2013-2015 Microchip Technology Inc.
FIGURE 8-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT
8.2 Low-Power Sleep Mode
This device contains an internal Low Dropout (LDO)
voltage regulator, which allows the device I/O pins to
operate at voltages up to 5.5V while the internal device
logic operates at a lower voltage. The LDO and its
associated reference circuitry must remain active when
the device is in Sleep mode.
Low-Power Sleep mode allows the user to optimize the
operating current in Sleep. Low-Power Sleep mode can
be selected by setting the VREGPM bit of the
VREGCON register, which puts the LDO and reference
circuitry in a low-power state whenever the device is in
Sleep.
8.2.1 SLEEP CURRENT VS. WAKE-UP
TIME
In the default operating mode, the LDO and reference
circuitry remain in the normal configuration while in
Sleep. The device is able to exit Sleep mode quickly
since all circuits remain active. In Low-Power Sleep
mode, when waking up from Sleep, an extra delay time
is required for these circuits to return to the normal
configuration and stabilize.
The Low-Power Sleep mode is beneficial for applica-
tions that stay in Sleep mode for long periods of time.
The normal mode is beneficial for applications that
need to wake from Sleep quickly and frequently.
8.2.2 PERIPHERAL USAGE IN SLEEP
Some peripherals that can operate in Sleep mode will
not operate properly with the Low-Power Sleep mode
selected. The LDO will remain in the normal power
mode when those peripherals are enabled. The Low-
Power Sleep mode is intended for use with these
peripherals:
• Brown-out Reset (BOR)
• Watchdog Timer (WDT)
• External interrupt pin/Interrupt-On-Change pins
• Timer1 (with external clock source)
The Complementary Waveform Generator (CWG)
module can utilize the HFINTOSC oscillator as either
a clock source or as an input source. Under certain
conditions, when the HFINTOSC is selected for use
with the CWG module, the HFINTOSC will remain
active during Sleep. This will have a direct effect on
the Sleep mode current.
Please refer to section Section 23.10 “Operation
During Sleep” for more information.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKIN(1)
CLKOUT(2)
Interrupt Flag
GIE bit
(INTCON reg.)
Instruction Flow
PC
Instruction
Fetched
Instruction
Executed
PC PC + 1 PC + 2
Inst(PC) = Sleep
Inst(PC – 1)
Inst(PC + 1)
Sleep
Processor in
Sleep
Interrupt Latency(4)
Inst(PC + 2)
Inst(PC + 1)
Inst(0004h) Inst(0005h)
Inst(0004h)
Forced NOP
PC + 2 0004h 0005h
Forced NOP
TOST(3)
PC + 2
Note 1: External Clock. High, Medium, Low mode assumed.
2: CLKOUT is shown here for timing reference.
3: TOST = 1024 TOSC. This delay does not apply to EC, RC and INTOSC Oscillator modes or Two-Speed Start-up (if available).
4: GIE = 1 assumed. In this case, after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.
Note: The PIC12LF1571/2 does not have a
configurable Low-Power Sleep mode.
PIC12LF1571/2 is an unregulated device
and is always in the lowest power state
when in Sleep with no wake-up time penalty.
This device has a lower maximum VDD and
I/O voltage than the PIC12F1571/2. See
Section 26.0 “Electrical Specifications”
for more information.
2013-2015 Microchip Technology Inc. DS40001723D-page 85
PIC12(L)F1571/2
8.3 Register Definitions: Voltage Regulator Control
TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE
REGISTER 8-1: VREGCON: VOLTAGE REGULATOR CONTROL REGISTER(1)
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-1/1
— — — — — —VREGPMReserved
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-2 Unimplemented: Read as ‘0’
bit 1 VREGPM: Voltage Regulator Power Mode Selection bit
1 = Low-Power Sleep mode enabled in Sleep(2)
Draws lowest current in Sleep, slower wake-up.
0 = Normal power mode enabled in Sleep(2)
Draws higher current in Sleep, faster wake-up.
bit 0 Reserved: Read as ‘1’, maintain this bit set
Note 1: PIC12F1571/2 only.
2: See Section 26.0 “Electrical Specifications”
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on
Page
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 74
IOCAF —— IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 122
IOCAN —— IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 121
IOCAP —— IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 121
PIE1 TMR1GIE ADIE RCIE(1) TXIE(1) —— TMR2IE TMR1IE 75
PIE2 ——C1IE————— 76
PIE3 — PWM3IE PWM2IE PWM1IE — — — — 77
PIR1 TMR1GIF ADIF RCIF(1) TXIF(1) —— TMR2IF TMR1IF 78
PIR2 ——C1IF————— 79
PIR3 — PWM3IF PWM2IF PWM1IF — — — — 80
STATUS — — —TOPD ZDC C19
WDTCON —— WDTPS<4:0> SWDTEN 89
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in Power-Down mode.
Note 1: PIC12(L)F1572 only.
PIC12(L)F1571/2
DS40001723D-page 86 2013-2015 Microchip Technology Inc.
NOTES:
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PIC12(L)F1571/2
9.0 WATCHDOG TIMER (WDT)
The Watchdog Timer is a system timer that generates
a Reset if the firmware does not issue a CLRWDT
instruction within the time-out period. The Watchdog
Timer is typically used to recover the system from
unexpected events.
The WDT has the following features:
• Independent clock source
• Multiple operating modes:
- WDT is always on
- WDT is off when in Sleep
- WDT is controlled by software
- WDT is always off
• Configurable time-out period is from 1 ms to
256 seconds (nominal)
• Multiple Reset conditions
• Operation during Sleep
FIGURE 9-1: WATCHDOG TIMER BLOCK DIAGRAM
WDTE<1:0> = 01
SWDTEN
WDTE<1:0> = 11
WDTE<1:0> = 10
23-%it Programmable
Prescaler WDT
LFINTOSC
WDTPS<4:0>
WDT
Time-out
Sleep
Rev. 10-000141A
7/30/2013
PIC12(L)F1571/2
DS40001723D-page 88 2013-2015 Microchip Technology Inc.
9.1 Independent Clock Source
The WDT derives its time base from the 31 kHz
LFINTOSC internal oscillator. Time intervals in this
chapter are based on a nominal interval of 1 ms. See
Section 26.0 “Electrical Specifications” for the
LFINTOSC tolerances.
9.2 WDT Operating Modes
The Watchdog Timer module has four operating modes
controlled by the WDTE<1:0> bits in the Configuration
Words. See Tabl e 9- 1 .
9.2.1 WDT IS ALWAYS ON
When the WDTEx bits of the Configuration Words are
set to ‘11’, the WDT is always on. WDT protection is
active during Sleep.
9.2.2 WDT IS OFF IN SLEEP
When the WDTEx bits of the Configuration Words are
set to ‘10’, the WDT is on, except in Sleep. WDT
protection is not active during Sleep.
9.2.3 WDT CONTROLLED BY SOFTWARE
When the WDTEx bits of the Configuration Words are
set to ‘01’, the WDT is controlled by the SWDTEN bit of
the WDTCON register.
WDT protection is unchanged by Sleep. See Table 9-1
for more details.
TABLE 9-1: WDT OPERATING MODES
9.3 Time-out Period
The WDTPS<4:0> bits of the WDTCON register set the
time-out period from 1 ms to 256 seconds (nominal).
After a Reset, the default time-out period is two
seconds.
9.4 Clearing the WDT
The WDT is cleared when any of the following conditions
occur:
•Any Reset
•CLRWDT instruction is executed
• Device enters Sleep
• Device wakes up from Sleep
• Oscillator fails
• WDT is disabled
• Oscillator Start-up Timer (OST) is running
See Table 9-2 for more information.
9.5 Operation During Sleep
When the device enters Sleep, the WDT is cleared. If
the WDT is enabled during Sleep, the WDT resumes
counting. When the device exits Sleep, the WDT is
cleared again.
The WDT remains clear until the OST, if enabled, com-
pletes. See Section 5.0 “Oscillator Module” for more
information on the OST.
When a WDT time-out occurs while the device is in
Sleep, no Reset is generated. Instead, the device
wakes up and resumes operation. The TO and PD bits
in the STATUS register are changed to indicate the
event. The RWDT bit in the PCON register can also be
used. See Section 3.0 “Memory Organization” for
more information.
WDTE<1:0> SWDTEN Device
Mode
WDT
Mode
11 X XActive
10 X Awake Active
Sleep Disabled
01 1XActive
0XDisabled
00 X XDisabled
TABLE 9-2: WDT CLEARING CONDITIONS
Conditions WDT
WDTE<1:0> = 00
Cleared
WDTE<1:0> = 01 and SWDTEN = 0
WDTE<1:0> = 10 and enter Sleep
CLRWDT Command
Oscillator Fail Detected
Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP Cleared until the end of OST
Change INTOSC divider (IRCF<3:0> bits) Unaffected
2013-2015 Microchip Technology Inc. DS40001723D-page 89
PIC12(L)F1571/2
9.6 Register Definitions: Watchdog Control
REGISTER 9-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0 U-0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1 R/W-1/1 R/W-0/0
—— WDTPS<4:0> SWDTEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-6 Unimplemented: Read as ‘0’
bit 5-1 WDTPS<4:0>: Watchdog Timer Period Select bits(1)
Bit Value = Prescale Rate
11111 = Reserved; results in minimum interval (1:32)
•
•
•
10011 = Reserved; results in minimum interval (1:32)
10010 = 1:8388608 (223) (Interval 256s nominal)
10001 = 1:4194304 (222) (Interval 128s nominal)
10000 = 1:2097152 (221) (Interval 64s nominal)
01111 = 1:1048576 (220) (Interval 32s nominal)
01110 = 1:524288 (219) (Interval 16s nominal)
01101 = 1:262144 (218) (Interval 8s nominal)
01100 = 1:131072 (217) (Interval 4s nominal)
01011 = 1:65536 (Interval 2s nominal) (Reset value)
01010 = 1:32768 (Interval 1s nominal)
01001 = 1:16384 (Interval 512 ms nominal)
01000 = 1:8192 (Interval 256 ms nominal)
00111 = 1:4096 (Interval 128 ms nominal)
00110 = 1:2048 (Interval 64 ms nominal)
00101 = 1:1024 (Interval 32 ms nominal)
00100 = 1:512 (Interval 16 ms nominal)
00011 = 1:256 (Interval 8 ms nominal)
00010 = 1:128 (Interval 4 ms nominal)
00001 = 1:64 (Interval 2 ms nominal)
00000 = 1:32 (Interval 1 ms nominal)
bit 0 SWDTEN: Software Enable/Disable for Watchdog Timer bit
If WDTE<1:0> = 1x:
This bit is ignored.
If WDTE<1:0> = 01:
1 = WDT is turned on
0 = WDT is turned off
If WDTE<1:0> = 00:
This bit is ignored.
Note 1: Times are approximate. WDT time is based on 31 kHz LFINTOSC.
PIC12(L)F1571/2
DS40001723D-page 90 2013-2015 Microchip Technology Inc.
TABLE 9-3: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER
TABLE 9-4: SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
OSCCON SPLLEN IRCF<3:0> —SCS<1:0>55
PCON STKOVF STKUNF —RWDTRMCLR RI POR BOR 66
STATUS ———TOPD ZDC C19
WDTCON —— WDTPS<4:0> SWDTEN 89
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 Register
on Page
CONFIG1 13:8 — — — — CLKOUTEN BOREN<1:0> —42
7:0 CP MCLRE PWRTE WDTE<1:0> —FOSC<1:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the Watchdog Timer.
2013-2015 Microchip Technology Inc. DS40001723D-page 91
PIC12(L)F1571/2
10.0 FLASH PROGRAM MEMORY
CONTROL
The Flash program memory is readable and writable
during normal operation over the full VDD range.
Program memory is indirectly addressed using Special
Function Registers (SFRs). The SFRs used to access
program memory are:
•PMCON1
•PMCON2
•PMDATL
•PMDATH
• PMADRL
•PMADRH
When accessing the program memory, the
PMDATH:PMDATL register pair forms a 2-byte word
that holds the 14-bit data for read/write, and the
PMADRH:PMADRL register pair forms a 2-byte word
that holds the 15-bit address of the program memory
location being read.
The write time is controlled by an on-chip timer. The
write/erase voltages are generated by an on-chip charge
pump.
The Flash program memory can be protected in two
ways; by code protection (CP bit in the Configuration
Words) and write protection (WRT<1:0> bits in the
Configuration Words).
Code protection (CP = 0) disables access, reading and
writing, to the Flash program memory via external
device programmers. Code protection does not affect
the self-write and erase functionality. Code protection
can only be reset by a device programmer performing
a bulk erase to the device, clearing all Flash program
memory, Configuration bits and User IDs.(1)
Write protection prohibits self-write and erase to a
portion or all of the Flash program memory as defined
by the bits WRT<1:0>. Write protection does not affect
a device programmers ability to read, write or erase the
device.
10.1 PMADRL and PMADRH Registers
The PMADRH:PMADRL register pair can address up
to a maximum of 16K words of program memory. When
selecting a program address value, the MSB of the
address is written to the PMADRH register and the LSB
is written to the PMADRL register.
10.1.1 PMCON1 AND PMCON2
REGISTERS
PMCON1 is the control register for Flash program
memory accesses.
Control bits, RD and WR, initiate read and write,
respectively. These bits cannot be cleared, only set, in
software. They are cleared by hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
The WREN bit, when set, will allow a write operation to
occur. On power-up, the WREN bit is clear. The
WRERR bit is set when a write operation is interrupted
by a Reset during normal operation. In these situations,
following Reset, the user can check the WRERR bit
and execute the appropriate error handling routine.
The PMCON2 register is a write-only register. Attempting
to read the PMCON2 register will return all ‘0’s.
To enable writes to the program memory, a specific
pattern (the unlock sequence), must be written to the
PMCON2 register. The required unlock sequence
prevents inadvertent writes to the program memory
write latches and Flash program memory.
10.2 Flash Program Memory Overview
It is important to understand the Flash program memory
structure for erase and programming operations. Flash
program memory is arranged in rows. A row consists of
a fixed number of 14-bit program memory words. A row
is the minimum size that can be erased by user software.
After a row has been erased, the user can reprogram
all or a portion of this row. Data to be written into the
program memory row is written to 14-bit wide data write
latches. These write latches are not directly accessible
to the user, but may be loaded via sequential writes to
the PMDATH:PMDATL register pair.
Note 1: Code protection of the entire Flash
program memory array is enabled by
clearing the CP bit of the Configuration
Words.
Note: If the user wants to modify only a portion of
a previously programmed row, then the
contents of the entire row must be read and
saved in RAM prior to the erase. Then, new
data and retained data can be written into
the write latches to reprogram the row of
Flash program memory. However, any
unprogrammed locations can be written
without first erasing the row. In this case, it
is not necessary to save and rewrite the
other previously programmed locations.
PIC12(L)F1571/2
DS40001723D-page 92 2013-2015 Microchip Technology Inc.
See Table 10-1 for erase row size and the number of
write latches for Flash program memory.
10.2.1 READING THE FLASH PROGRAM
MEMORY
To read a program memory location, the user must:
1. Write the desired address to the
PMADRH:PMADRL register pair.
2. Clear the CFGS bit of the PMCON1 register.
3. Then, set control bit, RD, of the PMCON1 register.
Once the read control bit is set, the program memory
Flash controller will use the second instruction cycle to
read the data. This causes the second instruction
immediately following the “BSF PMCON1,RD” instruction
to be ignored. The data is available in the very next cycle
in the PMDATH:PMDATL register pair; therefore, it can
be read as two bytes in the following instructions.
The PMDATH:PMDATL register pair will hold this value
until another read or until it is written to by the user.
FIGURE 10-1: FLASH PROGRAM
MEMORY READ
FLOWCHART
TABLE 10-1: FLASH MEMORY
ORGANIZATION BY DEVICE
Device Row Erase
(words)
Write
Latches
(words)
PIC12(L)F1571 16 16
PIC12(L)F1572
Note: The two instructions following a program
memory read are required to be NOPs.
This prevents the user from executing a
2-cycle instruction on the next instruction
after the RD bit is set.
Start
Read Operation
Select
Program or Configuration Memory
(CFGS)
Select
Word Address
(PMADRH:PMADRL)
Initiate Read operation
(RD = 1)
Instruction fetched ignored
NOP execution forced
Data read now in
PMDATH:PMDATL
Instruction fetched ignored
NOP execution forced
End
Read Operation
Rev. 10-000046A
7/30/2013
2013-2015 Microchip Technology Inc. DS40001723D-page 93
PIC12(L)F1571/2
FIGURE 10-2: FLASH PROGRAM MEMORY READ CYCLE EXECUTION
EXAMPLE 10-1: FLASH PROGRAM MEMORY READ
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
BSF PMCON1,RD
Executed Here
INSTR(PC + 1)
Executed Here
PC
PC + 1 PMADRH,PMADRL PC+3 PC + 5
Flash ADDR
RD bit
PMDATH,PMDATL
PC + 3 PC + 4
INSTR (PC + 1)
INSTR(PC – 1)
Executed Here INSTR(PC + 3)
Executed Here INSTR(PC + 4)
Executed Here
Flash Data
PMDATH
PMDATL
Register
INSTR (PC) INSTR (PC + 3) INSTR (PC + 4)
Instruction Ignored,
Forced NOP
INSTR(PC + 2)
Executed Here
Instruction Ignored,
Forced NOP
* This code block will read 1 word of program
* memory at the memory address:
PROG_ADDR_HI : PROG_ADDR_LO
* data will be returned in the variables;
* PROG_DATA_HI, PROG_DATA_LO
BANKSEL PMADRL ; Select Bank for PMCON registers
MOVLW PROG_ADDR_LO ;
MOVWF PMADRL ; Store LSB of address
MOVLW PROG_ADDR_HI ;
MOVWF PMADRH ; Store MSB of address
BCF PMCON1,CFGS ; Do not select Configuration Space
BSF PMCON1,RD ; Initiate read
NOP ; Ignored (Figure 10-2)
NOP ; Ignored (Figure 10-2)
MOVF PMDATL,W ; Get LSB of word
MOVWF PROG_DATA_LO ; Store in user location
MOVF PMDATH,W ; Get MSB of word
MOVWF PROG_DATA_HI ; Store in user location
PIC12(L)F1571/2
DS40001723D-page 94 2013-2015 Microchip Technology Inc.
10.2.2 FLASH MEMORY UNLOCK
SEQUENCE
The unlock sequence is a mechanism that protects the
Flash program memory from unintended self-write
programming or erasing. The sequence must be exe-
cuted and completed without interruption to successfully
complete any of the following operations:
• Row erase
• Load program memory write latches
• Write of program memory write latches to
program memory
• Write of program memory write latches to User
IDs
The unlock sequence consists of the following steps:
1. Write 55h to PMCON2
2. Write AAh to PMCON2
3. Set the WR bit in PMCON1
4. NOP instruction
5. NOP instruction
Once the WR bit is set, the processor will always force
two NOP instructions. When an erase row or program row
operation is being performed, the processor will stall
internal operations (typical 2 ms), until the operation is
complete and then resume with the next instruction.
When the operation is loading the program memory write
latches, the processor will always force the two NOP
instructions and continue uninterrupted with the next
instruction.
Since the unlock sequence must not be interrupted,
global interrupts should be disabled prior to the unlock
sequence and re-enabled after the unlock sequence is
completed.
FIGURE 10-3: FLASH PROGRAM
MEMORY UNLOCK
SEQUENCE FLOWCHART
Start
Unlock Sequence
End
Unlock Sequence
Write 0x55 to
PMCON2
Write 0xAA to
PMCON2
Initiate
Write or Erase operation
(WR = 1)
Instruction fetched ignored
NOP execution forced
Instruction fetched ignored
NOP execution forced
Rev. 10-000047A
7/30/2013
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10.2.3 ERASING FLASH PROGRAM
MEMORY
While executing code, program memory can only be
erased by rows. To erase a row:
1. Load the PMADRH:PMADRL register pair with
any address within the row to be erased.
2. Clear the CFGS bit of the PMCON1 register.
3. Set the FREE and WREN bits of the PMCON1
register.
4. Write 55h, then AAh, to PMCON2 (Flash
programming unlock sequence).
5. Set control bit, WR, of the PMCON1 register to
begin the erase operation.
See Example 10-2.
After the “BSF PMCON1,WR” instruction, the processor
requires two cycles to set up the erase operation. The
user must place two NOP instructions after the WR bit is
set. The processor will halt internal operations for the
typical 2 ms erase time. This is not Sleep mode as the
clocks and peripherals will continue to run. After the
erase cycle, the processor will resume operation with
the third instruction after the PMCON1 write instruction.
FIGURE 10-4: FLASH PROGRAM
MEMORY ERASE
FLOWCHART
Note 1: See Figure 10-3.
Start
Erase Operation
End
Erase Operation
Disable Interrupts
(GIE = 0)
Select
Program or Configuration Memory
(CFGS)
Select Erase Operation
(FREE = 1)
Select Row Address
(PMADRH:PMADRL)
Enable Write/Erase Operation
(WREN = 1)
Unlock Sequence
(See Note 1)
Re-enable Interrupts
(GIE = 1)
Disable Write/Erase Operation
(WREN = 0)
CPU stalls while
Erase operation completes
(2 ms typical)
Rev. 10-000048A
7/30/2013
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DS40001723D-page 96 2013-2015 Microchip Technology Inc.
EXAMPLE 10-2: ERASING ONE ROW OF PROGRAM MEMORY
; This row erase routine assumes the following:
; 1. A valid address within the erase row is loaded in ADDRH:ADDRL
; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)
BCF INTCON,GIE ; Disable ints so required sequences will execute properly
BANKSEL PMADRL
MOVF ADDRL,W ; Load lower 8 bits of erase address boundary
MOVWF PMADRL
MOVF ADDRH,W ; Load upper 6 bits of erase address boundary
MOVWF PMADRH
BCF PMCON1,CFGS ; Not configuration space
BSF PMCON1,FREE ; Specify an erase operation
BSF PMCON1,WREN ; Enable writes
MOVLW 55h ; Start of required sequence to initiate erase
MOVWF PMCON2 ; Write 55h
MOVLW 0AAh ;
MOVWF PMCON2 ; Write AAh
BSF PMCON1,WR ; Set WR bit to begin erase
NOP ; NOP instructions are forced as processor starts
NOP ; row erase of program memory.
;
; The processor stalls until the erase process is complete
; after erase processor continues with 3rd instruction
BCF PMCON1,WREN ; Disable writes
BSF INTCON,GIE ; Enable interrupts
Required
Sequence
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10.2.4 WRITING TO FLASH PROGRAM
MEMORY
Program memory is programmed using the following
steps:
1. Load the address in PMADRH:PMADRL of the
row to be programmed.
2. Load each write latch with data.
3. Initiate a programming operation.
4. Repeat Steps 1 through 3 until all data is written.
Before writing to program memory, the word(s) to be
written must be erased or previously unwritten. Pro-
gram memory can only be erased one row at a time. No
automatic erase occurs upon the initiation of the write.
Program memory can be written one or more words at
a time. The maximum number of words written at one
time is equal to the number of write latches. See
Figure 10-5 (row writes to program memory with
16 write latches) for more details.
The write latches are aligned to the Flash row
address boundary defined by the upper 11 bits of
PMADRH:PMADRL (PMADRH<6:0>:PMADRL<7:4>),
with the lower 4 bits of PMADRL (PMADRL<3:0>)
determining the write latch being loaded. Write opera-
tions do not cross these boundaries. At the completion
of a program memory write operation, the data in the
write latches is reset to contain 0x3FFF.
The following steps should be completed to load the
write latches and program a row of program memory.
These steps are divided into two parts. First, each write
latch is loaded with data from the PMDATH:PMDATL
using the unlock sequence with LWLO = 1. When the
last word to be loaded into the write latch is ready, the
LWLO bit is cleared and the unlock sequence
executed. This initiates the programming operation,
writing all the latches into Flash program memory.
1. Set the WREN bit of the PMCON1 register.
2. Clear the CFGS bit of the PMCON1 register.
3. Set the LWLO bit of the PMCON1 register.
When the LWLO bit of the PMCON1 register is
‘1’, the write sequence will only load the write
latches and will not initiate the write to Flash
program memory.
4. Load the PMADRH:PMADRL register pair with
the address of the location to be written.
5. Load the PMDATH:PMDATL register pair with
the program memory data to be written.
6. Execute the unlock sequence
(Section 10.2.2 “Flash Memory Unlock
Sequence”). The write latch is now loaded.
7. Increment the PMADRH:PMADRL register pair
to point to the next location.
8. Repeat Steps 5 through 7 until all but the last
write latch has been loaded.
9. Clear the LWLO bit of the PMCON1 register.
When the LWLO bit of the PMCON1 register is
‘0’, the write sequence will initiate the write to
Flash program memory.
10. Load the PMDATH:PMDATL register pair with
the program memory data to be written.
11. Execute the unlock sequence
(Section 10.2.2 “Flash Memory Unlock
Sequence”). The entire program memory latch
content is now written to Flash program
memory.
An example of the complete write sequence is shown in
Example 10-3. The initial address is loaded into the
PMADRH:PMADRL register pair; the data is loaded
using Indirect Addressing.
Note: The special unlock sequence is required
to load a write latch with data or initiate a
Flash programming operation. If the
unlock sequence is interrupted, writing to
the latches or program memory will not be
initiated.
Note: The program memory write latches are
reset to the blank state (0x3FFF) at the
completion of every write or erase
operation. As a result, it is not necessary
to load all the program memory write
latches. Unloaded latches will remain in
the blank state.
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FIGURE 10-5: BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 16 WRITE LATCHES
6 8
14
1414
Write Latch #15
0Fh
1414
Program Memory Write Latches
14 14 14
PMADRH<6:0>:
PMADRL<7:4>
Flash Program Memory
Row
Row
Address
Decode
Addr
Write Latch #14
0Eh
Write Latch #1
01h
Write Latch #0
00h
Addr Addr Addr
000h 000Fh
000Eh
0000h 0001h
001h 001Fh
001Eh
0010h 0011h
002h 002Fh002Eh0020h 0021h
7FEh 7FEFh7FEEh
7FE0h 7FE1h
7FFh 7FFFh7FFEh7FF0h 7FF1h
14
PMADRL<3:0>
800h 8009h - 801Fh8000h - 8003h
Configuration
Words
USERID0-3
8007h –8008h8006h
DEVICE ID
Dev / Rev
reserved reserved
Configuration Memory
CFGS = 0
CFGS = 1
PMADRH PMADRL
76 07 43 0
c3 c2 c1 c0r9 r8 r7 r6 r5 r4 r3-r1 r0r2
PMDATH PMDATL
75 07 0
--
8004h –8005h
411
rA
Rev. 10-000004B
7/25/2013
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FIGURE 10-6: FLASH PROGRAM MEMORY WRITE FLOWCHART
Disable Interrupts
(GIE = 0)
Start
Write Operation
Select
Program or Config. Memory
(CFGS)
Select Row Address
(PMADRH:PMADRL)
Select Write Operation
(FREE = 0)
Enable Write/Erase
Operation (WREN = 1)
Unlock Sequence
(Figure x-x)
Disable
Write/Erase Operation
(WREN = 0)
Re-enable Interrupts
(GIE = 1)
End
Write Operation
No delay when writing to
Program Memory Latches
Determine number of words
to be written into Program or
Configuration Memory.
The number of words cannot
exceed the number of words
per row.
(word_cnt) Load the value to write
(PMDATH:PMDATL)
Update the word counter
(word_cnt--)
Last word to
write ?
Increment Address
(PMADRH:PMADRL++)
Unlock Sequence
(Figure x-x)
CPU stalls while Write
operation completes
(2ms typical)
Load Write Latches Only
(LWLO = 1)
Write Latches to Flash
(LWLO = 0)
No
Yes
Figure 10-3
Figure 10-3
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EXAMPLE 10-3: WRITING TO FLASH PROGRAM MEMORY
; This write routine assumes the following:
; 1. 32 bytes of data are loaded, starting at the address in DATA_ADDR
; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR,
; stored in little endian format
; 3. A valid starting address (the Least Significant bits = 00000) is loaded in ADDRH:ADDRL
; 4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)
;BCF INTCON,GIE ; Disable ints so required sequences will execute properly
BANKSEL PMADRH ; Bank 3
MOVF ADDRH,W ; Load initial address
MOVWF PMADRH ;
MOVF ADDRL,W ;
MOVWF PMADRL ;
MOVLW LOW DATA_ADDR ; Load initial data address
MOVWF FSR0L ;
MOVLW HIGH DATA_ADDR ; Load initial data address
MOVWF FSR0H ;
BCF PMCON1,CFGS ; Not configuration space
BSF PMCON1,WREN ; Enable writes
BSF PMCON1,LWLO ; Only Load Write Latches
LOOP MOVIW FSR0++ ; Load first data byte into lower
MOVWF PMDATL ;
MOVIW FSR0++ ; Load second data byte into upper
MOVWF PMDATH ;
MOVF PMADRL,W ; Check if lower bits of address are '00000'
XORLW 0x1F ; Check if we're on the last of 16 addresses
ANDLW 0x1F ;
BTFSC STATUS,Z ; Exit if last of 16 words,
GOTO START_WRITE ;
MOVLW 55h ; Start of required write sequence:
MOVWF PMCON2 ; Write 55h
MOVLW 0AAh ;
MOVWF PMCON2 ; Write AAh
BSF PMCON1,WR ; Set WR bit to begin write
NOP ; NOP instructions are forced as processor
; loads program memory write latches
NOP ;
INCF PMADRL,F ; Still loading latches Increment address
GOTO LOOP ; Write next latches
START_WRITE
BCF PMCON1,LWLO ; No more loading latches - Actually start Flash program
; memory write
MOVLW 55h ; Start of required write sequence:
MOVWF PMCON2 ; Write 55h
MOVLW 0AAh ;
MOVWF PMCON2 ; Write AAh
BSF PMCON1,WR ; Set WR bit to begin write
NOP ; NOP instructions are forced as processor writes
; all the program memory write latches simultaneously
NOP ; to program memory.
; After NOPs, the processor
; stalls until the self-write process in complete
; after write processor continues with 3rd instruction
BCF PMCON1,WREN ; Disable writes
BSF INTCON,GIE ; Enable interrupts
Required
Sequence
Required
Sequence
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10.3 Modifying Flash Program Memory
When modifying existing data in a program memory
row, and data within that row must be preserved, it must
first be read and saved in a RAM image. Program
memory is modified using the following steps:
1. Load the starting address of the row to be
modified.
2. Read the existing data from the row into a RAM
image.
3. Modify the RAM image to contain the new data
to be written into program memory.
4. Load the starting address of the row to be
rewritten.
5. Erase the program memory row.
6. Load the write latches with data from the RAM
image.
7. Initiate a programming operation.
FIGURE 10-7: FLASH PROGRAM
MEMORY MODIFY
FLOWCHART
Start
Modify Operation
End
Modify Operation
Read Operation
(See Note 1)
An image of the entire row
read must be stored in RAM
Erase Operation
(See Note 2)
Modify Image
The words to be modified are
changed in the RAM image
Write Operation
Use RAM image
(See Note 3)
Rev. 10-000050A
7/30/2013
Note 1: See Figure 10-2.
2: See Figure 10-4.
3: See Figure 10-6.
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10.4 User ID, Device ID and
Configuration Word Access
Instead of accessing program memory, the User IDs,
Device ID/Revision ID and Configuration Words can be
accessed when CFGS = 1 in the PMCON1 register.
This is the region that would be pointed to by
PC<15> = 1, but not all addresses are accessible.
Different access may exist for reads and writes. Refer
to Table 1 0- 2.
When read access is initiated on an address outside the
parameters listed in Table 10-2, the PMDATH:PMDATL
register pair is cleared, reading back ‘0’s.
TABLE 10-2: USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS = 1)
EXAMPLE 10-4: CONFIGURATION WORD AND DEVICE ID ACCESS
Address Function Read Access Write Access
8000h-8003h User IDs Yes Yes
8006h/8005h Device ID/Revision ID Yes No
8007h-8008h Configuration Words 1 and 2 Yes No
* This code block will read 1 word of program memory at the memory address:
* PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables;
* PROG_DATA_HI, PROG_DATA_LO
BANKSEL PMADRL ; Select correct Bank
MOVLW PROG_ADDR_LO ;
MOVWF PMADRL ; Store LSB of address
CLRF PMADRH ; Clear MSB of address
BSF PMCON1,CFGS ; Select Configuration Space
BCF INTCON,GIE ; Disable interrupts
BSF PMCON1,RD ; Initiate read
NOP ; Executed (See Figure 10-2)
NOP ; Ignored (See Figure 10-2)
BSF INTCON,GIE ; Restore interrupts
MOVF PMDATL,W ; Get LSB of word
MOVWF PROG_DATA_LO ; Store in user location
MOVF PMDATH,W ; Get MSB of word
MOVWF PROG_DATA_HI ; Store in user location
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10.5 Write Verify
It is considered good programming practice to verify that
program memory writes agree with the intended value.
Since program memory is stored as a full page then the
stored program memory contents are compared with the
intended data stored in RAM after the last write is
complete.
FIGURE 10-8: FLASH PROGRAM
MEMORY VERIFY
FLOWCHART
Start
Verify Operation
This routine assumes that the last
rowofdatawrittenwasfroman
image saved on RAM. This image
will be used to verify the data
currently stored in Flash Program
Memory
Fail
Verify Operation
Last word ?
PMDAT =
RAM image ?
Read Operation
(See Note 1)
End
Verify Operation
No
No
Yes
Yes
Rev. 10-000051A
7/30/2013
Note 1: See Figure 10-1.
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10.6 Register Definitions: Flash Program Memory Control
REGISTER 10-1: PMDATL: PROGRAM MEMORY DATA LOW BYTE REGISTER
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
PMDAT<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-0 PMDAT<7:0>: Read/Write Value for Least Significant bits of Program Memory bits
REGISTER 10-2: PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER
U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
——PMDAT<13:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 PMDAT<13:8>: Read/Write Value for Most Significant bits of Program Memory bits
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REGISTER 10-3: PMADRL: PROGRAM MEMORY ADDRESS LOW BYTE REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
PMADR<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-0 PMADR<7:0>: Specifies Least Significant bits for Program Memory Address bits
REGISTER 10-4: PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER
U-1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
—(1) PMADR<14:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7 Unimplemented: Read as ‘1’(1)
bit 6-0 PMADR<14:8>: Specifies the Most Significant bits for Program Memory Address bits
Note 1: Unimplemented, read as ‘1’.
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REGISTER 10-5: PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER
U-1 R/W-0/0 R/W-0/0 R/W/HC-0/0 R/W/HC-x/q(2) R/W-0/0 R/S/HC-0/0 R/S/HC-0/0
—(1) CFGS LWLO(3) FREE WRERR WREN WR RD
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HC = Hardware Clearable bit
bit 7 Unimplemented: Read as ‘1’(1)
bit 6 CFGS: Configuration Select bit
1 = Accesses Configuration, User ID and Device ID registers
0 = Accesses Flash program memory
bit 5 LWLO: Load Write Latches Only bit(3)
1 = Only the addressed program memory write latch is loaded/updated on the next WR command
0 = The addressed program memory write latch is loaded/updated and a write of all program memory
write latches will be initiated on the next WR command
bit 4 FREE: Program Flash Erase Enable bit
1 = Performs an erase operation on the next WR command (hardware cleared upon completion)
0 = Performs a write operation on the next WR command
bit 3 WRERR: Program/Erase Error Flag bit(2)
1 = Condition indicates an improper program or erase sequence attempt or termination (bit is set
automatically on any set attempt (writes ‘1’) of the WR bit)
0 = The program or erase operation completed normally
bit 2 WREN: Program/Erase Enable bit
1 = Allows program/erase cycles
0 = Inhibits programming/erasing of program Flash
bit 1 WR: Write Control bit
1 = Initiates a program Flash program/erase operation
The operation is self-timed and the bit is cleared by hardware once operation is complete. The WR
bit can only be set (not cleared) in software.
0 = Program/erase operation to the Flash is complete and inactive
bit 0 RD: Read Control bit
1 = Initiates a program Flash read
Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in
software.
0 = Does not initiate a program Flash read
Note 1: Unimplemented bit, read as ‘1’.
2: The WRERR bit is automatically set by hardware when a program memory write or erase operation is
started (WR = 1).
3: The LWLO bit is ignored during a program memory erase operation (FREE = 1).
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TABLE 10-3: SUMMARY OF REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORY
TABLE 10-4: SUMMARY OF CONFIGURATION WORD WITH FLASH PROGRAM MEMORY
REGISTER 10-6: PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER
W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0
Program Memory Control Register 2
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
S = Bit can only be set x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-0 Flash Memory Unlock Pattern bits
To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the
PMCON1 register. The value written to this register is used to unlock the writes. There are specific
timing requirements on these writes.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 74
PMCON1 —(1) CFGS LWLO FREE WRERR WREN WR RD 106
PMCON2 Program Memory Control Register 2 107
PMADRL PMADRL<7:0> 105
PMADRH —(1) PMADRH<6:0> 105
PMDATL PMDATL<7:0> 104
PMDATH ——PMDATH<5:0>104
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory.
Note 1: Unimplemented, read as ‘1’.
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 Register
on Page
CONFIG1 13:8 — — — — CLKOUTEN BOREN<1:0> —42
7:0 CP MCLRE PWRTE WDTE<1:0> —FOSC<1:0>
CONFIG2 13:8 — — LVP DEBUG LPBOR BORV STVREN PLLEN 43
7:0 — — — — — —WRT<1:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory.
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NOTES:
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11.0 I/O PORTS
Each port has three standard registers for its operation.
These registers are:
• TRISx registers (Data Direction)
• PORTx registers (reads the levels on the pins of
the device)
• LATx registers (Output Latch)
• INLVLx (Input Level Control)
• ODCONx registers (Open-Drain Control)
• SLRCONx registers (Slew Rate Control)
Some ports may have one or more of the following
additional registers. These registers are:
• ANSELx (Analog Select)
• WPUx (Weak Pull-up)
In general, when a peripheral is enabled on a port pin,
that pin cannot be used as a general purpose output.
However, the pin can still be read.
The Data Latch (LATx registers) is useful for
Read-Modify-Write operations on the value that the I/O
pins are driving.
A write operation to the LATx register has the same
effect as a write to the corresponding PORTx register.
A read of the LATx register reads the values held in the
I/O port latches, while a read of the PORTx register
reads the actual I/O pin value.
Ports that support analog inputs have an associated
ANSELx register. When an ANSELx bit is set, the
digital input buffer associated with that bit is disabled.
Disabling the input buffer prevents analog signal levels
on the pin between a logic high and low from causing
excessive current in the logic input circuitry. A
simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 11-1.
FIGURE 11-1: GENERIC I/O PORT
OPERATION
TABLE 11-1: PORT AVAILABILITY PER
DEVICE
Device
PORTA
PIC12(L)F1571 ●
PIC12(L)F1572 ●
Write LATx
Write PORTx
Data bus
Read PORTx
To digital peripherals
To analog peripherals
Data Register
TRISx
VSS
I/O pin
ANSELx
DQ
CK
Read LATx
VDD
Rev. 10-000052A
7/30/2013
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11.1 Alternate Pin Function
The Alternate Pin Function Control (APFCON) register
is used to steer specific peripheral input and output
functions between different pins. The APFCON register
is shown in Register 11-1. For this device family, the
following functions can be moved between different
pins.
•RX/DT
•TX/CK
• CWGOUTA
• CWGOUTB
•PWM2
•PWM1
These bits have no effect on the values of any TRISx
register. PORTx and TRISx overrides will be routed to
the correct pin. The unselected pin will be unaffected.
11.2 Register Definitions: Alternate Pin Function Control
REGISTER 11-1: APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
RXDTSEL CWGASEL CWGBSEL — T1GSEL TXCKSEL P2SEL P1SEL
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7 RXDTSEL: Pin Selection bit
1 = RX/DT function is on RA5
0 = RX/DT function is on RA1
bit 6 CWGASEL: Pin Selection bit
1 = CWGOUTA function is on RA5
0 = CWGOUTA function is on RA2
bit 5 CWGBSEL: Pin Selection bit
1 = CWGOUTB function is on RA4
0 = CWGOUTB function is on RA0
bit 4 Unimplemented: Read as ‘0’
bit 3 T1GSEL: Pin Selection bit
1 = T1G function is on RA3
0 = T1G function is on RA4
bit 2 TXCKSEL: Pin Selection bit
1 = TX/CK function is on RA4
0 = TX/CK function is on RA0
bit 1 P2SEL: Pin Selection bit
1 = PWM2 function is on RA4
0 = PWM2 function is on RA0
bit 0 P1SEL: Pin Selection bit
1 = PWM1 function is on RA5
0 = PWM1 function is on RA1
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11.3 PORTA Registers
11.3.1 DATA REGISTER
PORTA is a 6-bit wide, bidirectional port. The
corresponding Data Direction register is TRISA
(Register 11-3). Setting a TRISA bit (= 1) will make the
corresponding PORTA pin an input (i.e., disable the
output driver). Clearing a TRISA bit (= 0) will make the
corresponding PORTA pin an output (i.e., enables
output driver and puts the contents of the output latch
on the selected pin). The exception is RA3, which is
input-only and its TRISA bit will always read as ‘1’.
Example 11-1 shows how to initialize an I/O port.
Reading the PORTA register (Register 11-2) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are Read-Modify-Write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then
written to the Port Data Latch (LATA).
11.3.2 DIRECTION CONTROL
The TRISA register (Register 11-3) controls the
PORTA pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits
in the TRISA register are maintained set when using
them as analog inputs. I/O pins configured as analog
input always read ‘0’.
11.3.3 OPEN-DRAIN CONTROL
The ODCONA register (Register 11-7) controls the
open-drain feature of the port. Open-drain operation is
independently selected for each pin. When an
ODCONA bit is set, the corresponding port output
becomes an open-drain driver capable of sinking
current only. When an ODCONA bit is cleared, the
corresponding port output pin is the standard push-pull
drive capable of sourcing and sinking current.
11.3.4 SLEW RATE CONTROL
The SLRCONA register (Register 11-8) controls the
slew rate option for each port pin. Slew rate control is
independently selectable for each port pin. When an
SLRCONA bit is set, the corresponding port pin drive is
slew rate limited. When an SLRCONA bit is cleared,
the corresponding port pin drive slews at the maximum
rate possible.
11.3.5 INPUT THRESHOLD CONTROL
The INLVLA register (Register 11-9) controls the input
voltage threshold for each of the available PORTA input
pins. A selection between the Schmitt Trigger CMOS or
the TTL compatible thresholds is available. The input
threshold is important in determining the value of a
read of the PORTA register and also the level at which
an Interrupt-On-Change occurs, if that feature is
enabled. See Section 26.3 “DC Characteristics” for
more information on threshold levels.
11.3.6 ANALOG CONTROL
The ANSELA register (Register 11-5) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELA bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELA bits has no effect on digital out-
put functions. A pin with TRIS clear and ANSELA set will
still operate as a digital output, but the Input mode will be
analog. This can cause unexpected behavior when
executing Read-Modify-Write instructions on the
affected port.
EXAMPLE 11-1: INITIALIZING PORTA
Note: Changing the input threshold selection
should be performed while all peripheral
modules are disabled. Changing the
threshold level during the time a module is
active may inadvertently generate a transi-
tion associated with an input pin, regardless
of the actual voltage level on that pin.
Note: The ANSELA bits default to the Analog
mode after Reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSELA bits
must be initialized to ‘0’ by user software.
BANKSEL PORTA ;
CLRF PORTA ;Init PORTA
BANKSEL LATA ;Data Latch
CLRF LATA ;
BANKSEL ANSELA ;
CLRF ANSELA ;digital I/O
BANKSEL TRISA ;
MOVLW B'00111000' ;Set RA<5:3> as inputs
MOVWF TRISA ;and set RA<2:0> as
;outputs
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11.3.7 PORTA FUNCTIONS AND OUTPUT
PRIORITIES
Each PORTA pin is multiplexed with other functions. The
pins, their combined functions and their output priorities
are shown in Table 11-2.
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the highest priority.
Analog input functions, such as ADC and comparator
inputs, are not shown in the priority lists. These inputs
are active when the I/O pin is set for Analog mode using
the ANSELx registers. Digital output functions may
control the pin when it is in Analog mode with the
priority shown below in Table 11-2.
TABLE 11-2: PORTA OUTPUT PRIORITY
Pin Name Function Priority(1)
RA0 ICSPDAT
CWG1B(3)
DAC1OUT
TX(2,3)
PWM2(3)
RA0
RA1 PWM1(3)
RA1
RA2 CWG1A
CWG1FLT
C1OUT
PWM3
RA2
RA3 None
RA4 CLKOUT
CWG1B
TX(2)
PWM2
RA4
RA5 CWG1A
PWM1
RA5
Note 1: Priority listed from highest to lowest.
2: PIC12(L)F1572 only.
3: Default pin (see APFCON register).
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11.4 Register Definitions: PORTA
REGISTER 11-2: PORTA: PORTA REGISTER
U-0 U-0 R/W-x/x R/W-x/x R-x/x R/W-x/x R/W-x/x R/W-x/x
——RA<5:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 RA<5:0>: PORTA I/O Value bits(1)
1 = Port pin is > VIH
0 = Port pin is < VIL
Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from the PORTA register are
the return of actual I/O pin values.
REGISTER 11-3: TRISA: PORTA TRI-STATE REGISTER
U-0 U-0 R/W-1/1 R/W-1/1 U-1 R/W-1/1 R/W-1/1 R/W-1/1
—— TRISA<5:4> —(1) TRISA<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 TRISA<5:4>: PORTA Tri-State Control bits
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
bit 3 Unimplemented: Read as ‘1’(1)
bit 2-0 TRISA<2:0>: PORTA Tri-State Control bits
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
Note 1: Unimplemented, read as ‘1’.
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REGISTER 11-4: LATA: PORTA DATA LATCH REGISTER
U-0 U-0 R/W-x/u R/W-x/u U-0 R/W-x/u R/W-x/u R/W-x/u
——LATA<5:4>
(1) —LATA<2:0>
(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 LATA<5:4>: RA<5:4> Output Latch Value bits(1)
bit 3 Unimplemented: Read as ‘0’
bit 2-0 LATA<2:0>: RA<2:0> Output Latch Value bits(1)
Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from the PORTA register are
the return of actual I/O pin values.
REGISTER 11-5: ANSELA: PORTA ANALOG SELECT REGISTER
U-0 U-0 U-0 R/W-1/1 U-0 R/W-1/1 R/W-1/1 R/W-1/1
— — — ANSA4 — ANSA<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-5 Unimplemented: Read as ‘0’
bit 4 ANSA4: Analog Select Between Analog or Digital Function on RA4 Pins (respectively) bit
1 = Analog input; pin is assigned as analog input, digital input buffer is disabled(1)
0 = Digital I/O; pin is assigned to port or digital special function
bit 3 Unimplemented: Read as ‘0’
bit 2-0 ANSA<2:0>: Analog Select Between Analog or Digital Function on RA<2:0> pins (respectively) bits
1 = Analog input; pin is assigned as analog input, digital input buffer is disabled(1)
0 = Digital I/O; pin is assigned to port or digital special function
Note 1: When setting a pin to an analog input, the corresponding TRISx bit must be set to Input mode in order to
allow external control of the voltage on the pin.
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REGISTER 11-6: WPUA: WEAK PULL-UP PORTA REGISTER
U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
—— WPUA<5:0>(1,2,3)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 WPUA<5:0>: Weak Pull-up Register bits(1,2,3)
1 = Pull-up is enabled
0 = Pull-up is disabled
Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is configured as an output.
3: For the WPUA3 bit, when MCLRE = 1, the weak pull-up is internally enabled, but not reported here.
REGISTER 11-7: ODCONA: PORTA OPEN-DRAIN CONTROL REGISTER
U-0 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
——ODA<5:4>—ODA<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 ODA<5:4>: PORTA Open-Drain Enable bits
For RA<5:4> Pins, Respectively:
1 = Port pin operates as open-drain drive (sink current only)
0 = Port pin operates as standard push-pull drive (source and sink current)
bit 3 Unimplemented: Read as ‘0’
bit 2-0 ODA<2:0>: PORTA Open-Drain Enable bits
For RA<2:0> Pins, Respectively:
1 = Port pin operates as open-drain drive (sink current only)
0 = Port pin operates as standard push-pull drive (source and sink current)
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REGISTER 11-8: SLRCONA: PORTA SLEW RATE CONTROL REGISTER
U-0 U-0 R/W-1/1 R/W-1/1 U-0 R/W-1/1 R/W-1/1 R/W-1/1
—— SLRA<5:4> — SLRA<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-6 Unimplemented: Read as ‘0’
bit 5-4 SLRA<5:4>: PORTA Slew Rate Enable bits
For RA<5:4> Pins, Respectively:
1 = Port pin slew rate is limited
0 = Port pin slews at maximum rate
bit 3 Unimplemented: Read as ‘0’
bit 2-0 SLRA<2:0>: PORTA Slew Rate Enable bits
For RA<2:0> Pins, Respectively:
1 = Port pin slew rate is limited
0 = Port pin slews at maximum rate
REGISTER 11-9: INLVLA: PORTA INPUT LEVEL CONTROL REGISTER
U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
—— INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 INLVLA<5:0>: PORTA Input Level Select bits
For RA<5:0> Pins, Respectively:
1 = ST input is used for PORT reads and Interrupt-On-Change
0 = TTL input is used for PORT reads and Interrupt-On-Change
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TABLE 11-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
TABLE 11-4: SUMMARY OF CONFIGURATION WORD WITH PORTA
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
ANSELA — — — ANSA4 — ANSA<2:0> 114
APFCON RXDTSEL CWGASEL CWGBSEL — T1GSEL TXCKSEL P2SEL P1SEL 110
INLVLA ——INLVLA<5:0>116
LATA —— LATA<5:4> — LATA<2:0> 114
ODCONA ——ODA<5:4>—ODA<2:0>115
OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 157
PORTA ——RA<5:0>113
SLRCONA —— SLRA<5:4> — SLRA<2:0> 116
TRISA —— TRISA<5:4> —(1) TRISA<2:0> 113
WPUA —— WPUA<5:0> 115
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA.
Note 1: Unimplemented, read as ‘1’.
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 Register
on Page
CONFIG1 13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0> —42
7:0 CP MCLRE PWRTE WDTE<1:0> FOSC<2:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA.
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NOTES:
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12.0 INTERRUPT-ON-CHANGE
The PORTA and PORTB pins can be configured to
operate as Interrupt-On-Change (IOC) pins. An interrupt
can be generated by detecting a signal that has either a
rising edge or a falling edge. Any individual port pin, or
combination of port pins, can be configured to generate
an interrupt. The Interrupt-On-Change module has the
following features:
• Interrupt-On-Change enable (Master Switch)
• Individual pin configuration
• Rising and falling edge detection
• Individual pin interrupt flags
Figure 12-1 is a block diagram of the IOC module.
12.1 Enabling the Module
To allow individual port pins to generate an interrupt, the
IOCIE bit of the INTCON register must be set. If the
IOCIE bit is disabled, the edge detection on the pin will
still occur, but an interrupt will not be generated.
12.2 Individual Pin Configuration
For each port pin, a rising edge detector and a falling
edge detector are present. To enable a pin to detect a
rising edge, the associated bit of the IOCxP register is
set. To enable a pin to detect a falling edge, the
associated bit of the IOCxN register is set.
A pin can be configured to detect rising and falling
edges simultaneously by setting both associated bits of
the IOCxP and IOCxN registers, respectively.
12.3 Interrupt Flags
The IOCAFx and IOCBFx bits located in the IOCAF and
IOCBF registers, respectively, are status flags that
correspond to the Interrupt-On-Change pins of the
associated port. If an expected edge is detected on an
appropriately enabled pin, then the status flag for that pin
will be set, and an interrupt will be generated if the IOCIE
bit is set. The IOCIF bit of the INTCON register reflects
the status of all IOCAFx and IOCBFx bits.
12.4 Clearing Interrupt Flags
The individual status flags, (IOCAFx and IOCBFx bits),
can be cleared by resetting them to zero. If another edge
is detected during this clearing operation, the associated
status flag will be set at the end of the sequence,
regardless of the value actually being written.
In order to ensure that no detected edge is lost while
clearing flags, only AND operations masking out known
changed bits should be performed. The following
sequence is an example of what should be performed.
EXAMPLE 12-1: CLEARING INTERRUPT
FLAGS (PORTA EXAMPLE)
12.5 Operation in Sleep
The Interrupt-On-Change interrupt sequence will wake
the device from Sleep mode, if the IOCIE bit is set.
If an edge is detected while in Sleep mode, the IOCxF
register will be updated prior to the first instruction
executed out of Sleep.
MOVLW 0xff
XORWF IOCAF, W
ANDWF IOCAF, F
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FIGURE 12-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM (PORTA EXAMPLE)
IOCANx
IOCAPx
Q2
Q4Q1
data bus =
0 or 1
write IOCAFx
IOCIE
to data bus
IOCAFx
edge
detect
IOC interrupt
to CPU core
from all other
IOCnFx individual
pin detectors
DQ
S
DQ
R
DQ
R
RAx
Q1
Q2
Q3
Q4
Q4Q1
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q4Q1 Q4Q1Q4Q1
FOSC
Rev . 10-000 037A
6/2/201 4
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12.6 Register Definitions: Interrupt-On-Change Control
REGISTER 12-1: IOCAP: INTERRUPT-ON-CHANGE PORTA POSITIVE EDGE REGISTER
U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
——IOCAP<5:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 IOCAP<5:0>: Interrupt-On-Change PORTA Positive Edge Enable bits
1 = Interrupt-On-Change is enabled on the pin for a positive going edge; IOCAFx bit and IOCIF flag
will be set upon detecting an edge
0 = Interrupt-On-Change is disabled for the associated pin
REGISTER 12-2: IOCAN: INTERRUPT-ON-CHANGE PORTA NEGATIVE EDGE REGISTER
U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
——IOCAN<5:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 IOCAN<5:0>: Interrupt-On-Change PORTA Negative Edge Enable bits
1 = Interrupt-On-Change is enabled on the pin for a negative going edge; IOCAFx bit and IOCIF flag
will be set upon detecting an edge.
0 = Interrupt-On-Change is disabled for the associated pin
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TABLE 12-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE
REGISTER 12-3: IOCAF: INTERRUPT-ON-CHANGE PORTA FLAG REGISTER
U-0 U-0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
——IOCAF<5:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 IOCAF<5:0>: Interrupt-On-Change PORTA Flag bits
1 = An enabled change was detected on the associated pin
Set when IOCAPx = 1 and a rising edge was detected on RAx, or when IOCANx = 1 and a falling
edge was detected on RAx.
0 = No change was detected or the user cleared the detected change
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
ANSELA ———ANSA4— ANSA<2:0> 114
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 74
IOCAF ——IOCAF<5:0>122
IOCAN ——IOCAN<5:0>121
IOCAP —— IOCAP<5:0> 121
TRISA —— TRISA<5:4> —(1) TRISA<2:0> 113
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Interrupt-On-Change.
Note 1: Unimplemented, read as ‘1’.
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13.0 FIXED VOLTAGE REFERENCE
(FVR)
The Fixed Voltage Reference (FVR) is a stable voltage
reference, independent of VDD, with a nominal output
level (VFVR) of 1.024V. The output of the FVR can be
configured to supply a reference voltage to the
following:
• ADC input channel
• Comparator positive input
• Comparator negative input
The FVR can be enabled by setting the FVREN bit of
the FVRCON register.
13.1 Independent Gain Amplifier
The output of the FVR supplied to the peripherals,
(listed above), is routed through a programmable gain
amplifier. Each amplifier can be programmed for a gain
of 1x, 2x or 4x, to produce the three possible voltage
levels.
The ADFVR<1:0> bits of the FVRCON register are
used to enable and configure the gain amplifier settings
for the reference supplied to the ADC module. Refer-
ence Section 15.0 “Analog-to-Digital Converter
(ADC) Module” for additional information.
The CDAFVR<1:0> bits of the FVRCON register are
used to enable and configure the gain amplifier settings
for the reference supplied to the comparator modules.
Reference Section 17.0 “Comparator Module” for
additional information.
To minimize current consumption when the FVR is
disabled, the FVR buffers should be turned off by
clearing the Buffer Gain Selection bits.
13.2 FVR Stabilization Period
The FVR can be enabled by setting the FVREN bit of
the FVRCON register.
When the Fixed Voltage Reference module is enabled, it
requires time for the reference and amplifier circuits to
stabilize. Once the circuits stabilize and are ready for use,
the FVRRDY bit of the FVRCON register will be set. See
the FVR Stabilization Period characterization graph,
Figure 27-21.
FIGURE 13-1: VOLTAGE REFERENCE BLOCK DIAGRAM
Note 1: Any peripheral requiring the Fixed Voltage Reference (see Table 13-1).
1x
2x
4x
1x
2x
4x
ADFVR<1:0>
CDAFVR<1:0>
FVR_buffer1
(To ADC Module)
FVR_buffer2
(To Comparators)
+
_
FVREN FVRRDY
Note 1
2
2
Rev. 10-000053A
8/6/2013
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TABLE 13-1: PERIPHERALS REQUIRING THE FIXED VOLTAGE REFERENCE (FVR)
Peripheral Conditions Description
HFINTOSC FOSC<2:0> = 010 and
IRCF<3:0> = 000x INTOSC is active and device is not in Sleep.
BOR
BOREN<1:0> = 11 BOR is always enabled.
BOREN<1:0> = 10 and BORFS = 1BOR is disabled in Sleep mode, BOR Fast Start is enabled.
BOREN<1:0> = 01 and BORFS = 1BOR under software control, BOR Fast Start is enabled.
LDO All PIC12F1571/2 devices, when
VREGPM = 1 and not in Sleep
The device runs off of the Low-Power Regulator when in
Sleep mode.
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13.3 Register Definitions: FVR Control
TABLE 13-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE FIXED VOLTAGE REFERENCE
REGISTER 13-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER
R/W-0/0 R-q/q R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
FVREN(1) FVRRDY(2) TSEN(3) TSRNG(3) CDAFVR<1:0>(1) ADFVR<1:0>(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7 FVREN: Fixed Voltage Reference Enable bit(1)
1 = Fixed Voltage Reference is enabled
0 = Fixed Voltage Reference is disabled
bit 6 FVRRDY: Fixed Voltage Reference Ready Flag bit(2)
1 = Fixed Voltage Reference output is ready for use
0 = Fixed Voltage Reference output is not ready or not enabled
bit 5 TSEN: Temperature Indicator Enable bit(3)
1 = Temperature indicator is enabled
0 = Temperature indicator is disabled
bit 4 TSRNG: Temperature Indicator Range Selection bit(3)
1 =VOUT = VDD – 4VT (High Range)
0 =V
OUT = VDD – 2VT (Low Range)
bit 3-2 CDAFVR<1:0>: Comparator FVR Buffer Gain Selection bits(1)
11 = Comparator FVR Buffer Gain is 4x, with output VCDAFVR = 4x VFVR(4)
10 = Comparator FVR Buffer Gain is 2x, with output VCDAFVR = 2x VFVR(4)
01 = Comparator FVR Buffer Gain is 1x, with output VCDAFVR = 1x VFVR
00 = Comparator FVR Buffer is off
bit 1-0 ADFVR<1:0>: ADC FVR Buffer Gain Selection bit(1)
11 = ADC FVR Buffer Gain is 4x, with output VADFVR = 4x VFVR(4)
10 = ADC FVR Buffer Gain is 2x, with output VADFVR = 2x VFVR(4)
01 = ADC FVR Buffer Gain is 1x, with output VADFVR = 1x VFVR
00 = ADC FVR Buffer is off
Note 1: To minimize current consumption when the FVR is disabled, the FVR buffers should be turned off by
clearing the Buffer Gain Selection bits.
2: FVRRDY is always ‘1’ for the PIC12F1571/2 devices.
3: See Section 14.0 “Temperature Indicator Module” for additional information.
4: Fixed Voltage Reference output cannot exceed VDD.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR>1:0> ADFVR<1:0> 125
PIC12(L)F1571/2
DS40001723D-page 126 2013-2015 Microchip Technology Inc.
NOTES:
2013-2015 Microchip Technology Inc. DS40001723D-page 127
PIC12(L)F1571/2
14.0 TEMPERATURE INDICATOR
MODULE
This family of devices is equipped with a temperature
circuit designed to measure the operating temperature
of the silicon die. The circuit’s range of operating
temperature falls between -40°C and +85°C. The
output is a voltage that is proportional to the device
temperature. The output of the temperature indicator is
internally connected to the device ADC.
The circuit may be used as a temperature threshold
detector or a more accurate temperature indicator,
depending on the level of calibration performed. A one-
point calibration allows the circuit to indicate a
temperature closely surrounding that point. A two-point
calibration allows the circuit to sense the entire range
of temperature more accurately. Reference Application
Note AN1333, “Use and Calibration of the Internal
Temperature Indicator” (DS00001333) for more details
regarding the calibration process.
14.1 Circuit Operation
Figure 14-1 shows a simplified block diagram of the
temperature circuit. The proportional voltage output is
achieved by measuring the forward voltage drop across
multiple silicon junctions.
Equation 14-1 describes the output characteristics of
the temperature indicator.
EQUATION 14-1: VOUT RANGES
The temperature sense circuit is integrated with the
Fixed Voltage Reference (FVR) module. See
Section 13.0 “Fixed Voltage Reference (FVR)” for
more information.
The circuit is enabled by setting the TSEN bit of the
FVRCON register. When disabled, the circuit draws no
current.
The circuit operates in either high or low range. The high
range, selected by setting the TSRNG bit of the
FVRCON register, provides a wider output voltage. This
provides more resolution over the temperature range,
but may be less consistent from part to part. This range
requires a higher bias voltage to operate and thus, a
higher VDD is needed.
The low range is selected by clearing the TSRNG bit of
the FVRCON register. The low range generates a lower
voltage drop and thus, a lower bias voltage is needed
to operate the circuit. The low range is provided for
low-voltage operation.
FIGURE 14-1: TEMPERATURE CIRCUIT
DIAGRAM
14.2 Minimum Operating VDD
When the temperature circuit is operated in low range,
the device may be operated at any operating voltage
that is within specifications.
When the temperature circuit is operated in high range,
the device operating voltage, VDD, must be high
enough to ensure that the temperature circuit is
correctly biased.
Table 14-1 shows the recommended minimum VDD vs.
range setting.
TABLE 14-1: RECOMMENDED VDD VS.
RANGE
14.3 Temperature Output
The output of the circuit is measured using the
internal Analog-to-Digital Converter. A channel is
reserved for the temperature circuit output. Refer to
Section 15.0 “Analog-to-Digital Converter (ADC)
Module” for detailed information.
14.4 ADC Acquisition Time
To ensure accurate temperature measurements, the
user must wait at least 200 s after the ADC input
multiplexer is connected to the temperature indicator
output before the conversion is performed. In addition,
the user must wait 200 s between sequential
conversions of the temperature indicator output.
High Range: VOUT = VDD – 4 VT
Low Range: VOUT = VDD – 2 VT
Min. VDD, TSRNG = 1Min. VDD, TSRNG = 0
3.6V 1.8V
VOUT
Temp. Indicator To ADC
TSRNG
TSEN
Rev. 10-000069A
7/31/2013
VDD
PIC12(L)F1571/2
DS40001723D-page 128 2013-2015 Microchip Technology Inc.
TABLE 14-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 118
Legend: Shaded cells are unused by the temperature indicator module.
2013-2015 Microchip Technology Inc. DS40001723D-page 129
PIC12(L)F1571/2
15.0 ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
The Analog-to-Digital Converter (ADC) allows
conversion of an analog input signal to a 10-bit binary
representation of that signal. This device uses analog
inputs, which are multiplexed into a single sample and
hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates a 10-bit binary result via successive
approximation and stores the conversion result into the
ADC result registers (ADRESH:ADRESL register pair).
Figure 15-1 shows the block diagram of the ADC.
The ADC voltage reference is software selectable to be
either internally generated or externally supplied.
The ADC can generate an interrupt upon completion of
a conversion. This interrupt can be used to wake-up the
device from Sleep.
FIGURE 15-1: ADC BLOCK DIAGRAM
V
RPOS
V
RNEG
Enable
DACx_output
FVR_buffer1
Temp Indicator
CHS<4:0>
External
Channel
Inputs
GO/DONE
complete
start
ADC
Sample Circuit
Writetobit
GO/DONE
V
SS
V
DD
V
REF
+ pin
V
DD
ADPREF
10-bit Result
ADRESH ADRESL
16
ADFM
10
Internal
Channel
Inputs
.
.
.
AN0
ANa
ANz
set bit ADIF
V
SS
ADON
sampled
input
Q1
Q2
Q4
Fosc
Divider F
OSC
F
OSC
/n
F
RC
ADC
Clock
Select
ADC_clk
ADCS<2:0>
F
RC
ADC CLOCK SOURCE
Trigger Select
Trigger Sources
...
TRIGSEL<3:0>
AUTO CONVERSION
TRIGGER
Positive
Reference
Select
Rev. 10-000033A
7/30/2013
PIC12(L)F1571/2
DS40001723D-page 130 2013-2015 Microchip Technology Inc.
15.1 ADC Configuration
When configuring and using the ADC the following
functions must be considered:
• Port configuration
• Channel selection
• ADC voltage reference selection
• ADC conversion clock source
• Interrupt control
• Result formatting
15.1.1 PORT CONFIGURATION
The ADC can be used to convert both analog and
digital signals. When converting analog signals, the I/O
pin should be configured for analog by setting the
associated TRISx and ANSELx bits. Refer to
Section 11.0 “I/O Ports” for more information.
15.1.2 CHANNEL SELECTION
There are 7 channel selections available:
• AN<3:0> pins
• Temperature Indicator
• DAC1_output
• FVR_buffer1
The CHS bits of the ADCON0 register determine which
channel is connected to the sample and hold circuit.
When changing channels, a delay (TACQ) is required
before starting the next conversion. Refer to
Section 15.2.6 “ADC Conversion Procedure” for
more information.
15.1.3 ADC VOLTAGE REFERENCE
The ADC module uses a positive and a negative
voltage reference. The positive reference is labeled
ref+ and the negative reference is labeled ref-.
The positive voltage reference (ref+) is selected by the
ADPREFx bits in the ADCON1 register. The positive
voltage reference source can be:
•V
REF+ pin
•V
DD
The negative voltage reference (ref-) source is:
•V
SS
15.1.4 CONVERSION CLOCK
The source of the conversion clock is software-selectable
via the ADCSx bits of the ADCON1 register. There are
seven possible clock options:
•F
OSC/2
•F
OSC/4
•FOSC/8
•FOSC/16
•F
OSC/32
•FOSC/64
• FRC (internal Fast RC oscillator)
The time to complete one bit conversion is defined as
TAD. One full 10-bit conversion requires 11.5 TAD
periods, as shown in Figure 15-2.
For correct conversion, the appropriate TAD specification
must be met. Refer to the ADC conversion requirements
in Section 26.0 “Electrical Specifications” for more
information. Table 15-1 gives examples of appropriate
ADC clock selections.
Note: Analog voltages on any pin that is defined
as a digital input may cause the input
buffer to conduct excess current.
Note: Unless using the FRC, any changes in the
system clock frequency will change the
ADC clock frequency, which may
adversely affect the ADC result.
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PIC12(L)F1571/2
TABLE 15-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
FIGURE 15-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES
ADC Clock Period (TAD) Device Frequency (FOSC)
ADC
Clock
Source
ADCS<2:0> 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz
Fosc/2 000 100 ns 125 ns 250 ns 500 ns 2.0 s
Fosc/4 100 200 ns 250 ns 500 ns 1.0 s4.0 s
Fosc/8 001 400 ns 500 ns 1.0 s2.0 s8.0 s
Fosc/16 101 800 ns 1.0 s2.0 s4.0 s16.0 s
Fosc/32 010 1.6 s2.0 s4.0 s8.0 s32.0 s
Fosc/64 110 3.2 s4.0 s8.0 s16.0 s64.0 s
FRC x11 1.0-6.0 s 1.0-6.0 s 1.0-6.0 s 1.0-6.0 s 1.0-6.0 s
Legend: Shaded cells are outside of recommended range.
Note: The TAD period when using the FRC clock source can fall within a specified range (see TAD parameter).
The TAD period when using the FOSC-based clock source can be configured for a more precise TAD period.
However, the FRC clock source must be used when conversions are to be performed with the device in
Sleep mode.
TAD1TAD2TAD3TAD4TAD5TAD6TAD7TAD8TAD9TAD10 TAD11
SetGObit
Conversion Starts
Holding capacitor disconnected
from analog input (THCD).
On the following cycle:
ADRESH:ADRESL is loaded,
GO bit is cleared,
ADIF bit is set,
holding capacitor is reconnected to analog input.
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Enable ADC (ADON bit)
and
Select channel (ACS bits)
THCD
TACQ
Rev. 10-000035A
7/30/2013
PIC12(L)F1571/2
DS40001723D-page 132 2013-2015 Microchip Technology Inc.
15.1.5 INTERRUPTS
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
conversion. The ADC Interrupt Flag is the ADIF bit in
the PIR1 register. The ADC Interrupt Enable is the
ADIE bit in the PIE1 register. The ADIF bit must be
cleared in software.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP instruc-
tion is always executed. If the user is attempting to
wake-up from Sleep and resume in-line code execu-
tion, the ADIE bit of the PIE1 register and the PEIE bit
of the INTCON register must both be set, and the GIE
bit of the INTCON register must be cleared. If all three
of these bits are set, the execution will switch to the
Interrupt Service Routine.
15.1.6 RESULT FORMATTING
The 10-bit ADC conversion result can be supplied in
two formats, left justified or right justified. The ADFM bit
of the ADCON1 register controls the output format.
Figure 15-3 shows the two output formats.
FIGURE 15-3: 10-BIT ADC CONVERSION RESULT FORMAT
Note 1: The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
2: The ADC operates during Sleep only
when the FRC oscillator is selected.
MSB
MSB
LSB
LSB
(ADFM = 0)
(ADFM = 1)
bit 7 bit 7
bit 7bit 7
bit 0
bit 0
bit 0
bit 0
10-bit ADC Result
10-bit ADC Result
Unimplemented: Read as ‘0’
Unimplemented: Read as ‘0’
ADRESH ADRESL
Rev. 10-000054A
7/30/2013
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PIC12(L)F1571/2
15.2 ADC Operation
15.2.1 STARTING A CONVERSION
To enable the ADC module, the ADON bit of the
ADCON0 register must be set to a ‘1’. Setting the
GO/DONE bit of the ADCON0 register to a ‘1’ will start
the Analog-to-Digital conversion.
15.2.2 COMPLETION OF A CONVERSION
When the conversion is complete, the ADC module will:
• Clear the GO/DONE bit
• Set the ADIF Interrupt Flag bit
• Update the ADRESH and ADRESL registers with
new conversion result
15.2.3 TERMINATING A CONVERSION
If a conversion must be terminated before completion,
the GO/DONE bit can be cleared in software. The
ADRESH and ADRESL registers will be updated with
the partially complete Analog-to-Digital conversion
sample. Incomplete bits will match the last bit
converted.
15.2.4 ADC OPERATION DURING SLEEP
The ADC module can operate during Sleep. This
requires the ADC clock source to be set to the FRC
option. Performing the ADC conversion during Sleep
can reduce system noise. If the ADC interrupt is
enabled, the device will wake-up from Sleep when the
conversion completes. If the ADC interrupt is disabled,
the ADC module is turned off after the conversion
completes, although the ADON bit remains set.
When the ADC clock source is something other than
FRC, a SLEEP instruction causes the present conver-
sion to be aborted and the ADC module is turned off,
although the ADON bit remains set.
15.2.5 AUTO-CONVERSION TRIGGER
The auto-conversion trigger allows periodic ADC
measurements without software intervention. When a
rising edge of the selected source occurs, the
GO/DONE bit is set by hardware.
The auto-conversion trigger source is selected with the
TRIGSEL<3:0> bits of the ADCON2 register.
Using the auto-conversion trigger does not assure
proper ADC timing. It is the user’s responsibility to
ensure that the ADC timing requirements are met.
The PWM module can trigger the ADC in two ways,
directly through the PWMx_OFx_match or through the
interrupts generated by all four match signals. See
Section 22.0 “16-Bit Pulse-Width Modulation (PWM)
Module”. If the interrupts are chosen, each enabled
interrupt in PWMxINTE will trigger a conversion. Refer
to Figure 15-4 for more information.
See Table 15-2 for auto-conversion sources.
FIGURE 15-4: 16-BIT PWM INTERRUPT
BLOCK DIAGRAM
Note: The GO/DONE bit should not be set in the
same instruction that turns on the ADC.
Refer to Section 15.2.6 “ADC Conversion
Procedure”.
Note: A device Reset forces all registers to their
Reset state. Thus, the ADC module is
turned off and any pending conversion is
terminated.
TABLE 15-2: AUTO-CONVERSION
SOURCES
Source Peripheral Signal Name
Timer0 T0_overflow
Timer1 T1_overflow
Timer2 T2_match
Comparator C1 C1OUT_sync
PWM1 PWM1_OF_match
PWM1 PWM1_interrupt
PWM2 PWM2_OF_match
PWM2 PWM2_interrupt
PWM3 PWM3_OF_match
PWM3 PWM3_interrupt
Rev. 10-000154A
10/24/2013
PWMx_interrupt
PWMxOFIE
PWMxPHIE
PWMxDCIE
PWMxPRIE
OFx_match
PRx_match
DCx_match
PHx_match
PIC12(L)F1571/2
DS40001723D-page 134 2013-2015 Microchip Technology Inc.
15.2.6 ADC CONVERSION PROCEDURE
This is an example procedure for using the ADC to
perform an Analog-to-Digital conversion:
1. Configure port:
• Disable pin output driver (refer to the
TRISx register)
• Configure pin as analog (refer to the
ANSELx register)
• Disable weak pull-ups either globally (refer to
the OPTION_REG register) or individually
(refer to the appropriate WPUx register)
2. Configure the ADC module:
• Select ADC conversion clock
• Configure voltage reference
• Select ADC input channel
• Turn on ADC module
3. Configure ADC interrupt (optional):
• Clear ADC interrupt flag
• Enable ADC interrupt
• Enable peripheral interrupt
• Enable global interrupt(1)
4. Wait the required acquisition time.(2)
5. Start conversion by setting the GO/DONE bit.
6. Wait for ADC conversion to complete by one of
the following:
• Polling the GO/DONE bit
• Waiting for the ADC interrupt (interrupts
enabled)
7. Read ADC result.
8. Clear the ADC interrupt flag (required if interrupt
is enabled).
EXAMPLE 15-1: ADC CONVERSION
Note 1: The global interrupt can be disabled if the
user is attempting to wake-up from Sleep
and resume in-line code execution.
2: Refer to Section 15.4 “ADC Acquisition
Requirements”.
;This code block configures the ADC
;for polling, Vdd and Vss references, FRC
;oscillator and AN0 input.
;
;Conversion start & polling for completion
; are included.
;
BANKSEL ADCON1 ;
MOVLW B’11110000’ ;Right justify, FRC
;oscillator
MOVWF ADCON1 ;Vdd and Vss Vref+
BANKSEL TRISA ;
BSF TRISA,0 ;Set RA0 to input
BANKSEL ANSEL ;
BSF ANSEL,0 ;Set RA0 to analog
BANKSEL WPUA
BCF WPUA,0 ;Disable weak
;pull-up on RA0
BANKSEL ADCON0 ;
MOVLW B’00000001’ ;Select channel AN0
MOVWF ADCON0 ;Turn ADC On
CALL SampleTime ;Acquisiton delay
BSF ADCON0,ADGO ;Start conversion
BTFSC ADCON0,ADGO ;Is conversion done?
GOTO $-1 ;No, test again
BANKSEL ADRESH ;
MOVF ADRESH,W ;Read upper 2 bits
MOVWF RESULTHI ;store in GPR space
BANKSEL ADRESL ;
MOVF ADRESL,W ;Read lower 8 bits
MOVWF RESULTLO ;Store in GPR space
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PIC12(L)F1571/2
15.3 Register Definitions: ADC Control
REGISTER 15-1: ADCON0: ADC CONTROL REGISTER 0
U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— CHS<4:0> GO/DONE ADON
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7 Unimplemented: Read as ‘0’
bit 6-2 CHS<4:0>: Analog Channel Select bits
00000 =AN0
00001 =AN1
00010 =AN2
00011 =AN3
00100 = Reserved; no channel connected
•
•
•
11100 = Reserved; no channel connected
11101 = Temperature indicator(1)
11110 = DAC (Digital-to-Analog Converter)(2)
11111 = FVR (Fixed Voltage Reference) Buffer 1 output(3)
bit 1 GO/DONE: ADC Conversion Status bit
1 = ADC conversion cycle is in progress
Setting this bit starts an ADC conversion cycle. This bit is automatically cleared by hardware when
the ADC conversion has completed.
0 = ADC conversion completed/not in progress
bit 0 ADON: ADC Enable bit
1 = ADC is enabled
0 = ADC is disabled and consumes no operating current
Note 1: See Section 14.0 “Temperature Indicator Module” for more information.
2: See Section 16.0 “5-Bit Digital-to-Analog Converter (DAC) Module” for more information.
3: See Section 13.0 “Fixed Voltage Reference (FVR)” for more information.
PIC12(L)F1571/2
DS40001723D-page 136 2013-2015 Microchip Technology Inc.
REGISTER 15-2: ADCON1: ADC CONTROL REGISTER 1
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0
ADFM ADCS<2:0> — — ADPREF<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7 ADFM: ADC Result Format Select bit
1 = Right justified; six Most Significant bits of ADRESH are set to ‘0’ when the conversion result is loaded
0 = Left justified; six Least Significant bits of ADRESL are set to ‘0’ when the conversion result is loaded
bit 6-4 ADCS<2:0>: ADC Conversion Clock Select bits
000 =F
OSC/2
001 =F
OSC/8
010 =F
OSC/32
011 = FRC (clock supplied from an internal RC oscillator)
100 =FOSC/4
101 =F
OSC/16
110 =F
OSC/64
111 = FRC (clock supplied from an internal RC oscillator)
bit 3-2 Unimplemented: Read as ‘0’
bit 1-0 ADPREF<1:0>: ADC Positive Voltage Reference Configuration bits
00 =V
RPOS is connected to VDD
01 = Reserved
10 =V
RPOS is connected to external VREF+ pin(1)
11 =VRPOS is connected to internal Fixed Voltage Reference (FVR)
Note 1: When selecting the VREF+ pin as the source of the positive reference, be aware that a minimum voltage
specification exists. See Section 26.0 “Electrical Specifications” for details.
2013-2015 Microchip Technology Inc. DS40001723D-page 137
PIC12(L)F1571/2
REGISTER 15-3: ADCON2: ADC CONTROL REGISTER 2
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0
TRIGSEL<3:0>(1) — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-4 TRIGSEL<3:0>: Auto-Conversion Trigger Selection bits(1)
0000 = No auto-conversion trigger selected
0001 = PWM1 – PWM1_interrupt
0010 = PWM2 – PWM2_interrupt
0011 = Timer0 – T0_overflow(2)
0100 = Timer1 – T1_overflow(2)
0101 = Timer2 – T2_match
0110 = Comparator C1 – C1OUT_sync
0111 = PWM3 – PWM3_interrupt
1000 = PWM1 – PWM1_OF1_match
1001 = PWM2 – PWM2_OF2_match
1010 = PWM3 – PWM3_OF3_match
1011 = Reserved
1100 = Reserved
1101 = Reserved
1110 = Reserved
1111 = Reserved
bit 3-0 Unimplemented: Read as ‘0’
Note 1: This is a rising edge sensitive input for all sources.
2: Signal also sets its corresponding interrupt flag.
PIC12(L)F1571/2
DS40001723D-page 138 2013-2015 Microchip Technology Inc.
REGISTER 15-4: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
ADRES<9:2>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-0 ADRES<9:2>: ADC Result Register bits
Upper eight bits of 10-bit conversion result.
REGISTER 15-5: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
ADRES<1:0> — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-6 ADRES<1:0>: ADC Result Register bits
Lower two bits of 10-bit conversion result.
bit 5-0 Reserved: Do not use
2013-2015 Microchip Technology Inc. DS40001723D-page 139
PIC12(L)F1571/2
REGISTER 15-6: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — — — — — ADRES<9:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-2 Reserved: Do not use
bit 1-0 ADRES<9:8>: ADC Result Register bits
Upper two bits of 10-bit conversion result.
REGISTER 15-7: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
ADRES<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-0 ADRES<7:0>: ADC Result Register bits
Lower eight bits of 10-bit conversion result.
PIC12(L)F1571/2
DS40001723D-page 140 2013-2015 Microchip Technology Inc.
15.4 ADC Acquisition Requirements
For the ADC to meet its specified accuracy, the Charge
Holding Capacitor (CHOLD) must be allowed to fully
charge to the input channel voltage level. The Analog
Input model is shown in Figure 15-5. The Source
Impedance (RS) and the internal Sampling Switch
Impedance (RSS) directly affect the time required to
charge the capacitor, CHOLD. The Sampling Switch
Impedance (RSS) varies over the device voltage (VDD);
refer to Figure 15-5. The maximum recommended
impedance for analog sources is 10 k. As the
Source Impedance is decreased, the acquisition time
may be decreased. After the analog input channel is
selected (or changed), an ADC acquisition must be
done before the conversion can be started. To calculate
the minimum acquisition time, Equation 15-1 may be
used. This equation assumes that 1/2 LSb error is used
(1,024 steps for the ADC). The 1/2 LSb error is the
maximum error allowed for the ADC to meet its
specified resolution.
EQUATION 15-1: ACQUISITION TIME EXAMPLE
TACQ Amplifier Settling Time Hold Capacitor Charging Time Temperature Coefficient++=
TAMP TCTCOFF++=
2µs TCTemperature - 25°C0.05µs/°C++=
TCCHOLD RIC RSS RS++ ln(1/2047)–=
1 2.5pF 1k
7k
10k
++– ln(0.0004885)=
1.715=µs
VAPPLIED 1e
Tc–
RC
---------
–
VAPPLIED 11
2n1+
1–
--------------------------–
=
VAPPLIED 11
2n1+
1–
--------------------------–
VCHOLD=
VAPPLIED 1e
TC–
RC
----------
–
VCHOLD=
;[1] VCHOLD charged to within 1/2 lsb
;[2] VCHOLD char ge response to VAPPLIED
;combining [1] and [2]
The value for TC can be approximated with the following equations:
Solving for TC:
Therefore:
Temperature 50°C and external impedance of 10k
5.0V V DD=
Assumptions:
Note: Where n = number of bits of the ADC.
TACQ 2µs 1.715µs 50°C- 25°C0.05µs/°C++=
4.96µs=
Note 1: The Reference Voltage (VRPOS) has no effect on the equation, since it cancels itself out.
2: The Charge Holding Capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
2013-2015 Microchip Technology Inc. DS40001723D-page 141
PIC12(L)F1571/2
FIGURE 15-5: ANALOG INPUT MODEL
FIGURE 15-6: ADC TRANSFER FUNCTION
VDD
Analog
Input pin
CPIN
5pF VT§ 0.6V
VT§ 0.6V
ILEAKAGE(1)
RIC 1K
Legend: CHOLD = Sample/Hold Capacitance
CPIN = Input Capacitance
ILEAKAGE = Leakage Current at the pin due to varies injunctions
RIC = Interconnect Resistance
RSS = Resistance of Sampling switch
SS = Sampling Switch
VT= Threshold Voltage
VA
RSRSS
SS
Sampling
switch
CHOLD = 12.5 pF
Ref-
567891011
2V
3V
4V
5V
6V
VDD RSS
Sampling Switch
(k )
Rev. 10-000070B
8/5/2014
Note 1: Refer to Section 26.0 “Electrical Specifications”.
3FFh
3FEh
ADC Output Code
3FDh
3FCh
03h
02h
01h
00h
Full-Scale
3FBh
0.5 LSB
Ref- Zero-Scale
Transition Ref+
Transition
1.5 LSB
Full-Scale Range
Analog Input Voltage
PIC12(L)F1571/2
DS40001723D-page 142 2013-2015 Microchip Technology Inc.
TABLE 15-3: SUMMARY OF REGISTERS ASSOCIATED WITH ADC
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
ADCON0 — CHS<4:0> GO/DONE ADON 135
ADCON1 ADFM ADCS<2:0> ——ADPREF<1:0>136
ADCON2 TRIGSEL<3:0> — — — — 137
ADRESH ADC Result Register High 138, 139
ADRESL ADC Result Register Low 138, 139
ANSELA — — — ANSA4 — ANSA<2:0> 114
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 74
PIE1 TMR1GIE ADIE RCIE(2) TXIE(2) — — TMR2IE TMR1IE 75
PIR1 TMR1GIF ADIF RCIF(2) TXIF(2) — — TMR2IF TMR1IF 78
TRISA — — TRISA5 TRISA4 —(1) TRISA<2:0> 113
FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 125
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for the ADC module.
Note 1: Unimplemented, read as ‘1’.
2: PIC12(L)F1572 only.
2013-2015 Microchip Technology Inc. DS40001723D-page 143
PIC12(L)F1571/2
16.0 5-BIT DIGITAL-TO-ANALOG
CONVERTER (DAC) MODULE
The Digital-to-Analog Converter supplies a variable
voltage reference, ratiometric with the input source,
with 32 selectable output levels.
The positive input source (VSOURCE+) of the DAC can
be connected to the:
•External V
REF+ pin
•V
DD supply voltage
• FVR buffered output
The negative input source (VSOURCE-) of the DAC can
be connected to the:
•Vss
The output of the DAC (DACx_output) can be selected
as a reference voltage to the following:
• Comparator positive input
• ADC input channel
•DACxOUT1 pin
The Digital-to-Analog Converter (DAC) can be enabled
by setting the DACEN bit of the DACxCON0 register.
FIGURE 16-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM
VREF+
VDD
VSOURCE+
VSOURCE-
VSS
R
32
Steps
R
R
R
R
R
R
32-to-1 MUX
To Peripherals
DACxOUT1 (1)
DACOE1
DACx_output
DACEN
DACR<4:0>
5
Note 1: The unbuffered DACx_output is provided on the DACxOUT pin(s).
Rev. 10-000026B
9/6/2013
00
11
10
01
FVR_buffer2
Reserved
DACPSS
PIC12(L)F1571/2
DS40001723D-page 144 2013-2015 Microchip Technology Inc.
16.1 Output Voltage Selection
The DAC has 32 voltage level ranges. The 32 levels
are set with the DACR<4:0> bits of the DACxCON1
register.
The DAC output voltage can be determined by using
Equation 16-1.
16.2 Ratiometric Output Level
The DAC output value is derived using a resistor ladder
with each end of the ladder tied to a positive and
negative voltage reference input source. If the voltage
of either input source fluctuates, a similar fluctuation will
result in the DAC output value.
The value of the individual resistors within the ladder
can be found in Table 26-16.
16.3 DAC Voltage Reference Output
The unbuffered DAC voltage can be output to the
DACxOUTn pin(s) by setting the respective DACOEn
bit(s) of the DACxCON0 register. Selecting the DAC
reference voltage for output on either DACxOUTn pin
automatically overrides the digital output buffer, the
weak pull-up and digital input threshold detector
functions of that pin.
Reading the DACxOUTn pin when it has been
configured for DAC reference voltage output will
always return a ‘0’.
16.4 Operation During Sleep
When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the DACxCON0 register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
16.5 Effects of a Reset
A device Reset affects the following:
• DACx is disabled.
•DAC
X output voltage is removed from the
DACxOUTn pin(s).
• The DACR<4:0> range select bits are cleared.
EQUATION 16-1: DAC OUTPUT VOLTAGE
Note: The unbuffered DAC output (DACxOUTn)
is not intended to drive an external load.
IF DACEN = 1
DACx_output VSOURCE+VSOURCE-–
DACR 4:0
25
-----------------------------
VSOURCE-+=
Note: See the DACxCON0 register for the available VSOURCE+ and VSOURCE- selections.
2013-2015 Microchip Technology Inc. DS40001723D-page 145
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16.6 Register Definitions: DAC Control
TABLE 16-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC MODULE
REGISTER 16-1: DACxCON0: DACx VOLTAGE REFERENCE CONTROL REGISTER 0
R/W-0/0 U-0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 U-0 U-0
DACEN —DACOE— DACPSS<1:0> — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7 DACEN: DAC Enable bit
1 = DACx is enabled
0 = DACx is disabled
bit 6 Unimplemented: Read as ‘0’
bit 5 DACOE: DAC Voltage Output Enable bit
1 = DACx voltage level is output on the DACxOUT1 pin
0 = DACx voltage level is disconnected from the DACxOUT1 pin
bit 4 Unimplemented: Read as ‘0’
bit 3-2 DACPSS<1:0>: DAC Positive Source Select bits
11 = Reserved
10 = FVR_buffer2
01 =V
REF+ pin
00 =V
DD
bit 1-0 Unimplemented: Read as ‘0’
REGISTER 16-2: DACxCON1: DACx VOLTAGE REFERENCE CONTROL REGISTER 1
U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— — — DACR<4:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-5 Unimplemented: Read as ‘0’
bit 4-0 DACR<4:0>: DAC Voltage Output Select bits
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
DACxCON0 DACEN —DACOE— DACPSS<1:0> — — 145
DACxCON1 — — — DACR<4:0> 145
Legend: — = Unimplemented location, read as ‘0’.
PIC12(L)F1571/2
DS40001723D-page 146 2013-2015 Microchip Technology Inc.
NOTES:
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PIC12(L)F1571/2
17.0 COMPARATOR MODULE
Comparators are used to interface analog circuits to a
digital circuit by comparing two analog voltages and
providing a digital indication of their relative magnitudes.
Comparators are very useful mixed signal building
blocks because they provide analog functionality inde-
pendent of program execution. The analog comparator
module includes the following features:
• Independent comparator control
• Programmable input selection
• Comparator output is available internally/externally
• Programmable output polarity
• Interrupt-On-Change
• Wake-up from Sleep
• Programmable speed/power optimization
•PWM shutdown
• Programmable and Fixed Voltage Reference
17.1 Comparator Overview
A single comparator is shown in Figure 17-2 along with
the relationship between the analog input levels and
the digital output. When the analog voltage at VIN+ is
less than the analog voltage at VIN-, the output of the
comparator is a digital low level. When the analog volt-
age at VIN+ is greater than the analog voltage at VIN-,
the output of the comparator is a digital high level.
The comparators available for this device are listed in
Table 17-1.
FIGURE 17-1: COMPARATOR MODULE SIMPLIFIED BLOCK DIAGRAM
TABLE 17-1: AVAILABLE COMPARATORS
Device C1
PIC12(L)F1571 ●
PIC12(L)F1572 ●
Rev. 10-000027C
9/6/2013
CxIN0-
CxIN1-
Reserved
Reserved
CxIN+
FVR_buffer2
DAC_out
+
CxVN
CxVP
CxPCH<1:0>
CxNCH<2:0>
2
3
CxON(1)
CxON(1)
CxON(1)
CxSP CxHYS
Interrupt
Rising
Edge
DQ
Q1
CxINTP
CxINTN
CxOUT
MCxOUT
CxOUT_async
DQ
0
1
CxSYNC
set bit
CxIF
TRIS bit
CxOUT
CxOUT_sync
CxOE
-
Interrupt
Falling
Edge
FVR_buffer2
CxPOL
Cx
(From Timer1 Module) T1CLK
to
peripherals
Note 1: When CxON = 0, all multiplexer inputs are disconnected and the Comparator will produce a ‘0’ at the output.
to
peripherals
000
011
010
001
100
101
110
111
Reserved
Reserved
00
11
10
01
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DS40001723D-page 148 2013-2015 Microchip Technology Inc.
FIGURE 17-2: SINGLE COMPARATOR
17.2 Comparator Control
The comparator has two control registers: CMxCON0
and CMxCON1.
The CMxCON0 register (see Register 17-1) contains
control and status bits for the following:
• Enable
•Output selection
• Output polarity
• Speed/power selection
• Hysteresis enable
• Output synchronization
The CMxCON1 register (see Register 17-2) contains
control bits for the following:
• Interrupt enable
• Interrupt edge polarity
• Positive input channel selection
• Negative input channel selection
17.2.1 COMPARATOR ENABLE
Setting the CxON bit of the CMxCON0 register enables
the comparator for operation. Clearing the CxON bit
disables the comparator resulting in minimum current
consumption.
17.2.2 COMPARATOR POSITIVE INPUT
SELECTION
Configuring the CxPCH<1:0> bits of the CMxCON1
register directs an internal voltage reference or an
analog pin to the non-inverting input of the comparator:
• CxIN+ analog pin
• DAC1_output
• FVR_buffer2
•V
SS
See Section 13.0 “Fixed Voltage Reference (FVR)”
for more information on the Fixed Voltage Reference
module.
See Section 16.0 “5-Bit Digital-to-Analog Converter
(DAC) Module” for more information on the DAC input
signal.
Any time the comparator is disabled (CxON = 0), all
comparator inputs are disabled.
17.2.3 COMPARATOR NEGATIVE INPUT
SELECTION
The CxNCH<2:0> bits of the CMxCON0 register direct
one of the input sources to the comparator inverting input.
17.2.4 COMPARATOR OUTPUT SELECTION
The output of the comparator can be monitored by
reading either the CxOUT bit of the CMxCON0 register
or the MCxOUT bit of the CMOUT register. In order to
make the output available for an external connection,
the following conditions must be true:
• CxOE bit of the CMxCON0 register must be set
• Corresponding TRISx bit must be cleared
• CxON bit of the CMxCON0 register must be set
The synchronous comparator output signal
(CxOUT_sync) is available to the following peripheral(s):
• Analog-to-Digital Converter (ADC)
•Timer1
The asynchronous comparator output signal
(CxOUT_async) is available to the following peripheral(s):
• Complementary Waveform Generator (CWG)
–
+
VIN+
VIN-Output
Output
VIN+
VIN-
Note: The black areas of the output of the
comparator represents the uncertainty
due to input offsets and response time.
Note: To use CxIN+ and CxIN- pins as analog
input, the appropriate bits must be set in
the ANSELx register and the correspond-
ing TRISx bits must also be set to disable
the output drivers.
Note 1: The CxOE bit of the CMxCON0 register
overrides the port data latch. Setting the
CxON bit of the CMxCON0 register has
no impact on the port override.
2: The internal output of the comparator is
latched with each instruction cycle.
Unless otherwise specified, external
outputs are not latched.
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17.2.5 COMPARATOR OUTPUT POLARITY
Inverting the output of the comparator is functionally
equivalent to swapping the comparator inputs. The
polarity of the comparator output can be inverted by
setting the CxPOL bit of the CMxCON0 register.
Clearing the CxPOL bit results in a non-inverted output.
Table 17-2 shows the output state versus input
conditions, including polarity control.
17.2.6 COMPARATOR SPEED/POWER
SELECTION
The trade-off between speed or power can be opti-
mized during program execution with the CxSP control
bit. The default state for this bit is ‘1’, which selects the
Normal Speed mode. Device power consumption can
be optimized at the cost of slower comparator
propagation delay by clearing the CxSP bit to ‘0’.
17.3 Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 17-3. Since the analog input pins share their
connection with a digital input, they have reverse
biased ESD protection diodes to VDD and VSS. The
analog input, therefore, must be between VSS and VDD.
If the input voltage deviates from this range by more
than 0.6V in either direction, one of the diodes is
forward-biased and a latch-up may occur.
A maximum source impedance of 10 k is recommended
for the analog sources. Also, any external component
connected to an analog input pin, such as a capacitor or
a Zener diode, should have very little leakage current to
minimize inaccuracies introduced.
FIGURE 17-3: ANALOG INPUT MODEL
TABLE 17-2: COMPARATOR OUTPUT
STATE VS. INPUT CONDITIONS
Input Condition CxPOL CxOUT
CxVN > CxVP00
CxVN < CxVP01
CxVN > CxVP11
CxVN < CxVP10 Note 1: When reading a PORT register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert as an analog input, according to
the input specification.
2: Analog levels on any pin defined as a
digital input, may cause the input buffer to
consume more current than is specified.
Note 1: See Section 26.0 “Electrical Specifications”.
VA
RS < 10K
VDD
Analog
Input pin
CPIN
5pF VT § 0.6V
VT § 0.6V
ILEAKAGE(1)
VSS
RIC
To Comparator
Legend: CPIN = Input Capacitance
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC = Interconnect Resistance
RS= Source Impedance
VA= Analog Voltage
VT= Threshold Voltage
Rev. 10-000071A
8/2/2013
PIC12(L)F1571/2
DS40001723D-page 150 2013-2015 Microchip Technology Inc.
17.4 Comparator Hysteresis
A selectable amount of separation voltage can be
added to the input pins of each comparator to provide a
hysteresis function to the overall operation. Hysteresis
is enabled by setting the CxHYS bit of the CMxCON0
register.
See Section 26.0 “Electrical Specifications” for
more information.
17.5 Timer1 Gate Operation
The output resulting from a comparator operation can
be used as a source for gate control of Timer1. See
Section 19.5 “Timer1 Gate” for more information.
This feature is useful for timing the duration or interval
of an analog event.
It is recommended that the comparator output be
synchronized to Timer1. This ensures that Timer1 does
not increment while a change in the comparator is
occurring.
17.5.1 COMPARATOR OUTPUT
SYNCHRONIZATION
The output from the Cx comparator can be
synchronized with Timer1 by setting the CxSYNC bit of
the CMxCON0 register.
Once enabled, the comparator output is latched on the
falling edge of the Timer1 source clock. If a prescaler is
used with Timer1, the comparator output is latched after
the prescaling function. To prevent a race condition, the
comparator output is latched on the falling edge of the
Timer1 clock source and Timer1 increments on the
rising edge of its clock source. See the Comparator
Block Diagram (Figure 17-2) and the Timer1 Block
Diagram (Figure 19-1) for more information.
17.6 Comparator Interrupt
An interrupt can be generated upon a change in the out-
put value of the comparator for each comparator, a rising
edge detector and a falling edge detector are present.
When either edge detector is triggered and its associ-
ated enable bit is set (CxINTP and/or CxINTN bits of
the CMxCON1 register), the corresponding interrupt
flag bit (CxIF bit of the PIR2 register) will be set.
To enable the interrupt, you must set the following bits:
• CxON and CxPOL bits of the CMxCON0 register
• CxIE bit of the PIE2 register
• CxINTP bit of the CMxCON1 register (for a rising
edge detection)
• CxINTN bit of the CMxCON1 register (for a falling
edge detection)
• PEIE and GIE bits of the INTCON register
The associated interrupt flag bit, CxIF bit of the PIR2
register, must be cleared in software. If another edge is
detected while this flag is being cleared, the flag will still
be set at the end of the sequence.
17.7 Comparator Response Time
The comparator output is indeterminate for a period of
time after the change of an input source or the selection
of a new reference voltage. This period is referred to as
the response time. The response time of the comparator
differs from the settling time of the voltage reference.
Therefore, both of these times must be considered when
determining the total response time to a comparator
input change. See the Comparator and Voltage
Reference Specifications in Section 26.0 “Electrical
Specifications” for more details.
Note: Although a comparator is disabled, an
interrupt can be generated by changing
the output polarity with the CxPOL bit of
the CMxCON0 register, or by switching
the comparator on or off with the CxON bit
of the CMxCON0 register.
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17.8 Register Definitions: Comparator Control
REGISTER 17-1: CMxCON0: COMPARATOR Cx CONTROL REGISTER 0
R/W-0/0 R-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
CxON CxOUT CxOE CxPOL —CxSP CxHYS CxSYNC
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7 CxON: Comparator Enable bit
1 = Comparator is enabled
0 = Comparator is disabled and consumes no active power
bit 6 CxOUT: Comparator Output bit
If CxPOL = 1 (inverted polarity):
1 = CxVP < CxVN
0 = CxVP > CxVN
If CxPOL = 0 (non-inverted polarity):
1 = CxVP > CxVN
0 = CxVP < CxVN
bit 5 CxOE: Comparator Output Enable bit
1 = CxOUT is present on the CxOUT pin; requires that the associated TRISx bit be cleared to actually
drive the pin, not affected by CxON
0 = CxOUT is internal only
bit 4 CxPOL: Comparator Output Polarity Select bit
1 = Comparator output is inverted
0 = Comparator output is not inverted
bit 3 Unimplemented: Read as ‘0’
bit 2 CxSP: Comparator Speed/Power Select bit
1 = Comparator mode is in Normal Power, Higher Speed mode
0 = Comparator mode is in Low-Power, Low-Speed mode
bit 1 CxHYS: Comparator Hysteresis Enable bit
1 = Comparator hysteresis is enabled
0 = Comparator hysteresis is disabled
bit 0 CxSYNC: Comparator Output Synchronous Mode bit
1 = Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source;
output updated on the falling edge of Timer1 clock source
0 = Comparator output to Timer1 and I/O pin is asynchronous
PIC12(L)F1571/2
DS40001723D-page 152 2013-2015 Microchip Technology Inc.
REGISTER 17-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
CxINTP CxINTN CxPCH<1:0> —CxNCH<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7 CxINTP: Comparator Interrupt on Positive Going Edge Enable bit
1 = The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit
0 = No interrupt flag will be set on a positive going edge of the CxOUT bit
bit 6 CxINTN: Comparator Interrupt on Negative Going Edge Enable bit
1 = The CxIF interrupt flag will be set upon a negative going edge of the CxOUT bit
0 = No interrupt flag will be set on a negative going edge of the CxOUT bit
bit 5-4 CxPCH<1:0>: Comparator Positive Input Channel Select bits
11 = CxVP connects to VSS
10 = CxVP connects to FVR Voltage Reference
01 = CxVP connects to DAC Voltage Reference
00 = CxVP connects to CxIN+ pin
bit 3 Unimplemented: Read as ‘0’
bit 2-0 CxNCH<1:0>: Comparator Negative Input Channel Select bits
111 = CxVN connects to GND
110 = CxVN connects to FVR Voltage Reference
101 = Reserved
100 = Reserved
011 = Reserved
010 = Reserved
001 = CxVN connects to CxIN1- pin
000 = CxVN connects to CxIN0- pin
REGISTER 17-3: CMOUT: COMPARATOR OUTPUT REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0/0
— — — — — — — MC1OUT
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-1 Unimplemented: Read as ‘0’
bit 0 MC1OUT: Mirror Copy of C1OUT bit
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TABLE 17-3: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
ANSELA — — — ANSA4 — ANSA<2:0> 114
CM1CON0 C1ON C1OUT C1OE C1POL — C1SP C1HYS C1SYNC 151
CM1CON1 C1NTP C1INTN C1PCH<1:0> — C1NCH<2:0> 152
CMOUT — — — — — — —MC1OUT152
DAC1CON0 DACEN —DACOE— DACPSS<1:0> — — 145
DAC1CON1 — — — DACR<4:0> 145
FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> ADFVR<1:0> 125
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 74
PIE2 ——C1IE— — — — — 76
PIR2 ——C1IF— — — — — 79
PORTA — — RA5 RA4 RA3 RA<2:0> 113
LATA — — LATA5 LATA4 —LATA<2:0>114
TRISA — — TRISA5 TRISA4 —(1) TRISA<2:0> 113
Legend: — = unimplemented location, read as ‘0’. Shaded cells are unused by the comparator module.
Note 1: Unimplemented, read as ‘1’.
PIC12(L)F1571/2
DS40001723D-page 154 2013-2015 Microchip Technology Inc.
NOTES:
2013-2015 Microchip Technology Inc. DS40001723D-page 155
PIC12(L)F1571/2
18.0 TIMER0 MODULE
The Timer0 module is an 8-bit timer/counter with the
following features:
• 8-Bit Timer/Counter register (TMR0)
• 3-bit prescaler (independent of Watchdog Timer)
• Programmable internal or external clock source
• Programmable external clock edge selection
• Interrupt on overflow
• TMR0 can be used to gate Timer1
Figure 18-1 is a block diagram of the Timer0 module.
18.1 Timer0 Operation
The Timer0 module can be used as either an 8-bit timer
or an 8-bit counter.
18.1.1 8-BIT TIMER MODE
The Timer0 module will increment every instruction
cycle if used without a prescaler. The 8-Bit Timer mode
is selected by clearing the TMR0CS bit of the
OPTION_REG register.
When TMR0 is written, the increment is inhibited for
two instruction cycles immediately following the write.
18.1.2 8-BIT COUNTER MODE
In 8-Bit Counter mode, the Timer0 module will increment
on every rising or falling edge of the T0CKI pin.
In 8-Bit Counter mode, the T0CKI pin is selected by
setting the TMR0CS bit in the OPTION_REG register
to ‘1’.
The rising or falling transition of the incrementing edge
for either input source is determined by the TMR0SE bit
in the OPTION_REG register.
FIGURE 18-1: TIMER0 BLOCK DIAGRAM
Note: The value written to the TMR0 register
can be adjusted in order to account for the
two instruction cycle delay when TMR0 is
written.
Rev. 10-000017A
8/5/2013
TMR0SE
0
1
Fosc/4
Prescaler
T0_overflow
R
write
to
TMR0 set bit
TMR0IF
T0CKI
Sync Circuit
FOSC/2
TMR0CS
T0CKI(1)
Note 1: The T0CKI prescale output frequency should not exceed F
OSC
/8.
PS<2:0>
0
1
PSA
TMR0
Q1
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18.1.3 SOFTWARE PROGRAMMABLE
PRESCALER
A software programmable prescaler is available for
exclusive use with Timer0. The prescaler is enabled by
clearing the PSA bit of the OPTION_REG register.
There are eight prescaler options for the Timer0 module,
ranging from 1:2 to 1:256. The prescale values are
selectable via the PS<2:0> bits of the OPTION_REG
register. In order to have a 1:1 prescaler value for the
Timer0 module, the prescaler must be disabled by
setting the PSA bit of the OPTION_REG register.
The prescaler is not readable or writable. All instructions
writing to the TMR0 register will clear the prescaler.
18.1.4 TIMER0 INTERRUPT
Timer0 will generate an interrupt when the TMR0 register
overflows from FFh to 00h. The TMR0IF interrupt flag bit
of the INTCON register is set every time the TMR0
register overflows, regardless of whether or not the
Timer0 interrupt is enabled. The TMR0IF bit can only be
cleared in software. The Timer0 interrupt enable is the
TMR0IE bit of the INTCON register.
18.1.5 8-BIT COUNTER MODE
SYNCHRONIZATION
When in 8-Bit Counter mode, the incrementing edge on
the T0CKI pin must be synchronized to the instruction
clock. Synchronization can be accomplished by
sampling the prescaler output on the Q2 and Q4 cycles
of the instruction clock. The high and low periods of the
external clocking source must meet the timing
requirements as shown in Section 26.0 “Electrical
Specifications”.
18.1.6 OPERATION DURING SLEEP
Timer0 cannot operate while the processor is in Sleep
mode. The contents of the TMR0 register will remain
unchanged while the processor is in Sleep mode.
Note: The Watchdog Timer (WDT) uses its own
independent prescaler.
Note: The Timer0 interrupt cannot wake the
processor from Sleep since the timer is
frozen during Sleep.
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18.2 Register Definitions: Option Register
TABLE 18-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
REGISTER 18-1: OPTION_REG: OPTION REGISTER
R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7 WPUEN: Weak Pull-Up Enable bit
1 = All weak pull-ups are disabled (except MCLR if it is enabled)
0 = Weak pull-ups are enabled by individual WPUx latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
bit 5 TMR0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (FOSC/4)
bit 4 TMR0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is not assigned to the Timer0 module
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
ADCON2 TRIGSEL<3:0> — — — — 137
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 74
OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS<2:0> 157
TMR0 Holding Register for the 8-bit Timer0 Count 155*
TRISA — — TRISA5 TRISA4 —(1) TRISA2 TRISA1 TRISA0 113
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module.
* Page provides register information.
Note 1: Unimplemented, read as ‘1’.
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
Bit Value Timer0 Rate
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NOTES:
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19.0 TIMER1 MODULE WITH GATE
CONTROL
The Timer1 module is a 16-bit timer/counter with the
following features:
• 16-bit Timer/Counter register pair (TMR1H:TMR1L)
• Programmable internal or external clock source
• 2-bit prescaler
• Optionally synchronized comparator out
• Multiple Timer1 gate (count enable) sources
• Interrupt on overflow
• Wake-up on overflow (external clock,
Asynchronous mode only)
• ADC auto-conversion trigger(s)
• Selectable gate source polarity
• Gate Toggle mode
• Gate Single-Pulse mode
• Gate value status
• Gate event interrupt
Figure 19-1 is a block diagram of the Timer1 module.
FIGURE 19-1: TIMER1 BLOCK DIAGRAM
00
11
10
01
T1G
T0_overflow
C1OUT_sync
Reserved
T1GSS<1:0>
T1GPOL
0
1
Single Pulse
Acq. Control
1
0
T1GSPM
TMR1ON
T1GTM
TMR1GE
TMR1ON
DQ
EN
TMR1LTMR1H
T1_overflow
set flag bit
TMR1IF
TMR1(2)
1
0
Fosc
Internal Clock
Fosc/4
Internal Clock
LFINTOSC
TMR1CS<1:0>
00
11
10
01
Prescaler
1,2,4,8
T1SYNC
Sleep
Input
Fosc/2
Internal
Clock
T1CKPS<1:0>
Synchronized Clock Input
2
det
Synchronize(3)
1: ST Buffer is high speed type when using T1CKI.
2: Timer1 register increments on rising edge.
3: Synchronize does not operate while in Sleep.
(1)
D
QCK
R
Q
Note
T1GGO/DONE
T1CLK
T1CKI
DQ
set bit
TMR1GIF
T1GVAL
Q1
det
Interrupt
Rev. 10-000018D
8/5/2013
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19.1 Timer1 Operation
The Timer1 module is a 16-bit incrementing counter
which is accessed through the TMR1H:TMR1L register
pair. Writes to TMR1H or TMR1L directly update the
counter.
When used with an internal clock source, the module is
a timer and increments on every instruction cycle.
When used with an external clock source, the module
can be used as either a timer or counter and
increments on every selected edge of the external
source.
Timer1 is enabled by configuring the TMR1ON and
TMR1GE bits in the T1CON and T1GCON registers,
respectively. Table 19-1 displays the Timer1 enable
selections.
19.2 Clock Source Selection
The TMR1CS<1:0> bits of the T1CON register are used
to select the clock source for Timer1. Tabl e 19-2
displays the clock source selections.
19.2.1 INTERNAL CLOCK SOURCE
When the internal clock source is selected, the
TMR1H:TMR1L register pair will increment on multiples
of FOSC, as determined by the Timer1 prescaler.
When the FOSC internal clock source is selected, the
Timer1 register value will increment by four counts every
instruction clock cycle. Due to this condition, a 2 LSB
error in resolution will occur when reading the Timer1
value. To utilize the full resolution of Timer1, an
asynchronous input signal must be used to gate the
Timer1 clock input.
The following asynchronous sources may be used:
• Asynchronous event on the T1G pin to Timer1 gate
• C1 or C2 comparator input to Timer1 gate
19.2.2 EXTERNAL CLOCK SOURCE
When the external clock source is selected, the Timer1
module may work as a timer or a counter.
When enabled to count, Timer1 is incremented on the ris-
ing edge of the external clock input T1CKI. The external
clock source can be synchronized to the microcontroller
system clock or it can run asynchronously.
TABLE 19-1: TIMER1 ENABLE
SELECTIONS
TMR1ON TMR1GE Timer1
Operation
00Off
01Off
10Always On
11Count Enabled
Note: In Counter mode, a falling edge must be
registered by the counter prior to the first
incrementing rising edge after any one or
more of the following conditions:
• Timer1 enabled after POR
• Write to TMR1H or TMR1L
• Timer1 is disabled
• Timer1 is disabled (TMR1ON = 0)
when T1CKI is high, then Timer1 is
enabled (TMR1ON = 1) when T1CKI
is low
TABLE 19-2: CLOCK SOURCE SELECTIONS
TMR1CS<1:0> T1OSCEN(1) Clock Source
11 x LFINTOSC
10 x External Clocking on T1CKI Pin
01 x System Clock (FOSC)
00 x Instruction Clock (FOSC/4)
Note 1: T1OSCEN is not available for these devices.
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19.3 Timer1 Prescaler
Timer1 has four prescaler options, allowing 1, 2, 4 or 8
divisions of the clock input. The T1CKPSx bits of the
T1CON register control the prescale counter. The
prescale counter is not directly readable or writable;
however, the prescaler counter is cleared upon a write to
TMR1H or TMR1L.
19.4 Timer1 Operation in
Asynchronous Counter Mode
If control bit, T1SYNC, of the T1CON register is set,
the external clock input is not synchronized. The timer
increments asynchronously to the internal phase
clocks. If the external clock source is selected then the
timer will continue to run during Sleep and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in
software are needed to read/write the timer (see
Section 19.4.1 “Reading and Writing Timer1 in
Asynchronous Counter Mode”).
19.4.1 READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will ensure a valid
read (taken care of in hardware). However, the user
should keep in mind that reading the 16-bit timer in two
8-bit values itself, poses certain problems, since the
timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
contention may occur by writing to the timer registers,
while the register is incrementing. This may produce an
unpredictable value in the TMR1H:TMR1L register pair.
19.5 Timer1 Gate
Timer1 can be configured to count freely or the count
can be enabled and disabled using Timer1 gate
circuitry. This is also referred to as Timer1 Gate Enable.
Timer1 gate can also be driven by multiple selectable
sources.
19.5.1 TIMER1 GATE ENABLE
The Timer1 Gate Enable mode is enabled by setting
the TMR1GE bit of the T1GCON register. The polarity
of the Timer1 Gate Enable mode is configured using
the T1GPOL bit of the T1GCON register.
When Timer1 Gate Enable mode is enabled, Timer1
will increment on the rising edge of the Timer1 clock
source. When Timer1 Gate Enable mode is disabled,
no incrementing will occur and Timer1 will hold the
current count. See Figure 19-3 for timing details.
19.5.2 TIMER1 GATE SOURCE
SELECTION
Timer1 gate source selections are shown in Table 19-4.
Source selection is controlled by the T1GSS<1:0> bits
of the T1GCON register. The polarity for each available
source is also selectable. Polarity selection is controlled
by the T1GPOL bit of the T1GCON register.
TABLE 19-4: TIMER1 GATE SOURCES
Note: When switching from synchronous to
asynchronous operation, it is possible to
skip an increment. When switching from
asynchronous to synchronous operation,
it is possible to produce an additional
increment.
TABLE 19-3: TIMER1 GATE ENABLE
SELECTIONS
T1CLK T1GPOL T1G Timer1 Operation
00Counts
01Holds Count
10Holds Count
11Counts
T1GSS<1:0> Timer1 Gate Source
00 Timer1 Gate Pin (T1G)
01 Overflow of Timer0 (T0_overflow)
(TMR0 increments from FFh to 00h)
10 Comparator 1 Output (C1OUT_sync)(1)
11 Reserved
Note 1: Optionally synchronized comparator output.
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19.5.2.1 T1G Pin Gate Operation
The T1G pin is one source for Timer1 gate control. It
can be used to supply an external source to the Timer1
gate circuitry.
19.5.2.2 Timer0 Overflow Gate Operation
When Timer0 increments from FFh to 00h, a low-to-
high pulse will automatically be generated and
internally supplied to the Timer1 gate circuitry.
19.5.3 TIMER1 GATE TOGGLE MODE
When Timer1 Gate Toggle mode is enabled, it is
possible to measure the full cycle length of a Timer1 gate
signal, as opposed to the duration of a single level pulse.
The Timer1 gate source is routed through a flip-flop that
changes state on every incrementing edge of the
signal. See Figure 19-4 for timing details.
Timer1 Gate Toggle mode is enabled by setting the
T1GTM bit of the T1GCON register. When the T1GTM
bit is cleared, the flip-flop is cleared and held clear. This
is necessary in order to control which edge is measured.
19.5.4 TIMER1 GATE SINGLE-PULSE MODE
When Timer1 Gate Single-Pulse mode is enabled, it is
possible to capture a single-pulse gate event. Timer1
Gate Single-Pulse mode is first enabled by setting the
T1GSPM bit in the T1GCON register. Next, the T1GGO/
DONE bit in the T1GCON register must be set. The
Timer1 will be fully enabled on the next incrementing
edge. On the next trailing edge of the pulse, the T1GGO/
DONE bit will automatically be cleared. No other gate
events will be allowed to increment Timer1 until the
T1GGO/DONE bit is once again set in software. See
Figure 19-5 for timing details.
If the Single-Pulse Gate mode is disabled by clearing the
T1GSPM bit in the T1GCON register, the T1GGO/DONE
bit should also be cleared.
Enabling the Toggle mode and the Single-Pulse mode
simultaneously will permit both sections to work
together. This allows the cycle times on the Timer1 gate
source to be measured. See Figure 19-6 for timing
details.
19.5.5 TIMER1 GATE VALUE STATUS
When Timer1 gate value status is utilized, it is possible
to read the most current level of the gate control value.
The value is stored in the T1GVAL bit in the T1GCON
register. The T1GVAL bit is valid even when the Timer1
gate is not enabled (TMR1GE bit is cleared).
19.5.6 TIMER1 GATE EVENT INTERRUPT
When Timer1 gate event interrupt is enabled, it is pos-
sible to generate an interrupt upon the completion of a
gate event. When the falling edge of T1GVAL occurs,
the TMR1GIF flag bit in the PIR1 register will be set. If
the TMR1GIE bit in the PIE1 register is set, then an
interrupt will be recognized.
The TMR1GIF flag bit operates even when the Timer1
gate is not enabled (TMR1GE bit is cleared).
Note: Enabling Toggle mode at the same time
as changing the gate polarity may result in
indeterminate operation.
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19.6 Timer1 Interrupt
The Timer1 register pair (TMR1H:TMR1L) increments
to FFFFh and rolls over to 0000h. When Timer1 rolls
over, the Timer1 interrupt flag bit of the PIR1 register is
set. To enable the interrupt on rollover, you must set
these bits:
• TMR1ON bit of the T1CON register
• TMR1IE bit of the PIE1 register
• PEIE bit of the INTCON register
• GIE bit of the INTCON register
The interrupt is cleared by clearing the TMR1IF bit in
the Interrupt Service Routine.
19.7 Timer1 Operation During Sleep
Timer1 can only operate during Sleep when set up in
Asynchronous Counter mode. In this mode, an external
crystal or clock source can be used to increment the
counter. To set up the timer to wake the device:
• TMR1ON bit of the T1CON register must be set
• TMR1IE bit of the PIE1 register must be set
• PEIE bit of the INTCON register must be set
• T1SYNC bit of the T1CON register must be set
• TMR1CS bits of the T1CON register must be
configured
The device will wake-up on an overflow and execute
the next instructions. If the GIE bit of the INTCON
register is set, the device will call the Interrupt Service
Routine.
Timer1 oscillator will continue to operate in Sleep
regardless of the T1SYNC bit setting.
19.7.1 ALTERNATE PIN LOCATIONS
This module incorporates I/O pins that can be moved to
other locations with the use of the Alternate Pin Func-
tion register, APFCON. To determine which pins can be
moved and what their default locations are upon a
Reset, see Section 11.1 “Alternate Pin Function” for
more information.
FIGURE 19-2: TIMER1 INCREMENTING EDGE
Note: The TMR1H:TMR1L register pair and the
TMR1IF bit should be cleared before
enabling interrupts.
T1CKI = 1
when TMR1
is Enabled
T1CKI = 0
when TMR1
is Enabled
Note 1: Arrows indicate counter increments.
2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising
edge of the clock.
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FIGURE 19-3: TIMER1 GATE ENABLE MODE
FIGURE 19-4: TIMER1 GATE TOGGLE MODE
TMR1GE
T1GPOL
t1g_in
T1CKI
T1GVAL
Timer1 N N + 1 N + 2 N + 3 N + 4
TMR1GE
T1GPOL
T1GTM
t1g_in
T1CKI
T1GVAL
Timer1 N
N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8
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FIGURE 19-5: TIMER1 GATE SINGLE-PULSE MODE
TMR1GE
T1GPOL
t1g_in
T1CKI
T1GVAL
Timer1 N N + 1 N + 2
T1GSPM
T1GGO/
DONE Set by Software
Cleared by Hardware on
Falling Edge of T1GVAL
Set by Hardware on
Falling Edge of T1GVAL
Cleared by Software Cleared by
Software
TMR1GIF
Counting Enabled on
Rising Edge of T1G
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FIGURE 19-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE
TMR1GE
T1GPOL
t1g_in
T1CKI
T1GVAL
Timer1 NN + 1N + 2
T1GSPM
T1GGO/
DONE Set by Software
Cleared by Hardware on
Falling Edge of T1GVAL
Set by Hardware on
Falling Edge of T1GVAL
Cleared by Software Cleared by
Software
TMR1GIF
T1GTM
Counting Enabled on
Rising Edge of T1G
N + 4N + 3
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19.8 Register Definitions: Timer1 Control
REGISTER 19-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0/u R/W-0/u R/W-0/u R/W-0/u U-0 R/W-0/u U-0 R/W-0/u
TMR1CS<1:0> T1CKPS<1:0> — T1SYNC —TMR1ON
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-6 TMR1CS<1:0>: Timer1 Clock Source Select bits
11 = Timer1 clock source is the LFINTOSC
10 = Timer1 clock source is the T1CKI pin (on the rising edge)
01 = Timer1 clock source is the system clock (FOSC)
00 = Timer1 clock source is the instruction clock (FOSC/4)
bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3 Unimplemented: Read as ‘0’
bit 2 T1SYNC: Timer1 Synchronization Control bit
1 = Does not synchronize the asynchronous clock input
0 = Synchronizes the asynchronous clock input with the system clock (FOSC)
bit 1 Unimplemented: Read as ‘0’
bit 0 TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1 and clears Timer1 gate flip-flop
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REGISTER 19-2: T1GCON: TIMER1 GATE CONTROL REGISTER
R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x R/W-0/u R/W-0/u
TMR1GE T1GPOL T1GTM T1GSPM T1GGO/
DONE
T1GVAL T1GSS<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit HC = Hardware Clearable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7 TMR1GE: Timer1 Gate Enable bit
If TMR1ON = 0:
This bit is ignored.
If TMR1ON = 1:
1 = Timer1 counting is controlled by the Timer1 gate function
0 = Timer1 counts regardless of Timer1 gate function
bit 6 T1GPOL: Timer1 Gate Polarity bit
1 = Timer1 gate is active-high (Timer1 counts when gate is high)
0 = Timer1 gate is active-low (Timer1 counts when gate is low)
bit 5 T1GTM: Timer1 Gate Toggle Mode bit
1 = Timer1 Gate Toggle mode is enabled
0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared
Timer1 gate flip-flop toggles on every rising edge.
bit 4 T1GSPM: Timer1 Gate Single-Pulse Mode bit
1 = Timer1 Gate Single-Pulse mode is enabled and is controlling Timer1 gate
0 = Timer1 Gate Single-Pulse mode is disabled
bit 3 T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit
1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge
0 = Timer1 gate single-pulse acquisition has completed or has not been started
bit 2 T1GVAL: Timer1 Gate Value Status bit
Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L. Unaffected
by Timer1 Gate Enable bit (TMR1GE).
bit 1-0 T1GSS<1:0>: Timer1 Gate Source Select bits
11 = Reserved
10 = Comparator 1 optionally synchronized output (C1OUT_sync)
01 = Timer0 overflow output (T0_overflow)
00 = Timer1 gate pin (T1G)
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TABLE 19-5: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
ANSELA — — — ANSA4 —ANSA<2:0> 114
APFCON RXDTSEL CWGASEL CWGBSEL — T1GSEL TXCKSEL P2SEL P1SEL 110
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 74
OSCSTAT —PLLROSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS 56
PIE1 TMR1GIE ADIE RCIE(2) TXIE(2) — — TMR2IE TMR1IE 75
PIR1 TMR1GIF ADIF RCIF(2) TXIF(2) — — TMR2IF TMR1IF 79
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Count 163*
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Count 163*
TRISA —— TRISA<5:4> —(1) TRISA<2:0> 113
T1CON TMR1CS<1:0> T1CKPS<1:0> — T1SYNC —TMR1ON167
T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/
DONE
T1GVAL T1GSS<1:0> 168
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the Timer1 module.
* Page provides register information.
Note 1: Unimplemented, read as ‘1’.
2: PIC12(L)F1572 only.
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20.0 TIMER2 MODULE
The Timer2 module incorporates the following features:
• 8-Bit Timer and Period registers (TMR2 and PR2,
respectively)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4, 1:16
and 1:64)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR2 match with PR2
See Figure 20-1 for a block diagram of Timer2.
FIGURE 20-1: TIMER2 BLOCK DIAGRAM
FIGURE 20-2: TIMER2 TIMING DIAGRAM
Prescaler
1:1, 1:4, 1:16, 1:64
Fosc/4
2
T2CKPS<1:0> Comparator Postscaler
1:1 to 1:16
4
T2OUTPS<3:0>
set bit
TMR2IF
TMR2 R
PR2
T2_match To Peripherals
Rev. 10-000019A
7/30/2013
0x03
0x00 0x01 0x02 0x03 0x00 0x01 0x02
1:4
Pulse Width(1)
Note 1: The Pulse Width of T2_match is equal to the scaled input of TMR2.
FOSC/4
Prescale
PR2
TMR2
T2_match
Rev. 10-000020A
7/30/2013
PIC12(L)F1571/2
DS40001723D-page 172 2013-2015 Microchip Technology Inc.
20.1 Timer2 Operation
The clock input to the Timer2 module is the system
instruction clock (FOSC/4).
TMR2 increments from 00h on each clock edge.
A 4-bit counter/prescaler on the clock input allows direct
input, divide-by-4 and divide-by-16 prescale options.
These options are selected by the prescaler control bits,
T2CKPS<1:0> of the T2CON register. The value of
TMR2 is compared to that of the Period register, PR2, on
each clock cycle. When the two values match, the
comparator generates a match signal as the timer
output. This signal also resets the value of TMR2 to 00h
on the next cycle and drives the output counter/
postscaler (see Section 20.2 “Timer2 Interrupt”).
The TMR2 and PR2 registers are both directly readable
and writable. The TMR2 register is cleared on any
device Reset, whereas the PR2 register initializes to
FFh. Both the prescaler and postscaler counters are
cleared on the following events:
• A write to the TMR2 register
• A write to the T2CON register
• Power-on Reset (POR)
• Brown-out Reset (BOR)
•MCLR
Reset
• Watchdog Timer (WDT) Reset
• Stack Overflow Reset
• Stack Underflow Reset
•RESET Instruction
20.2 Timer2 Interrupt
Timer2 can also generate an optional device interrupt.
The Timer2 output signal (T2_match) provides the input
for the 4-bit counter/postscaler. This counter generates
the TMR2 match interrupt flag which is latched in
TMR2IF of the PIR1 register. The interrupt is enabled by
setting the TMR2 Match Interrupt Enable bit, TMR2IE of
the PIE1 register.
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS<3:0>, of the T2CON register.
20.3 Timer2 Output
The output of TMR2 is T2_match.
The T2_match signal is synchronous with the system
clock. Figure 20-3 shows two examples of the timing of
the T2_match signal relative to FOSC and prescale
value, T2CKPS<1:0>. The upper diagram illustrates 1:1
prescale timing and the lower diagram, 1:X prescale
timing.
FIGURE 20-3: T2_MATCH TIMING
DIAGRAM
20.4 Timer2 Operation During Sleep
Timer2 cannot be operated while the processor is in
Sleep mode. The contents of the TMR2 and PR2
registers will remain unchanged while the processor is
in Sleep mode.
Note: TMR2 is not cleared when T2CON is
written.
T2_match
FOSC/4
TMR2 = PR2
match
TMR2 = 0
...
PRESCALE = 1:X
(T2CKPS<1:0>=01,10,11)
TCY1TCY2TCYX
...
...
Q1 Q2 Q3
FOSC
TMR2 = PR2
match
TMR2 = 0
Q1Q4
T2_match
FOSC/4
PRESCALE = 1:1
(T2CKPS<1:0>=00)
TCY1
Rev. 10-000021A
7/30/2013
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20.5 Register Definitions: Timer2 Control
TABLE 20-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2
REGISTER 20-1: T2CON: TIMER2 CONTROL REGISTER
U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
— T2OUTPS<3:0> TMR2ON T2CKPS<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7 Unimplemented: Read as ‘0’
bit 6-3 T2OUTPS<3:0>: Timer2 Output Postscaler Select bits
0000 = 1:1 Postscaler
0001 = 1:2 Postscaler
0010 = 1:3 Postscaler
0011 = 1:4 Postscaler
0100 = 1:5 Postscaler
0101 = 1:6 Postscaler
0110 = 1:7 Postscaler
0111 = 1:8 Postscaler
1000 = 1:9 Postscaler
1001 = 1:10 Postscaler
1010 = 1:11 Postscaler
1011 = 1:12 Postscaler
1100 = 1:13 Postscaler
1101 = 1:14 Postscaler
1110 = 1:15 Postscaler
1111 = 1:16 Postscaler
bit 2 TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
10 = Prescaler is 16
11 = Prescaler is 64
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 74
PIE1 TMR1GIE ADIE RCIE(1) TXIE(1) ——TMR2IETMR1IE 75
PIR1 TMR1GIF ADIF RCIF(1) TXIF(1) ——TMR2IFTMR1IF 78
PR2 Timer2 Module Period Register 171*
T2CON — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> 173
TMR2 Holding Register for the 8-bit TMR2 Count 171*
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2 module.
* Page provides register information.
Note 1: PIC12(L)F1572 only.
PIC12(L)F1571/2
DS40001723D-page 174 2013-2015 Microchip Technology Inc.
NOTES:
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PIC12(L)F1571/2
21.0 ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
The Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module is a serial I/O
communications peripheral. It contains all the clock
generators, shift registers and data buffers necessary
to perform an input or output serial data transfer, inde-
pendent of device program execution. The EUSART,
also known as a Serial Communications Interface
(SCI), can be configured as a full-duplex asynchronous
system or half-duplex synchronous system.
Full-Duplex mode is useful for communications with
peripheral systems, such as CRT terminals and per-
sonal computers. Half-Duplex Synchronous mode is
intended for communications with peripheral devices,
such as A/D or D/A integrated circuits, serial EEPROMs
or other microcontrollers. These devices typically do not
have internal clocks for baud rate generation and require
the external clock signal provided by a master
synchronous device.
The EUSART module includes the following capabilities:
• Full-duplex asynchronous transmit and receive
• Two-character input buffer
• One-character output buffer
• Programmable 8-bit or 9-bit character length
• Address detection in 9-bit mode
• Input buffer overrun error detection
• Received character framing error detection
• Half-duplex synchronous master
• Half-duplex synchronous slave
• Programmable clock polarity in synchronous
modes
• Sleep operation
The EUSART module implements the following
additional features, making it ideally suited for use in
Local Interconnect Network (LIN) bus systems:
• Automatic detection and calibration of the baud rate
• Wake-up on Break reception
• 13-bit Break character transmit
Block diagrams of the EUSART transmitter and
receiver are shown in Figure 21-1 and Figure 21-2.
FIGURE 21-1: EUSART TRANSMIT BLOCK DIAGRAM
TXREG register
8
Pin Buffer
and Control
TXIF
TRMT
TX9D
Data bus
8TXIE
Interrupt
TX/CK
TX9
TXEN
Transmit Shift Register (TSR)
(8) 0
MSb LSb
÷ n
Multiplier x4
SYNC
BRGH
BRG16
x16 x64
1
1
1
1
1
x
x
x0
0
0
0
0
0
0
n
+ 1
SPBRGH SPBRGL
Baud Rate Generator FOSC
BRG16
Rev. 10-000113B
7/14/2015
PIC12(L)F1571/2
DS40001723D-page 176 2013-2015 Microchip Technology Inc.
FIGURE 21-2: EUSART RECEIVE BLOCK DIAGRAM
The operation of the EUSART module is controlled
through three registers:
• Transmit Status and Control (TXSTA)
• Receive Status and Control (RCSTA)
• Baud Rate Control (BAUDCON)
These registers are detailed in Register 21-1,
Register 21-2 and Register 21-3, respectively.
When the receiver or transmitter section is not enabled,
then the corresponding RX or TX pin may be used for
general purpose input and output.
÷n
Multiplier x4
SYNC
BRGH
BRG16
x16 x64
1
1
1
1
1
x
x
x0
0
0
0
0
0
0
n
+1
SPBRGH SPBRGL
Baud Rate Generator FOSC
BRG16
SPEN
CREN OERR RCIDL
Pin Buffer
and Control
Data
Recovery
RX/DT pin
Stop (8) 7 Start01
MSb LSb
RSR Register
RX9
FERR RX9D RCREG Register
FIFO
8
Data Bus
RCIE
RCIF Interrupt
Rev. 10-000114A
7/30/2013
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PIC12(L)F1571/2
21.1 EUSART Asynchronous Mode
The EUSART transmits and receives data using the
standard Non-Return-to-Zero (NRZ) format. NRZ is
implemented with two levels: a VOH mark state which
represents a ‘1’ data bit, and a VOL space state which
represents a ‘0’ data bit. NRZ refers to the fact that con-
secutively transmitted data bits of the same value stay
at the output level of that bit without returning to a neutral
level between each bit transmission. An NRZ transmis-
sion port Idles in the mark state. Each character
transmission consists of one Start bit, followed by eight
or nine data bits and is always terminated by one or
more Stop bits. The Start bit is always a space and the
Stop bits are always marks. The most common data for-
mat is eight bits. Each transmitted bit persists for a
period of 1/(Baud Rate). An on-chip dedicated
8-bit/16-bit Baud Rate Generator is used to derive
standard baud rate frequencies from the system
oscillator. See Table 21-5 for examples of baud rate
configurations.
The EUSART transmits and receives the LSb first. The
EUSART’s transmitter and receiver are functionally
independent, but share the same data format and baud
rate. Parity is not supported by the hardware, but can be
implemented in software and stored as the ninth data bit.
21.1.1 EUSART ASYNCHRONOUS
TRANSMITTER
The EUSART transmitter block diagram is shown in
Figure 21-1. The heart of the transmitter is the serial
Transmit Shift Register (TSR), which is not directly
accessible by software. The TSR obtains its data from
the transmit buffer, which is the TXREG register.
21.1.1.1 Enabling the Transmitter
The EUSART transmitter is enabled for asynchronous
operations by configuring the following three control bits:
•TXEN = 1
• SYNC = 0
• SPEN = 1
All other EUSART control bits are assumed to be in
their default state.
Setting the TXEN bit of the TXSTA register enables the
transmitter circuitry of the EUSART. Clearing the SYNC
bit of the TXSTA register configures the EUSART for
asynchronous operation. Setting the SPEN bit of the
RCSTA register enables the EUSART and automatically
configures the TX/CK I/O pin as an output. If the TX/CK
pin is shared with an analog peripheral, the analog I/O
function must be disabled by clearing the corresponding
ANSELx bit.
21.1.1.2 Transmitting Data
A transmission is initiated by writing a character to the
TXREG register. If this is the first character, or the previ-
ous character has been completely flushed from the
TSR, the data in the TXREG is immediately transferred
to the TSR register. If the TSR still contains all or part of
a previous character, the new character data is held in
the TXREG until the Stop bit of the previous character
has been transmitted. The pending character in the
TXREG is then transferred to the TSR in one TCY
immediately following the Stop bit transmission. The
transmission of the Start bit, data bits and Stop bit
sequence commences immediately following the
transfer of the data to the TSR from the TXREG.
21.1.1.3 Transmit Data Polarity
The polarity of the transmit data can be controlled with
the SCKP bit of the BAUDCON register. The default
state of this bit is ‘0’ which selects high true transmit Idle
and data bits. Setting the SCKP bit to ‘1’ will invert the
transmit data resulting in low true Idle and data bits. The
SCKP bit controls transmit data polarity in Asynchro-
nous mode only. In Synchronous mode, the SCKP bit
has a different function. See Section 21.5.1.2 “Clock
Polarity”.
21.1.1.4 Transmit Interrupt Flag
The TXIF interrupt flag bit of the PIR1 register is set
whenever the EUSART transmitter is enabled and no
character is being held for transmission in the TXREG.
In other words, the TXIF bit is only clear when the TSR
is busy with a character and a new character has been
queued for transmission in the TXREG. The TXIF flag bit
is not cleared immediately upon writing TXREG. TXIF
becomes valid in the second instruction cycle following
the write execution. Polling TXIF immediately following
the TXREG write will return invalid results. The TXIF bit
is read-only, it cannot be set or cleared by software.
The TXIF interrupt can be enabled by setting the TXIE
interrupt enable bit of the PIE1 register. However, the
TXIF flag bit will be set whenever the TXREG is empty,
regardless of the state of the TXIE enable bit.
To use interrupts when transmitting data, set the TXIE
bit only when there is more data to send. Clear the
TXIE interrupt enable bit upon writing the last character
of the transmission to the TXREG.
Note: The TXIF transmitter interrupt flag is set
when the TXEN enable bit is set.
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21.1.1.5 TSR Status
The TRMT bit of the TXSTA register indicates the
status of the TSR register. This is a read-only bit. The
TRMT bit is set when the TSR register is empty and is
cleared when a character is transferred to the TSR
register from the TXREG. The TRMT bit remains clear
until all bits have been shifted out of the TSR register.
No interrupt logic is tied to this bit, so the user has to
poll this bit to determine the TSR status.
21.1.1.6 Transmitting 9-Bit Characters
The EUSART supports 9-bit character transmissions.
When the TX9 bit of the TXSTA register is set, the
EUSART will shift nine bits out for each character trans-
mitted. The TX9D bit of the TXSTA register is the ninth
and Most Significant data bit. When transmitting 9-bit
data, the TX9D data bit must be written before writing
the eight Least Significant bits into the TXREG. All nine
bits of data will be transferred to the TSR register
immediately after the TXREG is written.
A special 9-Bit Address mode is available for use with
multiple receivers. See Section 21.1.2.7 “Address
Detection” for more information on this mode.
21.1.1.7 Asynchronous Transmission Setup
1. Initialize the SPBRGH/SPBRGL register pair,
and the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 21.4 “EUSART
Baud Rate Generator (BRG)”).
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
3. If 9-bit transmission is desired, set the TX9 con-
trol bit. A set ninth data bit will indicate that the
eight Least Significant data bits are an address
when the receiver is set for address detection.
4. Set the SCKP bit if inverted transmit is desired.
5. Enable the transmission by setting the TXEN
control bit. This will cause the TXIF interrupt bit
to be set.
6. If interrupts are desired, set the TXIE interrupt
enable bit of the PIE1 register. An interrupt will
occur immediately provided that the GIE and
PEIE bits of the INTCON register are also set.
7. If 9-bit transmission is selected, the ninth bit
should be loaded into the TX9D data bit.
8. Load 8-bit data into the TXREG register. This
will start the transmission.
FIGURE 21-3: ASYNCHRONOUS TRANSMISSION
FIGURE 21-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Note: The TSR register is not mapped in data
memory, so it is not available to the user.
Word 1
Word 1
Transmit Shift Reg.
Start bit bit 0 bit 1 bit 7/8
Write to TXREG
BRG Output
(Shift Clock)
TX/CK Pin
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
1 TCY
Word 1
Stop bit
Transmit Shift Reg.
Write to TXREG
BRG Output
(Shift Clock)
TX/CK Pin
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1 Word 2
Word 1 Word 2
Start bit Stop bit Start bit
Transmit Shift Reg.
Word 1 Word 2
bit 0 bit 1 bit 7/8 bit 0
Note: This timing diagram shows two consecutive transmissions.
1 TCY
1 TCY
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
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TABLE 21-1: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
BAUDCON ABDOVF RCIDL — SCKP BRG16 —WUE ABDEN 186
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 74
PIE1 TMR1GIE ADIE RCIE(1) TXIE(1) — — TMR2IE TMR1IE 75
PIR1 TMR1GIF ADIF RCIF(1) TXIF(1) — — TMR2IF TMR1IF 78
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 185*
SPBRGL BRG<7:0> 187*
SPBRGH BRG<15:8> 187*
TXREG EUSART Transmit Data Register 177
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 184
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for asynchronous transmission.
* Page provides register information.
Note 1: PIC12(L)F1572 only.
PIC12(L)F1571/2
DS40001723D-page 180 2013-2015 Microchip Technology Inc.
21.1.2 EUSART ASYNCHRONOUS
RECEIVER
The Asynchronous mode is typically used in RS-232
systems. The receiver block diagram is shown in
Figure 21-2. The data is received on the RX/DT pin and
drives the data recovery block. The data recovery block
is actually a high-speed shifter operating at 16 times
the baud rate, whereas the serial Receive Shift
Register (RSR) operates at the bit rate. When all eight
or nine bits of the character have been shifted in, they
are immediately transferred to a two character
First-In-First-Out (FIFO) memory. The FIFO buffering
allows reception of two complete characters and the
start of a third character before software must start ser-
vicing the EUSART receiver. The FIFO and RSR regis-
ters are not directly accessible by software. Access to
the received data is via the RCREG register.
21.1.2.1 Enabling the Receiver
The EUSART receiver is enabled for asynchronous
operation by configuring the following three control bits:
• CREN = 1
• SYNC = 0
• SPEN = 1
All other EUSART control bits are assumed to be in
their default state.
Setting the CREN bit of the RCSTA register enables the
receiver circuitry of the EUSART. Clearing the SYNC bit
of the TXSTA register configures the EUSART for asyn-
chronous operation. Setting the SPEN bit of the RCSTA
register enables the EUSART. The programmer must
set the corresponding TRIS bit to configure the RX/DT
I/O pin as an input.
21.1.2.2 Receiving Data
The receiver data recovery circuit initiates character
reception on the falling edge of the first bit. The first bit,
also known as the Start bit, is always a zero. The data
recovery circuit counts one-half bit time to the center of
the Start bit and verifies that the bit is still a zero. If it is
not a zero then the data recovery circuit aborts charac-
ter reception, without generating an error, and resumes
looking for the falling edge of the Start bit. If the Start bit
zero verification succeeds, then the data recovery
circuit counts a full bit time to the center of the next bit.
The bit is then sampled by a majority detect circuit and
the resulting ‘0’ or ‘1’ is shifted into the RSR. This
repeats until all data bits have been sampled and
shifted into the RSR. One final bit time is measured and
the level sampled. This is the Stop bit, which is always
a ‘1’. If the data recovery circuit samples a ‘0’ in the
Stop bit position then a framing error is set for this char-
acter; otherwise, the framing error is cleared for this
character. See Section 21.1.2.4 “Receive Framing
Error” for more information on framing errors.
Immediately after all data bits and the Stop bit have
been received, the character in the RSR is transferred
to the EUSART receive FIFO and the RCIF interrupt
flag bit of the PIR1 register is set. The top character in
the FIFO is transferred out of the FIFO by reading the
RCREG register.
21.1.2.3 Receive Interrupts
The RCIF interrupt flag bit of the PIR1 register is set
whenever the EUSART receiver is enabled and there is
an unread character in the receive FIFO. The RCIF
interrupt flag bit is read-only, it cannot be set or cleared
by software.
RCIF interrupts are enabled by setting all of the
following bits:
• RCIE, Interrupt Enable bit of the PIE1 register
• PEIE, Peripheral Interrupt Enable bit of the
INTCON register
• GIE, Global Interrupt Enable bit of the INTCON
register
The RCIF interrupt flag bit will be set when there is an
unread character in the FIFO, regardless of the state of
interrupt enable bits.
Note: If the RX/DT function is on an analog pin,
the corresponding ANSELx bit must be
cleared for the receiver to function.
Note: If the receive FIFO is overrun, no
additional characters will be received
until the overrun condition is cleared. See
Section 21.1.2.5 “Receive Overrun
Error” for more information on overrun
errors.
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21.1.2.4 Receive Framing Error
Each character in the receive FIFO buffer has a
corresponding framing error status bit. A framing error
indicates that a Stop bit was not seen at the expected
time. The framing error status is accessed via the
FERR bit of the RCSTA register. The FERR bit rep-
resents the status of the top unread character in the
receive FIFO. Therefore, the FERR bit must be read
before reading the RCREG.
The FERR bit is read-only and only applies to the top
unread character in the receive FIFO. A framing error
(FERR = 1) does not preclude reception of additional
characters. It is not necessary to clear the FERR bit.
Reading the next character from the FIFO buffer will
advance the FIFO to the next character and the next
corresponding framing error.
The FERR bit can be forced clear by clearing the SPEN
bit of the RCSTA register which resets the EUSART.
Clearing the CREN bit of the RCSTA register does not
affect the FERR bit. A framing error by itself does not
generate an interrupt.
21.1.2.5 Receive Overrun Error
The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its
entirety, is received before the FIFO is accessed. When
this happens the OERR bit of the RCSTA register is set.
The characters already in the FIFO buffer can be read,
but no additional characters will be received until the
error is cleared. The error must be cleared by either
clearing the CREN bit of the RCSTA register or by
resetting the EUSART by clearing the SPEN bit of the
RCSTA register.
21.1.2.6 Receiving 9-Bit Characters
The EUSART supports 9-bit character reception. When
the RX9 bit of the RCSTA register is set, the EUSART
will shift nine bits into the RSR for each character
received. The RX9D bit of the RCSTA register is the
ninth and Most Significant data bit of the top unread
character in the receive FIFO. When reading 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the eight Least Significant bits
from the RCREG.
21.1.2.7 Address Detection
A special Address Detection mode is available for use
when multiple receivers share the same transmission
line, such as in RS-485 systems. Address detection is
enabled by setting the ADDEN bit of the RCSTA
register.
Address detection requires 9-bit character reception.
When address detection is enabled, only characters
with the ninth data bit set will be transferred to the
receive FIFO buffer, thereby setting the RCIF interrupt
bit. All other characters will be ignored.
Upon receiving an address character, user software
determines if the address matches its own. Upon
address match, user software must disable address
detection by clearing the ADDEN bit before the next
Stop bit occurs. When user software detects the end of
the message, determined by the message protocol
used, software places the receiver back into the
Address Detection mode by setting the ADDEN bit.
Note: If all receive characters in the receive
FIFO have framing errors, repeated reads
of the RCREG will not clear the FERR bit.
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21.1.2.8 Asynchronous Reception Setup
1. Initialize the SPBRGH, SPBRGL register pair
and the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 21.4 “EUSART
Baud Rate Generator (BRG)”).
2. Clear the ANSELx bit for the RX pin (if applicable).
3. Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
4. If interrupts are desired, set the RCIE bit of the
PIE1 register, and the GIE and PEIE bits of the
INTCON register.
5. If 9-bit reception is desired, set the RX9 bit.
6. Enable reception by setting the CREN bit.
7. The RCIF interrupt flag bit will be set when a
character is transferred from the RSR to the
receive buffer. An interrupt will be generated if
the RCIE interrupt enable bit was also set.
8. Read the RCSTA register to get the error flags
and, if 9-bit data reception is enabled, the ninth
data bit.
9. Get the received eight Least Significant data bits
from the receive buffer by reading the RCREG
register.
10. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
21.1.2.9 9-Bit Address Detection Mode Setup
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1. Initialize the SPBRGH/SPBRGL register pair,
and the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 21.4 “EUSART
Baud Rate Generator (BRG)”).
2. Clear the ANSELx bit for the RX pin (if applicable).
3. Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
4. If interrupts are desired, set the RCIE bit of the
PIE1 register, and the GIE and PEIE bits of the
INTCON register.
5. Enable 9-bit reception by setting the RX9 bit.
6. Enable address detection by setting the ADDEN
bit.
7. Enable reception by setting the CREN bit.
8. The RCIF interrupt flag bit will be set when a
character with the ninth bit set is transferred
from the RSR to the receive buffer. An interrupt
will be generated if the RCIE interrupt enable bit
was also set.
9. Read the RCSTA register to get the error flags.
The ninth data bit will always be set.
10. Get the received eight Least Significant data bits
from the receive buffer by reading the RCREG
register. Software determines if this is the
device’s address.
11. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
12. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and generate interrupts.
FIGURE 21-5: ASYNCHRONOUS RECEPTION
Start
bit bit 7/8
bit 1bit 0 bit 7/8 bit 0Stop
bit
Start
bit bit 7/8
RX/DT Pin
Rcv Buffer Reg.
Rcv Shift Reg.
Read Rcv
Buffer Reg. (RCREG)
RCIF
(Interrupt Flag)
OERR bit
CREN
Word 1
RCREG
Word 2
RCREG
Stop
bit
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
RCIDL
Stop
bit
Start
bit
2013-2015 Microchip Technology Inc. DS40001723D-page 183
PIC12(L)F1571/2
TABLE 21-2: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
21.2 Clock Accuracy with
Asynchronous Operation
The factory calibrates the Internal Oscillator Block
(INTOSC) output. However, the INTOSC frequency
may drift as VDD or temperature changes, and this
directly affects the asynchronous baud rate.
The Auto-Baud Detect feature (see Section 21.4.1
“Auto-Baud Detect”) can be used to compensate for
changes in the INTOSC frequency.
There may not be fine enough resolution when
adjusting the Baud Rate Generator to compensate for
a gradual change in the peripheral clock frequency.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
BAUDCON ABDOVF RCIDL —SCKP BRG16 —WUEABDEN 186
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 74
PIE1 TMR1GIE ADIE RCIE(1) TXIE(1) — — TMR2IE TMR1IE 75
PIR1 TMR1GIF ADIF RCIF(1) TXIF(1) — — TMR2IF TMR1IF 78
RCREG EUSART Receive Data Register 180*
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 185*
SPBRGL BRG<7:0> 187*
SPBRGH BRG<15:8> 187*
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 184
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for asynchronous reception.
* Page provides register information.
Note 1: PIC12(L)F1572 only.
PIC12(L)F1571/2
DS40001723D-page 184 2013-2015 Microchip Technology Inc.
21.3 Register Definitions: EUSART Control
REGISTER 21-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-1/1 R/W-0/0
CSRC TX9 TXEN(1) SYNC SENDB BRGH TRMT TX9D
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7 CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care.
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
bit 6 TX9: 9-Bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5 TXEN: Transmit Enable bit(1)
1 = Transmit is enabled
0 = Transmit is disabled
bit 4 SYNC: EUSART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3 SENDB: Send Break Character bit
Asynchronous mode:
1 = Sends Sync Break on next transmission (cleared by hardware upon completion)
0 = Sync Break transmission completed
Synchronous mode:
Don’t care.
bit 2 BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode.
bit 1 TRMT: Transmit Shift Register Status bit
1 = TSR is empty
0 = TSR is full
bit 0 TX9D: Ninth bit of Transmit Data
Can be address/data bit or a parity bit.
Note 1: SREN/CREN overrides TXEN in Sync mode.
2013-2015 Microchip Technology Inc. DS40001723D-page 185
PIC12(L)F1571/2
REGISTER 21-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7 SPEN: Serial Port Enable bit
1 = Serial port is enabled (configures RX/DT and TX/CK pins as serial port pins)
0 = Serial port is disabled (held in Reset)
bit 6 RX9: 9-Bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care.
Synchronous mode – Master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave:
Don’t care.
bit 4 CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables receiver
0 = Disables receiver
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3 ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set
0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 8-bit (RX9 = 0):
Don’t care.
bit 2 FERR: Framing Error bit
1 = Framing error (can be updated by reading RCREG register and receiving next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (can be cleared by clearing bit, CREN)
0 = No overrun error
bit 0 RX9D: Ninth Bit of Received Data bit
This can be address/data bit or a parity bit and must be calculated by user firmware.
PIC12(L)F1571/2
DS40001723D-page 186 2013-2015 Microchip Technology Inc.
REGISTER 21-3: BAUDCON: BAUD RATE CONTROL REGISTER
R-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0
ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7 ABDOVF: Auto-Baud Detect Overflow bit
Asynchronous mode:
1 = Auto-baud timer overflowed
0 = Auto-baud timer did not overflow
Synchronous mode:
Don’t care.
bit 6 RCIDL: Receive Idle Flag bit
Asynchronous mode:
1 = Receiver is Idle
0 = Start bit has been received and the receiver is receiving
Synchronous mode:
Don’t care.
bit 5 Unimplemented: Read as ‘0’
bit 4 SCKP: Synchronous Clock Polarity Select bit
Asynchronous mode:
1 = Transmits inverted data to the TX/CK pin
0 = Transmits non-inverted data to the TX/CK pin
Synchronous mode:
1 = Data is clocked on rising edge of the clock
0 = Data is clocked on falling edge of the clock
bit 3 BRG16: 16-Bit Baud Rate Generator bit
1 = 16-bit Baud Rate Generator is used
0 = 8-bit Baud Rate Generator is used
bit 2 Unimplemented: Read as ‘0’
bit 1 WUE: Wake-up Enable bit
Asynchronous mode:
1 = Receiver is waiting for a falling edge; no character will be received, RCIF bit will be set, WUE will
automatically clear after RCIF is set
0 = Receiver is operating normally
Synchronous mode:
Don’t care
bit 0 ABDEN: A.uto-Baud Detect Enable bit
Asynchronous mode:
1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete)
0 = Auto-Baud Detect mode is disabled
Synchronous mode:
Don’t care.
2013-2015 Microchip Technology Inc. DS40001723D-page 187
PIC12(L)F1571/2
21.4 EUSART Baud Rate Generator
(BRG)
The Baud Rate Generator (BRG) is an 8-bit or 16-bit
timer that is dedicated to the support of both the asyn-
chronous and synchronous EUSART operation. By
default, the BRG operates in 8-bit mode. Setting the
BRG16 bit of the BAUDCON register selects 16-bit
mode.
The SPBRGH/SPBRGL register pair determines the
period of the free-running baud rate timer. In Asynchro-
nous mode, the multiplier of the baud rate period is
determined by both the BRGH bit of the TXSTA register
and the BRG16 bit of the BAUDCON register. In
Synchronous mode, the BRGH bit is ignored.
Table 21-3 contains the formulas for determining the
baud rate. Example 21-1 provides a sample calculation
for determining the baud rate and baud rate error.
Typical baud rates and error values for various
Asynchronous modes have been computed for your
convenience and are shown in Table 21-3. It may be
advantageous to use the high baud rate (BRGH = 1) or
the 16-bit BRG (BRG16 = 1) to reduce the baud rate
error. The 16-bit BRG mode is used to achieve slow
baud rates for fast oscillator frequencies.
Writing a new value to the SPBRGH/SPBRGL register
pair causes the BRG timer to be reset (or cleared). This
ensures that the BRG does not wait for a timer overflow
before outputting the new baud rate.
If the system clock is changed during an active receive
operation, a receive error or data loss may result. To
avoid this problem, check the status of the RCIDL bit to
make sure that the receive operation is Idle before
changing the system clock.
EXAMPLE 21-1: CALCULATING BAUD
RATE ERROR
For a device with FOSC of 16 MHz, desired baud rate
of 9600, Asynchronous mode, 8-bit BRG:
Solving for SPBRGH:SPBRGL:
X
FOSC
Desired Ba ud R at e
---------------------------------------------
64
--------------------------------------------- 1–=
Desired Baud Rate FOSC
64 [SPBRGH:SPBRGL] 1+
------------------------------------------------------------------------=
16000000
9600
------------------------
64
------------------------1–=
25.04225==
Calculated Baud Rate 16000000
64 25 1+
---------------------------=
9615=
Error Calc. Bau d Rate Desired Baud Rate –
Desired Baud Rate
--------------------------------------------------------------------------------------------=
9615 9600–
9600
---------------------------------- 0. 16%==
PIC12(L)F1571/2
DS40001723D-page 188 2013-2015 Microchip Technology Inc.
TABLE 21-3: BAUD RATE FORMULAS
TABLE 21-4: SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
Configuration Bits
BRG/EUSART Mode Baud Rate Formula
SYNC BRG16 BRGH
000 8-bit/Asynchronous FOSC/[64 (n+1)]
001 8-bit/Asynchronous FOSC/[16 (n+1)]
010 16-bit/Asynchronous
011 16-bit/Asynchronous
FOSC/[4 (n+1)]10x 8-bit/Synchronous
11x 16-bit/Synchronous
Legend: x = Don’t care; n = value of SPBRGH/SPBRGL register pair.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
BAUDCON ABDOVF RCIDL —SCKP BRG16 —WUE ABDEN 186
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 185
SPBRGL BRG<7:0> 187*
SPBRGH BRG<15:8> 187*
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 184
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for the Baud Rate Generator.
* Page provides register information.
2013-2015 Microchip Technology Inc. DS40001723D-page 189
PIC12(L)F1571/2
TABLE 21-5: BAUD RATES FOR ASYNCHRONOUS MODES
BAUD
RATE
SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz
Actual
Rate
%
Error
SPBRG
Value
(decimal)
Actual
Rate
%
Error
SPBRG
Value
(decimal)
Actual
Rate
%
Error
SPBRG
Value
(decimal)
Actual
Rate
%
Error
SPBRG
Value
(decimal)
300—— — —— — —— — —— —
1200 1221 1.73 255 1200 0.00 239 1202 0.16 207 1200 0.00 143
2400 2404 0.16 129 2400 0.00 119 2404 0.16 103 2400 0.00 71
9600 9470 -1.36 32 9600 0.00 29 9615 0.16 25 9600 0.00 17
10417 10417 0.00 29 10286 -1.26 27 10417 0.00 23 10165 -2.42 16
19.2k 19.53k 1.73 15 19.20k 0.00 14 19.23k 0.16 12 19.20k 0.00 8
57.6k — — — 57.60k 0.00 7 — — — 57.60k 0.00 2
115.2k — — — — — — — — — — — —
BAUD
RATE
SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
Actual
Rate
%
Error
SPBRG
Value
(decimal)
Actual
Rate
%
Error
SPBRG
Value
(decimal)
Actual
Rate
%
Error
SPBRG
Value
(decimal)
Actual
Rate
%
Error
SPBRG
Value
(decimal)
300 — — — 300 0.16 207 300 0.00 191 300 0.16 51
1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12
2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 — — —
9600 9615 0.16 12 — — — 9600 0.00 5 — — —
10417 10417 0.00 11 10417 0.00 5 — — — — — —
19.2k — — — — — — 19.20k 0.00 2 — — —
57.6k — — — — — — 57.60k 0.00 0 — — —
115.2k — — — — — — — — — — — —
BAUD
RATE
SYNC = 0, BRGH = 1, BRG16 = 0
FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz
Actual
Rate
%
Error
SPBRG
Value
(decimal)
Actual
Rate
%
Error
SPBRG
Value
(decimal)
Actual
Rate
%
Error
SPBRG
Value
(decimal)
Actual
Rate
%
Error
SPBRG
Value
(decimal)
300—— — —— — —— — —— —
1200 — — — — — — — — — — — —
2400 — — — — — — — — — — — —
9600 9615 0.16 129 9600 0.00 119 9615 0.16 103 9600 0.00 71
10417 10417 0.00 119 10378 -0.37 110 10417 0.00 95 10473 0.53 65
19.2k 19.23k 0.16 64 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35
57.6k 56.82k -1.36 21 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11
115.2k 113.64k -1.36 10 115.2k 0.00 9 111.1k -3.55 8 115.2k 0.00 5
PIC12(L)F1571/2
DS40001723D-page 190 2013-2015 Microchip Technology Inc.
BAUD
RATE
SYNC = 0, BRGH = 1, BRG16 = 0
FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
Actual
Rate
%
Error
SPBRG
Value
(decimal)
Actual
Rate
%
Error
SPBRG
Value
(decimal)
Actual
Rate
%
Error
SPBRG
Value
(decimal)
Actual
Rate
%
Error
SPBRG
Value
(decimal)
300 — — — — — — — — — 300 0.16 207
1200 — — — 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — —
57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —
115.2k — — — — — — 115.2k 0.00 1 — — —
BAUD
RATE
SYNC = 0, BRGH = 0, BRG16 = 1
FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz
Actual
Rate
%
Error
SPBRG
Value
(decimal)
Actual
Rate
%
Error
SPBRG
Value
(decimal)
Actual
Rate
%
Error
SPBRG
Value
(decimal)
Actual
Rate
%
Error
SPBRG
Value
(decimal)
300 300.0 -0.01 4166 300.0 0.00 3839 300.03 0.01 3332 300.0 0.00 2303
1200 1200 -0.03 1041 1200 0.00 959 1200.5 0.04 832 1200 0.00 575
2400 2399 -0.03 520 2400 0.00 479 2398 -0.08 416 2400 0.00 287
9600 9615 0.16 129 9600 0.00 119 9615 0.16 103 9600 0.00 71
10417 10417 0.00 119 10378 -0.37 110 10417 0.00 95 10473 0.53 65
19.2k 19.23k 0.16 64 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35
57.6k 56.818 -1.36 21 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11
115.2k 113.636 -1.36 10 115.2k 0.00 9 111.11k -3.55 8 115.2k 0.00 5
BAUD
RATE
SYNC = 0, BRGH = 0, BRG16 = 1
FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
Actual
Rate
%
Error
SPBRG
Value
(decimal)
Actual
Rate
%
Error
SPBRG
Value
(decimal)
Actual
Rate
%
Error
SPBRG
Value
(decimal)
Actual
Rate
%
Error
SPBRG
Value
(decimal)
300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207
1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — —
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 — — —
57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — —
115.2k — — — — — — 115.2k 0.00 1 — — —
TABLE 21-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
2013-2015 Microchip Technology Inc. DS40001723D-page 191
PIC12(L)F1571/2
BAUD
RATE
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 16.000 MHz FOSC = 11.0592 MHz
Actual
Rate
%
Error
SPBRG
Value
(decimal)
Actual
Rate
%
Error
SPBRG
Value
(decimal)
Actual
Rate
%
Error
SPBRG
Value
(decimal)
Actual
Rate
%
Error
SPBRG
Value
(decimal)
300 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 13332 300.0 0.00 9215
1200 1200 -0.01 4166 1200 0.00 3839 1200.1 0.01 3332 1200 0.00 2303
2400 2400 0.02 2082 2400 0.00 1919 2399.5 -0.02 1666 2400 0.00 1151
9600 9597 -0.03 520 9600 0.00 479 9592 -0.08 416 9600 0.00 287
10417 10417 0.00 479 10425 0.08 441 10417 0.00 383 10433 0.16 264
19.2k 19.23k 0.16 259 19.20k 0.00 239 19.23k 0.16 207 19.20k 0.00 143
57.6k 57.47k -0.22 86 57.60k 0.00 79 57.97k 0.64 68 57.60k 0.00 47
115.2k 116.3k 0.94 42 115.2k 0.00 39 114.29k -0.79 34 115.2k 0.00 23
BAUD
RATE
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
Actual
Rate
%
Error
SPBRG
Value
(decimal)
Actual
Rate
%
Error
SPBRG
Value
(decimal)
Actual
Rate
%
Error
SPBRG
Value
(decimal)
Actual
Rate
%
Error
SPBRG
Value
(decimal)
300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832
1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207
2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103
9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25
10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23
19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12
57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 — — —
115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 — — —
TABLE 21-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
PIC12(L)F1571/2
DS40001723D-page 192 2013-2015 Microchip Technology Inc.
21.4.1 AUTO-BAUD DETECT
The EUSART module supports automatic detection
and calibration of the baud rate.
In the Auto-Baud Detect (ABD) mode, the clock to the
BRG is reversed. Rather than the BRG clocking the
incoming RX signal, the RX signal is timing the BRG.
The Baud Rate Generator is used to time the period of
a received 55h (ASCII “U”), which is the Sync character
for the LIN bus. The unique feature of this character is
that it has five rising edges, including the Stop bit edge.
Setting the ABDEN bit of the BAUDCON register starts
the auto-baud calibration sequence (Figure 21-6).
While the ABD sequence takes place, the EUSART
state machine is held in Idle. On the first rising edge of
the receive line, after the Start bit, the SPBRG begins
counting up using the BRG counter clock as shown in
Table 21-6. The fifth rising edge will occur on the RX pin
at the end of the eighth bit period. At that time, an
accumulated value totaling the proper BRG period is
left in the SPBRGH/SPBRGL register pair, the ABDEN
bit is automatically cleared and the RCIF interrupt flag
is set. The value in the RCREG needs to be read to
clear the RCIF interrupt. RCREG content should be
discarded. When calibrating for modes that do not use
the SPBRGH register, the user can verify that the
SPBRGL register did not overflow by checking for 00h
in the SPBRGH register.
The BRG auto-baud clock is determined by the BRG16
and BRGH bits, as shown in Table 21-6 . During ABD,
both the SPBRGH and SPBRGL registers are used as
a 16-bit counter, independent of the BRG16 bit setting.
While calibrating the baud rate period, the SPBRGH
and SPBRGL registers are clocked at 1/8th the BRG
base clock rate. The resulting byte measurement is the
average bit time when clocked at full speed.
TABLE 21-6: BRG COUNTER CLOCK RATES
FIGURE 21-6: AUTOMATIC BAUD RATE CALIBRATION
Note 1: If the WUE bit is set with the ABDEN bit,
Auto-Baud Detection will occur on the
byte following the Break character
(see Section 21.4.3 “Auto-Wake-up on
Break”).
2: It is up to the user to determine that the
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible.
3: During the auto-baud process, the
auto-baud counter starts counting at 1.
Upon completion of the auto-baud
sequence, to achieve maximum accuracy,
subtract 1 from the SPBRGH:SPBRGL
register pair.
BRG16 BRGH BRG Base
Clock
BRG ABD
Clock
00FOSC/64 FOSC/512
01FOSC/16 FOSC/128
10FOSC/16 FOSC/128
11 FOSC/4 FOSC/32
Note: During the ABD sequence, the SPBRGL
and SPBRGH registers are both used as a
16-bit counter, independent of the BRG16
setting.
BRG Value
RX Pin
ABDEN bit
RCIF bit
bit 0 bit 1
(Interrupt)
Read
RCREG
BRG Clock
Start
Auto Cleared
Set by User
XXXXh 0000h
Edge #1
bit 2 bit 3
Edge #2
bit 4 bit 5
Edge #3
bit 6 bit 7
Edge #4
Stop bit
Edge #5
001Ch
Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.
SPBRGL XXh 1Ch
SPBRGH XXh 00h
RCIDL
2013-2015 Microchip Technology Inc. DS40001723D-page 193
PIC12(L)F1571/2
21.4.2 AUTO-BAUD OVERFLOW
During the course of Automatic Baud Detection, the
ABDOVF bit of the BAUDCON register will be set if the
baud rate counter overflows before the fifth rising edge
is detected on the RX pin. The ABDOVF bit indicates
that the counter has exceeded the maximum count that
can fit in the 16 bits of the SPBRGH:SPBRGL register
pair. The overflow condition will set the RCIF flag. The
counter continues to count until the fifth rising edge is
detected on the RX pin. The RCIDL bit will remain false
(‘0’) until the fifth rising edge, at which time, the RDICL
bit will set. If the RCREG is read after the overflow
occurs, but before the fifth rising edge, the fifth rising
edge will set the RCIF again.
Terminating the auto-baud process early to clear an
overflow condition will prevent proper detection of the
Sync character fifth rising edge. If any falling edges of
the Sync character have not yet occurred when the
ABDEN bit is cleared, then those will be falsely
detected as Start bits. The following steps are
recommended to clear the overflow condition:
1. Read RCREG to clear RCIF.
2. If RCIDL is zero, then wait for RCIF and repeat
Step 1.
3. Clear the ABDOVF bit.
21.4.3 AUTO-WAKE-UP ON BREAK
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the Baud Rate Generator
is inactive and a proper character reception cannot be
performed. The auto-wake-up feature allows the
controller to wake-up due to activity on the RX/DT line.
This feature is available only in Asynchronous mode.
The auto-wake-up feature is enabled by setting the WUE
bit of the BAUDCON register. Once set, the normal
receive sequence on RX/DT is disabled, and the
EUSART remains in an Idle state, monitoring for a
wake-up event independent of the CPU mode. A
wake-up event consists of a high-to-low transition on the
RX/DT line. (This coincides with the start of a Sync Break
or a wake-up signal character for the LIN protocol.)
The EUSART module generates an RCIF interrupt
coincident with the wake-up event. The interrupt is
generated synchronously to the Q clocks in normal CPU
operating modes (Figure 21-7), and asynchronously if
the device is in Sleep mode (Figure 21-8). The interrupt
condition is cleared by reading the RCREG register.
The WUE bit is automatically cleared by the low-to-high
transition on the RX line at the end of the Break. This
signals to the user that the Break event is over. At this
point, the EUSART module is in Idle mode waiting to
receive the next character.
21.4.3.1 Special Considerations
Break Character
To avoid character errors or character fragments during
a wake-up event, the wake-up character must be all
zeros.
When the wake-up is enabled, the function works
independent of the low time on the data stream. If the
WUE bit is set and a valid non-zero character is
received, the low time from the Start bit to the first rising
edge will be interpreted as the wake-up event. The
remaining bits in the character will be received as a
fragmented character and subsequent characters can
result in framing or overrun errors.
Therefore, the initial character in the transmission must
be all ‘0’s. This must be ten or more bit times; 13-bit
times are recommended for LIN bus or any number of
bit times for standard RS-232 devices.
Oscillator Start-up Time
Oscillator start-up time must be considered, especially
in applications using oscillators with longer start-up
intervals (i.e., LP, XT or HS/PLL mode). The Sync
Break (or wake-up signal) character must be of
sufficient length, and be followed by a sufficient
interval, to allow enough time for the selected oscillator
to start and provide proper initialization of the EUSART.
WUE Bit
The wake-up event causes a receive interrupt by
setting the RCIF bit. The WUE bit is cleared in
hardware by a rising edge on RX/DT. The interrupt
condition is then cleared in software by reading the
RCREG register and discarding its contents.
To ensure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process
before setting the WUE bit. If a receive operation is not
occurring, the WUE bit may then be set just prior to
entering the Sleep mode.
PIC12(L)F1571/2
DS40001723D-page 194 2013-2015 Microchip Technology Inc.
FIGURE 21-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION
FIGURE 21-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2Q3 Q4 Q1 Q2 Q3 Q4
OSC1
WUE bit
RX/DT
RCIF
Note 1: The EUSART remains in Idle while the WUE bit is set.
Line
Bit Set by User
Cleared due to User Read of RCREG
Auto-Cleared
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
Q4
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
WUE bit
RX/DT
RCIF
Auto Cleared
Cleared due to User Read of RCREG
Sleep Command Executed
Note 1
Note 1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal
is still active. This sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.
Sleep Ends
Line
Bit Set by User
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21.4.4 BREAK CHARACTER SEQUENCE
The EUSART module has the capability of sending the
special Break character sequences that are required by
the LIN bus standard. A Break character consists of a
Start bit, followed by twelve ‘0’ bits and a Stop bit.
To send a Break character, set the SENDB and TXEN
bits of the TXSTA register. The Break character trans-
mission is then initiated by a write to the TXREG. The
value of data written to TXREG will be ignored and all
‘0’s will be transmitted.
The SENDB bit is automatically reset by hardware after
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte
following the Break character (typically, the Sync
character in the LIN specification).
The TRMT bit of the TXSTA register indicates when the
transmit operation is active or idle, just as it does during
normal transmission. See Figure 21-9 for the timing of
the Break character sequence.
21.4.4.1 Break and Sync Transmit Sequence
The following sequence will start a message frame
header made up of a Break, followed by an auto-baud
Sync byte. This sequence is typical of a LIN bus master.
1. Configure the EUSART for the desired mode.
2. Set the TXEN and SENDB bits to enable the
Break sequence.
3. Load the TXREG with a dummy character to
initiate transmission (the value is ignored).
4. Write ‘55h’ to TXREG to load the Sync character
into the transmit FIFO buffer.
5. After the Break has been sent, the SENDB bit is
reset by hardware and the Sync character is
then transmitted.
When the TXREG becomes empty, as indicated by the
TXIF, the next data byte can be written to TXREG.
21.4.5 RECEIVING A BREAK CHARACTER
The Enhanced USART module can receive a Break
character in two ways.
The first method to detect a Break character uses the
FERR bit of the RCSTA register and the received data
as indicated by RCREG. The Baud Rate Generator is
assumed to have been initialized to the expected baud
rate.
A Break character has been received when:
• RCIF bit is set
• FERR bit is set
• RCREG = 00h
The second method uses the auto-wake-up feature
described in Section 21.4.3 “Auto-Wake-up on
Break”. By enabling this feature, the EUSART will
sample the next two transitions on RX/DT, cause an
RCIF interrupt and receive the next data byte followed
by another interrupt.
Note that following a Break character, the user will
typically want to enable the Auto-Baud Detect feature.
For both methods, the user can set the ABDEN bit of
the BAUDCON register before placing the EUSART in
Sleep mode.
FIGURE 21-9: SEND BREAK CHARACTER SEQUENCE
Write to TXREG
BRG Output
(Shift Clock)
Start bit bit 0 bit 1 bit 11 Stop bit
Break
TXIF bit
(Transmit
Interrupt Flag)
TX (pin)
TRMT bit
(Transmit Shift
Empty Flag)
SENDB
(send Break
control bit)
SENDB Sampled Here Auto Cleared
Dummy Write
PIC12(L)F1571/2
DS40001723D-page 196 2013-2015 Microchip Technology Inc.
21.5 EUSART Synchronous Mode
Synchronous serial communications are typically used
in systems with a single master and one or more
slaves. The master device contains the necessary
circuitry for baud rate generation and supplies the clock
for all devices in the system. Slave devices can take
advantage of the master clock by eliminating the
internal clock generation circuitry.
There are two signal lines in Synchronous mode: a
bidirectional data line and a clock line. Slaves use the
external clock supplied by the master to shift the serial
data into and out of their respective Receive and Trans-
mit Shift registers. Since the data line is bidirectional,
synchronous operation is half-duplex only. Half-duplex
refers to the fact that master and slave devices can
receive and transmit data but not both simultaneously.
The EUSART can operate as either a master or slave
device.
Start and Stop bits are not used in synchronous
transmissions.
21.5.1 SYNCHRONOUS MASTER MODE
The following bits are used to configure the EUSART
for synchronous master operation:
• SYNC = 1
• CSRC = 1
• SREN = 0 (for transmit); SREN = 1 (for receive)
• CREN = 0 (for transmit); CREN = 1 (for receive)
• SPEN = 1
Setting the SYNC bit of the TXSTA register configures
the device for synchronous operation. Setting the CSRC
bit of the TXSTA register configures the device as a
master. Clearing the SREN and CREN bits of the RCSTA
register ensures that the device is in the Transmit mode,
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the
EUSART.
21.5.1.1 Master Clock
Synchronous data transfers use a separate clock line,
which is synchronous with the data. A device config-
ured as a master transmits the clock on the TX/CK line.
The TX/CK pin output driver is automatically enabled
when the EUSART is configured for synchronous
transmit or receive operation. Serial data bits change
on the leading edge to ensure they are valid at the trail-
ing edge of each clock. One clock cycle is generated
for each data bit. Only as many clock cycles are
generated as there are data bits.
21.5.1.2 Clock Polarity
A clock polarity option is provided for Microwire
compatibility. Clock polarity is selected with the SCKP
bit of the BAUDCON register. Setting the SCKP bit sets
the clock Idle state as high. When the SCKP bit is set,
the data changes on the falling edge of each clock.
Clearing the SCKP bit sets the Idle state as low. When
the SCKP bit is cleared, the data changes on the rising
edge of each clock.
21.5.1.3 Synchronous Master Transmission
Data is transferred out of the device on the RX/DT pin.
The RX/DT and TX/CK pin output drivers are automat-
ically enabled when the EUSART is configured for
synchronous master transmit operation.
A transmission is initiated by writing a character to the
TXREG register. If the TSR still contains all or part of a
previous character the new character data is held in the
TXREG until the last bit of the previous character has
been transmitted. If this is the first character, or the
previous character has been completely flushed from
the TSR, the data in the TXREG is immediately trans-
ferred to the TSR. The transmission of the character
commences immediately following the transfer of the
data to the TSR from the TXREG.
Each data bit changes on the leading edge of the
master clock and remains valid until the subsequent
leading clock edge.
21.5.1.4 Synchronous Master Transmission
Setup
1. Initialize the SPBRGH, SPBRGL register pair
and the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 21.4 “EUSART
Baud Rate Generator (BRG)”).
2. Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
3. Disable Receive mode by clearing bits, SREN
and CREN.
4. Enable Transmit mode by setting the TXEN bit.
5. If 9-bit transmission is desired, set the TX9 bit.
6. If interrupts are desired, set the TXIE bit of the
PIE1 register, and the GIE and PEIE bits of the
INTCON register.
7. If 9-bit transmission is selected, the ninth bit
should be loaded in the TX9D bit.
8. Start transmission by loading data to the TXREG
register.
Note: The TSR register is not mapped in data
memory, so it is not available to the user.
2013-2015 Microchip Technology Inc. DS40001723D-page 197
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FIGURE 21-10: SYNCHRONOUS TRANSMISSION
FIGURE 21-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
TABLE 21-7: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER
TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
BAUDCON ABDOVF RCIDL — SCKP BRG16 —WUE ABDEN 186
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 74
PIE1 TMR1GIE ADIE RCIE(1) TXIE(1) — — TMR2IE TMR1IE 75
PIR1 TMR1GIF ADIF RCIF(1) TXIF(1) — — TMR2IF TMR1IF 78
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 185
SPBRGL BRG<7:0> 187*
SPBRGH BRG<15:8> 187*
TXREG EUSART Transmit Data Register 177*
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 184
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous master transmission.
* Page provides register information.
Note 1: PIC12(L)F1572 only.
bit 0 bit 1 bit 7
Word 1
bit 2 bit 0 bit 1 bit 7
RX/DT
Write to
TXREG Reg
TXIF bit
(Interrupt Flag)
TXEN bit
‘1’‘1’
Word 2
TRMT bit
Write Word 1 Write Word 2
Note: Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words.
Pin
TX/CK Pin
TX/CK Pin
(SCKP =
0
)
(SCKP =
1
)
RX/DT Pin
TX/CK Pin
Write to
TXREG Reg.
TXIF bit
TRMT bit
bit 0 bit 1 bit 2 bit 6 bit 7
TXEN bit
PIC12(L)F1571/2
DS40001723D-page 198 2013-2015 Microchip Technology Inc.
21.5.1.5 Synchronous Master Reception
Data is received at the RX/DT pin. The RX/DT pin
output driver is automatically disabled when the
EUSART is configured for synchronous master receive
operation.
In Synchronous mode, reception is enabled by setting
either the Single Receive Enable bit (SREN of the
RCSTA register) or the Continuous Receive Enable bit
(CREN of the RCSTA register).
When SREN is set and CREN is clear, only as many
clock cycles are generated as there are data bits in a
single character. The SREN bit is automatically cleared
at the completion of one character. When CREN is set,
clocks are continuously generated until CREN is
cleared. If CREN is cleared in the middle of a character,
the CK clock stops immediately and the partial charac-
ter is discarded. If SREN and CREN are both set, then
SREN is cleared at the completion of the first character
and CREN takes precedence.
To initiate reception, set either SREN or CREN. Data is
sampled at the RX/DT pin on the trailing edge of the
TX/CK clock pin and is shifted into the Receive Shift
Register (RSR). When a complete character is
received into the RSR, the RCIF bit is set and the char-
acter is automatically transferred to the two-character
receive FIFO. The Least Significant eight bits of the top
character in the receive FIFO are available in RCREG.
The RCIF bit remains set as long as there are unread
characters in the receive FIFO.
21.5.1.6 Slave Clock
Synchronous data transfers use a separate clock line,
which is synchronous with the data. A device configured
as a slave receives the clock on the TX/CK line. The
TX/CK pin output driver is automatically disabled when
the device is configured for synchronous slave transmit
or receive operation. Serial data bits change on the
leading edge to ensure they are valid at the trailing edge
of each clock. One data bit is transferred for each clock
cycle. Only as many clock cycles should be received as
there are data bits.
21.5.1.7 Receive Overrun Error
The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its
entirety, is received before RCREG is read to access
the FIFO. When this happens, the OERR bit of the
RCSTA register is set. Previous data in the FIFO will
not be overwritten. The two characters in the FIFO
buffer can be read, however, no additional characters
will be received until the error is cleared. The OERR bit
can only be cleared by clearing the overrun condition.
If the overrun error occurred when the SREN bit is set
and CREN is clear, then the error is cleared by reading
RCREG. If the overrun occurred when the CREN bit is
set, then the error condition is cleared by either clearing
the CREN bit of the RCSTA register or by clearing the
SPEN bit which resets the EUSART.
21.5.1.8 Receiving 9-Bit Characters
The EUSART supports 9-bit character reception. When
the RX9 bit of the RCSTA register is set the EUSART
will shift 9 bits into the RSR for each character
received. The RX9D bit of the RCSTA register is the
ninth, and Most Significant, data bit of the top unread
character in the receive FIFO. When reading 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the eight Least Significant bits
from the RCREG.
21.5.1.9 Synchronous Master Reception Setup
1. Initialize the SPBRGH/SPBRGL register pair for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
2. Clear the ANSELx bit for the RX pin (if applicable).
3. Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
4. Ensure bits, CREN and SREN, are clear.
5. If interrupts are desired, set the RCIE bit of the
PIE1 register, and the GIE and PEIE bits of the
INTCON register.
6. If 9-bit reception is desired, set bit, RX9.
7. Start reception by setting the SREN bit or for
continuous reception, set the CREN bit.
8. Interrupt flag bit, RCIF, will be set when recep-
tion of a character is complete. An interrupt will
be generated if the enable bit, RCIE, was set.
9. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
10. Read the 8-bit received data by reading the
RCREG register.
11. If an overrun error occurs, clear the error by either
clearing the CREN bit of the RCSTA register or by
clearing the SPEN bit which resets the EUSART.
Note: If the RX/DT function is on an analog pin,
the corresponding ANSELx bit must be
cleared for the receiver to function.
Note: If the device is configured as a slave and
the TX/CK function is on an analog pin, the
corresponding ANSELx bit must be
cleared.
2013-2015 Microchip Technology Inc. DS40001723D-page 199
PIC12(L)F1571/2
FIGURE 21-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
TABLE 21-8: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER
RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
BAUDCON ABDOVF RCIDL — SCKP BRG16 —WUE ABDEN 186
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 74
PIE1 TMR1GIE ADIE RCIE(1) TXIE(1) — — TMR2IE TMR1IE 75
PIR1 TMR1GIF ADIF RCIF(1) TXIF(1) — — TMR2IF TMR1IF 78
RCREG EUSART Receive Data Register 180*
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 185
SPBRGL BRG<7:0> 187*
SPBRGH BRG<15:8> 187*
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 184
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous master reception.
* Page provides register information.
Note 1: PIC12(L)F1572 only.
CREN bit
RX/DT
Write to
SREN bit
SREN bit
RCIF bit
(Interrupt)
Read
RCREG
‘0’
bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
‘0’
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TX/CK Pin
TX/CK Pin
Pin
(SCKP = 0)
(SCKP = 1)
PIC12(L)F1571/2
DS40001723D-page 200 2013-2015 Microchip Technology Inc.
21.5.2 SYNCHRONOUS SLAVE MODE
The following bits are used to configure the EUSART
for synchronous slave operation:
• SYNC = 1
• CSRC = 0
• SREN = 0 (for transmit); SREN = 1 (for receive)
• CREN = 0 (for transmit); CREN = 1 (for receive)
• SPEN = 1
Setting the SYNC bit of the TXSTA register configures the
device for synchronous operation. Clearing the CSRC bit
of the TXSTA register configures the device as a slave.
Clearing the SREN and CREN bits of the RCSTA register
ensures that the device is in Transmit mode; otherwise,
the device will be configured to receive. Setting the SPEN
bit of the RCSTA register enables the EUSART.
21.5.2.1 EUSART Synchronous Slave
Transmit
The operation of the Synchronous Master and
Slave modes is identical (see Section 21.5.1.3
“Synchronous Master Transmission”), except in the
case of Sleep mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
1. The first character will immediately transfer to
the TSR register and transmit.
2. The second word will remain in the TXREG
register.
3. The TXIF bit will not be set.
4. After the first character has been shifted out of
TSR, the TXREG register will transfer the
second character to the TSR and the TXIF bit
will now be set.
5. If the PEIE and TXIE bits are set, the interrupt
will wake the device from Sleep and execute the
next instruction. If the GIE bit is also set, the
program will call the Interrupt Service Routine.
21.5.2.2 Synchronous Slave Transmission
Setup
1. Set the SYNC and SPEN bits, and clear the
CSRC bit.
2. Clear the ANSELx bit for the CK pin (if applicable).
3. Clear the CREN and SREN bits.
4. If interrupts are desired, set the TXIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
5. If 9-bit transmission is desired, set the TX9 bit.
6. Enable transmission by setting the TXEN bit.
7. If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
8. Start transmission by writing the Least
Significant eight bits to the TXREG register.
TABLE 21-9: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE
TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
BAUDCON ABDOVF RCIDL —SCKPBRG16 —WUE ABDEN 186
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 74
PIE1 TMR1GIE ADIE RCIE(1) TXIE(1) — — TMR2IE TMR1IE 75
PIR1 TMR1GIF ADIF RCIF(1) TXIF(1) — — TMR2IF TMR1IF 78
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 185
TXREG EUSART Transmit Data Register 177*
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 184
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
* Page provides register information.
Note 1: PIC12(L)F1572 only.
2013-2015 Microchip Technology Inc. DS40001723D-page 201
PIC12(L)F1571/2
21.5.2.3 EUSART Synchronous Slave
Reception
The operation of the Synchronous Master and Slave
modes is identical (Section 21.5.1.5 “Synchronous
Master Reception”), with the following exceptions:
• Sleep
• CREN bit is always set, therefore, the receiver is
never Idle
• SREN bit, which is a “don’t care” in Slave mode
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCREG register. If the RCIE enable bit is set, the
interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE bit is also
set, the program will branch to the interrupt vector.
21.5.2.4 Synchronous Slave Reception Setup
1. Set the SYNC and SPEN bits, and clear the
CSRC bit.
2. Clear the ANSELx bit for both the CK and DT
pins (if applicable).
3. If interrupts are desired, set the RCIE bit of the
PIE1 register, and the GIE and PEIE bits of the
INTCON register.
4. If 9-bit reception is desired, set the RX9 bit.
5. Set the CREN bit to enable reception.
6. The RCIF bit will be set when reception is
complete. An interrupt will be generated if the
RCIE bit was set.
7. If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCSTA
register.
8. Retrieve the eight Least Significant bits from the
receive FIFO by reading the RCREG register.
9. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.
TABLE 21-10: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE
RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
BAUDCON ABDOVF RCIDL —SCKPBRG16 —WUE ABDEN 186
INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 74
PIE1 TMR1GIE ADIE RCIE(1) TXIE(1) — — TMR2IE TMR1IE 75
PIR1 TMR1GIF ADIF RCIF(1) TXIF(1) — — TMR2IF TMR1IF 78
RCREG EUSART Receive Data Register 180*
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 185
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 184
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous slave reception.
* Page provides register information.
Note 1: PIC12(L)F1572 only.
PIC12(L)F1571/2
DS40001723D-page 202 2013-2015 Microchip Technology Inc.
NOTES:
2013-2015 Microchip Technology Inc. DS40001723D-page 203
PIC12(L)F1571/2
22.0 16-BIT PULSE-WIDTH
MODULATION (PWM) MODULE
The Pulse-Width Modulation (PWM) module generates
a pulse-width modulated signal determined by the
phase, duty cycle, period and offset event counts that
are contained in the following registers:
• PWMxPH register
• PWMxDC register
• PWMxPR register
• PWMxOF register
Figure 22-1 shows a simplified block diagram of the
PWM operation.
Each PWM module has four modes of operation:
• Standard
• Set On Match
• Toggle On Match
• Center-Aligned
For a more detailed description of each PWM mode,
refer to Section 22.2 “PWM Modes”.
Each PWM module has four Offset modes:
• Independent Run
• Slave Run with Synchronous Start
• One-Shot Slave with Synchronous Start
• Continuous Run Slave with Synchronous Start
and Timer Reset
Using the Offset modes, each PWM module can offset
its waveform relative to any other PWM module in the
same device. For a more detailed description of the
Offset modes, refer to Section 22.3 “Offset Modes”.
Every PWM module has a configurable reload
operation to ensure all event count buffers change at
the end of a period, thereby avoiding signal glitches.
Figure 22-2 shows a simplified block diagram of the
reload operation. For a more detailed description of
the reload operation, refer to Section 22.4 “Reload
Operation”.
FIGURE 22-1: 16-BIT PWM BLOCK DIAGRAM
Rev. 10-000152A
4/21/2014
PWM Control
Unit
MODE<1:0>
PWMxPR
Comparator
PWMxTMR
PRx_match
PWMxDC
Comparator
16-bt Latch
DCx_match
PWMxOF
Comparator
16-bt Latch
OFx_match
PWMxPH
Comparator
16-bt Latch
PHx_match
16-bt Latch LDx_trigger LDx_trigger LDx_trigger LDx_trigger
PWMxPOL
PWMx
PWMxOUT
To Peripherals
TRIS Control
PWMxOE
set PRIF set PHIF set OFIF set DCIF
D
CK
Q
Q4
PWMx_output
Offset
Control
ERU/D
OFM<1:0>
PRx_match
00
11
10
01
OF3_match(1)
OF2_match(1)
OF1_match(1)
Reserved
OFS
OF_match
EN
PHx_match
DCx_match
Note 1: A PWM module cannot trigger from its own offset match event.
The input corresponding to a PWM module’s own offset match is reserved.
PWM_clock
PIC12(L)F1571/2
DS40001723D-page 204 2013-2015 Microchip Technology Inc.
FIGURE 22-2: LOAD TRIGGER BLOCK DIAGRAM
22.1 Fundamental Operation
The PWM module produces a 16-bit resolution
pulse-width modulated output.
Each PWM module has an independent timer driven by
a selection of clock sources determined by the
PWMxCLKCON register (Register 22-4). The timer
value is compared to event count registers to generate
the various events of a the PWM waveform, such as the
period and duty cycle. For a block diagram describing
the clock sources, refer to Figure 22-3.
Each PWM module can be enabled individually using
the EN bit of the PWMxCON register, or several PWM
modules can be enabled simultaneously using the
mirror bits of the PWMEN register.
The current state of the PWM output can be read using
the OUT bit of the PWMxCON register. In some modes,
this bit can be set and cleared by software, giving
additional software control over the PWM waveform.
This bit is synchronized to FOSC/4 and therefore, does
not change in real time with respect to the PWM_clock.
FIGURE 22-3: PWM CLOCK SOURCE
BLOCK DIAGRAM
22.1.1 PWMx PIN CONFIGURATION
All PWM outputs are multiplexed with the PORT data
latch, so the pins must also be configured as outputs by
clearing the associated PORT TRISx bits.
The slew rate feature may be configured to optimize
the rate to be used in conjunction with the PWM
outputs. High-speed output switching is attained by
clearing the associated PORT SLRCONx bits.
The PWM outputs can be configured to be open-drain
outputs by setting the associated PORT ODCONx bits.
22.1.2 PWMx Output Polarity
The output polarity is inverted by setting the POL bit of
the PWMxCON register. The polarity control affects the
PWM output even when the module is not enabled.
Rev. 10-000153A
4/21/2014
00
11
10
01
LD3_trigger(1)
LD2_trigger(1)
LD1_trigger(1)
Reserved
PWMxLDS PRx_match
1
0PWMxLDA(2)
DQ
PWM_clock
LDx_trigger
PWMxLDT
Note 1. The input corresponding to a PWM module’s own load trigger is reserved.
2. PWMxLDA is cleared by hardware upon LDx_trigger.
Note: If PWM_clock > FOSC/4, the OUT bit may
not accurately represent the output state of
the PWM.
Rev. 10-000156A
1/7/2015
00
11
10
01
HFINTOSC
LFINTOSC
FOSC
Reserved
PWMxCS<1:0>
Prescaler PWMx_clock
PWMxPS<2:0>
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PIC12(L)F1571/2
22.2 PWM Modes
PWM modes are selected with the MODE<1:0> bits of
the PWMxCON register (Register 22-1).
In all PWM modes, an offset match event can also be
used to synchronize the PWMxTMR in three Offset
modes. See Section 22.3 “Offset Modes” for more
information.
22.2.1 STANDARD MODE
The Standard mode (MODE<1:0> = 00) selects a
single-phase PWM output. The PWM output in this
mode is determined by when the period, duty cycle and
phase counts match the PWMxTMR value. The start of
the duty cycle occurs on the phase match and the end
of the duty cycle occurs on the duty cycle match. The
period match resets the timer. The offset match can
also be used to synchronize the PWMxTMR in the
Offset modes. See Section 22.3 “Offset Modes” for
more information.
Equation 22-1 is used to calculate the PWM period in
Standard mode.
Equation 22-2 is used to calculate the PWM duty cycle
ratio in Standard mode.
EQUATION 22-1: PWM PERIOD IN
STANDARD MODE
EQUATION 22-2: PWM DUTY CYCLE IN
STANDARD MODE
A detailed timing diagram for Standard mode is shown
in Figure 22-4.
22.2.2 SET ON MATCH MODE
The Set On Match mode (MODE<1:0> = 01) generates
an active output when the phase count matches the
PWMxTMR value. The output stays active until the
OUT bit of the PWMxCON register is cleared or the
PWM module is disabled. The duty cycle count has no
effect in this mode. The period count only determines
the maximum PWMxTMR value above which no phase
matches can occur.
The OUT bit can be used to set or clear the output of
the PWM in this mode. Writes to this bit will take place
on the next rising edge of the PWM_clock after the bit
is written.
A detailed timing diagram for Set On Match mode is
shown in Figure 22-5.
22.2.3 TOGGLE ON MATCH MODE
The Toggle On Match mode (MODE<1:0> = 10) gener-
ates a 50% duty cycle PWM with a period twice as long
as that computed for the Standard PWM mode. Duty
cycle count has no effect in this mode. The phase count
determines how many PWMxTMR periods, after a
period event, the output will toggle.
Writes to the OUT bit of the PWMxCON register will
have no effect in this mode.
A detailed timing diagram for Toggle On Match mode is
shown in Figure 22-6.
22.2.4 CENTER-ALIGNED MODE
The Center-Aligned mode (MODE = 11) generates a
PWM waveform that is centered in the period. In this
mode, the period is two times the PWMxPR count. The
PWMxTMR counts up to the period value, then counts
back down to 0. The duty cycle count determines both
the start and end of the active PWM output. The start of
the duty cycle occurs at the match event when
PWMxTMR is incrementing and the duty cycle ends at
the match event when PWMxTMR is decrementing.
The incrementing match value is the period count
minus the duty cycle count. The decrementing match
value is the incrementing match value plus 1.
Equation 22-3 is used to calculate the PWM period in
Center-Aligned mode.
EQUATION 22-3: PWM PERIOD IN
CENTER-ALIGNED MODE
Equation 22-4 is used to calculate the PWM duty cycle
ratio in Center-Aligned mode.
EQUATION 22-4: PWM DUTY CYCLE IN
CENTER-ALIGNED MODE
Writes to the OUT bit will have no effect in this mode.
A detailed timing diagram for Center-Aligned mode is
shown in Figure 22-7.
Period PWMxPR 1+Prescale
PWMxCLK
--------------------------------------------------------------------=
Duty Cycle PWMxDC PWMxPH–
PWMxPR 1+
-----------------------------------------------------------------=
Period PWMxPR 1+Prescale 2
PWMxCLK
---------------------------------------------------------------------------=
Duty Cycle PWMxDC 2
PWMxPR 1+2
-------------------------------------------------=
PIC12(L)F1571/2
DS40001723D-page 206 2013-2015 Microchip Technology Inc.
FIGURE 22-4: STANDARD PWM MODE TIMING DIAGRAM
FIGURE 22-5: SET ON MATCH PWM MODE TIMING DIAGRAM
Rev. 10-000142A
9/5/2013
PWMxCLK
10
4
9
PWMxPR
PWMxPH
PWMxDC
Phase
Duty Cycle
Period
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6PWMxTMR
PWMxOUT
Rev. 10-000143A
9/5/2013
PWMxCLK
10
4
PWMxPR
PWMxPH
Phase
Period
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6PWMxTMR
PWMxOUT
2013-2015 Microchip Technology Inc. DS40001723D-page 207
PIC12(L)F1571/2
FIGURE 22-6: TOGGLE ON MATCH PWM MODE TIMING DIAGRAM
FIGURE 22-7: CENTER-ALIGNED PWM MODE TIMING DIAGRAM
Rev. 10-000144A
9/5/2013
PWMxCLK
10
4
PWMxPR
PWMxPH
Phase
Period
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6PWMxTMR
PWMxOUT
Rev. 10 -000 145A
4/22 /201 4
PWMxCL K
6
4
PWMxPR
PWMxDC
Duty Cycle
Period
0 1 2 3 4 5 6 6 5 4 3 2 1 0 0 1 2 3PWMxTMR
PWMxOUT
Rev. 10 -000 145A
4/22 /201 4
PWMxCL K
6
4
PWMxPR
PWMxDC
Duty Cycle
Period
0 1 2 3 4 5 6 6 5 4 3 2 1 0 0 1 2 3PWMxTMR
PWMxOUT
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DS40001723D-page 208 2013-2015 Microchip Technology Inc.
22.3 Offset Modes
The Offset modes provide the means to adjust the wave-
form of a slave PWM module relative to the waveform of
a master PWM module in the same device.
22.3.1 INDEPENDENT RUN MODE
In Independent Run mode (OFM<1:0> = 00), the PWM
module is unaffected by the other PWM modules in the
device. The PWMxTMR associated with the PWM
module in this mode starts counting as soon as the EN bit
associated with this PWM module is set and continues
counting until the EN bit is cleared. Period events reset
the PWMxTMR to zero, after which, the timer continues to
count.
A detailed timing diagram of this mode used with
Standard PWM mode is shown in Figure 22-8.
22.3.2 SLAVE RUN MODE WITH SYNC START
In Slave Run mode with Sync Start (OFM<1:0> = 01),
the slave PWMxTMR waits for the master’s OFx_match
event. When this event occurs, if the EN bit is set, the
PWMxTMR begins counting and continues to count
until software clears the EN bit. Slave period events
reset the PWMxTMR to zero, after which, the timer
continues to count.
A detailed timing diagram of this mode used with
Standard PWM mode is shown in Figure 22-9.
22.3.3 ONE-SHOT SLAVE MODE WITH
SYNC START
In One-Shot Slave mode with Synchronous Start
(OFM<1:0> = 10), the slave PWMxTMR waits until the
master's OFx_match event. The timer then begins count-
ing, starting from the value that is already in the timer, and
continues to count until the period match event. When the
period event occurs, the timer resets to zero and stops
counting. The timer then waits until the next master
OFx_match event, after which, it begins counting again to
repeat the cycle. An OFx_match event that occurs before
the slave PWM has completed the previously triggered
period will be ignored. A slave period that is greater than
the master period, but less than twice the master period,
will result in a slave output every other master period.
A detailed timing diagram of this mode used with
Standard PWM mode is shown in Figure 22-10.
22.3.4 CONTINUOUS RUN SLAVE MODE
WITH SYNC START AND TIMER
RESET
In Continuous Run Slave mode with Synchronous
Start and Timer Reset (OFM<1:0> = 11), the slave
PWMxTMR is inhibited from counting after the slave
PWM enable is set. The first master OFx_match event
starts the slave PWMxTMR. Subsequent master
OFx_match events reset the slave PWMxTMR timer
value back to 1, after which, the slave PWMxTMR con-
tinues to count. The next master OFx_match event
resets the slave PWMxTMR back to 1 to repeat the
cycle. Slave period events that occur before the
master’s OFx_match event will reset the slave
PWMxTMR to zero, after which, the timer will continue
to count. Slaves operating in this mode must have a
PWMxPH register pair value equal to or greater than 1;
otherwise, the phase match event will not occur
precluding the start of the PWM output duty cycle.
The offset timing will persist If both the master and
slave PWMxPR values are the same, and the Slave
Offset mode is changed to Independent Run mode
while the PWM module is operating.
A detailed timing diagram of this mode used in
Standard PWM mode is shown in Figure 22-11.
22.3.5 OFFSET MATCH IN
CENTER-ALIGNED MODE
When a master is operating in Center-Aligned mode,
the offset match event depends on which direction the
PWMxTMR is counting. Clearing the OFO bit of the
PWMxOFCON register will cause the OFx_match
event to occur when the timer is counting up. Setting
the OFO bit of the PWMxOFCON register will cause
the OFx_match event to occur when the timer is
counting down. The OFO bit is ignored in
non-Center-Aligned modes.
The OFO bit is double-buffered and requires setting the
LDA bit to take effect when the PWM module is
operating.
Detailed timing diagrams of Center-Aligned mode
using offset match control in Independent Slave with
Sync Start mode can be seen in Figure 22-12 and
Figure 22-13.
Note: During the time the slave timers are
resetting to zero, if another offset match
event is received, it is possible that the slave
PWM would not recognize this match event
and the slave timers would fail to begin
counting again. This would result in missing
duty cycles from the output of the slave
PWM. To prevent this from happening,
avoid using the same period for both the
master and slave PWMs.
Note: Unexpected results will occur if the slave
PWM_clock is a higher frequency than the
master PWM_clock.
2013-2015 Microchip Technology Inc. DS40001723D-page 209
PIC12(L)F1571/2
FIGURE 22-8: INDEPENDENT RUN MODE TIMING DIAGRAM
Rev. 10 -000 146B
7/8/ 201 5
PWMxCL K
10
3
5
2
PWMxPR
PWMxPH
PWMxDC
PWMxOF
Off set
Phase
Duty Cycle
Period
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6PWMxTMR
PWMxOUT
OFx_match
PHx_match
DCx_match
PRx_match
0 1 2 3 4 0 1 2 3 4 0 1 2 3 4 0 1 2PWMyTMR
4
0
1
PWMyPR
PWMyPH
PWMyDC
PWMyOUT
Note: PWMx = Master, PWMy = Slave
PIC12(L)F1571/2
DS40001723D-page 210 2013-2015 Microchip Technology Inc.
FIGURE 22-9: SLAVE RUN MODE WITH SYNC START TIMING DIAGRAM
Rev. 10 -000 147B
7/8/ 201 5
PWMxCL K
10
3
5
2
PWMxPR
PWMxPH
PWMxDC
PWMxOF
Off set
Phase
Duty Cycle
Period
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6PWMxTMR
PWMxOUT
OFx_match
PWMyTMR
4
0
1
PWMyPR
PWMyPH
PWMyDC
PWMyOUT
10 2 3 4 0 1 2 3 4 0 1 2 3 4 0
Note: Master = PWMx, Slave = PWMy
2013-2015 Microchip Technology Inc. DS40001723D-page 211
PIC12(L)F1571/2
FIGURE 22-10: ONE-SHOT SLAVE RUN MODE WITH SYNC START TIMING DIAGRAM
Rev. 10 -000 148B
7/8/ 201 5
PWMxCL K
10
3
5
2
PWMxPR
PWMxPH
PWMxDC
PWMxOF
Off set
Phase
Duty Cycle
Period
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6PWMxTMR
PWMxOUT
OFx_match
PWMyTMR
4
0
1
PWMyPR
PWMyPH
PWMyDC
PWMyOUT
10 2 3 4 1 2 3 40
Note: Master = PWMx, Slave = PWMy
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DS40001723D-page 212 2013-2015 Microchip Technology Inc.
FIGURE 22-11: CONTINUOUS SLAVE RUN MODE WITH IMMEDIATE RESET AND SYNC START TIMING DIAGRAM
Rev. 10 -000 149B
7/8/ 201 5
PWMxCL K
10
3
5
2
PWMxPR
PWMxPH
PWMxDC
PWMxOF
Off set
Phase
Duty Cycle
Period
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6PWMxTMR
PWMxOUT
OFx_match
PWMyTMR
4
1
2
PWMyPR
PWMyPH
PWMyDC
PWMyOUT
10 2 3 4 1 2 3 401 2 3 40 1
Note: Maste r= PW Mx, Slave=PWMy
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PIC12(L)F1571/2
FIGURE 22-12: OFFSET MATCH ON INCREMENTING TIMER TIMING DIAGRAM
Rev. 10 -000 150B
7/9/ 201 5
PWMxCL K
6
2
2
PWMxPR
PWMxDC
PWMxOF
Off set
Duty Cycle
Period
0 1 2 3 4 5 6 6 5 4 3 2 1 0 0 1 2 3PWMxTMR
PWMxOUT
OFx_match
PHx_match
DCx_match
PRx_match
0 12 3 4 4 3 2 1 0PWMyTMR
4
1
PWMyPR
PWMyDC
PWMyOUT
0100
Note: Master = PWMx, Slave = PWMy
PIC12(L)F1571/2
DS40001723D-page 214 2013-2015 Microchip Technology Inc.
FIGURE 22-13: OFFSET MATCH ON DECREMENTING TIMER TIMING DIAGRAM
Rev. 10 -000 151B
7/9/ 201 5
PWMxCL K
6
2
2
PWMxPR
PWMxDC
PWMxOF
Off set
Duty Cycle
Period
0 1 2 3 4 5 6 6 5 4 3 2 1 0 0 1 2 3PWMxTMR
PWMxOUT
OF5_match
PH5_match
DC5_match
PR5_match
PWMyTMR
4
1
PWMyPR
PWMyDC
PWMyOUT
0 1 2 3 4 4 30
Note: Master = PWMx, Slave = PWMy
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PIC12(L)F1571/2
22.4 Reload Operation
Four of the PWM module control register pairs and one
control bit are double-buffered so that all can be
updated simultaneously. These include:
• PWMxPHH:PWMxPHL register pair
• PWMxDCH:PWMxDCL register pair
• PWMxPRH:PWMxPRL register pair
• PWMxOFH:PWMxOFL register pair
• OFO control bit
When written to, these registers do not immediately
affect the operation of the PWM. By default, writes to
these registers will not be loaded into the PWM Oper-
ating Buffer registers until after the arming conditions
are met. The arming control has two methods of
operation:
• Immediate
• Triggered
The LDT bit of the PWMxLDCON register controls the
arming method. Both methods require the LDA bit to be
set. All four buffer pairs will load simultaneously at the
loading event.
22.4.1 IMMEDIATE RELOAD
When the LDT bit is clear, then the immediate mode is
selected and the buffers will be loaded at the first period
event after the LDA bit is set. Immediate reloading is
used when a PWM module is operating stand-alone or
when the PWM module is operating as a master to
other slave PWM modules.
22.4.2 TRIGGERED RELOAD
When the LDT bit is set, then the Triggered mode is
selected and a trigger event is required for the LDA bit
to take effect. The trigger source is the buffer load
event of one of the other PWM modules in the device.
The triggering source is selected by the LDS<1:0> bits
of the PWMxLDCON register. The buffers will be
loaded at the first period event following the trigger
event. Triggered reloading is used when a PWM
module is operating as a slave to another PWM and it
is necessary to synchronize the buffer reloads in both
modules.
22.5 Operation in Sleep Mode
Each PWM module will continue to operate in Sleep
mode when either the HFINTOSC or LFINTOSC is
selected as the clock source by PWMxCLKCON<1:0>.
22.6 Interrupts
Each PWM module has four independent interrupts
based on the phase, duty cycle, period and offset match
events. The interrupt flag is set on the rising edge of
each of these signals. Refer to Figures 22-12 and 22-13
for detailed timing diagrams of the match signals.
Note 1: The buffer load operation clears the
LDA bit.
2: If the LDA bit is set at the same time as
PWMxTMR = PWMxPR, the LDA bit is
ignored until the next period event. Such
is the case when triggered reload is
selected and the triggering event occurs
simultaneously with the target’s period
event.
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DS40001723D-page 216 2013-2015 Microchip Technology Inc.
22.7 Register Definitions: PWM Control
Long bit name prefixes for the 16-bit PWM peripherals
are shown in Table 22-1. Refer to Section
1.1 “Register and Bit Naming Conventions” for more
information
TABLE 22-1: BIT NAME PREFIXES
Peripheral Bit Name Prefix
PWM1 PWM1
PWM2 PWM2
PWM3 PWM3
REGISTER 22-1: PWMxCON: PWMx CONTROL REGISTER
R/W-0/0 R/W-0/0 R/HS/HC-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0
EN OE OUT POL MODE<1:0> — —
bit 7 bit 0
Legend:
HC = Hardware Clearable bit HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7 EN: PWMx Module Enable bit
1 = Module is enabled
0 = Module is disabled
bit 6 OE: PWMx Output Enable bit
1 = PWM output pin is enabled
0 = PWM output pin is disabled
bit 5 OUT: Output State of the PWMx Module bit
bit 4 POL: PWMx Output Polarity Control bit
1 = PWM output active state is low
0 = PWM output active state is high
bit 3-2 MODE<1:0>: PWMx Mode Control bits
11 = Center-Aligned mode
10 = Toggle On Match mode
01 = Set On Match mode
00 = Standard PWM mode
bit 1-0 Unimplemented: Read as ‘0’
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REGISTER 22-2: PWMxINTE: PWMx INTERRUPT ENABLE REGISTER
U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
———— OFIE PHIE DCIE PRIE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-4 Unimplemented: Read as ‘0’
bit 3 OFIE: Offset Interrupt Enable bit
1 = Interrupts CPU on offset match
0 = Does not interrupt CPU on offset match
bit 2 PHIE: Phase Interrupt Enable bit
1 = Interrupts CPU on phase match
0 = Does not Interrupt CPU on phase match
bit 1 DCIE: Duty Cycle Interrupt Enable bit
1 = Interrupts CPU on duty cycle match
0 = Does not interrupt CPU on duty cycle match
bit 0 PRIE: Period Interrupt Enable bit
1 = Interrupts CPU on period match
0 = Does not interrupt CPU on period match
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DS40001723D-page 218 2013-2015 Microchip Technology Inc.
REGISTER 22-3: PWMxINTF: PWMx INTERRUPT REQUEST REGISTER
U-0 U-0 U-0 U-0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
— — — — OFIF PHIF DCIF PRIF
bit 7 bit 0
Legend:
HC = Hardware Clearable bit HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-4 Unimplemented: Read as ‘0’
bit 3 OFIF: Offset Interrupt Flag bit(1)
1 = Offset match event occurred
0 = Offset match event did not occur
bit 2 PHIF: Phase Interrupt Flag bit(1)
1 = Phase match event occurred
0 = Phase match event did not occur
bit 1 DCIF: Duty Cycle Interrupt Flag bit(1)
1 = Duty cycle match event occurred
0 = Duty cycle match event did not occur
bit 0 PRIF: Period Interrupt Flag bit(1)
1 = Period match event occurred
0 = Period match event did not occur
Note 1: Bit is forced clear by hardware while module is disabled (EN = 0).
2013-2015 Microchip Technology Inc. DS40001723D-page 219
PIC12(L)F1571/2
REGISTER 22-4: PWMxCLKCON: PWMx CLOCK CONTROL REGISTER
U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0
—PS<2:0>—— CS<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7 Unimplemented: Read as ‘0’
bit 6-4 PS<2:0>: Clock Source Prescaler Select bits
111 = Divides clock source by 128
110 = Divides clock source by 64
101 = Divides clock source by 32
100 = Divides clock source by 16
011 = Divides clock source by 8
010 = Divides clock source by 4
001 = Divides clock source by 2
000 = No prescaler
bit 3-2 Unimplemented: Read as ‘0’
bit 1-0 CS<1:0>: Clock Source Select bits
11 = Reserved
10 = LFINTOSC (continues to operate during Sleep)
01 = HFINTOSC (continues to operate during Sleep)
00 =FOSC
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REGISTER 22-5: PWMxLDCON: PWMx RELOAD TRIGGER SOURCE SELECT REGISTER
R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0
LDA(1) LDT ————LDS<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7 LDA: Load Buffer Armed bit(1)
If LDT = 1:
1 = Loads the OFx, PHx, DCx and PRx buffers at the end of the period when the selected trigger occurs
0 = Does not load buffers or load has completed
If LDT = 0:
1 = Loads the OFx, PHx, DCx and PRx buffers at the end of the current period
0 = Does not load buffers or load has completed
bit 6 LDT: Load Buffer on Trigger bit
1 = Loads buffers on trigger enabled
0 = Loads buffers on trigger disabled
Loads the OFx, PHx, DCx and PRx buffers at the end of every period after the selected trigger occurs.
Reloads internal double buffers at the end of current period. The LDS<1:0> bits are ignored.
bit 5-2 Unimplemented: Read as ‘0’
bit 1-0 LDS<1:0>: Load Trigger Source Select bits
11 = LD3_trigger(2)
10 = LD2_trigger(2)
01 = LD1_trigger(2)
00 = Reserved
Note 1: This bit is cleared by the module after a reload operation. It can be cleared in software to clear an existing
arming event.
2: The LD_trigger corresponding to the PWM used becomes reserved.
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REGISTER 22-6: PWMxOFCON: PWMx OFFSET TRIGGER SOURCE SELECT REGISTER
U-0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0
— OFM<1:0> OFO
(1) ——OFS<1:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7 Unimplemented: Read as ‘0’
bit 6-5 OFM<1:0>: Offset Mode Select bits
11 = Continuous Slave Run mode with immediate Reset and synchronized start when the selected
offset trigger occurs
10 = One-Shot Slave Run mode with synchronized start when the selected offset trigger occurs
01 = Independent Slave Run mode with synchronized start when the selected offset trigger occurs
00 = Independent Run mode
bit 4 OFO: Offset Match Output Control bit(1)
If MODE<1:0> = 11 (PWM Center-Aligned mode):
1 = OFx_match occurs on counter match when counter decrementing, (second match)
0 = OFx_match occurs on counter match when counter incrementing, (first match)
If MODE<1:0> = 00, 01 or 10 (all other modes):
Bit is ignored.
bit 3-2 Unimplemented: Read as ‘0’
bit 1-0 OFS<1:0>: Offset Trigger Source Select bits
11 =OF3_match
(1)
10 =OF2_match
(1)
01 =OF1_match
(1)
00 = Reserved
Note 1: The OFx_match corresponding to the PWM used becomes reserved.
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REGISTER 22-7: PWMxPHH: PWMx PHASE COUNT HIGH REGISTER
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
PH<15:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-0 PH<15:8>: PWMx Phase High bits
Upper eight bits of PWM phase count.
REGISTER 22-8: PWMxPHL: PWMx PHASE COUNT LOW REGISTER
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
PH<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-0 PH<7:0>: PWMx Phase Low bits
Lower eight bits of PWM phase count.
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REGISTER 22-9: PWMxDCH: PWMx DUTY CYCLE COUNT HIGH REGISTER
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
DC<15:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-0 DC<15:8>: PWMx Duty Cycle High bits
Upper eight bits of PWM duty cycle count.
REGISTER 22-10: PWMxDCL: PWMx DUTY CYCLE COUNT LOW REGISTER
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
DC<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-0 DC<7:0>: PWMx Duty Cycle Low bits
Lower eight bits of PWM duty cycle count.
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REGISTER 22-11: PWMxPRH: PWMx PERIOD COUNT HIGH REGISTER
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
PR<15:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-0 PR<15:8>: PWMx Period High bits
Upper eight bits of PWM period count.
REGISTER 22-12: PWMxPRL: PWMx PERIOD COUNT LOW REGISTER
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
PR<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-0 PR<7:0>: PWMx Period Low bits
Lower eight bits of PWM period count.
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REGISTER 22-13: PWMxOFH: PWMx OFFSET COUNT HIGH REGISTER
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
OF<15:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-0 OF<15:8>: PWMx Offset High bits
Upper eight bits of PWM offset count.
REGISTER 22-14: PWMxOFL: PWMx OFFSET COUNT LOW REGISTER
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
OF<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-0 OF<7:0>: PWMx Offset Low bits
Lower eight bits of PWM offset count.
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REGISTER 22-15: PWMxTMRH: PWMx TIMER HIGH REGISTER
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
TMR<15:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-0 TMR<15:8>: PWMx Timer High bits
Upper eight bits of PWM timer counter.
REGISTER 22-16: PWMxTMRL: PWMx TIMER LOW REGISTER
R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
TMR<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-0 TMR<7:0>: PWMx Timer Low bits
Lower eight bits of PWM timer counter.
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Note: There are no long and short bit name variants for the following three mirror registers
REGISTER 22-17: PWMEN: PWMEN BIT ACCESS REGISTER
U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
————— PWM3EN_A PWM2EN_A PWM1EN_A
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-3 Unimplemented: Read as ‘0’
bit 2-0 PWMxEN_A: PWM3/PWM2/PWM1 Enable bits
Mirror copy of EN bit (PWMxCON<7>).
REGISTER 22-18: PWMLD: LD BIT ACCESS REGISTER
U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — — PWM3LDA_A PWM2LDA_A PWM1LDA_A
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-3 Unimplemented: Read as ‘0’
bit 2-0 PWMxLDA_A: PWM3/PWM2/PWM1 LD bits
Mirror copy of LD bit (PWMxLDCON<7>).
REGISTER 22-19: PWMOUT: PWMOUT BIT ACCESS REGISTER
U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
— — — — — PWM3OUT_A PWM2OUT_A PWM1OUT_A
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-3 Unimplemented: Read as ‘0’
bit 2-0 PWMxOUT_A: PWM3/PWM2/PWM1 Output bits
Mirror copy of OUT bit (PWMxCON<5>).
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TABLE 22-2: SUMMARY OF REGISTERS ASSOCIATED WITH PWM
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
OSCCON SPLLEN IRCF<3:0> —SCS<1:0>55
PIE3 — PWM3IE PWM2IE PWM1IE — — — — 77
PIR3 — PWM3IF PWM2IF PWM1IF — — — — 80
PWMEN — — — — — PWM3EN_A PWM2EN_A PWM1EN_A 227
PWMLD — — — — — PWM3LDA_A PWM2LDA_A PWM1LDA_A 227
PWMOUT — — — — — PWM3OUT_A PWM2OUT_A PWM1OUT_A 227
PWM1PHL PH<7:0> 222
PWM1PHH PH<15:8> 222
PWM1DCL DC<7:0> 223
PWM1DCH DC<15:8> 223
PWM1PRH PR<7:0> 224
PWM1PRL PR<15:8> 224
PWM1OFH OF<7:0> 225
PWM1OFL OF<15:8> 225
PWM1TMRH TMR<7:0> 226
PWM1TMRL TMR<15:8> 226
PWM1CON EN OE OUT POL MODE<1:0> — — 216
PWM1INTE ———— OFIE PHIE DCIE PRIE 217
PWM1INTF ———— OFIF PHIF DCIF PRIF 218
PWM1CLKCON — PS<2:0> ——CS<1:0>219
PWM1LDCON LDA LDT — — — —LDS<1:0>220
PWM1OFCON — OFM<1:0> OFO ——OFS<1:0>221
PWM2PHL PH<7:0> 222
PWM2PHH PH<15:8> 222
PWM2DCL DC<7:0> 223
PWM2DCH DC<15:8> 223
PWM2PRL PR<7:0> 224
PWM2PRH PR<15:8> 224
PWM2OFL OF<7:0> 225
PWM2OFH OF<15:8> 225
PWM2TMRL TMR<7:0> 226
PWM2TMRH TMR<15:8> 226
PWM2CON EN OE OUT POL MODE<1:0> — — 216
PWM2INTE ———— OFIE PHIE DCIE PRIE 217
PWM2INTF ———— OFIF PHIF DCIF PRIF 218
PWM2CLKCON — PS<2:0> ——CS<1:0>219
PWM2LDCON LDA LDT — — — —LDS<1:0>220
PWM2OFCON — OFM<1:0> OFO ——OFS<1:0>221
PWM3PHL PH<7:0> 222
PWM3PHH PH<15:8> 222
PWM3DCL DC<7:0> 223
PWM3DCH DC<15:8> 223
PWM3PRL PR<7:0> 224
PWM3PRH PR<15:8> 224
PWM3OFL OF<7:0> 225
PWM3OFH OF<15:8> 225
PWM3TMRL TMR<7:0> 226
PWM3TMRH TMR<15:8> 226
PWM3CON EN OE OUT POL MODE<1:0> — — 216
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the PWM.
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TABLE 22-3: SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES
PWM3INTE ———— OFIE PHIE DCIE PRIE 217
PWM3INTF ———— OFIF PHIF DCIF PRIF 218
PWM3CLKCON —PS<2:0> ——CS<1:0>219
PWM3LDCON LDA LDT — — — —LDS<1:0>220
PWM3OFCON — OFM<1:0> OFO ——OFS<1:0>221
Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 Register
on Page
CONFIG1 13:8 — — — —CLKOUTENBOREN<1:0> —42
7:0 CP MCLRE PWRTE WDTE<1:0> — FOSC<1:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.
TABLE 22-2: SUMMARY OF REGISTERS ASSOCIATED WITH PWM (CONTINUED)
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the PWM.
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NOTES:
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23.0 COMPLEMENTARY WAVEFORM
GENERATOR (CWG) MODULE
The Complementary Waveform Generator (CWG)
produces a complementary waveform with dead-band
delay from a selection of input sources.
The CWG module has the following features:
• Selectable dead-band clock source control
• Selectable input sources
• Output enable control
• Output polarity control
• Dead-band control with independent 6-bit rising
and falling edge dead-band counters
• Auto-shutdown control with:
- Selectable shutdown sources
- Auto-restart enable
- Auto-shutdown pin override control
23.1 Fundamental Operation
The CWG generates two output waveforms from the
selected input source.
The off-to-on transition of each output can be delayed
from the on-to-off transition of the other output, thereby,
creating a time delay immediately where neither output
is driven. This is referred to as dead time and is covered
in Section 23.5 “Dead-Band Control”. A typical
operating waveform with dead band, generated from a
single input signal, is shown in Figure 23-2.
It may be necessary to guard against the possibility of
circuit Faults or a feedback event arriving too late, or
not at all. In this case, the active drive must be termi-
nated before the Fault condition causes damage. This
is referred to as auto-shutdown and is covered in
Section 23.9 “Auto-Shutdown Control”.
23.2 Clock Source
The CWG module allows the following clock sources
to be selected:
•F
OSC (system clock)
• HFINTOSC (16 MHz only)
The clock sources are selected using the G1CS0 bit of
the CWGxCON0 register (Register 23-1).
23.3 Selectable Input Sources
The CWG generates the output waveforms from the
input sources in Tab le 23-1 .
The input sources are selected using the GxIS<2:0>
bits in the CWGxCON1 register (Register 23-2).
23.4 Output Control
Immediately after the CWG module is enabled, the
complementary drive is configured with both CWGxA
and CWGxB drives cleared.
23.4.1 OUTPUT ENABLES
Each CWG output pin has individual output enable
control. Output enables are selected with the GxOEA
and GxOEB bits of the CWGxCON0 register. When an
output enable control is cleared, the module asserts no
control over the pin. When an output enable is set, the
override value or active PWM waveform is applied to
the pin per the port priority selection. The output pin
enables are dependent on the module enable bit,
GxEN. When GxEN is cleared, CWG output enables
and CWG drive levels have no effect.
23.4.2 POLARITY CONTROL
The polarity of each CWG output can be selected
independently. When the output polarity bit is set, the
corresponding output is active-high. Clearing the output
polarity bit configures the corresponding output as
active-low. However, polarity does not affect the
override levels. Output polarity is selected with the
GxPOLA and GxPOLB bits of the CWGxCON0 register.
TABLE 23-1: SELECTABLE INPUT
SOURCES
Source Peripheral Signal Name
Comparator C1 C1OUT_sync
PWM1 PWM1_output
PWM2 PWM2_output
PWM3 PWM3_output
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FIGURE 23-1: SIMPLIFIED CWG BLOCK DIAGRAM
Rev. 10-000123D
7/10/2015
11
10
00
11
10
00
0
1
1
0
S
QR
QDQ
S
S
QR
Q
6
6
2
2
1
3
EN
R
=
EN
R
=
C1OUT_async
Reserved
PWM1_out
Reserved
Reserved
PWM2_out
PWM3_out
Reserved
GxIS
FOSC
HFINTOSC
GxCS
C1OUT_async
CWG1FLT (INT pin)
GxASDSFLT
GxASDSC1
GxASE Data Bit
WRITE
GxARSEN
Auto-Shutdown
Source
set dominate
GxASE
shutdown
Input Source
cwg_clock
GxPOLA
GxPOLB
CWGxDBR
CWGxDBF
‘0'
‘0'
‘1'
‘1'
GxASDLA
GxASDLB
TRISx
TRISx
GxASDLA = 01
GxASDLB = 01
GxOEA
GxOEB
CWGxB
CWGxA
x = CWG module number
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FIGURE 23-2: TYPICAL CWG OPERATION WITH PWM1 (NO AUTO-SHUTDOWN)
23.5 Dead-Band Control
Dead-band control provides for non-overlapping output
signals to prevent shoot-through current in power
switches. The CWG contains two 6-bit dead-band
counters. One dead-band counter is used for the rising
edge of the input source control. The other is used for
the falling edge of the input source control.
Dead band is timed by counting CWG clock periods
from zero, up to the value in the rising or falling Dead-
Band Counter registers. See the CWGxDBR and
CWGxDBF registers (Register 23-4 and Register 23-5,
respectively).
23.6 Rising Edge Dead Band
The rising edge dead band delays the turn-on of the
CWGxA output from when the CWGxB output is turned
off. The rising edge dead-band time starts when the
rising edge of the input source signal goes true. When
this happens, the CWGxB output is immediately turned
off and the rising edge dead-band delay time starts.
When the rising edge dead-band delay time is reached,
the CWGxA output is turned on.
The CWGxDBR register sets the duration of the dead-
band interval on the rising edge of the input source
signal. This duration is from 0 to 64 counts of dead band.
Dead band is always counted off the edge on the input
source signal. A count of 0 (zero), indicates that no
dead band is present.
If the input source signal is not present for enough time
for the count to be completed, no output will be seen on
the respective output.
23.7 Falling Edge Dead Band
The falling edge dead band delays the turn-on of the
CWGxB output from when the CWGxA output is turned
off. The falling edge dead-band time starts when the
falling edge of the input source goes true. When this
happens, the CWGxA output is immediately turned off
and the falling edge dead-band delay time starts. When
the falling edge dead-band delay time is reached, the
CWGxB output is turned on.
The CWGxDBF register sets the duration of the dead-
band interval on the falling edge of the input source
signal. This duration is from 0 to 64 counts of
dead band.
Dead band is always counted off the edge on the input
source signal. A count of 0 (zero), indicates that no
dead band is present.
If the input source signal is not present for enough time
for the count to be completed, no output will be seen on
the respective output.
Refer to Figure 23-3 and Figure 23-4 for examples.
Rising Edge
Falling Edge Dead Band
Rising Edge Dead Band
Falling Edge Dead Band
cwg_clock
PWM1
CWGxA
CWGxB
Rising Edge
Dead Band
Dead Band
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FIGURE 23-3: DEAD-BAND OPERATION, CWGxDBR = 01h, CWGxDBF = 02h
FIGURE 23-4: DEAD-BAND OPERATION, CWGxDBR = 03h, CWGxDBF = 04h, SOURCE SHORTER THAN DEAD BAND
Input Source
CWGxA
CWGxB
cwg_clock
Source Shorter than Dead Band
Input Source
CWGxA
CWGxB
cwg_clock
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23.8 Dead-Band Uncertainty
When the rising and falling edges of the input source
triggers the dead-band counters, the input may be
asynchronous. This will create some uncertainty in the
dead-band time delay. The maximum uncertainty is
equal to one CWG clock period. Refer to Equation 23-1
for more detail.
EQUATION 23-1: DEAD-BAND
UNCERTAINTY
23.9 Auto-Shutdown Control
Auto-shutdown is a method to immediately override the
CWG output levels with specific overrides that allow for
safe shutdown of the circuit. The shutdown state can be
either cleared automatically or held until cleared by
software.
23.9.1 SHUTDOWN
The shutdown state can be entered by either of the
following two methods:
• Software generated
• External Input
23.9.1.1 Software Generated Shutdown
Setting the GxASE bit of the CWGxCON2 register will
force the CWG into the shutdown state.
When auto-restart is disabled, the shutdown state will
persist as long as the GxASE bit is set.
When auto-restart is enabled, the GxASE bit will clear
automatically and resume operation on the next rising
edge event. See Figure 23-6.
23.9.1.2 External Input Source
External shutdown inputs provide the fastest way to
safely suspend CWG operation in the event of a Fault
condition. When any of the selected shutdown inputs
goes active, the CWG outputs will immediately go to
the selected override levels without software delay. Any
combination of two input sources can be selected to
cause a shutdown condition. The sources are:
• Comparator C1 – C1OUT_async
•CWG1FLT
Shutdown inputs are selected in the CWGxCON2
register (Register 23-3).
TDEADBAND_UNCERTAINTY 1
Fcwg_clock
-----------------------------=
Therefore:
Fcwg_clock 16 MHz=
1
16 MHz
-------------------=
62.5ns=
TDEADBAND_UNCERTAINTY 1
Fcwg_clock
-----------------------------=
Example:
Note: Shutdown inputs are level sensitive, not
edge sensitive. The shutdown state
cannot be cleared, except by disabling
auto-shutdown, as long as the shutdown
input level persists.
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23.10 Operation During Sleep
The CWG module operates independently from the
system clock, and will continue to run during Sleep
provided that the clock and input sources selected
remain active.
The HFINTOSC remains active during Sleep, provided
that the CWG module is enabled, the input source is
active and the HFINTOSC is selected as the clock
source, regardless of the system clock source
selected.
In other words, if the HFINTOSC is simultaneously
selected as the system clock and the CWG clock
source, when the CWG is enabled and the input source
is active, the CPU will go idle during Sleep, but the
CWG will continue to operate and the HFINTOSC will
remain active.
This will have a direct effect on the Sleep mode current.
23.11 Configuring the CWG
The following steps illustrate how to properly configure
the CWG to ensure a synchronous start:
1. Ensure that the TRISx control bits correspond-
ing to CWGxA and CWGxB are set so that both
are configured as inputs.
2. Clear the GxEN bit if not already cleared.
3. Set desired dead-band times with the CWGxDBR
and CWGxDBF registers.
4. Set up the following controls in the CWGxCON2
auto-shutdown register:
• Select desired shutdown source.
• Select both output overrides to the desired
levels (this is necessary even if not using
auto-shutdown because start-up will be from
a shutdown state).
• Set the GxASE bit and clear the GxARSEN
bit.
5. Select the desired input source using the
CWGxCON1 register.
6. Configure the following controls in the
CWGxCON0 register:
• Select desired clock source.
• Select the desired output polarities.
• Set the output enables for the outputs to be
used.
7. Set the GxEN bit.
8. Clear the TRISx control bits corresponding to
CWGxA and CWGxB to be used to configure
those pins as outputs.
9. If auto-restart is to be used, set the GxARSEN
bit and the GxASE bit will be cleared automati-
cally. Otherwise, clear the GxASE bit to start the
CWG.
23.11.1 PIN OVERRIDE LEVELS
The levels driven to the output pins, while the shutdown
input is true, are controlled by the GxASDLA
and GxASDLB bits of the CWGxCON1 register
(Register 23-3). GxASDLA controls the CWG1A over-
ride level and GxASDLB controls the CWG1B override
level. The control bit logic level corresponds to the out-
put logic drive level while in the shutdown state. The
polarity control does not apply to the override level.
23.11.2 AUTO-SHUTDOWN RESTART
After an auto-shutdown event has occurred, there are
two ways to resume operation:
• Software controlled
• Auto-restart
The restart method is selected with the GxARSEN bit
of the CWGxCON2 register. Waveforms of software
controlled and automatic restarts are shown in
Figure 23-5 and Figure 23-6.
23.11.2.1 Software Controlled Restart
When the GxARSEN bit of the CWGxCON2 register
is cleared, the CWG must be restarted after an
auto-shutdown event by software.
Clearing the shutdown state requires all selected shut-
down inputs to be low, otherwise, the GxASE bit will
remain set. The overrides will remain in effect until the
first rising edge event after the GxASE bit is cleared.
The CWG will then resume operation.
23.11.2.2 Auto-Restart
When the GxARSEN bit of the CWGxCON2 register is
set, the CWG will restart from the auto-shutdown state
automatically.
The GxASE bit will clear automatically when all shut-
down sources go low. The overrides will remain in
effect until the first rising edge event after the GxASE
bit is cleared. The CWG will then resume operation.
2013-2015 Microchip Technology Inc. DS40001723D-page 237
PIC12(L)F1571/2
FIGURE 23-5: SHUTDOWN FUNCTIONALITY, AUTO-RESTART DISABLED (GxARSEN = 0, GxASDLA = 01, GxASDLB = 01)
FIGURE 23-6: SHUTDOWN FUNCTIONALITY, AUTO-RESTART ENABLED (GxARSEN = 1, GxASDLA = 01, GxASDLB = 01)
Shutdown
GxASE Cleared by Software
Output Resumes
No Shutdown
CWG Input
G
x
ASE
CWG1A
Source
Shutdown Source
Shutdown Event Ceases
Tri-State (No Pulse)
CWG1B
Tri-State (No Pulse)
Shutdown
Tri-State (No Pulse)
GxASE Auto-Cleared by Hardware
Output Resumes
No Shutdown
CWG Input
G
x
ASE
CWG1A
Source
Shutdown Source
Shutdown Event Ceases
CWG1B
Tri-State (No Pulse)
PIC12(L)F1571/2
DS40001723D-page 238 2013-2015 Microchip Technology Inc.
23.12 Register Definitions: CWG Control
REGISTER 23-1: CWGxCON0: CWGx CONTROL REGISTER 0
R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0
GxEN GxOEB GxOEA GxPOLB GxPOLA ——GxCS0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7 GxEN: CWGx Enable bit
1 = Module is enabled
0 = Module is disabled
bit 6 GxOEB: CWGxB Output Enable bit
1 = CWGxB is available on appropriate I/O pin
0 = CWGxB is not available on appropriate I/O pin
bit 5 GxOEA: CWGxA Output Enable bit
1 = CWGxA is available on appropriate I/O pin
0 = CWGxA is not available on appropriate I/O pin
bit 4 GxPOLB: CWGxB Output Polarity bit
1 = Output is inverted polarity
0 = Output is normal polarity
bit 3 GxPOLA: CWGxA Output Polarity bit
1 = Output is inverted polarity
0 = Output is normal polarity
bit 2-1 Unimplemented: Read as ‘0’
bit 0 GxCS0: CWGx Clock Source Select bit
1 =HFINTOSC
0 =F
OSC
2013-2015 Microchip Technology Inc. DS40001723D-page 239
PIC12(L)F1571/2
REGISTER 23-2: CWGxCON1: CWGx CONTROL REGISTER 1
R/W-x/u R/W-x/u R/W-x/u R/W-x/u U-0 R/W-0/0 R/W-0/0 R/W-0/0
GxASDLB<1:0> GxASDLA<1:0> — GxIS<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7-6 GxASDLB<1:0>: CWGx Shutdown State for CWGxB bits
When an Auto-Shutdown Event is Present (GxASE = 1):
11 = CWGxB pin is driven to ‘1’, regardless of the setting of the GxPOLB bit
10 = CWGxB pin is driven to ‘0’, regardless of the setting of the GxPOLB bit
01 = CWGxB pin is tri-stated
00 = CWGxB pin is driven to its inactive state after the selected dead-band interval; GxPOLB will still
control the polarity of the output
bit 5-4 GxASDLA<1:0>: CWGx Shutdown State for CWGxA bits
When an Auto-Shutdown Event is Present (GxASE = 1):
11 = CWGxA pin is driven to ‘1’, regardless of the setting of the GxPOLA bit
10 = CWGxA pin is driven to ‘0’, regardless of the setting of the GxPOLA bit
01 = CWGxA pin is tri-stated
00 = CWGxA pin is driven to its inactive state after the selected dead-band interval; GxPOLA will still
control the polarity of the output
bit 3 Unimplemented: Read as ‘0’
bit 2-0 GxIS<2:0>: CWGx Input Source Select bits
111 =Reserved
110 =Reserved
101 =Reserved
100 = PWM3 – PWM3_out
011 = PWM2 – PWM2_out
010 = PWM1 – PWM1_out
001 =Reserved
000 = Comparator C1 – C1OUT_async
PIC12(L)F1571/2
DS40001723D-page 240 2013-2015 Microchip Technology Inc.
REGISTER 23-3: CWGxCON2: CWGx CONTROL REGISTER 2
R/W-0/0 R/W-0/0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 U-0
GxASE GxARSEN — — — GxASDSC1 GxASDSFLT —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit
u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets
bit 7 GxASE: Auto-Shutdown Event Status bit
1 = An auto-shutdown event has occurred
0 = No auto-shutdown event has occurred
bit 6 GxARSEN: Auto-Restart Enable bit
1 = Auto-restart is enabled
0 = Auto-restart is disabled
bit 5-3 Unimplemented: Read as ‘0’
bit 2 GxASDSC1: CWGx Auto-Shutdown on Comparator C1 Enable bit
1 = Shutdown when Comparator C1 output (C1OUT_async) is high
0 = Comparator C1 output has no effect on shutdown
bit 1 GxASDSFLT: CWGx Auto-Shutdown on FLT Enable bit
1 = Shutdown when CWG1FLT input is low
0 =CWG1FLT
input has no effect on shutdown
bit 0 Unimplemented: Read as ‘0’
2013-2015 Microchip Technology Inc. DS40001723D-page 241
PIC12(L)F1571/2
REGISTER 23-4: CWGxDBR: CWGx COMPLEMENTARY WAVEFORM GENERATOR RISING
DEAD-BAND COUNT REGISTER
REGISTER 23-5: CWGxDBF: CWGx COMPLEMENTARY WAVEFORM GENERATOR FALLING
DEAD-BAND COUNT REGISTER
U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
— — CWGxDBR<5:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 CWGxDBR<5:0>: Complementary Waveform Generator (CWGx) Rising Counts bits
11 1111 = 63-64 counts of dead band
11 1110 = 62-63 counts of dead band
•
•
•
00 0010 = 2-3 counts of dead band
00 0001 = 1-2 counts of dead band
00 0000 = 0 counts of dead band
U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u
——CWGxDBF<5:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 CWGxDBF<5:0>: Complementary Waveform Generator (CWGx) Falling Counts bits
11 1111 = 63-64 counts of dead band
11 1110 = 62-63 counts of dead band
•
•
•
00 0010 = 2-3 counts of dead band
00 0001 = 1-2 counts of dead band
00 0000 = 0 counts of dead band; dead-band generation is bypassed
PIC12(L)F1571/2
DS40001723D-page 242 2013-2015 Microchip Technology Inc.
TABLE 23-2: SUMMARY OF REGISTERS ASSOCIATED WITH CWG
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register
on Page
ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 114
CWG1CON0 G1EN G1OEB G1OEA G1POLB G1POLA ——G1CS0238
CWG1CON1 G1ASDLB<1:0> G1ASDLA<1:0> ——G1IS<1:0>239
CWG1CON2 G1ASE G1ARSEN — — — G1ASDSC1 G1ASDSFLT —240
CWG1DBF ——CWG1DBF<5:0>241
CWG1DBR ——CWG1DBR<5:0>241
TRISA — — TRISA<5:4> —(1) TRISA2 TRISA<1:0> 113
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the CWG.
Note 1: Unimplemented, read as ‘1’.
2013-2015 Microchip Technology Inc. DS40001723D-page 243
PIC12(L)F1571/2
24.0 IN-CIRCUIT SERIAL
PROGRAMMING™ (ICSP™)
ICSP™ programming allows customers to manufacture
circuit boards with unprogrammed devices. Programming
can be done after the assembly process, allowing the
device to be programmed with the most recent firmware
or a custom firmware. Five pins are needed for ICSP™
programming:
• ICSPCLK
• ICSPDAT
•MCLR
/VPP
•VDD
•VSS
In Program/Verify mode, the program memory, User IDs
and the Configuration Words are programmed through
serial communications. The ICSPDAT pin is a bidirec-
tional I/O used for transferring the serial data and the
ICSPCLK pin is the clock input. For more information on
ICSP™, refer to the “PIC12(L)F1501/PIC16(L)F150X
Memory Programming Specification” (DS41573).
24.1 High-Voltage Programming Entry
Mode
The device is placed into High-Voltage Programming
Entry mode by holding the ICSPCLK and ICSPDAT pins
low, then raising the voltage on MCLR/VPP to VIHH.
24.2 Low-Voltage Programming Entry
Mode
The Low-Voltage Programming Entry mode allows the
PIC® MCUs (Flash) to be programmed using VDD only,
without high voltage. When the LVP bit of the
Configuration Words is set to ‘1’, the ICSP Low-Voltage
Programming Entry mode is enabled. To disable the
Low-Voltage ICSP mode, the LVP bit must be
programmed to ‘0’.
Entry into the Low-Voltage Programming Entry mode
requires the following steps:
1. MCLR is brought to VIL.
2. A 32-bit key sequence is presented on
ICSPDAT while clocking ICSPCLK.
Once the key sequence is complete, MCLR must be
held at VIL for as long as Program/Verify mode is to be
maintained.
If Low-Voltage Programming is enabled (LVP = 1), the
MCLR Reset function is automatically enabled and
cannot be disabled. See Section 6.5 “MCLR” for more
information.
The LVP bit can only be reprogrammed to ‘0’ by using
the High-Voltage Programming mode.
24.3 Common Programming Interfaces
Connection to a target device is typically done through
an ICSP™ header. A commonly found connector on
development tools is the RJ-11 in the 6P6C (6-pin,
6-connector) configuration. See Figure 24-1.
FIGURE 24-1: ICD RJ-11 STYLE
CONNECTOR INTERFACE
Another connector often found in use with the PICkit™
programmers is a standard 6-pin header with 0.1 inch
spacing. Refer to Figure 24-2.
1
2
3
4
5
6
Target
Bottom Side
PC Board
VPP/MCLR VSS
ICSPCLK
VDD
ICSPDAT
NC
Pin Description*
1 = VPP/MCLR
2 = VDD Target
3 = VSS (ground)
4 = ICSPDAT
5 = ICSPCLK
6 = No Connect
PIC12(L)F1571/2
DS40001723D-page 244 2013-2015 Microchip Technology Inc.
FIGURE 24-2: PICkit™ PROGRAMMER STYLE CONNECTOR INTERFACE
For additional interface recommendations, refer to your
specific device programmer manual prior to PCB
design.
It is recommended that isolation devices be used to
separate the programming pins from other circuitry.
The type of isolation is highly dependent on the specific
application and may include devices, such as resistors,
diodes or even jumpers. See Figure 24-3 for more
information.
FIGURE 24-3: TYPICAL CONNECTION FOR ICSP™ PROGRAMMING
1
3
5
6
4
2
Pin 1 Indicator
Pin Description*
1=V
PP/MCLR
2=V
DD Target
3=V
SS (ground)
4 = ICSPDAT
5 = ICSPCLK
6 = No connect
* The 6-pin header (0.100" spacing) accepts 0.025" square pins
Rev. 10-000128A
7/30/2013
Device to be
Programmed
VDD VDD
VSS VSS
VPP MCLR/VPP
VDD
Data
Clock
ICSPDAT
ICSPCLK
***
External
Programming
Signals
To Normal Connections
* Isolation devices (as required).
Rev. 10-000129A
7/30/2013
2013-2015 Microchip Technology Inc. DS40001723D-page 245
PIC12(L)F1571/2
25.0 INSTRUCTION SET SUMMARY
Each instruction is a 14-bit word containing the opera-
tion code (opcode) and all required operands. The
opcodes are broken into three broad categories.
• Byte-Oriented
• Bit-Oriented
• Literal and Control
The literal and control category contains the most
varied instruction word format.
Table 25-3 lists the instructions recognized by the
MPASM™ assembler.
All instructions are executed within a single instruction
cycle, with the following exceptions, which may take
two or three cycles:
• Subroutine takes two cycles (CALL, CALLW)
• Returns from interrupts or subroutines take two
cycles (RETURN, RETLW, RETFIE)
• Program branching takes two cycles (GOTO, BRA,
BRW, BTFSS, BTFSC, DECFSZ, INCSFZ)
• One additional instruction cycle will be used when
any instruction references an indirect file register
and the file select register is pointing to program
memory
One instruction cycle consists of 4 oscillator cycles; for
an oscillator frequency of 4 MHz, this gives a nominal
instruction execution rate of 1 MHz.
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit.
25.1 Read-Modify-Write Operations
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified and
the result is stored according to either the instruction or
the destination designator, ‘d’. A read operation is
performed on a register even if the instruction writes to
that register.
TABLE 25-1: OPCODE FIELD
DESCRIPTIONS
TABLE 25-2: ABBREVIATION
DESCRIPTIONS
Field Description
f Register file address (0x00 to 0x7F).
W Working register (accumulator).
b Bit address within an 8-bit file register.
k Literal field, constant data or label.
x Don’t care location (= 0 or 1).
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
d Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
n FSR or INDF number (0-1).
mm Pre-Post Increment-Decrement mode
selection.
Field Description
PC Program Counter
TO Time-out bit
C Carry bit
DC Digit Carry bit
Z Zero bit
PD Power-Down bit
PIC12(L)F1571/2
DS40001723D-page 246 2013-2015 Microchip Technology Inc.
FIGURE 25-1: GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13 8 7 6 0
d = 0 for destination W
OPCODE d f (FILE #)
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13 10 9 7 6 0
OPCODE b (BIT #) f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
13 8 7 0
OPCODE k (literal)
k = 8-bit immediate value
13 11 10 0
OPCODE k (literal)
k = 11-bit immediate value
General
CALL and GOTO instructions only
MOVLP instruction only
13 5 4 0
OPCODE k (literal)
k = 5-bit immediate value
MOVLB instruction only
13 9 8 0
OPCODE k (literal)
k = 9-bit immediate value
BRA instruction only
FSR Offset instructions
13 7 6 5 0
OPCODE n k (literal)
n = appropriate FSR
FSR Increment instructions
13 7 6 0
OPCODE k (literal)
k = 7-bit immediate value
13 3 2 1 0
OPCODE n m (mode)
n = appropriate FSR
m = 2-bit mode value
k = 6-bit immediate value
13 0
OPCODE
OPCODE only
2013-2015 Microchip Technology Inc. DS40001723D-page 247
PIC12(L)F1571/2
TABLE 25-3: ENHANCED MID-RANGE INSTRUCTION SET
Mnemonic,
Operands Description Cycles
14-Bit Opcode Status
Affected Notes
MSb LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ADDWFC
ANDWF
ASRF
LSLF
LSRF
CLRF
CLRW
COMF
DECF
INCF
IORWF
MOVF
MOVWF
RLF
RRF
SUBWF
SUBWFB
SWAPF
XORWF
f, d
f, d
f, d
f, d
f, d
f, d
f
–
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
Add W and f
Add with Carry W and f
AND W with f
Arithmetic Right Shift
Logical Left Shift
Logical Right Shift
Clear f
Clear W
Complement f
Decrement f
Increment f
Inclusive OR W with f
Move f
Move W to f
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Subtract with Borrow W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
00
11
00
11
11
11
00
00
00
00
00
00
00
00
00
00
00
11
00
00
0111
1101
0101
0111
0101
0110
0001
0001
1001
0011
1010
0100
1000
0000
1101
1100
0010
1011
1110
0110
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0000
dfff
dfff
dfff
dfff
dfff
1fff
dfff
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
00xx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
C, DC, Z
C, DC, Z
Z
C, Z
C, Z
C, Z
Z
Z
Z
Z
Z
Z
Z
C
C
C, DC, Z
C, DC, Z
Z
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
BYTE-ORIENTED SKIP OPERATIONS
DECFSZ
INCFSZ
f, d
f, d
Decrement f, Skip if 0
Increment f, Skip if 0
1(2)
1(2)
00
00 1011
1111 dfff
dfff ffff
ffff
1, 2
1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
f, b
f, b
Bit Clear f
Bit Set f
1
1
01
01 00bb
01bb bfff
bfff ffff
ffff
2
2
BIT-ORIENTED SKIP OPERATIONS
BTFSC
BTFSS
f, b
f, b
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1 (2)
1 (2)
01
01 10bb
11bb bfff
bfff ffff
ffff
1, 2
1, 2
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
MOVLB
MOVLP
MOVLW
SUBLW
XORLW
k
k
k
k
k
k
k
k
Add literal and W
AND literal with W
Inclusive OR literal with W
Move literal to BSR
Move literal to PCLATH
Move literal to W
Subtract W from literal
Exclusive OR literal with W
1
1
1
1
1
1
1
1
11
11
11
00
11
11
11
11
1110
1001
1000
0000
0001
0000
1100
1010
kkkk
kkkk
kkkk
001k
1kkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
C, DC, Z
Z
Z
C, DC, Z
Z
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one
additional instruction cycle.
3: See the table in the MOVIW and MOVWI instruction descriptions.
PIC12(L)F1571/2
DS40001723D-page 248 2013-2015 Microchip Technology Inc.
TABLE 25-3: ENHANCED MID-RANGE INSTRUCTION SET (CONTINUED)
Mnemonic,
Operands Description Cycles
14-Bit Opcode Status
Affected Notes
MSb LSb
CONTROL OPERATIONS
BRA
BRW
CALL
CALLW
GOTO
RETFIE
RETLW
RETURN
k
–
k
–
k
k
k
–
Relative Branch
Relative Branch with W
Call Subroutine
Call Subroutine with W
Go to address
Return from interrupt
Return with literal in W
Return from Subroutine
2
2
2
2
2
2
2
2
11
00
10
00
10
00
11
00
001k
0000
0kkk
0000
1kkk
0000
0100
0000
kkkk
0000
kkkk
0000
kkkk
0000
kkkk
0000
kkkk
1011
kkkk
1010
kkkk
1001
kkkk
1000
INHERENT OPERATIONS
CLRWDT
NOP
OPTION
RESET
SLEEP
TRIS
–
–
–
–
–
f
Clear Watchdog Timer
No Operation
Load OPTION_REG register with W
Software device Reset
Go into Standby mode
Load TRIS register with W
1
1
1
1
1
1
00
00
00
00
00
00
0000
0000
0000
0000
0000
0000
0110
0000
0110
0000
0110
0110
0100
0000
0010
0001
0011
0fff
TO, PD
TO, PD
C COMPILER OPTIMIZED
ADDFSR
MOVIW
MOVWI
n, k
n mm
k[n]
n mm
k[n]
Add Literal k to FSRn
Move Indirect FSRn to W with pre/post inc/dec
modifier, mm
Move INDFn to W, Indexed Indirect.
Move W to Indirect FSRn with pre/post inc/dec
modifier, mm
Move W to INDFn, Indexed Indirect.
1
1
1
1
1
11
00
11
00
11
0001
0000
1111
0000
1111
0nkk
0001
0nkk
0001
1nkk
kkkk
0nmm
kkkk
1nmm
kkkk
Z
Z
2, 3
2
2, 3
2
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
3: See the table in the MOVIW and MOVWI instruction descriptions.
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25.2 Instruction Descriptions
ADDFSR Add Literal to FSRn
Syntax: [ label ] ADDFSR FSRn, k
Operands: -32 k 31
n [ 0, 1]
Operation: FSR(n) + k FSR(n)
Status Affected: None
Description: The signed 6-bit literal ‘k’ is added to
the contents of the FSRnH:FSRnL
register pair.
FSRn is limited to the range 0000h -
FFFFh. Moving beyond these bounds
will cause the FSR to wraparound.
ADDLW Add literal and W
Syntax: [ label ] ADDLW k
Operands: 0 k 255
Operation: (W) + k (W)
Status Affected: C, DC, Z
Description: The contents of the W register are
added to the 8-bit literal ‘k’ and the
result is placed in the W register.
ADDWF Add W and f
Syntax: [ label ] ADDWF f,d
Operands: 0 f 127
d 0,1
Operation: (W) + (f) (destination)
Status Affected: C, DC, Z
Description: Add the contents of the W register
with register ‘f’. If ‘d’ is ‘0’, the result is
stored in the W register. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
ADDWFC ADD W and CARRY bit to f
Syntax: [ label ] ADDWFC f {,d}
Operands: 0 f 127
d [0,1]
Operation: (W) + (f) + (C) dest
Status Affected: C, DC, Z
Description: Add W, the Carry flag and data mem-
ory location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory location ‘f’.
ANDLW AND literal with W
Syntax: [ label ] ANDLW k
Operands: 0 k 255
Operation: (W) .AND. (k) (W)
Status Affected: Z
Description: The contents of W register are
AND’ed with the 8-bit literal ‘k’. The
result is placed in the W register.
ANDWF AND W with f
Syntax: [ label ] ANDWF f,d
Operands: 0 f 127
d 0,1
Operation: (W) .AND. (f) (destination)
Status Affected: Z
Description: AND the W register with register ‘f’. If
‘d’ is ‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
ASRF Arithmetic Right Shift
Syntax: [ label ] ASRF f {,d}
Operands: 0 f 127
d [0,1]
Operation: (f<7>) dest<7>
(f<7:1>) dest<6:0>,
(f<0>) C,
Status Affected: C, Z
Description: The contents of register ‘f’ are shifted
one bit to the right through the Carry
flag. The MSb remains unchanged. If
‘d’ is ‘0’, the result is placed in W. If ‘d’
is ‘1’, the result is stored back in
register ‘f’.
register f C
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BCF Bit Clear f
Syntax: [ label ] BCF f,b
Operands: 0 f 127
0 b 7
Operation: 0 (f<b>)
Status Affected: None
Description: Bit ‘b’ in register ‘f’ is cleared.
BRA Relative Branch
Syntax: [ label ] BRA label
[ label ] BRA $+k
Operands: -256 label - PC + 1 255
-256 k 255
Operation: (PC) + 1 + k PC
Status Affected: None
Description: Add the signed 9-bit literal ‘k’ to the
PC. Since the PC will have incre-
mented to fetch the next instruction,
the new address will be PC + 1 + k.
This instruction is a 2-cycle instruc-
tion. This branch has a limited range.
BRW Relative Branch with W
Syntax: [ label ] BRW
Operands: None
Operation: (PC) + (W) PC
Status Affected: None
Description: Add the contents of W (unsigned) to
the PC. Since the PC will have incre-
mented to fetch the next instruction,
the new address will be PC + 1 + (W).
This instruction is a 2-cycle instruc-
tion.
BSF Bit Set f
Syntax: [ label ] BSF f,b
Operands: 0 f 127
0 b 7
Operation: 1 (f<b>)
Status Affected: None
Description: Bit ‘b’ in register ‘f’ is set.
BTFSC Bit Test f, Skip if Clear
Syntax: [ label ] BTFSC f,b
Operands: 0 f 127
0 b 7
Operation: skip if (f<b>) = 0
Status Affected: None
Description: If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
If bit ‘b’, in register ‘f’, is ‘0’, the next
instruction is discarded, and a NOP is
executed instead, making this a
2-cycle instruction.
BTFSS Bit Test f, Skip if Set
Syntax: [ label ] BTFSS f,b
Operands: 0 f 127
0 b < 7
Operation: skip if (f<b>) = 1
Status Affected: None
Description: If bit ‘b’ in register ‘f’ is ‘0’, the next
instruction is executed.
If bit ‘b’ is ‘1’, then the next
instruction is discarded and a NOP is
executed instead, making this a
2-cycle instruction.
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CALL Call Subroutine
Syntax: [ label ] CALL k
Operands: 0 k 2047
Operation: (PC)+ 1 TOS,
k PC<10:0>,
(PCLATH<6:3>) PC<14:11>
Status Affected: None
Description: Call Subroutine. First, return address
(PC + 1) is pushed onto the stack.
The 11-bit immediate address is
loaded into PC bits <10:0>. The upper
bits of the PC are loaded from
PCLATH. CALL is a 2-cycle instruc-
tion.
CALLW Subroutine Call With W
Syntax: [ label ] CALLW
Operands: None
Operation: (PC) +1 TOS,
(W) PC<7:0>,
(PCLATH<6:0>) PC<14:8>
Status Affected: None
Description: Subroutine call with W. First, the
return address (PC + 1) is pushed
onto the return stack. Then, the con-
tents of W is loaded into PC<7:0>,
and the contents of PCLATH into
PC<14:8>. CALLW is a 2-cycle
instruction.
CLRF Clear f
Syntax: [ label ] CLRF f
Operands: 0 f 127
Operation: 00h (f)
1 Z
Status Affected: Z
Description: The contents of register ‘f’ are cleared
and the Z bit is set.
CLRW Clear W
Syntax: [ label ] CLRW
Operands: None
Operation: 00h (W)
1 Z
Status Affected: Z
Description: W register is cleared. Zero bit (Z) is
set.
CLRWDT Clear Watchdog Timer
Syntax: [ label ] CLRWDT
Operands: None
Operation: 00h WDT
0 WDT prescaler,
1 TO
1 PD
Status Affected: TO, PD
Description: CLRWDT instruction resets the Watch-
dog Timer. It also resets the prescaler
of the WDT.
Status bits TO and PD are set.
COMF Complement f
Syntax: [ label ] COMF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) (destination)
Status Affected: Z
Description: The contents of register ‘f’ are com-
plemented. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
DECF Decrement f
Syntax: [ label ] DECF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) - 1 (destination)
Status Affected: Z
Description: Decrement register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
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DECFSZ Decrement f, Skip if 0
Syntax: [ label ] DECFSZ f,d
Operands: 0 f 127
d [0,1]
Operation: (f) - 1 (destination);
skip if result = 0
Status Affected: None
Description: The contents of register ‘f’ are decre-
mented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’.
If the result is ‘1’, the next instruction is
executed. If the result is ‘0’, then a
NOP is executed instead, making it a
2-cycle instruction.
GOTO Unconditional Branch
Syntax: [ label ] GOTO k
Operands: 0 k 2047
Operation: k PC<10:0>
PCLATH<6:3> PC<14:11>
Status Affected: None
Description: GOTO is an unconditional branch. The
11-bit immediate value is loaded into
PC bits <10:0>. The upper bits of PC
are loaded from PCLATH<4:3>. GOTO
is a 2-cycle instruction.
INCF Increment f
Syntax: [ label ] INCF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) + 1 (destination)
Status Affected: Z
Description: The contents of register ‘f’ are incre-
mented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’.
INCFSZ Increment f, Skip if 0
Syntax: [ label ] INCFSZ f,d
Operands: 0 f 127
d [0,1]
Operation: (f) + 1 (destination),
skip if result = 0
Status Affected: None
Description: The contents of register ‘f’ are incre-
mented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’.
If the result is ‘1’, the next instruction is
executed. If the result is ‘0’, a NOP is
executed instead, making it a 2-cycle
instruction.
IORLW Inclusive OR literal with W
Syntax: [ label ] IORLW k
Operands: 0 k 255
Operation: (W) .OR. k (W)
Status Affected: Z
Description: The contents of the W register are
OR’ed with the 8-bit literal ‘k’. The
result is placed in the W register.
IORWF Inclusive OR W with f
Syntax: [ label ] IORWF f,d
Operands: 0 f 127
d [0,1]
Operation: (W) .OR. (f) (destination)
Status Affected: Z
Description: Inclusive OR the W register with regis-
ter ‘f’. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
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LSLF Logical Left Shift
Syntax: [ label ] LSLF f {,d}
Operands: 0 f 127
d [0,1]
Operation: (f<7>) C
(f<6:0>) dest<7:1>
0 dest<0>
Status Affected: C, Z
Description: The contents of register ‘f’ are shifted
one bit to the left through the Carry flag.
A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’,
the result is placed in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
LSRF Logical Right Shift
Syntax: [ label ] LSRF f {,d}
Operands: 0 f 127
d [0,1]
Operation: 0 dest<7>
(f<7:1>) dest<6:0>,
(f<0>) C,
Status Affected: C, Z
Description: The contents of register ‘f’ are shifted
one bit to the right through the Carry
flag. A ‘0’ is shifted into the MSb. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is stored back in register ‘f’.
register f 0
C
register f C0
MOVF Move f
Syntax: [ label ] MOVF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) (dest)
Status Affected: Z
Description: The contents of register f is moved to
a destination dependent upon the
status of d. If d = 0,
destination is W register. If d = 1, the
destination is file register f itself. d = 1
is useful to test a file register since
status flag Z is affected.
Words: 1
Cycles: 1
Example: MOVF FSR, 0
After Instruction
W = value in FSR register
Z= 1
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MOVIW Move INDFn to W
Syntax: [ label ] MOVIW ++FSRn
[ label ] MOVIW --FSRn
[ label ] MOVIW FSRn++
[ label ] MOVIW FSRn--
[ label ] MOVIW k[FSRn]
Operands: n [0,1]
mm [00,01, 10, 11]
-32 k 31
Operation: INDFn W
Effective address is determined by
• FSR + 1 (preincrement)
• FSR - 1 (predecrement)
• FSR + k (relative offset)
After the Move, the FSR value will be
either:
• FSR + 1 (all increments)
• FSR - 1 (all decrements)
• Unchanged
Status Affected: Z
Mode Syntax mm
Preincrement ++FSRn 00
Predecrement --FSRn 01
Postincrement FSRn++ 10
Postdecrement FSRn-- 11
Description: This instruction is used to move data
between W and one of the indirect
registers (INDFn). Before/after this
move, the pointer (FSRn) is updated by
pre/post incrementing/decrementing it.
Note: The INDFn registers are not
physical registers. Any instruction that
accesses an INDFn register actually
accesses the register at the address
specified by the FSRn.
FSRn is limited to the range 0000h -
FFFFh. Incrementing/decrementing it
beyond these bounds will cause it to
wraparound.
MOVLB Move literal to BSR
Syntax: [ label ] MOVLB k
Operands: 0 k 31
Operation: k BSR
Status Affected: None
Description: The 5-bit literal ‘k’ is loaded into the
Bank Select Register (BSR).
MOVLP Move literal to PCLATH
Syntax: [ label ] MOVLP k
Operands: 0 k 127
Operation: k PCLATH
Status Affected: None
Description: The 7-bit literal ‘k’ is loaded into the
PCLATH register.
MOVLW Move literal to W
Syntax: [ label ] MOVLW k
Operands: 0 k 255
Operation: k (W)
Status Affected: None
Description: The 8-bit literal ‘k’ is loaded into W reg-
ister. The “don’t cares” will assemble as
‘0’s.
Words: 1
Cycles: 1
Example: MOVLW 0x5A
After Instruction
W = 0x5A
MOVWF Move W to f
Syntax: [ label ] MOVWF f
Operands: 0 f 127
Operation: (W) (f)
Status Affected: None
Description: Move data from W register to register
‘f’.
Words: 1
Cycles: 1
Example: MOVWF OPTION_REG
Before Instruction
OPTION_REG = 0xFF
W = 0x4F
After Instruction
OPTION_REG = 0x4F
W = 0x4F
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MOVWI Move W to INDFn
Syntax: [ label ] MOVWI ++FSRn
[ label ] MOVWI --FSRn
[ label ] MOVWI FSRn++
[ label ] MOVWI FSRn--
[ label ] MOVWI k[FSRn]
Operands: n [0,1]
mm [00,01, 10, 11]
-32 k 31
Operation: W INDFn
Effective address is determined by
• FSR + 1 (preincrement)
• FSR - 1 (predecrement)
• FSR + k (relative offset)
After the Move, the FSR value will be
either:
• FSR + 1 (all increments)
• FSR - 1 (all decrements)
Unchanged
Status Affected: None
Mode Syntax mm
Preincrement ++FSRn 00
Predecrement --FSRn 01
Postincrement FSRn++ 10
Postdecrement FSRn-- 11
Description: This instruction is used to move data
between W and one of the indirect
registers (INDFn). Before/after this
move, the pointer (FSRn) is updated by
pre/post incrementing/decrementing it.
Note: The INDFn registers are not
physical registers. Any instruction that
accesses an INDFn register actually
accesses the register at the address
specified by the FSRn.
FSRn is limited to the range 0000h -
FFFFh. Incrementing/decrementing it
beyond these bounds will cause it to
wraparound.
The increment/decrement operation on
FSRn WILL NOT affect any Status bits.
NOP No Operation
Syntax: [ label ] NOP
Operands: None
Operation: No operation
Status Affected: None
Description: No operation.
Words: 1
Cycles: 1
Example: NOP
OPTION Load OPTION_REG Register
with W
Syntax: [ label ] OPTION
Operands: None
Operation: (W) OPTION_REG
Status Affected: None
Description: Move data from W register to
OPTION_REG register.
RESET Software Reset
Syntax: [ label ] RESET
Operands: None
Operation: Execute a device Reset. Resets the
nRI flag of the PCON register.
Status Affected: None
Description: This instruction provides a way to
execute a hardware Reset by soft-
ware.
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RETFIE Return from Interrupt
Syntax: [ label ] RETFIE
Operands: None
Operation: TOS PC,
1 GIE
Status Affected: None
Description: Return from Interrupt. Stack is POPed
and Top-of-Stack (TOS) is loaded in
the PC. Interrupts are enabled by
setting Global Interrupt Enable bit,
GIE (INTCON<7>). This is a 2-cycle
instruction.
Words: 1
Cycles: 2
Example: RETFIE
After Interrupt
PC = TOS
GIE = 1
RETLW Return with literal in W
Syntax: [ label ] RETLW k
Operands: 0 k 255
Operation: k (W);
TOS PC
Status Affected: None
Description: The W register is loaded with the 8-bit
literal ‘k’. The Program Counter is
loaded from the top of the stack (the
return address). This is a 2-cycle
instruction.
Words: 1
Cycles: 2
Example:
TABLE
CALL TABLE;W contains table
;offset value
• ;W now has table value
•
•
ADDWF PC ;W = offset
RETLW k1 ;Begin table
RETLW k2 ;
•
•
•
RETLW kn ; End of table
Before Instruction
W = 0x07
After Instruction
W = value of k8
RETURN Return from Subroutine
Syntax: [ label ] RETURN
Operands: None
Operation: TOS PC
Status Affected: None
Description: Return from subroutine. The stack is
POPed and the top of the stack (TOS)
is loaded into the Program Counter.
This is a 2-cycle instruction.
RLF Rotate Left f through Carry
Syntax: [ label ] RLF f,d
Operands: 0 f 127
d [0,1]
Operation: See description below
Status Affected: C
Description: The contents of register ‘f’ are rotated
one bit to the left through the Carry
flag. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
Words: 1
Cycles: 1
Example: RLF REG1,0
Before Instruction
REG1 = 1110 0110
C=0
After Instruction
REG1 = 1110 0110
W = 1100 1100
C=1
Register fC
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RRF Rotate Right f through Carry
Syntax: [ label ] RRF f,d
Operands: 0 f 127
d [0,1]
Operation: See description below
Status Affected: C
Description: The contents of register ‘f’ are rotated
one bit to the right through the Carry
flag. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
SLEEP Enter Sleep mode
Syntax: [ label ]SLEEP
Operands: None
Operation: 00h WDT,
0 WDT prescaler,
1 TO,
0 PD
Status Affected: TO, PD
Description: The power-down Status bit, PD is
cleared. Time-out Status bit, TO is
set. Watchdog Timer and its pres-
caler are cleared.
The processor is put into Sleep mode
with the oscillator stopped.
Register fC
SUBLW Subtract W from literal
Syntax: [ label ]SUBLW k
Operands: 0 k 255
Operation: k - (W) W)
Status Affected: C, DC, Z
Description: The W register is subtracted (2’s com-
plement method) from the 8-bit literal
‘k’. The result is placed in the W regis-
ter.
SUBWF Subtract W from f
Syntax: [ label ] SUBWF f,d
Operands: 0 f 127
d [0,1]
Operation: (f) - (W) destination)
Status Affected: C, DC, Z
Description: Subtract (2’s complement method) W
register from register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f.
SUBWFB Subtract W from f with Borrow
Syntax: SUBWFB f {,d}
Operands: 0 f 127
d [0,1]
Operation: (f) – (W) – (B) dest
Status Affected: C, DC, Z
Description: Subtract W and the BORROW flag
(CARRY) from register ‘f’ (2’s comple-
ment method). If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
C = 0W k
C = 1W k
DC = 0W<3:0> k<3:0>
DC = 1W<3:0> k<3:0>
C = 0W f
C = 1W f
DC = 0W<3:0> f<3:0>
DC = 1W<3:0> f<3:0>
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SWAPF Swap Nibbles in f
Syntax: [ label ] SWAPF f,d
Operands: 0 f 127
d [0,1]
Operation: (f<3:0>) (destination<7:4>),
(f<7:4>) (destination<3:0>)
Status Affected: None
Description: The upper and lower nibbles of regis-
ter ‘f’ are exchanged. If ‘d’ is ‘0’, the
result is placed in the W register. If ‘d’
is ‘1’, the result is placed in register ‘f’.
TRIS Load TRIS Register with W
Syntax: [ label ] TRIS f
Operands: 5 f 7
Operation: (W) TRIS register ‘f’
Status Affected: None
Description: Move data from W register to TRIS
register.
When ‘f’ = 5, TRISA is loaded.
When ‘f’ = 6, TRISB is loaded.
When ‘f’ = 7, TRISC is loaded.
XORLW Exclusive OR literal with W
Syntax: [ label ]XORLW k
Operands: 0 k 255
Operation: (W) .XOR. k W)
Status Affected: Z
Description: The contents of the W register are
XOR’ed with the 8-bit
literal ‘k’. The result is placed in the
W register.
XORWF Exclusive OR W with f
Syntax: [ label ] XORWF f,d
Operands: 0 f 127
d [0,1]
Operation: (W) .XOR. (f) destination)
Status Affected: Z
Description: Exclusive OR the contents of the W
register with register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W register. If ‘d’
is ‘1’, the result is stored back in regis-
ter ‘f’.
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26.0 ELECTRICAL SPECIFICATIONS
26.1 Absolute Maximum Ratings(†)
Ambient temperature under bias............................................................................................................ -40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on pins with respect to VSS:
on VDD pin
PIC12F1571/2 ................................................................................................................. -0.3V to +6.5V
PIC12LF1571/2 ............................................................................................................... -0.3V to +4.0V
on MCLR pin ................................................................................................................................. -0.3V to +9.0V
on all other pins .................................................................................................................. -0.3V to (VDD + 0.3V)
Maximum current:
on VSS pin(1)
-40°C TA +85°C .................................................................................................................... 250 mA
+85°C TA +125°C ................................................................................................................... 85 mA
on VDD pin(1)
-40°C TA +85°C .................................................................................................................... 250 mA
+85°C TA +125°C ................................................................................................................... 85 mA
Sunk by any standard I/O pin ..................................................................................................................... 50 mA
Sourced by any standard I/O pin ................................................................................................................ 50 mA
Clamp current, IK (VPIN < 0 or VPIN > VDD) ......................................................................................................... 20 mA
Total power dissipation(2) .....................................................................................................................................800 mW
Note 1: Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be
limited by the device package power dissipation characterizations, see Table 26-6: “Thermal
Characteristics” to calculate device specifications.
2: Power dissipation is calculated as follows: PDIS = VDD x {IDD – IOH} + {(VDD – VOH) x IOH} + (VOl x IOL).
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.
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26.2 Standard Operating Conditions
The standard operating conditions for any device are defined as:
Operating Voltage: VDDMIN VDD VDDMAX
Operating Temperature: TA_MIN TA TA_MAX
VDD — Operating Supply Voltage(1)
PIC12LF1571/2
VDDMIN (FOSC 16 MHz)............................................................................................................... +1.8V
VDDMIN (FOSC 32 MHz)............................................................................................................... +2.5V
VDDMAX .......................................................................................................................................... +3.6V
PIC12F1571/2
VDDMIN (FOSC 16 MHz)............................................................................................................... +2.3V
VDDMIN (FOSC 32 MHz)............................................................................................................... +2.5V
VDDMAX .......................................................................................................................................... +5.5V
TA — Operating Ambient Temperature Range
Industrial Temperature
TA_MIN ............................................................................................................................................ -40°C
TA_MAX .......................................................................................................................................... +85°C
Extended Temperature
TA_MIN ............................................................................................................................................ -40°C
TA_MAX ........................................................................................................................................ +125°C
Note 1: See Parameter D001, DS Characteristics: Supply Voltage.
2013-2015 Microchip Technology Inc. DS40001723D-page 261
PIC12(L)F1571/2
FIGURE 26-1: VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C, PIC12F1571/2 ONLY
FIGURE 26-2: VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C, PIC12LF1571/2 ONLY
Rev. 10-000130B
9/19/2013
5.5
2.5
2.3
01632
VDD (V)
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Tab le 26- 7 for each Oscillator mode’s supported frequencies.
Rev. 10-000131B
9/19/2013
3.6
2.5
1.8
01632
VDD (V)
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 26-7 for each Oscillator mode’s supported frequencies.
PIC12(L)F1571/2
DS40001723D-page 262 2013-2015 Microchip Technology Inc.
26.3 DC Characteristics
TABLE 26-1: SUPPLY VOLTAGE
PIC12LF1571/2 Standard Operating Conditions (unless otherwise stated)
PIC12F1571/2
Param.
No. Sym. Characteristic Min. Typ† Max. Units Conditions
D001 VDD Supply Voltage
VDDMIN
1.8
2.5
—
—
VDDMAX
3.6
3.6
V
V
FOSC 16 MHz
FOSC 32 MHz (Note 3)
D001 2.3
2.5
—
—
5.5
5.5
V
V
FOSC 16 MHz
FOSC 32 MHz (Note 3)
D002* VDR RAM Data Retention Voltage(1)
1.5 — — V Device in Sleep mode
D002* 1.7 — — V Device in Sleep mode
D002A* VPOR Power-on Reset Release Voltage(2)
—1.6— V
D002A* —1.6 — V
D002B* VPORR*Power-on Reset Rearm Voltage(2)
—0.8— V
D002B* —1.5 — V
D003 VFVR Fixed Voltage Reference Voltage — 1.024 — V -40°C TA +85°C
D003A VADFVR FVR Gain Voltage Accuracy for
ADC -4 — +4 % 1x VFVR, ADFVR = 01, VDD 2.5V
2x VFVR, ADFVR = 10, VDD 2.5V
4x VFVR, ADFVR = 11, VDD 4.75V
D003B VCDAFVR FVR Gain Voltage Accuracy for
Comparator -4 — +4 % 1x VFVR, CDAFVR = 01, VDD 2.5V
2x VFVR, CDAFVR = 10, VDD 2.5V
4x VFVR, CDAFVR = 11, VDD 4.75V
D004* SVDD VDD Rise Rate(2) 0.05 — — V/ms Ensures that the Power-on Reset
signal is released properly
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
2: See Figure 26-3, POR and POR Rearm with Slow Rising VDD.
3: PLL required for 32 MHz operation.
2013-2015 Microchip Technology Inc. DS40001723D-page 263
PIC12(L)F1571/2
FIGURE 26-3: POR AND POR REARM WITH SLOW RISING VDD
VDD
VPOR
VPORR
VSS
VSS
NPOR(1)
TPOR(2)
POR Rearm
Note 1: When NPOR is low, the device is held in Reset.
2: TPOR: 1 s typical.
3: TVLOW: 2.7 s typical.
TVLOW(3)
SVDD
PIC12(L)F1571/2
DS40001723D-page 264 2013-2015 Microchip Technology Inc.
TABLE 26-2: SUPPLY CURRENT (IDD)(1,2)
PIC12LF1571/2 Standard Operating Conditions (unless otherwise stated)
PIC12F1571/2
Param.
No.
Device
Characteristics Min. Typ† Max. Units
Conditions
VDD Note
D013 — 35 44 A1.8FOSC = 1 MHz,
External Clock (ECM),
Medium Power mode
—6069A3.0
D013 —68 93 A2.3 FOSC = 1 MHz,
External Clock (ECM),
Medium Power mode
—91 120 A3.0
—131 160 A5.0
D014 — 116 132 A1.8F
OSC = 4 MHz,
External Clock (ECM),
Medium Power mode
— 203 233 A3.0
D014 —174 221 A2.3 FOSC = 4 MHz,
External Clock (ECM),
Medium Power mode
—234 286 A3.0
—299 374 A5.0
D015 — 5.5 11 A1.8F
OSC = 31 kHz,
LFINTOSC,
-40°C TA +85°C
—7.312 A3.0
D015 —13 21 A2.3 FOSC = 31 kHz,
LFINTOSC,
-40°C TA +85°C
—15 24 A3.0
—17 25 A5.0
D016 — 111 151 A1.8F
OSC = 500 kHz,
MFINTOSC
— 133 176 A3.0
D016 —144 209 A2.3 FOSC = 500 kHz,
MFINTOSC
—162 237 A3.0
—216 288 A5.0
D017* — 0.5 0.6 mA 1.8 FOSC = 8 MHz,
HFINTOSC
— 0.7 0.9 mA 3.0
D017* —0.6 0.8 mA 2.3 FOSC = 8 MHz,
HFINTOSC
—0.8 0.9 mA 3.0
—0.9 1.0 mA 5.0
D018 — 0.7 0.8 mA 1.8 FOSC = 16 MHz,
HFINTOSC
— 1.1 1.2 mA 3.0
D018 —0.9 1.1 mA 2.3 FOSC = 16 MHz,
HFINTOSC
—1.1 1.3 mA 3.0
—1.3 1.5 mA 5.0
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: CLKIN = external square wave,
from rail-to-rail; all I/O pins tri-stated, pulled to VSS; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have
an impact on the current consumption.
3: PLL required for 32 MHz operation.
2013-2015 Microchip Technology Inc. DS40001723D-page 265
PIC12(L)F1571/2
D018A* — 2 2.4 mA 3.0 FOSC = 32 MHz,
HFINTOSC (Note 3)
D018A* —2.1 2.5 mA 3.0 FOSC = 32 MHz,
HFINTOSC (Note 3)
—2.2 2.6 mA 5.0
D019A — 1.7 1.9 mA 3.0 FOSC = 32 MHz,
External Clock (ECH),
High-Power mode (Note 3)
D019A —1.8 2mA 3.0 FOSC = 32 MHz,
External Clock (ECH),
High-Power mode (Note 3)
—1.9 2.3 mA 5.0
D019B — 2.2 5.9 A1.8FOSC = 32 kHz,
External Clock (ECL),
Low-Power mode
—4.38.3A3.0
D019B —12 20 A2.3 FOSC = 32 kHz,
External Clock (ECL),
Low-Power mode
—15 25 A3.0
—17 26 A5.0
D019C — 18 25 A1.8F
OSC = 500 kHz,
External Clock (ECL),
Low-Power mode
—3038A3.0
D019C —29 40 A2.3 FOSC = 500 kHz,
External Clock (ECL),
Low-Power mode
—37 51 A3.0
—42 53 A5.0
TABLE 26-2: SUPPLY CURRENT (IDD)(1,2) (CONTINUED)
PIC12LF1571/2 Standard Operating Conditions (unless otherwise stated)
PIC12F1571/2
Param.
No.
Device
Characteristics Min. Typ† Max. Units
Conditions
VDD Note
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: CLKIN = external square wave,
from rail-to-rail; all I/O pins tri-stated, pulled to VSS; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have
an impact on the current consumption.
3: PLL required for 32 MHz operation.
PIC12(L)F1571/2
DS40001723D-page 266 2013-2015 Microchip Technology Inc.
TABLE 26-3: POWER-DOWN CURRENTS (IPD)(1,2)
PIC12LF1571/2 Operating Conditions (unless otherwise stated)
Low-Power Sleep Mode
PIC12F1571/2 Low-Power Sleep Mode, VREGPM = 1
Param.
No. Device Characteristics Min. Typ† Max.
+85°C
Max.
+125°C Units
Conditions
VDD Note
D022 Base IPD — 0.020 0.6 2.6 A 1.8 WDT, BOR and FVR disabled,
all peripherals inactive,
VREGPM = 1
— 0.025 0.8 2.9 A3.0
D022 Base IPD —0.2 0.9 2.8 A2.3 WDT, BOR and FVR disabled,
all peripherals inactive,
Low-Power Sleep mode,
VREGPM = 1
—0.3 3.0 3.8 A3.0
—0.4 3.6 4.5 A5.0
D022A Base IPD — 9 14 15 A2.3 WDT, BOR and FVR disabled,
all peripherals inactive,
Normal Power Sleep mode,
VREGPM = 0
—11 19 21 A3.0
—12 21 22 A5.0
D023 — 0.3 0.8 2.9 A 1.8 WDT Current
— 0.5 1.1 3.5 A3.0
D023 —0.5 1.7 4.1 A2.3 WDT Current
—0.6 1.9 4.4 A3.0
—0.7 2.1 4.7 A5.0
D023A — 13 18 20 A 1.8 FVR Current
—22 28 29 A3.0
D023A —16 24 25 A2.3 FVR Current
—19 30 31 A3.0
—20 33 35 A5.0
D024 — 6.5 9 11 A 3.0 BOR Current
D024 —7.0 10 11 A3.0 BOR Current
—8.0 12 13 A5.0
D24A — 0.2 2 4 A 3.0 LPBOR Current
D24A —0.4 2 4 A3.0 LPBOR Current
—0.5 3 5 A5.0
D026 — 0.03 0.7 2.7 A 1.8 ADC Current (Note 3),
No conversion in progress
— 0.04 0.8 3 A3.0
D026 —0.2 1.3 3.8 A2.3 ADC Current (Note 3),
No conversion in progress
—0.3 1.4 3.9 A3.0
—0.4 1.5 4A5.0
D026A* — 250 — — A 1.8 ADC Current (Note 3),
Conversion in progress
—250 — — A3.0
D026A* —280 — — A2.3 ADC Current (Note 3),
Conversion in progress
—280 — — A3.0
—280 — — A5.0
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The peripheral current can be determined by subtracting the base IPD current from this limit. Max. values should be
used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VSS.
3: ADC clock source is FRC.
2013-2015 Microchip Technology Inc. DS40001723D-page 267
PIC12(L)F1571/2
D027 — 4 7 9 A 1.8 Comparator,
CxSP = 0
—4.2 8 10 A3.0
D027 —13 20 21 A2.3 Comparator,
CxSP = 0
—14 23 25 A3.0
—16 24 26 A5.0
D028A — 20 35 36 A 1.8 Comparator,
Normal Power, CxSP = 1
(Note 1)
—21 36 38 A3.0
D028A —28 47 48 A2.3 Comparator,
Normal Power, CxSP = 1,
VREGPM = 1 (Note 1)
—29 51 52 A3.0
—31 52 53 A5.0
TABLE 26-3: POWER-DOWN CURRENTS (IPD)(1,2) (CONTINUED)
PIC12LF1571/2 Operating Conditions (unless otherwise stated)
Low-Power Sleep Mode
PIC12F1571/2 Low-Power Sleep Mode, VREGPM = 1
Param.
No. Device Characteristics Min. Typ† Max.
+85°C
Max.
+125°C Units
Conditions
VDD Note
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The peripheral current can be determined by subtracting the base IPD current from this limit. Max. values should be
used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VSS.
3: ADC clock source is FRC.
PIC12(L)F1571/2
DS40001723D-page 268 2013-2015 Microchip Technology Inc.
TABLE 26-4: I/O PORTS
Standard Operating Conditions (unless otherwise stated)
Param.
No. Sym. Characteristic Min. Typ† Max. Units Conditions
VIL Input Low Voltage
I/O Ports:
D030 with TTL Buffer — — 0.8 V 4.5V VDD 5.5V
D030A — — 0.15 VDD V1.8V VDD 4.5V
D031 with Schmitt Trigger Buffer — — 0.2 VDD V2.0V VDD 5.5V
with I2C Levels — — 0.3 VDD V
with SMbus Levels — — 0.8 V 2.7V VDD 5.5V
D032 MCLR ——0.2VDD V
VIH Input High Voltage
I/O Ports:
D040 with TTL Buffer 2.0 — — V 4.5V VDD 5.5V
D040A 0.25 VDD + 0.8 — — V 1.8V VDD 4.5V
D041 with Schmitt Trigger Buffer 0.8 VDD ——V2.0V VDD 5.5V
with I2C Levels 0.7 VDD ——V
with SMbus Levels 2.1 — — V 2.7V VDD 5.5V
D042 MCLR 0.8 VDD ——V
IIL Input Leakage Current(1)
D060 I/O Ports — ± 5 ± 125 nA VSS VPIN VDD,
Pin at high-impedance, +85°C
— ± 5 ± 1000 nA VSS VPIN VDD,
Pin at high-impedance, +125°C
D061 MCLR(2) — ± 50 ± 200 nA VSS VPIN VDD,
Pin at high-impedance, +85°C
IPUR Weak Pull-up Current
D070* 25 100 200 AVDD = 3.3V, VPIN = VSS
25 140 300 AVDD = 5.0V, VPIN = VSS
VOL Output Low Voltage
D080 I/O Ports — — 0.6 V IOL = 8 mA, VDD = 5V
IOL = 6 mA, VDD = 3.3V
IOL = 1.8 mA, VDD = 1.8V
VOH Output High Voltage
D090 I/O Ports VDD – 0.7 — — V IOH = 3.5 mA, VDD = 5V
IOH = 3 mA, VDD = 3.3V
IOH = 1 mA, VDD = 1.8V
Capacitive Loading Specifications on Output Pins
D101A* CIO All I/O Pins — — 50 pF
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Negative current is defined as current sourced by the pin.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
2013-2015 Microchip Technology Inc. DS40001723D-page 269
PIC12(L)F1571/2
TABLE 26-5: MEMORY PROGRAMMING SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
Param.
No. Sym. Characteristic Min. Typ† Max. Units Conditions
Program Memory
Programming Specifications
D110 VIHH Voltage on MCLR/VPP Pin 8.0 — 9.0 V (Note 2)
D111 IDDP Supply Current during
Programming
——10mA
D112 VBE VDD for Bulk Erase 2.7 — VDDMAX V
D113 VPEW VDD for Write or Row Erase VDDMIN —VDDMAX V
D114 IPPPGM Current on MCLR/VPP during
Erase/Write
—1.0—mA
D115 IDDPGM Current on VDD during
Erase/Write
—5.0—mA
Program Flash Memory
D121 EPCell Endurance 10K — — E/W -40C TA +85C
(Note 1)
D122 VPRW VDD for Read/Write VDDMIN —VDDMAX V
D123 TIW Self-Timed Write Cycle Time — 2 2.5 ms
D124 TRETD Characteristic Retention — 40 — Year Provided no other
specifications are violated
D125 EHEFC High-Endurance Flash Cell 100K — — E/W 0C TA +60°C, lower
byte last 128 addresses
† Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
Note 1: Self-write and block erase.
2: Required only if single-supply programming is disabled.
PIC12(L)F1571/2
DS40001723D-page 270 2013-2015 Microchip Technology Inc.
TABLE 26-6: THERMAL CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Param.
No. Sym. Characteristic Typ. Units Conditions
TH01 JA Thermal Resistance Junction to Ambient 56.7 C/W 8-pin DFN 3x3 mm package
89.3 C/W 8-pin PDIP package
149.5 C/W 8-pin SOIC package
39.4 C/W 8-pin UDFN 3x3 mm package
TH02 JC Thermal Resistance Junction to Case 9.0 C/W 8-pin DFN 3x3 mm package
43.1 C/W 8-pin PDIP package
39.9 C/W 8-pin SOIC package
40.3 C/W 8-pin UDFN 3x3 mm package
TH03 TJMAX Maximum Junction Temperature 150 C
TH04 PD Power Dissipation — W PD = PINTERNAL + PI/O
TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDD x VDD(1)
TH06 PI/OI/O Power Dissipation — W PI/O = (IOL * VOL) + (IOH * (VDD – VOH))
TH07 PDER Derated Power — W PDER = PDMAX (TJ – TA)/JA(2)
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature; TJ = Junction Temperature.
2013-2015 Microchip Technology Inc. DS40001723D-page 271
PIC12(L)F1571/2
26.4 AC Characteristics
Timing Parameter Symbology has been created with one of the following formats:
FIGURE 26-4: LOAD CONDITIONS
1. TppS2ppS
2. TppS
T
F Frequency T Time
Lowercase letters (pp) and their meanings:
pp
cc CCP1 osc CLKIN
ck CLKOUT rd RD
cs CS rw RD or WR
di SDIx sc SCKx
do SDO ss SS
dt Data in t0 T0CKI
io I/O PORT t1 T1CKI
mc MCLR wr WR
Uppercase letters and their meanings:
S
FFall PPeriod
HHigh RRise
I Invalid (High-impedance) V Valid
L Low Z High-impedance
Load Condition
Legend: CL=50 pF for all pins
Pin
CL
VSS
Rev. 10-000133A
8/1/2013
PIC12(L)F1571/2
DS40001723D-page 272 2013-2015 Microchip Technology Inc.
FIGURE 26-5: CLOCK TIMING
TABLE 26-7: CLOCK OSCILLATOR TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param.
No. Sym. Characteristic Min. Typ† Max. Units Conditions
OS01 FOSC External CLKIN Frequency(1) DC — 0.5 MHz External Clock (ECL)
DC — 4 MHz External Clock (ECM)
DC — 20 MHz External Clock (ECH)
OS02 TOSC External CLKIN Period(1) 50 — ns External Clock (EC)
OS03 TCY Instruction Cycle Time(1) 200 TCY DC ns TCY = 4/FOSC
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-
sumption. All devices are tested to operate at “min” values with an external clock applied to the CLKIN pin. When an
external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
CLKIN
CLKOUT
Q4 Q1 Q2 Q3 Q4 Q1
OS02
OS03
OS04 OS04
(CLKOUT Mode)
Note 1: See Table 26-10.
2013-2015 Microchip Technology Inc. DS40001723D-page 273
PIC12(L)F1571/2
TABLE 26-8: OSCILLATOR PARAMETERS
FIGURE 26-6: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE
TABLE 26-9: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.7V TO 5.5V)
Standard Operating Conditions (unless otherwise stated)
Param.
No. Sym. Characteristic Freq.
Tolerance Min. Typ† Max. Units Conditions
OS08 HFOSC Internal Calibrated HFINTOSC
Frequency(1)
±2% — 16.0 — MHz VDD = 3.0V, TA = 25°C
(Note 2)
OS09 LFOSC Internal LFINTOSC Frequency — — 31 — kHz
OS10* TWARM HFINTOSC
Wake-up from Sleep Start-up Time
——515s
LFINTOSC
Wake-up from Sleep Start-up Time
——0.5—ms
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
2: See Figure 26-6: “HFINTOSC Frequency Accuracy Over Device VDD and Temperature.
Param
No. Sym. Characteristic Min. Typ† Max. Units Conditions
F10 FOSC Oscillator Frequency Range 4 — 8 MHz
F11 FSYS On-Chip VCO System Frequency 16 — 32 MHz
F12 TRC PLL Start-up Time (Lock Time) — — 2 ms
F13* CLK CLKOUT Stability (Jitter) -0.25% — +0.25% %
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3V, +25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
+125
+25
2.0
0
+60
+85
VDD (V)
4.0 5.04.5
Temperature (°C)
2.5 3.0 3.5 5.51.8
-40
± 5%
± 2%
± 5%
± 3%
PIC12(L)F1571/2
DS40001723D-page 274 2013-2015 Microchip Technology Inc.
FIGURE 26-7: CLKOUT AND I/O TIMING
TABLE 26-10: CLKOUT AND I/O TIMING PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Param.
No. Sym. Characteristic Min. Typ† Max. Units Conditions
OS11 TosH2ckL FOSC to CLKOUT(1) — — 70 ns 3.3V VDD 5.0V
OS12 TosH2ckH FOSC to CLKOUT(1) — — 72 ns 3.3V VDD 5.0V
OS13 TckL2ioV CLKOUT to Port Out Valid(1) — — 20 ns
OS14 TioV2ckH Port Input Valid Before CLKOUT(1) TOSC + 200 ns — — ns
OS15 TosH2ioV Fosc (Q1 cycle) to Port Out Valid — 50 70* ns 3.3V VDD 5.0V
OS16 TosH2ioI Fosc (Q2 cycle) to Port Input Invalid
(I/O in setup time)
50 — — ns 3.3V VDD 5.0V
OS17 TioV2osH Port Input Valid to Fosc(Q2 cycle)
(I/O in setup time)
20 — — ns
OS18* TioR Port Output Rise Time —
—
40
15
72
32
ns VDD = 1.8V,
3.3V VDD 5.0V
OS19* TioF Port Output Fall Time —
—
28
15
55
30
ns VDD = 1.8V,
3.3V VDD 5.0V
OS20* Tinp INT Pin Input High or Low Time 25 — — ns
OS21* Tioc Interrupt-On-Change New Input Level Time 25 — — ns
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, +25C unless otherwise stated.
Note 1: Measurements are taken in EXTRC mode where CLKOUT output is 4 x TOSC.
FOSC
CLKOUT
I/O pin
(Input)
I/O pin
(Output)
Q4 Q1 Q2 Q3
OS11
OS19
OS13
OS15
OS18, OS19
OS20
OS21
OS17
OS16
OS14
OS12
OS18
Old Value New Value
Write Fetch Read ExecuteCycle
2013-2015 Microchip Technology Inc. DS40001723D-page 275
PIC12(L)F1571/2
FIGURE 26-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
V
DD
MCLR
Internal
POR
PWRT
Time-out
OSC
Start-up Time
Internal Reset
(1)
Watchdog Timer
33
32
30
31
34
I/O Pins
34
Note 1: Asserted low.
Reset
(1)
PIC12(L)F1571/2
DS40001723D-page 276 2013-2015 Microchip Technology Inc.
TABLE 26-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET PARAMETERS
FIGURE 26-9: BROWN-OUT RESET TIMING AND CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Param.
No. Sym. Characteristic Min. Typ† Max. Units Conditions
30 TMCLMCLR Pulse Width (low) 2 — — s
31 TWDTLP Low-Power Watchdog Timer
Time-out Period
10 16 27 ms VDD = 3.3V-5V,
1:512 prescaler used
32 TOST Oscillator Start-up Timer Period(1) — 1024 — TOSC
33* TPWRT Power-up Timer Period 40 65 140 ms PWRTE =0
34* TIOZ I/O High-Impedance from MCLR Low
or Watchdog Timer Reset
——2.0s
35 VBOR Brown-out Reset Voltage(2) 2.55
2.35
1.80
2.70
2.45
1.90
2.85
2.58
2.05
V
V
V
BORV = 0
BORV = 1 (PIC12F1571/2)
BORV = 1 (PIC12LF1571/2)
36* VHYST Brown-out Reset Hysteresis 0 25 60 mV -40°C TA +85°C
37* TBORDC Brown-out Reset DC Response Time 1 16 35 sVDD VBOR
38 VLPBOR Low-Power Brown-out Reset Voltage 1.8 2.1 2.5 V LPBOR = 1
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: By design, the Oscillator Start-up Timer (OST) counts the first 1024 cycles, independent of frequency.
2: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
VBOR
VDD
(Device in Brown-out Reset) (Device not in Brown-out Reset)
33
Reset
(due to BOR)
VBOR and VHYST
37
2013-2015 Microchip Technology Inc. DS40001723D-page 277
PIC12(L)F1571/2
FIGURE 26-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
TABLE 26-12: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param.
No. Sym. Characteristic Min. Typ† Max. Units Conditions
40* TT0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20 — — ns
With Prescaler 10 — — ns
41* TT0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20 — — ns
With Prescaler 10 — — ns
42* TT0P T0CKI Period Greater of:
20 or TCY + 40
N
— — ns N = Prescale value
45* TT1H T1CKI High
Time
Synchronous, No Prescaler 0.5 TCY + 20 — — ns
Synchronous, with Prescaler 15 — — ns
Asynchronous 30 — — ns
46* TT1L T1CKI Low
Time
Synchronous, No Prescaler 0.5 TCY + 20 — — ns
Synchronous, with Prescaler 15 — — ns
Asynchronous 30 — — ns
47* TT1P T1CKI Input
Period
Synchronous Greater of:
30 or TCY + 40
N
— — ns N = Prescale value
Asynchronous 60 — — ns
49* TCKEZTMR1 Delay from External Clock Edge to Timer
Increment
2 TOSC —7 TOSC — Timers in Sync
mode
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
T0CKI
T1CKI
40 41
42
45 46
47 49
TMR0 or
TMR1
PIC12(L)F1571/2
DS40001723D-page 278 2013-2015 Microchip Technology Inc.
TABLE 26-13: ANALOG-TO-DIGITAL CONVERTER (ADC) CHARACTERISTICS(1,2,3)
Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = +25°C
Param.
No. Sym. Characteristic Min. Typ† Max. Units Conditions
AD01 NRResolution — — 10 bit
AD02 EIL Integral Error — ±1 ±1.7 LSb VREF = 3.0V
AD03 EDL Differential Error — ±1 ±1 LSb No missing codes, VREF = 3.0V
AD04 EOFF Offset Error — ±1 ±2.5 LSb VREF = 3.0V
AD05 EGN Gain Error — ±1 ±2.0 LSb VREF = 3.0V
AD06 VREF Reference Voltage 1.8 — VDD VVREF = (VRPOS – VRNEG) (Note 4)
AD07 VAIN Full-Scale Range VSS —VREF V
AD08 ZAIN Recommended Impedance of
Analog Voltage Source
—— 10kCan go higher if external 0.01 F capacitor is
present on input pin.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Total absolute error includes integral, differential, offset and gain errors.
2: The ADC conversion result never decreases with an increase in the input voltage and has no missing codes.
3: See Section 27.0 “DC and AC Characteristics Graphs and Charts” for operating characterization.
4: ADC VREF is selected by the ADPREF<0> bit.
2013-2015 Microchip Technology Inc. DS40001723D-page 279
PIC12(L)F1571/2
FIGURE 26-11: ADC CONVERSION TIMING (ADC CLOCK FOSC-BASED)
FIGURE 26-12: ADC CONVERSION TIMING (ADC CLOCK FROM FRC)
AD131
AD130
BSF ADCON0, GO
Q4
ADC_clk
ADC Data
ADRES
ADIF
GO
Sample
OLD_DATA
Sampling Stopped
DONE
NEW_DATA
987 3210
1 TCY
6
AD133
1 TCY
AD132
AD132
AD131
AD130
BSF ADCON0, GO
Q4
ADC_clk
ADC Data
ADRES
ADIF
GO
Sample
OLD_DATA
Sampling Stopped
DONE
NEW_DATA
9 7 3210
Note 1: If the ADC clock source is selected as FRC, a time of TCY is added before the ADC clock starts; this allows the
SLEEP instruction to be executed.
AD133
6
8
1 TCY
1 TCY
PIC12(L)F1571/2
DS40001723D-page 280 2013-2015 Microchip Technology Inc.
TABLE 26-14: ADC CONVERSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param.
No. Sym. Characteristic Min. Typ† Max. Units Conditions
AD130* TAD ADC Clock Period (TADC)1.0—6.0sFOSC-based
ADC Internal FRC Oscillator Period (TFRC)1.0 2.0 6.0s ADCS<2:0> = x11 (ADC FRC mode)
AD131 TCNV Conversion Time
(not including Acquisition Time)(1)
—11—TAD Set GO/DONE bit to conversion
complete
AD132* TACQ Acquisition Time — 5.0 — s
AD133* THCD Holding Capacitor Disconnect Time —
—
1/2 TAD
1/2 TAD + 1TCY
—
—
FOSC-based,
ADCS<2:0> = x11 (ADC FRC mode)
* These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The ADRES register may be read on the following TCY cycle.
2013-2015 Microchip Technology Inc. DS40001723D-page 281
PIC12(L)F1571/2
TABLE 26-15: COMPARATOR SPECIFICATIONS(1)
TABLE 26-16: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS(1)
Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = +25°C
Param.
No. Sym. Characteristics Min. Typ. Max. Units Comments
CM01 VIOFF Input Offset Voltage — ±7.5 ±60 mV CxSP = 1,
VICM = VDD/2
CM02 VICM Input Common-Mode Voltage 0 — VDD V
CM03 CMRR Common-Mode Rejection Ration — 50 — dB
CM04A TRESP(2) Response Time Rising Edge — 400 800 ns CxSP = 1
CM04B Response Time Falling Edge — 200 400 ns CxSP = 1
CM04C Response Time Rising Edge — 1200 — ns CxSP = 0
CM04D Response Time Falling Edge — 550 — ns CxSP = 0
CM05* TMC2OV Comparator Mode Change to
Output Valid
——10s
CM06 CHYSTER Comparator Hysteresis — 25 — mV CxHYS = 1,
CxSP = 1
* These parameters are characterized but not tested.
Note 1: See Section 27.0 “DC and AC Characteristics Graphs and Charts” for operating characterization.
2: Response time measured with one comparator input at VDD/2, while the other input transitions from
VSS to VDD.
Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = +25°C
Param.
No. Sym. Characteristics Min. Typ. Max. Units Comments
DAC01* CLSB Step Size — VDD/32 — V
DAC02* CACC Absolute Accuracy — — 1/2 LSb
DAC03* CRUnit Resistor Value (R) — 5K —
DAC04* CST Settling Time(2) ——10s
* These parameters are characterized but not tested.
Note 1: See Section 27.0 “DC and AC Characteristics Graphs and Charts” for operating characterization.
2: Settling time measured while DACR<4:0> transitions from ‘0000’ to ‘1111’.
PIC12(L)F1571/2
DS40001723D-page 282 2013-2015 Microchip Technology Inc.
FIGURE 26-13: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 26-17: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
FIGURE 26-14: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
TABLE 26-18: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param.
No. Symbol Characteristic Min. Max. Units Conditions
US120 TCKH2DTV SYNC XMIT (Master and Slave)
Clock High to Data-Out Valid
—80ns3.0V VDD 5.5V
— 100 ns 1.8V VDD 5.5V
US121 TCKRF Clock Out Rise Time and Fall Time
(Master mode)
—45ns3.0V VDD 5.5V
—50ns1.8V VDD 5.5V
US122 TDTRF Data-Out Rise Time and Fall Time — 45 ns 3.0V VDD 5.5V
—50ns1.8V VDD 5.5V
Standard Operating Conditions (unless otherwise stated)
Param.
No. Symbol Characteristic Min. Max. Units Conditions
US125 TDTV2CKL SYNC RCV (Master and Slave)
Data-Hold before CK (DT hold time) 10 — ns
US126 TCKL2DTL Data-Hold after CK (DT hold time) 15 — ns
Note: Refer to Figure 26-4 for load conditions.
US121 US121
US120 US122
CK
DT
Note: Refer to Figure 26-4 for load conditions.
US125
US126
CK
DT
2013-2015 Microchip Technology Inc. DS40001723D-page 283
PIC12(L)F1571/2
27.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented is outside specified operating range (i.e., outside specified VDD range).
This is for information only and devices are ensured to operate properly only within the specified range.
“Typical” represents the mean of the distribution at +25C. “MAXIMUM”, “Max.”, “MINIMUM” or “Min.”
represents (mean + 3) or (mean – 3) respectively, where is a standard deviation over each
temperature range.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
PIC12(L)F1571/2
DS40001723D-page 284 2013-2015 Microchip Technology Inc.
FIGURE 27-1: IDD, EC OSCILLATOR, LOW-POWER MODE, FOSC = 32 kHz, PIC12LF1571/2 ONLY
FIGURE 27-2: IDD, EC OSCILLATOR, LOW-POWER MODE, FOSC = 32 kHz, PIC12F1571/2 ONLY
Typical
Max.
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
IDD (µA)
VDD (V)
Max: 85°C + 3ı
Typical: 25°C
Typical
Max.
0
5
10
15
20
25
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IDD (µA)
VDD (V)
Max: 85°C + 3ı
Typical: 25°C
2013-2015 Microchip Technology Inc. DS40001723D-page 285
PIC12(L)F1571/2
FIGURE 27-3: IDD, EC OSCILLATOR, LOW-POWER MODE, FOSC = 500 kHz, PIC12LF1571/2 ONLY
FIGURE 27-4: IDD, EC OSCILLATOR, LOW-POWER MODE, FOSC = 500 kHz, PIC12F1571/2 ONLY
Max.
Typical
15
20
25
30
35
40
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
IDD (µA)
VDD (V)
Max: 85°C + 3ı
Typical: 25°C
Typical
Max.
20
25
30
35
40
45
50
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IDD (µA)
VDD (V)
Max: 85°C + 3ı
Typical: 25°C
PIC12(L)F1571/2
DS40001723D-page 286 2013-2015 Microchip Technology Inc.
FIGURE 27-5: IDD TYPICAL, EC OSCILLATOR, MEDIUM POWER MODE, PIC12LF1571/2 ONLY
FIGURE 27-6: IDD MAXIMUM, EC OSCILLATOR, MEDIUM POWER MODE, PIC12LF1571/2 ONLY
4 MHz
1 MHz
0
50
100
150
200
250
300
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
IDD (µA)
VDD (V)
Typical: 25°C
4 MHz
1 MHz
0
50
100
150
200
250
300
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
IDD (µA)
VDD (V)
Max: 85°C + 3ı
2013-2015 Microchip Technology Inc. DS40001723D-page 287
PIC12(L)F1571/2
FIGURE 27-7: IDD TYPICAL, EC OSCILLATOR, MEDIUM POWER MODE, PIC12F1571/2 ONLY
FIGURE 27-8: IDD MAXIMUM, EC OSCILLATOR, MEDIUM POWER MODE, PIC12F1571/2 ONLY
4 MHz
1 MHz
0
50
100
150
200
250
300
350
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IDD (µA)
VDD (V)
Typical: 25°C
4 MHz
1 MHz
0
50
100
150
200
250
300
350
400
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IDD (µA)
VDD (V)
Max: 85°C + 3ı
PIC12(L)F1571/2
DS40001723D-page 288 2013-2015 Microchip Technology Inc.
FIGURE 27-9: IDD TYPICAL, EC OSCILLATOR, HIGH-POWER MODE, PIC12LF1571/2 ONLY
FIGURE 27-10: IDD MAXIMUM, EC OSCILLATOR, HIGH-POWER MODE, PIC12LF1571/2 ONLY
32 MHz
16 MHz
8 MHz
0.0
0.5
1.0
1.5
2.0
2.5
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
IDD (mA)
VDD (V)
Typical: 25°C
32 MHz
16 MHz
8 MHz
0.0
0.5
1.0
1.5
2.0
2.5
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
IDD (mA)
VDD (V)
Max: 85°C + 3ı
2013-2015 Microchip Technology Inc. DS40001723D-page 289
PIC12(L)F1571/2
FIGURE 27-11: IDD TYPICAL, EC OSCILLATOR, HIGH-POWER MODE, PIC12F1571/2 ONLY
FIGURE 27-12: IDD MAXIMUM, EC OSCILLATOR, HIGH-POWER MODE, PIC12F1571/2 ONLY
32 MHz
16 MHz
8 MHz
0.0
0.5
1.0
1.5
2.0
2.5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IDD (mA)
VDD (V)
Typical: 25°C
32 MHz
16 MHz
8 MHz
0.0
0.5
1.0
1.5
2.0
2.5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IDD (mA)
VDD (V)
Max: 85°C + 3ı
PIC12(L)F1571/2
DS40001723D-page 290 2013-2015 Microchip Technology Inc.
FIGURE 27-13: IDD, LFINTOSC, FOSC = 31 kHz, PIC12LF1571/2 ONLY
FIGURE 27-14: IDD, LFINTOSC, FOSC = 31 kHz, PIC12F1571/2 ONLY
Typical
Max.
2
3
4
5
6
7
8
9
10
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
IDD (µA)
VDD (V)
Max: 85°C + 3ı
Typical: 25°C
Typical
Max.
0
5
10
15
20
25
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IDD (µA)
VDD (V)
Max: 85°C + 3ı
Typical: 25°C
2013-2015 Microchip Technology Inc. DS40001723D-page 291
PIC12(L)F1571/2
FIGURE 27-15: IDD, MFINTOSC, FOSC = 500 kHz, PIC12LF1571/2 ONLY
FIGURE 27-16: IDD, MFINTOSC, FOSC = 500 kHz, PIC12F1571/2 ONLY
Typical
Max.
100
110
120
130
140
150
160
170
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
IDD (µA)
VDD (V)
Max: 85°C + 3ı
Typical: 25°C
Typical
Max.
100
120
140
160
180
200
220
240
260
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IDD (µA)
VDD (V)
Max: 85°C + 3ı
Typical: 25°C
PIC12(L)F1571/2
DS40001723D-page 292 2013-2015 Microchip Technology Inc.
FIGURE 27-17: IDD TYPICAL, HFINTOSC, PIC12LF1571/2 ONLY
FIGURE 27-18: IDD MAXIMUM, HFINTOSC, PIC12LF1571/2 ONLY
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
IDD (mA)
VDD (V)
Typical: 25°C
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
IDD (mA)
VDD (V)
Max: 85°C + 3ı
2013-2015 Microchip Technology Inc. DS40001723D-page 293
PIC12(L)F1571/2
FIGURE 27-19: IDD TYPICAL, HFINTOSC, PIC12F1571/2 ONLY
FIGURE 27-20: IDD MAXIMUM, HFINTOSC, PIC12F1571/2 ONLY
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IDD (mA)
VDD (V)
Typical: 25°C
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IDD (mA)
VDD (V)
Max: 85°C + 3ı
PIC12(L)F1571/2
DS40001723D-page 294 2013-2015 Microchip Technology Inc.
FIGURE 27-21: IPD BASE, LOW-POWER SLEEP MODE, PIC12LF1571/2 ONLY
FIGURE 27-22: IPD BASE, LOW-POWER SLEEP MODE, PIC12F1571/2 ONLY
350
Max.
150
200
250
300
350
IPD (nA)
Max: 85°C + 3ı
Typical: 25°C
Typical
0
50
100
150
200
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
IPD (n
A
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
0.8
Max
0.4
0.5
0.6
0.7
0.8
IPD (µA)
Max: 85°C + 3ı
Typical: 25°C
Typical
0.0
0.1
0.2
0.3
0.4
20
25
30
35
40
45
50
55
60
IPD (µ
A
0.0
0.1
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
2013-2015 Microchip Technology Inc. DS40001723D-page 295
PIC12(L)F1571/2
FIGURE 27-23: IPD, WATCHDOG TIMER (WDT), PIC12LF1571/2 ONLY
FIGURE 27-24: IPD, WATCHDOG TIMER (WDT), PIC12F1571/2 ONLY
1.0
Max.
Typical
04
0.5
0.6
0.7
0.8
0.9
1.0
I
PD (µA)
Max: 85°C + 3ı
Typical: 25°C
Typical
0.0
0.1
0.2
0.3
0.4
0.5
16
18
20
22
24
26
28
30
32
34
36
38
IPD (µA
)
0.0
0
.
1
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
1.6
Max.
Typical
0.8
1.0
1.2
1.4
1.6
I
PD (µA)
Max: 85°C + 3ı
Typical: 25°C
Typical
0.0
0.2
0.4
0.6
0.8
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
IPD (µ
A
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
PIC12(L)F1571/2
DS40001723D-page 296 2013-2015 Microchip Technology Inc.
FIGURE 27-25: IPD, FIXED VOLTAGE REFERENCE (FVR), PIC12LF1571/2 ONLY
FIGURE 27-26: IPD, FIXED VOLTAGE REFERENCE (FVR), PIC12F1571/2 ONLY
28
Max: 85
°
C+3
ı
Max.
Til
18
20
22
24
26
28
I
PD (uA)
Max: 85°C + 3ı
Typical: 25°C
Typical
10
12
14
16
18
20
16
18
20
22
24
26
28
30
32
34
36
38
IPD (uA
)
10
12
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
24
Max.
Typical
16
18
20
22
24
IPD (uA)
10
12
14
16
18
20
25
30
35
40
45
50
55
60
IPD (u
A
Max: 85°C + 3ı
Typical: 25°C
10
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
Typical:
25
C
2013-2015 Microchip Technology Inc. DS40001723D-page 297
PIC12(L)F1571/2
FIGURE 27-27: IPD, BROWN-OUT RESET (BOR), BORV = 1, PIC12LF1571/2 ONLY
FIGURE 27-28: IPD, BROWN-OUT RESET (BOR), BORV = 1, PIC12F1571/2 ONLY
9
Max.
Typical
6.5
7
7.5
8
8.5
9
IPD (uA)
Max: 85°C + 3ı
Typical: 25°C
Typical
4.5
5
5.5
6
6.5
7
24
25
26
27
28
29
30
31
32
33
34
35
36
37
IPD (
4.5
5
2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7
VDD (V)
12
T
yp
ical
8
9
10
11
12
P
D(uA)
Max: 85°C + 3ı
Typical: 25°C
Max.
Typical
4
5
6
7
8
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
IPD (uA)
4
2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
VDD (V)
PIC12(L)F1571/2
DS40001723D-page 298 2013-2015 Microchip Technology Inc.
FIGURE 27-29: IPD, LOW-POWER BROWN-OUT RESET (LPBOR = 0), PIC12LF1571/2 ONLY
FIGURE 27-30: IPD, LOW-POWER BROWN-OUT RESET (LPBOR = 0), PIC12F1571/2 ONLY
16
1.8
Max.
0.8
1
1.2
1.4
1.6
1.8
IPD (uA)
Max: 85°C + 3ı
Typical: 25°C
Typical
0
0.2
0.4
0.6
0.8
2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7
IPD (u
A
0
2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7
VDD (V)
1.8
Max: 85
°
C+3
ı
Max.
0.8
1.0
1.2
1.4
1.6
1.8
IDD (µA)
Max: 85°C + 3ı
Typical: 25°C
Typical
0.0
0.2
0.4
0.6
0.8
1
.
0
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
IDD (µ
A
0.0
0
.
2
2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
VDD (V)
2013-2015 Microchip Technology Inc. DS40001723D-page 299
PIC12(L)F1571/2
FIGURE 27-31: IPD, ADC NON-CONVERTING, PIC12LF1571/2 ONLY
FIGURE 27-32: IPD, ADC NON-CONVERTING, PIC12F1571/2 ONLY
500
Max.
200
250
300
350
400
450
500
PD (µA)
Max: 85°C + 3ı
Typical: 25°C
Typical
0
50
100
150
200
250
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
IPD (µA
)
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
1.4
Max.
0
.
6
0.8
1.0
1.2
1.4
D
D(µA)
Max: 85°C + 3ı
Typical: 25°C
Typical
0.0
0.2
0.4
0.6
0
.
8
15
20
25
30
35
40
45
50
55
60
IDD (µA)
0.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
PIC12(L)F1571/2
DS40001723D-page 300 2013-2015 Microchip Technology Inc.
FIGURE 27-33: IPD, COMPARATOR, LOW-POWER MODE (CxSP = 0), PIC12F1571/2 ONLY
FIGURE 27-34: IPD, COMPARATOR, NORMAL POWER MODE (CxSP = 1), PIC12LF1571/2 ONLY
20
22
Max: 85
°
C+3
ı
Max.
Typical
12
14
16
18
20
22
IPD (µA)
Max: 85°C + 3ı
Typical: 25°C
4
6
8
10
12
20
25
30
35
40
45
50
55
60
IPD (
µ
4
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
30
32
Max:
-
40
°
C+3
ı
Max.
Typical
20
22
24
26
28
30
32
IPD (µA)
Max: -40°C + 3ı
Typical: 25°C
Typical
12
14
16
18
20
22
16
18
20
22
24
26
28
30
32
34
36
38
IPD (µ
A
12
14
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
2013-2015 Microchip Technology Inc. DS40001723D-page 301
PIC12(L)F1571/2
FIGURE 27-35: IPD, COMPARATOR, NORMAL POWER MODE (CxSP = 1), PIC12F1571/2 ONLY
45
Max:
40
°
C+3
ı
Max.
Typical
25
30
35
40
45
IPD (µA)
Max: -40°C + 3ı
Typical: 25°C
10
15
20
25
2.
0
2.
5
3
.
0
3
.
5
4.
0
4.
5
5
.
0
5
.
5
6
.
0
IPD (µ
A
10
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
PIC12(L)F1571/2
DS40001723D-page 302 2013-2015 Microchip Technology Inc.
FIGURE 27-36: IPD, PWM, HFINTOSC MODE (16 MHz), PIC12LF1571/2 ONLY
FIGURE 27-37: IPD, PWM, HFINTOSC MODE (16 MHz), PIC12F1571/2 ONLY
1100
Max: 85
°
C+3
ı
Max.
Typical
600
700
800
900
1000
1100
IPD (µA)
Max: 85°C + 3ı
Typical: 25°C
Typical
200
300
400
500
600
700
16
18
20
22
24
26
28
30
32
34
36
38
IPD (µ
A
200
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
VDD (V)
1,200
Max: 85
°
C
+
3
ı
Max.
Typical
700
800
900
1,000
1,100
1,200
IPD (µA)
Max: 85°C + 3ı
Typical: 25°C
400
500
600
700
800
2.
0
2.
5
3
.
0
3
.
5
4.
0
4.
5
5
.
0
5
.
5
6
.
0
IPD (µ
A
400
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (V)
2013-2015 Microchip Technology Inc. DS40001723D-page 303
PIC12(L)F1571/2
FIGURE 27-38: FVR STABILIZATION PERIOD
Typical
Max.
0
10
20
30
40
50
60
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
Time (us)
VDD (V)
Max: Typical + 3ı
Typical: statistical mean @ 25°C
Note:
The FVR Stabilization Period applies when:
1) coming out of RESET or exiting Sleep mode for PIC12/16LFxxxx devices.
2) when exiting sleep mode with VREGPM = 1for PIC12/16Fxxxx devices
In all other cases, the FVR is stable when released from RESET.
PIC12(L)F1571/2
DS40001723D-page 304 2013-2015 Microchip Technology Inc.
NOTES:
2013-2015 Microchip Technology Inc. DS40001723D-page 305
PIC12(L)F1571/2
28.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers (MCU) and dsPIC® digital
signal controllers (DSC) are supported with a full range
of software and hardware development tools:
• Integrated Development Environment
- MPLAB® X IDE Software
• Compilers/Assemblers/Linkers
- MPLAB XC Compiler
- MPASMTM Assembler
-MPLINK
TM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB X SIM Software Simulator
•Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers/Programmers
- MPLAB ICD 3
- PICkit™ 3
• Device Programmers
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Development Boards,
Evaluation Kits and Starter Kits
• Third-party development tools
28.1 MPLAB X Integrated Development
Environment Software
The MPLAB X IDE is a single, unified graphical user
interface for Microchip and third-party software, and
hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
MPLAB X IDE is an entirely new IDE with a host of free
software components and plug-ins for high-
performance application development and debugging.
Moving between tools and upgrading from software
simulators to hardware debugging and programming
tools is simple with the seamless user interface.
With complete project management, visual call graphs,
a configurable watch window and a feature-rich editor
that includes code completion and context menus,
MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
multiple projects with simultaneous debugging, MPLAB
X IDE is also suitable for the needs of experienced
users.
Feature-Rich Editor:
• Color syntax highlighting
• Smart code completion makes suggestions and
provides hints as you type
• Automatic code formatting based on user-defined
rules
• Live parsing
User-Friendly, Customizable Interface:
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project-Based Workspaces:
• Multiple projects
• Multiple tools
• Multiple configurations
• Simultaneous debugging sessions
File History and Bug Tracking:
• Local file history feature
• Built-in support for Bugzilla issue tracker
PIC12(L)F1571/2
DS40001723D-page 306 2013-2015 Microchip Technology Inc.
28.2 MPLAB XC Compilers
The MPLAB XC Compilers are complete ANSI C
compilers for all of Microchip’s 8, 16, and 32-bit MCU
and DSC devices. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use. MPLAB XC Compilers run on Windows,
Linux or MAC OS X.
For easy source level debugging, the compilers provide
debug information that is optimized to the MPLAB X
IDE.
The free MPLAB XC Compiler editions support all
devices and commands, with no time or memory
restrictions, and offer sufficient code optimization for
most applications.
MPLAB XC Compilers include an assembler, linker and
utilities. The assembler generates relocatable object
files that can then be archived or linked with other relo-
catable object files and archives to create an execut-
able file. MPLAB XC Compiler uses the assembler to
produce its object file. Notable features of the assem-
bler include:
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command-line interface
• Rich directive set
• Flexible macro language
• MPLAB X IDE compatibility
28.3 MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code, and COFF files for
debugging.
The MPASM Assembler features include:
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process
28.4 MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
28.5 MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
then be archived or linked with other relocatable object
files and archives to create an executable file. Notable
features of the assembler include:
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command-line interface
• Rich directive set
• Flexible macro language
• MPLAB X IDE compatibility
2013-2015 Microchip Technology Inc. DS40001723D-page 307
PIC12(L)F1571/2
28.6 MPLAB X SIM Software Simulator
The MPLAB X SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB X SIM Software Simulator fully supports
symbolic debugging using the MPLAB XC Compilers,
and the MPASM and MPLAB Assemblers. The soft-
ware simulator offers the flexibility to develop and
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software
development tool.
28.7 MPLAB REAL ICE In-Circuit
Emulator System
The MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs all 8, 16 and 32-bit MCU, and DSC devices
with the easy-to-use, powerful graphical user interface of
the MPLAB X IDE.
The emulator is connected to the design engineer’s
PC using a high-speed USB 2.0 interface and is
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11)
or with the new high-speed, noise tolerant, Low-
Voltage Differential Signal (LVDS) interconnection
(CAT5).
The emulator is field upgradable through future firmware
downloads in MPLAB X IDE. MPLAB REAL ICE offers
significant advantages over competitive emulators
including full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, logic
probes, a ruggedized probe interface and long (up to
three meters) interconnection cables.
28.8 MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB ICD 3 In-Circuit Debugger System is
Microchip’s most cost-effective, high-speed hardware
debugger/programmer for Microchip Flash DSC and
MCU devices. It debugs and programs PIC Flash
microcontrollers and dsPIC DSCs with the powerful,
yet easy-to-use graphical user interface of the MPLAB
IDE.
The MPLAB ICD 3 In-Circuit Debugger probe is
connected to the design engineer’s PC using a high-
speed USB 2.0 interface and is connected to the target
with a connector compatible with the MPLAB ICD 2 or
MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
supports all MPLAB ICD 2 headers.
28.9 PICkit 3 In-Circuit Debugger/
Programmer
The MPLAB PICkit 3 allows debugging and program-
ming of PIC and dsPIC Flash microcontrollers at a most
affordable price point using the powerful graphical user
interface of the MPLAB IDE. The MPLAB PICkit 3 is
connected to the design engineer’s PC using a full-
speed USB interface and can be connected to the tar-
get via a Microchip debug (RJ-11) connector (compati-
ble with MPLAB ICD 3 and MPLAB REAL ICE). The
connector uses two device I/O pins and the Reset line
to implement in-circuit debugging and In-Circuit Serial
Programming™ (ICSP™).
28.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages, and a mod-
ular, detachable socket assembly to support various
package types. The ICSP cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.
PIC12(L)F1571/2
DS40001723D-page 308 2013-2015 Microchip Technology Inc.
28.11 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully
functional systems. Most boards include prototyping
areas for adding custom circuitry and provide applica-
tion firmware and source code for examination and
modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a line of evaluation kits and demonstra-
tion software for analog filter design, KEELOQ® security
ICs, CAN, IrDA®, PowerSmart battery management,
SEEVAL® evaluation system, Sigma-Delta ADC, flow
rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
28.12 Third-Party Development Tools
Microchip also offers a great collection of tools from
third-party vendors. These tools are carefully selected
to offer good value and unique functionality.
• Device Programmers and Gang Programmers
from companies, such as SoftLog and CCS
• Software Tools from companies, such as Gimpel
and Trace Systems
• Protocol Analyzers from companies, such as
Saleae and Total Phase
• Demonstration Boards from companies, such as
MikroElektronika, Digilent® and Olimex
• Embedded Ethernet Solutions from companies,
such as EZ Web Lynx, WIZnet and IPLogika®
2013-2015 Microchip Technology Inc. DS40001723D-page 309
PIC12(L)F1571/2
29.0 PACKAGING INFORMATION
29.1 Package Marking Information
8-Lead SOIC (3.90 mm) Example
NNN
8-Lead PDIP (300 mil) Example
XXXXXXXX
XXXXXNNN
YYWW
12F1571
3
e
E/P
1310
12F1571
E/SN1310
017
017
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
PIC12(L)F1571/2
DS40001723D-page 310 2013-2015 Microchip Technology Inc.
Package Marking Information (Continued)
8-Lead MSOP (3x3 mm) Example
L1571I
310017
8-Lead DFN (3x3x0.9 mm)
Example
XXXX
NNN
YYWW
PIN 1 PIN 1
MFQ0
1312
017
8-Lead UDFN (3x3x0.5 mm)
2013-2015 Microchip Technology Inc. DS40001723D-page 311
PIC12(L)F1571/2
TABLE 29-1: 8-LEAD 3x3x0.9 DFN (MF) TOP
MARKING
Part Number Marking
PIC12F1571-E/MF MFY0/YYWW/NNN
PIC12F1572-E/MF MGA0/YYWW/NNN
PIC12F1571-I/MF MFZ0
PIC12F1572-I/MF MGB0
PIC12LF1571-E/MF MGC0
PIC12LF1572-E/MF MGE0
PIC12LF1571-I/MF MGD0
PIC12LF1572-I/MF MGF0
TABLE 29-2: 8-LEAD 3x3x0.5 UDFN (RF)
TOP MARKING
Part Number Marking
PIC12F1571-E/MF MFY0/YYWW/NNN
PIC12F1572-E/MF MGA0/YYWW/NNN
PIC12F1571-I/MF MFZ0
PIC12F1572-I/MF MGB0
PIC12LF1571-E/MF MGC0
PIC12LF1572-E/MF MGE0
PIC12LF1571-I/MF MGD0
PIC12LF1572-I/MF MGF0
PIC12(L)F1571/2
DS40001723D-page 312 2013-2015 Microchip Technology Inc.
29.2 Package Details
The following sections give the technical details of the packages.
B
A
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Microchip Technology Drawing No. C04-018D Sheet 1 of 2
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
eB
E
A
A1
A2
L
8X b
8X b1
D
E1
c
C
PLANE
.010 C
12
N
NOTE 1
TOP VIEW
END VIEWSIDE VIEW
e
2013-2015 Microchip Technology Inc. DS40001723D-page 313
PIC12(L)F1571/2
Microchip Technology Drawing No. C04-018D Sheet 2 of 2
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Units INCHES
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e.100 BSC
Top to Seating Plane A - - .210
Molded Package Thickness A2 .115 .130 .195
Base to Seating Plane A1 .015
Shoulder to Shoulder Width E .290 .310 .325
Molded Package Width E1 .240 .250 .280
Overall Length D .348 .365 .400
Tip to Seating Plane L .115 .130 .150
Lead Thickness c.008 .010 .015
Upper Lead Width b1 .040 .060 .070
Lower Lead Width b.014 .018 .022
Overall Row Spacing eB - - .430
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
3.
1.
protrusions shall not exceed .010" per side.
2.
4.
Notes:
§
--
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
Pin 1 visual index feature may vary, but must be located within the hatched area.
§ Significant Characteristic
Dimensioning and tolerancing per ASME Y14.5M
e
DATUM A DATUM A
e
b
e
2
b
e
2
ALTERNATE LEAD DESIGN
(VENDOR DEPENDENT)
PIC12(L)F1571/2
DS40001723D-page 314 2013-2015 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2013-2015 Microchip Technology Inc. DS40001723D-page 315
PIC12(L)F1571/2
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
PIC12(L)F1571/2
DS40001723D-page 316 2013-2015 Microchip Technology Inc.
!"#$%
& !"#$%&"'""($)%
*++&&&!!+$
2013-2015 Microchip Technology Inc. DS40001723D-page 317
PIC12(L)F1571/2
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
PIC12(L)F1571/2
DS40001723D-page 318 2013-2015 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2013-2015 Microchip Technology Inc. DS40001723D-page 319
PIC12(L)F1571/2
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
PIC12(L)F1571/2
DS40001723D-page 320 2013-2015 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2013-2015 Microchip Technology Inc. DS40001723D-page 321
PIC12(L)F1571/2
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
PIC12(L)F1571/2
DS40001723D-page 322 2013-2015 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2013-2015 Microchip Technology Inc. DS40001723D-page 323
PIC12(L)F1571/2
B
A
0.10 C
0.10 C
0.10 C A B
(DATUM B)
(DATUM A)
C
SEATING
PLANE
2X
TOP VIEW
SIDE VIEW
BOTTOM VIEW
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
NOTE 1
12
N
0.10 C A B
0.10 C A B
0.05 C
0.05 C
Microchip Technology Drawing C04-254A Sheet 1 of 2
8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (RF) - 3x3x0.50 mm Body [UDFN]
2X
8X
D
E
A
(A3)
A1
NOTE 1
D2
E2
8X be
K
L
e
2
12
N
PIC12(L)F1571/2
DS40001723D-page 324 2013-2015 Microchip Technology Inc.
Microchip Technology Drawing C04-254A Sheet 2 of 2
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Number of Terminals
Overall Height
Terminal Width
Overall Width
Overall Length
Terminal Length
Exposed Pad Width
Exposed Pad Length
Terminal Thickness
Pitch
Standoff
Units
Dimension Limits
A1
A
b
D
E2
D2
A3
e
L
E
N
0.65 BSC
0.065 REF
1.40
2.20
0.35
0.25
0.45
0.00
0.30
3.00 BSC
0.45
2.30
1.50
0.50
0.02
3.00 BSC
MILLIMETERS
MIN NOM
8
1.60
2.40
0.55
0.35
0.55
0.05
MAX
K-0.20 -
REF: Reference Dimension, usually without tolerance, for information purposes only.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
1.
2.
3.
Notes:
Pin 1 visual index feature may vary, but must be located within the hatched area.
Package is saw singulated
Dimensioning and tolerancing per ASME Y14.5M
Terminal-to-Exposed-Pad
8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (RF) - 3x3x0.50 mm Body [UDFN]
2013-2015 Microchip Technology Inc. DS40001723D-page 325
PIC12(L)F1571/2
RECOMMENDED LAND PATTERN
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
Dimension Limits
Units
Optional Center Pad Width
Optional Center Pad Length
Contact Pitch
Y2
X2
2.40
1.60
MILLIMETERS
0.65 BSC
MIN
E
MAX
Contact Pad Length (X8)
Contact Pad Width (X8)
Y1
X1
0.85
0.35
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
Microchip Technology Drawing C04-2254A
NOM
8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (RF) - 3x3x0.50 mm Body [UDFN]
SILK SCREEN
CContact Pad Spacing 2.90
Contact Pad to Center Pad (X8) G2 0.30
C
X2
X1
E
Y2
G2
Y1
Contact Pad to Contact Pad (X6) G1 0.20
G1
PIC12(L)F1571/2
DS40001723D-page 326 2013-2015 Microchip Technology Inc.
NOTES:
2013-2015 Microchip Technology Inc. DS40001723D-page 327
PIC12(L)F1571/2
APPENDIX A: DATA SHEET
REVISION HISTORY
Revision A (10/2013)
Original release of this document.
Revision B (2/2014)
Updated PIC12(L)F1571/2 Family Types table
Program Memory Flash heading (words to K words).
Revision C (8/2014)
Updated PWM chapter. Changed to Final data sheet.
Updated IDD and IPD parameters in the Electrical
Specification chapter. Added Characterization Graphs.
Added Section 1.1: Register and Bit Naming
Conventions.
Updated Figures 5-3 and 15-5. Updated Tables 3-1,
3-7, and 3-10. Updated Section 15.2.5. Updated Equa-
tion 15-1.
Revision D (8/2015)
Updated Clocking Structure, Memory, Low-Power
Features, Family Types table and Pin Diagram Table
on cover pages.
Added Sections 3.2: High-Endurance Flash and
5.4: Clock Switching Before Sleep. Added Table 29-2
and 8-pin UDFN packaging.
Updated Examples 3-2 and 15-1.
Updated Figures 8-1, 21-1, 22-8 through 22-13 and
23-1.
Updated Registers 7-5, 8-1, 22-6 and 23-3.
Updated Sections 8.2.2, 15.2.6, 16.0, 21.0, 21.4.2,
22.3.3, 23.9.1.2, 23.11.1, 26.1 and 29.1.
Updated Tables 1, 3-3, 3-4, 3-10, 5-1, 16-1, 17-3, 22-2,
23-2, 26-6, 26-8 and 29-1.
PIC12(L)F1571/2
DS40001723D-page 328 2013-2015 Microchip Technology Inc.
NOTES:
2013-2015 Microchip Technology Inc. DS40001723D-page 329
PIC12(L)F1571/2
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
•Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
•General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
•Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
Customers should contact their distributor,
representative or Field Application Engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
PIC12(L)F1571/2
DS40001723D-page 330 2013-2015 Microchip Technology Inc.
NOTES:
2013-2015 Microchip Technology Inc. DS40001723D-page 331
PIC12(L)F1571/2
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X/XX XXX
PatternPackageTemperature
Range
Device
Device: PIC12LF1571, PIC12F1571
PIC12LF1572, PIC12F1572
Tape and Reel
Option:
Blank = Standard packaging (tube or tray)
T = Tape and Reel(1)
Temperature
Range:
I= -40C to +85C(Industrial)
E= -40
C to +125C (Extended)
Package:(2) MF = Micro Lead Frame (DFN) 3x3x0.9 mm
MS = MSOP
P=Plastic DIP
SN = SOIC
RF = Micro Lead Frame (UDFN) 3x3x0.5 mm
Pattern: QTP, SQTP, Code or Special Requirements
(blank otherwise)
Examples:
a) PIC12LF1571T - I/SO
Tape and Reel,
Industrial temperature,
SOIC package
b) PIC12F1572 - I/P
Industrial temperature,
PDIP package
c) PIC12F1571-E/MF
Extended Temperature,
DFN package
Note 1: Tape and Reel identifier only appears in the
catalog part number description. This identifier
is used for ordering purposes and is not printed
on the device package. Check with your
Microchip Sales Office for package availability
with the Tape and Reel option.
2: For other small form-factor package availability
and marking information, please visit
www.microchip.com/packaging or contact your
local sales office.
[X](1)
Tape and Reel
Option
-
PIC12(L)F1571/2
DS40001723D-page 332 2013-2015 Microchip Technology Inc.
NOTES:
2013-2015 Microchip Technology Inc. DS40001723D-page 333
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo,
MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2013-2015, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-63277-715-7
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and d sPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS40001723D-page 334 2013-2015 Microchip Technology Inc.
AMERICAS
Corporate Office
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Tel: 480-792-7200
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Tel: 631-435-6000
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Tel: 408-735-9110
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Tel: 905-673-0699
Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office
Suites 3707-14, 37th Floor
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Tel: 852-2943-5100
Fax: 852-2401-3431
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Tel: 86-532-8502-7355
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Tel: 86-21-5407-5533
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Tel: 86-27-5980-5300
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Tel: 86-29-8833-7252
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ASIA/PACIFIC
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
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Tel: 86-756-3210040
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Tel: 81-3-6880- 3770
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Tel: 82-53-744-4301
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Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
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Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Malaysia - Penang
Tel: 60-4-227-8870
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Tel: 63-2-634-9065
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Tel: 65-6334-8870
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Tel: 886-3-5778-366
Fax: 886-3-5770-955
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Tel: 886-7-213-7828
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Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
EUROPE
Austria - Wels
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Fax: 43-7242-2244-393
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Fax: 45-4485-2829
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Fax: 33-1-69-30-90-79
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Tel: 49-2129-3766400
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Tel: 49-721-625370
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Tel: 49-89-627-144-0
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Tel: 39-0331-742611
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Tel: 44-118-921-5800
Fax: 44-118-921-5820
Worldwide Sales and Service
07/14/15
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Microchip:
PIC12F1571-I/MF PIC12F1571-I/MS PIC12F1571-I/SN PIC12F1572-I/MF PIC12F1572-I/MS PIC12F1572-I/P
PIC12F1572-I/SN PIC12F1571-I/P PIC12LF1571-E/P PIC12LF1572-I/SN PIC12LF1571-E/SN PIC12LF1571-I/MF
PIC12LF1571-I/SN PIC12LF1571T-I/MF PIC12LF1572-E/MF PIC12LF1571-E/MF PIC12LF1572-I/MF PIC12LF1572-
I/P PIC12LF1571-I/MS PIC12LF1572-E/P PIC12LF1571T-I/MS PIC12LF1572-I/MS PIC12LF1572T-I/SN
PIC12LF1571-I/P PIC12LF1572-E/MS PIC12LF1572-E/SN PIC12LF1571-E/MS PIC12LF1572T-I/MF
PIC12LF1571T-I/SN PIC12LF1572T-I/MS PIC12F1572-E/MS PIC12F1571-E/MS PIC12F1572T-I/MF PIC12F1571-
E/MF PIC12F1571T-I/MF PIC12F1572-E/SN PIC12F1571-E/P PIC12F1572-E/MF PIC12F1572-E/P PIC12F1571T-
I/SN PIC12F1571T-I/MS PIC12F1572T-I/SN PIC12F1572T-I/MS PIC12F1571-E/SN PIC12F1572-E/RF
PIC12LF1571-I/RF PIC12F1571-E/RF PIC12F1572-I/RF PIC12LF1572-I/RF PIC12F1571-I/RF PIC12F1572T-I/RF
PIC12LF1572T-I/RF PIC12LF1572-E/RF PIC12F1571T-I/RF PIC12LF1571-E/RF PIC12LF1571T-I/RF
