5-1
FAST AND LS TTL DATA
4-BIT D LATCH
The SN54/74LS375 is a 4-Bit D-Type Latch for use as temporary storage
for binary information between processing limits and input/output or indicator
units. When the Enable (E) is HIGH, information present at the D input will be
transferred to the Q output and, if E is HIGH, the Q output will follow the input.
When E goes LOW, the information present at the D input prior to its setup time
will be retained at the Q outputs.
CONNECTION DIAGRAM DIP (TOP VIEW)
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
14 13 12 11 10 9
1234567
16 15
8
VCC
D0
D3Q3Q3E2,3 Q2
Q2D2
Q0Q0E0,1 Q1Q1D1GND
TRUTH TABLE
(Each latch) NOTES:
t = bit time before enable
tntn+1 tn = bit time before enable
negative-going transition.
D Q
ggg
tn+1 = bit time after enable
ne
g
ative-
g
oin
g
transition.
H H
negative
-
going
transition
.
L L
PIN NAMES LOADING (Note a)
HIGH LOW
D1–D4Data Inputs 0.5 U.L. 0.25 U.L.
E0–1 Enable Input Latches 0, 1 2.0 U.L. 1.0 U.L.
E2–3 Enable Input Latches 2, 3 2.0 U.L. 1.0 U.L.
Q1–Q4Latch Outputs (Note b) 10 U.L. 5 (2.5) U.L.
Q1–Q4Complimentary Latch Outputs (Note b) 10 U.L. 5 (2.5) U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 25 U.L. for Military (54) and 5 U.L. for Commercial (74)
Temperature Ranges.
LOGIC DIAGRAM
DATA
ENABLE
TO OTHER LATCH
Q
Q
SN54/74LS375
4-BIT D LATCH
LOW POWER SCHOTTKY
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16 1
16
1
16 1
D SUFFIX
SOIC
CASE 751B-03
LOGIC SYMBOL
VCC = PIN 16
GND = PIN 8
17 915
4
12
2 3 6 5 10 11 14 13
D0D1D2D3
E0,1
E2,3Q0Q1Q2Q3
5-2
FAST AND LS TTL DATA
SN54/74LS375
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Sbl
P
Limits
Ui
T C di i
Symbol Parameter Min Typ Max Unit Test Conditions
VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for
All Inputs
VIL
Input LOW Voltage
54 0.7
V
Guaranteed Input LOW Voltage for
V
IL
I
npu
t
LOW
V
o
lt
age 74 0.8
V
pg
All Inputs
VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
VOH
Output HIGH Voltage
54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH
V
OH
O
u
t
pu
t
HIGH
V
o
lt
age 74 2.7 3.5 V
CC ,OH ,IN IH
or VIL per T ruth Table
VOL
Output LOW Voltage
54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,
VIN =V
IL or VIH
V
OL
O
u
t
pu
t
LOW
V
o
lt
age 74 0.35 0.5 V IOL = 8.0 mA
V
IN =
V
IL or
V
IH
per T ruth Table
IIH
Input HIGH Current
D Input
E Input 20
80 µA VCC = MAX, VIN = 2.7 V
I
IH
I
npu
t
HIGH
C
urren
t
D Input
E Input 0.1
0.4 mA VCC = MAX, VIN = 7.0 V
IIL Input LOW Current D Input
E Input –0.4
–1.6 mA VCC = MAX, VIN = 0.4 V
IOS Short Circuit Current (Note 1) –20 –100 mA VCC = MAX
ICC Power Supply Current 12 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Sbl
P
Limits
Ui
T C di i
Symbol Parameter Min Typ Max Unit Test Conditions
tPLH
tPHL Propagation Delay, Data to Q 15
9.0 27
17 ns
V50V
tPLH
tPHL Propagation Delay, Data to Q 12
7.0 20
15 ns VCC = 5.0 V
tPLH
tPHL Propagation Delay, Enable to Q 15
14 27
25 ns
CC
CL = 15 pF
tPLH
tPHL Propagation Delay, Enable to Q 16
7.0 30
15 ns
5-3
FAST AND LS TTL DATA
SN54/74LS375
Q (SN54LS/74LS375 ONLY)
DATA
ENABLE
TO OTHER LATCH
Q
LOGIC DIAGRAM
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 54
74 4.5
4.75 5.0
5.0 5.5
5.25 V
TAOperating Ambient Temperature Range 54
74 –55
025
25 125
70 °C
IOH Output Current — High 54, 74 –0.4 mA
IOL Output Current — Low 54
74 4.0
8.0 mA
AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Sbl
P
Limits
Ui
T C di i
Symbol Parameter Min Typ Max Unit Test Conditions
tWEnable Pulse Width 20 ns
V50V
tsSetup T ime 20 ns VCC = 5.0 V
thHold T ime 0 ns
D
E
Q
Q
1.3 V 1.3 V
1.3 V 1.3 V 1.3 V
1.3 V
1.3 V1.3 V
1.3 V
tPLH
tPLH
tPLH
tPLH
tPHL
tPHL
tPHL
tPHL
tsth
AC WAVEFORMS
DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from LOW-to-HIGH in order to be recog-
nized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following
the clock transition from LOW-to-HIGH that the logic level
must be maintained at the input in order to ensure continued
recognition. A negative HOLD TIME indicates that the correct
logic level may be released prior to the clock transition from
LOW-to-HIGH and still be recognized.
