LM5025C www.ti.com SNVS568C - SEPTEMBER 2008 - REVISED MARCH 2013 LM5025C Active Clamp Voltage Mode PWM Controller Check for Samples: LM5025C FEATURES DESCRIPTION * * * The LM5025C is a functional variant of the LM5025 active clamp PWM controller. The functional differences of the LM5025C are: The maximum duty cycle of the LM5025C is increased from 80% to 91%. The soft-start capacitor charging current is increased from 20 A to 90 A. The VCC regulator current limit threshold is increased from 25 mA to 55 mA. The CS1 and CS2 current limit thresholds have been increased to 0.5V. The internal CS2 filter discharge device has been disabled and no longer operates each clock cycle. The internal VCC and VREF regulators continue to operate when the line UVLO pin is below threshold. 1 2 * * * * * * * * * * Internal Start-Up Bias Regulator 3A Compound Main Gate Driver Programmable Line Under-Voltage Lockout (UVLO) with Adjustable Hysteresis Voltage Mode Control with Feed-Forward Adjustable Dual Mode Over-Current Protection Programmable Overlap or Deadtime between the Main and Active Clamp Outputs Volt x Second Clamp Programmable Soft-start Leading Edge Blanking Single Resistor Programmable Oscillator Oscillator UP / DOWN Sync Capability Precision 5V Reference Thermal Shutdown PACKAGE * TSSOP-16 The LM5025C PWM controller contains all of the features necessary to implement power converters utilizing the Active Clamp / Reset technique. With the active clamp technique, higher efficiencies and greater power densities can be realized compared to conventional catch winding or RDC clamp / reset techniques. Two control outputs are provided, the main power switch control (OUT_A) and the active clamp switch control (OUT_B). The two internal compound gate drivers parallel both MOS and Bipolar devices, providing superior gate drive characteristics. This controller is designed for high-speed operation including an oscillator frequency range up to 1MHz and total PWM and current sense propagation delays less than 100 ns. The LM5025C includes a highvoltage start-up regulator that operates over a wide input range of 13V to 90V. Additional features include: Line Under Voltage Lockout (UVLO), softstart, oscillator UP/DOWN sync capability, precision reference and thermal shutdown. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2008-2013, Texas Instruments Incorporated LM5025C SNVS568C - SEPTEMBER 2008 - REVISED MARCH 2013 www.ti.com Typical Application Circuit VOUT 3.3V VIN 35V - 78V LM5025C CS1 VIN UVLO VCC ERROR AMP and ISOLATION OUT_A OUT_B RAMP COMP REF CS2 SYNC Rt TIME SS PGND AGND UP/DOWN SYNC Figure 1. Simplified Active Clamp Forward Power Converter 2 Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM5025C LM5025C www.ti.com SNVS568C - SEPTEMBER 2008 - REVISED MARCH 2013 Connection Diagram VIN 1 16 UVLO RAMP 2 15 SYNC CS1 3 14 RT CS2 4 13 COMP TIME 5 12 SS REF 6 11 AGND VCC 7 10 PGND OUT_A 8 9 OUT_B Figure 2. 16-Lead TSSOP Package Number PW0016A PIN DESCRIPTIONS Pin Name Description Application Information 1 VIN Source Input Voltage Input to start-up regulator. Input range 13V to 90V, with transient capability to 105V. 2 RAMP Modulator ramp signal An external RC circuit from Vin sets the ramp slope. This pin is discharged at the conclusion of every cycle by an internal FET, initiated by either the internal clock or the V*Sec Clamp comparator. 3 CS1 Current sense input for cycle-by-cycle limiting If CS1 exceeds 0.5V the outputs will go into Cycle-byCycle current limit. CS1 is held low for 50ns after OUT_A switches high providing leading edge blanking. 4 CS2 Current sense input for soft restart If CS2 exceeds 0.5V the outputs will be disabled and a softstart commenced. The soft-start capacitor will be fully discharged and then released with a pull-up current of 1A. After the first output pulse (when SS =1V), the SS charge current will revert back to 90 A. 5 TIME Output overlap/Deadtime control An external resistor (RSET) sets either the overlap time or dead time for the active clamp output. An RSET resistor connected between TIME and GND produces in-phase OUT_A and OUT_B pulses with overlap. An RSET resistor connected between TIME and REF produces out-of-phase OUT_A and OUT_B pulses with deadtime. 6 REF Precision 5 volt reference output Maximum output current: 10 mA Locally decouple with a 0.1 F capacitor. Reference stays low until the VCC UV comparator is satisfied. 7 VCC Output from the internal high voltage start-up regulator. The VCC voltage is regulated to 7.6V. If an auxiliary winding raises the voltage on this pin above the regulation setpoint, the internal start-up regulator will shutdown, reducing the IC power dissipation. 8 OUT_A Main output driver Output of the main switch PWM output gate driver. Output capability of 3A peak sink current. 9 OUT_B Active Clamp output driver Output of the Active Clamp switch gate driver. Capable of 1.25A peak sink current.. 10 PGND Power ground Connect directly to analog ground. 11 AGND Analog ground Connect directly to power ground. 12 SS Soft-start control An external capacitor and an internal 90 A current source set the softstart ramp. The SS current source is reduced to 1 A initially following a CS2 over-current event or an over temperature event. 13 COMP Input to the Pulse Width Modulator An internal 5 k resistor pull-up is provided on this pin. The external opto-coupler sinks current from COMP to control the PWM duty cycle. 14 RT Oscillator timing resistor pin An external resistor connected from RT to ground sets the internal oscillator frequency. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM5025C 3 LM5025C SNVS568C - SEPTEMBER 2008 - REVISED MARCH 2013 www.ti.com PIN DESCRIPTIONS (continued) Pin Name 15 SYNC Oscillator UP/DOWN synchronization input Description The internal oscillator can be synchronized to an external clock with a frequency 20% lower than the internal oscillator's free running frequency. There is no constraint on the maximum sync frequency. Application Information 16 UVLO Line Under-Voltage shutdown An external voltage divider from the power source sets the shutdown comparator levels. The comparator threshold is 2.5V. Hysteresis is set by an internal current source (20 A) that is switched on or off as the UVLO pin potential crosses the 2.5V threshold. Block Diagram 7.6V SERIES REGULATOR VCC VIN 5V REFERENCE VCC REF UVLO UVLO + - LOGIC 2.5V ENABLE OUTPUTS UVLO HYSTERESIS (20 PA) RT VCC OUT_A CLK DRIVER OSCILLATOR SYNC SLOPE D TO VIN DEADTIME OR OVERLAP CONTROL FF RAMP RAMP TIME VCC 5V 5k OUT_B PWM + - COMP 1V SS Amp (Sink Only) LOGIC SS 0.5V Q R Q + - 2.5V MAX V*S CLAMP CS1 S DRIVER PGND + - CS2 0.5V + AGND CLK + LEB SS 90 PA SS 89 PA 4 Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM5025C LM5025C www.ti.com SNVS568C - SEPTEMBER 2008 - REVISED MARCH 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) VIN to GND -0.3V to 105V VCC to GND -0.3V to 16V CS1, CS2 to GND -0.3 to 1.00V All other inputs to GND -0.3 to 7V ESD Rating (3) Human Body Model 2kV Storage Temperature Range -55C to 150C Junction Temperature 150C (1) (2) (3) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For specifications and test conditions, see the Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. For detailed information on soldering plastic TSSOP package, refer to the Packaging Data Book available from Texas Instruments. Operating Ratings (1) VIN Voltage 13 to 90V External Voltage Applied to VCC 8 to 15V Operating Junction Temperature -40C to +125C (1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For specifications and test conditions, see the Electrical Characteristics. Electrical Characteristics Specifications with standard typeface are for TJ = 25C, and those with boldface type apply over full Operating Junction Temperature range. VIN = 48V, VCC = 10V, RT = 32 k, RSET = 27.4 k) unless otherwise stated (1) Symbol Parameter Conditions Min Typ Max 7.3 7.6 7.9 40 55 Units Startup Regulator VCC Reg VCC Regulation VCC Current Limit I-VIN Startup Regulator Leakage (external Vcc Supply) No Load (2) VIN = 100V 165 V mA 500 A VCC Supply VCC Under-voltage Lockout Voltage (positive going Vcc) VCC Under-voltage Hysteresis VCC Supply Current (ICC) VCC Reg 220mV VCC Reg 120mV 1.0 1.5 Cgate = 0 V 2.0 V 4.2 mA Reference Supply VREF Ref Voltage IREF = 0 mA Ref Voltage Regulation IREF = 0 to 10 mA 4.85 Ref Current Limit 10 5 5.15 V 25 50 mV 20 mA 40 ns Current Limit CS1 Prop (1) (2) CS1 Delay to Output CS1 Step from 0 to 0.6V Time to onset of OUT Transition (90%) Cgate = 0 All electrical characteristics having room temperature limits are tested during production with TA = TJ = 25C. All hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Device thermal limitations may limit usable range. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM5025C 5 LM5025C SNVS568C - SEPTEMBER 2008 - REVISED MARCH 2013 www.ti.com Electrical Characteristics (continued) Specifications with standard typeface are for TJ = 25C, and those with boldface type apply over full Operating Junction Temperature range. VIN = 48V, VCC = 10V, RT = 32 k, RSET = 27.4 k) unless otherwise stated (1) Symbol CS2 Prop Parameter CS2 Delay to Output Conditions Cycle by Cycle Threshold Voltage (CS1) Cycle Skip Threshold Voltage (CS2) Min CS2 Step from 0 to 0.6V Time to onset of OUT Transition (90%) Cgate = 0 Resets SS capacitor; auto restart Typ Max 50 Units ns 0.45 0.5 0.55 V 0.45 0.5 0.55 V Leading Edge Blanking Time (CS1) 50 ns CS1 Sink Impedance (clocked) CS1 = 0.4V 30 50 CS1 Sink Impedance (Post Fault Discharge) CS1 = 0.6V 15 30 CS2 Sink Impedance (Post Fault Discharge) CS2 = 0.6V 55 85 CS1 and CS2 Leakage Current CS = CS Threshold - 100mV 1 A Soft-Start Soft-start Current Source Normal 65 90 115 A Soft-start Current Source following a CS2 event 0.5 1 1.5 A Oscillator Frequency1 TA = 25C TJ = Tlow to Thigh 180 175 200 220 225 kHz Frequency2 RT = 10.8 k 510 580 650 kHz 100 ns Sync threshold 2 Min Sync Pulse Width Sync Frequency Range V 160 kHz PWM Comparator Delay to Output COMP step 5V to 0V Time to onset of OUT_A transition low Duty Cycle Range 40 0 COMP to PWM Offset 0.7 COMP Open Circuit Voltage 4.3 COMP Short Circuit Current 1 ns 91 % 1.3 V 5.9 V COMP = 0V 0.6 1 1.4 mA Delta RAMP measured from onset of OUT_A to Ramp peak. COMP = 5V 2.4 2.5 2.6 V Undervoltage Shutdown Threshold 2.44 2.5 2.56 V Undervoltage Shutdown Hysteresis 16 20 24 A 5 10 Volt x Second Clamp Ramp Clamp Level UVLO Shutdown Output Section OUT_A High Saturation 6 MOS Device @ Iout = -10mA, Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM5025C LM5025C www.ti.com SNVS568C - SEPTEMBER 2008 - REVISED MARCH 2013 Electrical Characteristics (continued) Specifications with standard typeface are for TJ = 25C, and those with boldface type apply over full Operating Junction Temperature range. VIN = 48V, VCC = 10V, RT = 32 k, RSET = 27.4 k) unless otherwise stated (1) Symbol Parameter Conditions Min OUTPUT_A Peak Current Bipolar Device @ Vcc/2 Sink Typ Max Units 3 A OUT_A Low Saturation MOS Device @ Iout = 10mA, 6 OUTPUT_A Rise Time Cgate = 2.2nF 20 9 ns OUTPUT_A Fall Time Cgate = 2.2nF 15 ns OUT_B High Saturation MOS Device @ Iout = -10mA, 10 20 OUTPUT_B Peak Current Bipolar Device @ Vcc/2 Sink 1 A OUT_B Low Saturation MOS Device @ Iout = 10mA, 12 OUTPUT_B Rise Time Cgate = 1nF 20 ns OUTPUT_B Fall Time Cgate = 1nF 15 ns 18 Output Timing Control Overlap Time RSET = 38 k connected to GND, 50% to 50% transitions 75 105 135 ns Deadtime RSET = 29.5 k connected to REF, 50% to 50% transitions 75 105 135 ns Thermal Shutdown TSD Thermal Shutdown Threshold 165 C Thermal Shutdown Hysteresis 25 C 125 C/W Thermal Resistance JA Junction to Ambient PW0016A Package Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM5025C 7 LM5025C SNVS568C - SEPTEMBER 2008 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics VCC Regulator Start-up Characteristics, VCC vs Vin VCC vs ICC 10 16 VIN 14 8 12 VCC (V) VCC (V) 10 VCC 8 6 6 4 4 2 2 0 0 0 2 4 6 8 10 12 14 0 16 20 30 40 50 60 ICC (mA) VIN (V) Figure 3. Figure 4. VREF vs IREF Oscillator Frequency vs RT 6 5 VREF (V) 4 3 2 1 0 0 5 10 15 20 25 IREF (mA) Figure 5. Figure 6. Overlap Time vs RSET Overlap Time vs Temperature RSET = 38K 140 400 130 300 OVERLAP TIME (ns) OVERLAP TIME (ns) 350 250 200 150 100 120 110 100 90 50 0 0 20 40 60 80 100 120 RSET (k:) 25 _ 75 _ 125 TEMPERATURE (oC) Figure 7. 8 80 -40 Figure 8. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM5025C LM5025C www.ti.com SNVS568C - SEPTEMBER 2008 - REVISED MARCH 2013 Typical Performance Characteristics (continued) Dead Time vs Temperature RSET = 29.5K Dead Time vs RSET 140 400 350 130 DEADTIME (ns) DEADTIME (ns) 300 250 200 150 120 110 100 100 90 50 0 0 20 40 60 80 100 80 -40 120 RSET (k:) 25 75 125 o TEMPERATURE ( C) Figure 9. Figure 10. SS Pin Current vs Temperature Figure 11. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM5025C 9 LM5025C SNVS568C - SEPTEMBER 2008 - REVISED MARCH 2013 www.ti.com DETAILED OPERATING DESCRIPTION The LM5025C is a functional variant of the LM5025 active clamp PWM controller. The functional differences of the LM5025C are: The maximum duty cycle of the LM5025C is increased from 80% to 91%. The soft-start capacitor charging current is increased from 20 A to 90 A. The VCC regulator current limit threshold is increased from 25 mA to 55 mA. The CS1 and CS2 current limit thresholds have been increased to 0.5V (same as LM5025A). The internal CS2 filter discharge device has been disabled and no longer operates each clock cycle (same as LM5025A). The internal VCC and VREF regulators continue to operate when the line UVLO pin is below threshold (same as LM5025A). The LM5025C PWM controller contains all of the features necessary to implement power converters utilizing the Active Clamp Reset technique. The device can be configured to control either a P-Channel clamp switch or an NChannel clamp switch. With the active clamp technique higher efficiencies and greater power densities can be realized compared to conventional catch winding or RDC clamp / reset techniques. Two control outputs are provided, the main power switch control (OUT_A) and the active clamp switch control (OUT_B). The active clamp output can be configured for either a specified overlap time (for P-Channel switch applications) or a specified dead time (for N_Channel applications). The two internal compound gate drivers parallel both MOS and Bipolar devices, providing superior gate drive characteristics. This controller is designed for high-speed operation including an oscillator frequency range up to 1MHz and total PWM and current sense propagation delays less than 100ns. The LM5025C includes a high-voltage start-up regulator that operates over a wide input range of 13V to 90V. Additional features include: Line Under Voltage Lockout (UVLO), softstart, oscillator UP/DOWN sync capability, precision reference and thermal shutdown. High Voltage Start-Up Regulator The LM5025C contains an internal high voltage start-up regulator that allows the input pin (VIN) to be connected directly to the line voltage. The regulator output is internally current limited to 55 mA. When power is applied, the regulator is enabled and sources current into an external capacitor connected to the VCC pin. The recommended capacitance range for the VCC regulator is 0.1 F to 100 F. When the voltage on the VCC pin reaches the regulation point of 7.6V and the internal voltage reference (REF) reaches its regulation point of 5V, the controller outputs are enabled. The outputs will remain enabled until VCC falls below 6.2V or the line Under Voltage Lock Out detector indicates that VIN is out of range. In typical applications, an auxiliary transformer winding is connected through a diode to the VCC pin. This winding must raise the VCC voltage above 8V to shut off the internal start-up regulator. Powering VCC from an auxiliary winding improves efficiency while reducing the controller power dissipation. When the converter auxiliary winding is inactive, external current draw on the VCC line should be limited so the power dissipated in the start-up regulator does not exceed the maximum power dissipation of the controller. An external start-up regulator or other bias rail can be used instead of the internal start-up regulator by connecting the VCC and the VIN pins together and feeding the external bias voltage into the two pins. Line Under-Voltage Detector The LM5025C contains a line Under Voltage Lock Out (UVLO) circuit. An external set-point voltage divider from Vin to GND, sets the operational range of the converter. The divider must be designed such that the voltage at the UVLO pin will be greater than 2.5V when Vin is in the desired operating range. If the undervoltage threshold is not met, both outputs are disabled,all other functions of the controller remain active. UVLO hysteresis is accomplished with an internal 20 uA current source that is switched on or off into the impedance of the set-point divider. When the UVLO threshold is exceeded, the current source is activated to instantly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below the 2.5V threshold, the current source is turned off causing the voltage at the UVLO pin to fall. The UVLO pin can also be used to implement a remote enable / disable function. Pulling the UVLO pin below the 2.5V threshold disables the PWM outputs. 10 Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM5025C LM5025C www.ti.com SNVS568C - SEPTEMBER 2008 - REVISED MARCH 2013 PWM Outputs The relative phase of the main (OUT_A) and active clamp outputs (OUT_B) can be configured for the specific application. For active clamp configurations utilizing a ground referenced P-Channel clamp switch, the two outputs should be in phase with the active clamp output overlapping the main output. For active clamp configurations utilizing a high side N-Channel switch, the active clamp output should be out of phase with main output and there should be a dead time between the two gate drive pulses. A distinguishing feature of the LM5025C is the ability to accurately configure either dead time (both off) or overlap time (both on) of the gate driver outputs. The overlap / deadtime magnitude is controlled by the resistor value connected to the TIME pin of the controller. The opposite end of the resistor can be connected to either REF for deadtime control or GND for overlap control. The internal configuration detector senses the connection and configures the phase relationship of the main and active clamp outputs. The magnitude of the overlap/dead time can be calculated as follows: * Overlap Time (ns) = 2.8 x RSET - 1.2 * Dead Time (ns) = 2.9 x RSET +20 * RSET in k, Time in ns OUT_A P-Channel Active Clamp (RSET to GND) K1 * RSET K1 * RSET OUT_B OUT_A N-Channel Active Clamp (RSET to REF) K2 * RSET K2 * RSET OUT_B Figure 12. Active Clamp Configurations Compound Gate Drivers The LM5025C contains two unique compound gate drivers, which parallel both MOS and Bipolar devices to provide high drive current throughout the entire switching event. The Bipolar device provides most of the drive current capability and provides a relatively constant sink current which is ideal for driving large power MOSFETs. As the switching event nears conclusion and the Bipolar device saturates, the internal MOS device continues to provide a low impedance to compete the switching event. During turn-off at the Miller plateau region, typically around 2V - 3V, is where gate driver current capability is needed most. The resistive characteristics of all MOS gate drivers are adequate for turn-on since the supply to output voltage differential is fairly large at the Miller region. During turn-off however, the voltage differential is small and the current source characteristic of the Bipolar gate driver is beneficial to provide fast drive capability. VCC OUT CNTRL PGND Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM5025C 11 LM5025C SNVS568C - SEPTEMBER 2008 - REVISED MARCH 2013 www.ti.com PWM Comparator The PWM comparator compares the ramp signal (RAMP) to the loop error signal (COMP). This comparator is optimized for speed in order to achieve minimum controllable duty cycles. The internal 5k pull-up resistor, connected between the internal 5V reference and COMP, can be used as the pull-up for an optocoupler. The comparator polarity is such that 0V on the COMP pin will produce a zero duty cycle on both gate driver outputs. Volt Second Clamp The Volt x Second Clamp comparator compares the ramp signal (RAMP) to a fixed 2.5V reference. By proper selection of RFF and CFF, the maximum ON time of the main switch can be set to the desired duration. The ON time set by Volt x Second Clamp varies inversely with the line voltage because the RAMP capacitor is charged by a resistor connected to Vin while the threshold of the clamp is a fixed voltage (2.5V). An example will illustrate the use of the Volt x Second Clamp comparator to achieve a 50% duty cycle limit, at 200 kHz, at a 48V line input: A 50% duty cycle at a 200 kHz requires a 2.5 s of ON time. At 48V input the Volt x Second product is 120V x s (48V x 2.5s). To achieve this clamp level: RFF x CFF = VIN x TON / 2.5V * Select CFF = 470 pF * RFF = 102k 48 x 2.5 / 2.5 = 48 (1) (2) The recommended capacitor value range for CFF is 100 pF to 1000 pF. The CFF ramp capacitor is discharged at the conclusion of every cycle by an internal discharge switch controlled by either the internal clock or by the V x S Clamp comparator, whichever event occurs first. Current Limit The LM5025C contains two modes of over-current protection. If the sense voltage at the CS1 input exceeds 0.5V the present power cycle is terminated (cycle-by-cycle current limit). If the sense voltage at the CS2 input exceeds 0.5V, the controller will terminate the present cycle, discharge the softstart capacitor and reduce the softstart current source to 1 A. The softstart (SS) capacitor is released after being fully discharged and slowly charges with a 1 A current source. When the voltage at the SS pin reaches approximately 1V, the PWM comparator will produce the first output pulse at OUT_A. After the first pulse occurs, the softstart current source will revert to the normal 90 A level. Fully discharging and then slowly charging the SS capacitor protects a continuously overloaded converter with a low duty cycle hiccup mode. These two modes of over-current protection allow the user great flexibility to configure the system behavior in over-load conditions. If it is desired for the system to act as a current source during an over-load, then the CS1 cycle-by-cycle current limiting should be used. In this case the current sense signal should be applied to the CS1 input and the CS2 input should be grounded. If during an overload condition it is desired for the system to briefly shutdown, followed by softstart retry, then the CS2 hiccup current limiting mode should be used. In this case the current sense signal should be applied to the CS2 input and the CS1 input should be grounded. This shutdown / soft-start retry will repeat indefinitely while the over-load condition remains. The hiccup mode will greatly reduce the thermal stresses to the system during heavy overloads. The cycle-by-cycle mode will have higher system thermal dissipations during heavy overloads, but provides the advantage of continuous operation for short duration overload conditions. It is possible to utilize both over-current modes concurrently, whereby slight overload conditions activate the CS1 cycle-by-cycle mode while more severe overloading activates the CS2 hiccup mode. Generally the CS1 input will always be configured to monitor the main switch FET current each cycle. The CS2 input can be configured in several different ways depending upon the system requirements. a. The CS2 input can also be set to monitor the main switch FET current except scaled to a higher threshold than CS1. b. An external over-current timer can be configured which trips after a pre-determined over-current time, driving the CS2 input high, initiating a hiccup event. c. In a closed loop voltage regulaton system, the COMP input will rise to saturation when the cycle-by-cycle current limit is active. An external filter/delay timer and voltage divider can be configured between the COMP pin and the CS2 pin to scale and delay the COMP voltage. If the CS2 pin voltage reaches 0.5V a hiccup event will initiate. 12 Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM5025C LM5025C www.ti.com SNVS568C - SEPTEMBER 2008 - REVISED MARCH 2013 A small RC filter, located near the controller, is recommended for each of the CS pins. The CS1 input has an internal FET which discharges the current sense filter capacitor at the conclusion of every cycle, to improve dynamic performance. This same FET remains on an additional 50ns at the start of each main switch cycle to attenuate the leading edge spike in the current sense signal. The CS2 discharge FET only operates following a CS2 event, UVLO and thermal shutdown. The LM5025C CS comparators are very fast and may respond to short duration noise pulses. Layout considerations are critical for the current sense filter and sense resistor. The capacitor associated with the CS filter must be placed very close to the device and connected directly to the pins of the IC (CS and GND). If a current sense transformer is used, both leads of the transformer secondary should be routed to the filter network , which should be located close to the IC. If a sense resistor in the source of the main switch MOSFET is used for current sensing, a low inductance type of resistor is required. When designing with a current sense resistor, all of the noise sensitive low power ground connections should be connected together near the IC GND and a single connection should be made to the power ground (sense resistor ground point). Oscillator and Sync Capability The LM5025C oscillator is set by a single external resistor connected between the RT pin and GND. To set a desired oscillator frequency (F), the necessary RT resistor can be calculated from: RT = (6002/F)1.0192 where * * F is in kHz RT in k (3) The RT resistor should be located very close to the device and connected directly to the pins of the IC (RT and GND). A unique feature of LM5025C is the ability to synchronize the oscillator to an external clock with a frequency that is either higher or lower than the frequency of the internal oscillator. The lower frequency sync frequency range is 91% of the free running internal oscillator frequency. There is no constraint on the maximum SYNC frequency. A minimum pulse width of 100 ns is required for the synchronization clock . If the synchronization feature is not required, the SYNC pin should be connected to GND to prevent any abnormal interference . The internal oscillator can be completely disabled by connecting the RT pin to REF. Once disabled, the sync signal will act directly as the master clock for the controller. Both the frequency and the maximum duty cycle of the PWM controller can be controlled by the SYNC signal (within the limitations of the Volt x Second Clamp). The maximum duty cycle (D) will be (1-D) of the SYNC signal. CS2 SS 90 PA 1 PA Feed-Forward Ramp An external resistor (RFF) and capacitor (CFF) connected to VIN and GND are required to create the PWM ramp signal. The slope of the signal at the RAMP pin will vary in proportion to the input line voltage. This varying slope provides line feedforward information necessary to improve line transient response with voltage mode control. The RAMP signal is compared to the error signal at the COMP pin by the pulse width modulator comparator to control the duty cycle of the main switch output. The Volt Second Clamp comparator also monitors the RAMP pin and if the ramp amplitude exceeds 2.5V the present cycle is terminated. The ramp signal is reset to GND at the end of each cycle by either the internal clock or the Volt Second comparator, which ever occurs first. Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM5025C 13 LM5025C SNVS568C - SEPTEMBER 2008 - REVISED MARCH 2013 www.ti.com Soft-Start The softstart feature allows the power converter to gradually reach the initial steady state operating point, thus reducing start-up stresses and surges. At power on, a 90 A current is sourced out of the softstart pin (SS) into an external capacitor. The capacitor voltage will ramp up slowly and will limit the COMP pin voltage and therefore the PWM duty cycle. In the event of a fault as determined by VCC undervoltage, line undervoltage (UVLO) or second level current limit, the output gate drivers are disabled and the softstart capacitor is fully discharged. When the fault condition is no longer present a softstart sequence will be initiated. Following a second level current limit detection (CS2), the softstart current source is reduced to 1 A until the first output pulse is generated by the PWM comparator. The current source returns to the nominal 90 A level after the first output pulse (~1V at the SS pin). Thermal Protection Internal Thermal Shutdown circuitry is provided to protect the integrated circuit in the event the maximum junction temperature is exceeded. When activated, typically at 165C, the controller is forced into a low power standby state with the output drivers and the bias regulator disabled. The device will restart after the thermal hysteresis (typically 25C). During a restart after thermal shutdown, the softstart capacitor will be fully discharged and then charged in the low current mode (1 A) similar to a second level current limit event. The thermal protection feature is provided to prevent catastrophic failures from accidental device overheating. Application Circuit: Input 36-78V, Output 3.3V, 30A 14 Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM5025C LM5025C www.ti.com SNVS568C - SEPTEMBER 2008 - REVISED MARCH 2013 REVISION HISTORY Changes from Revision B (March 2013) to Revision C * Page Changed layout of National Data Sheet to TI format .......................................................................................................... 14 Submit Documentation Feedback Copyright (c) 2008-2013, Texas Instruments Incorporated Product Folder Links: LM5025C 15 PACKAGE OPTION ADDENDUM www.ti.com 10-Sep-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LM5025CMTC/NOPB ACTIVE TSSOP PW 16 92 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 L5025C MTC LM5025CMTCE/NOPB ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 L5025C MTC LM5025CMTCX/NOPB ACTIVE TSSOP PW 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 L5025C MTC (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM5025CMTCE/NOPB TSSOP PW 16 250 180.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 LM5025CMTCX/NOPB TSSOP PW 16 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5025CMTCE/NOPB TSSOP PW LM5025CMTCX/NOPB TSSOP PW 16 250 210.0 185.0 35.0 16 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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