LM5025C
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SNVS568C –SEPTEMBER 2008–REVISED MARCH 2013
LM5025C Active Clamp Voltage Mode PWM Controller
Check for Samples: LM5025C
1FEATURES DESCRIPTION
The LM5025C is a functional variant of the LM5025
2• Internal Start-Up Bias Regulator active clamp PWM controller. The functional
• 3A Compound Main Gate Driver differences of the LM5025C are: The maximum duty
• Programmable Line Under-Voltage Lockout cycle of the LM5025C is increased from 80% to 91%.
(UVLO) with Adjustable Hysteresis The soft-start capacitor charging current is increased
from 20 µA to 90 µA. The VCC regulator current limit
• Voltage Mode Control with Feed-Forward threshold is increased from 25 mA to 55 mA. The
• Adjustable Dual Mode Over-Current Protection CS1 and CS2 current limit thresholds have been
• Programmable Overlap or Deadtime between increased to 0.5V. The internal CS2 filter discharge
the Main and Active Clamp Outputs device has been disabled and no longer operates
each clock cycle. The internal VCC and VREF
• Volt x Second Clamp regulators continue to operate when the line UVLO
• Programmable Soft-start pin is below threshold.
• Leading Edge Blanking The LM5025C PWM controller contains all of the
• Single Resistor Programmable Oscillator features necessary to implement power converters
• Oscillator UP / DOWN Sync Capability utilizing the Active Clamp / Reset technique. With the
active clamp technique, higher efficiencies and
• Precision 5V Reference greater power densities can be realized compared to
• Thermal Shutdown conventional catch winding or RDC clamp / reset
techniques. Two control outputs are provided, the
PACKAGE main power switch control (OUT_A) and the active
clamp switch control (OUT_B). The two internal
• TSSOP-16 compound gate drivers parallel both MOS and Bipolar
devices, providing superior gate drive characteristics.
This controller is designed for high-speed operation
including an oscillator frequency range up to 1MHz
and total PWM and current sense propagation delays
less than 100 ns. The LM5025C includes a high-
voltage start-up regulator that operates over a wide
input range of 13V to 90V. Additional features
include: Line Under Voltage Lockout (UVLO),
softstart, oscillator UP/DOWN sync capability,
precision reference and thermal shutdown.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2008–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LM5025C
UVLO
PGND AGND
COMP
OUT_A
OUT_B
VCC
SS
Rt SYNC
REF
TIME
RAMP
CS1
VIN
VIN
35V - 78V
VOUT
3.3V
UP/DOWN
SYNC
ERROR
AMP and
ISOLATION
CS2
LM5025C
SNVS568C –SEPTEMBER 2008–REVISED MARCH 2013
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Typical Application Circuit
Figure 1. Simplified Active Clamp Forward Power Converter
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RAMP
CS1
CS2
TIME
REF
VCC
OUT_A
VIN
RT
COMP
SS
AGND
PGND
OUT_B
SYNC
UVLO
14
13
12
11
10
8 9
15
16
1
2
3
4
5
7
6
LM5025C
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SNVS568C –SEPTEMBER 2008–REVISED MARCH 2013
Connection Diagram
Figure 2. 16-Lead TSSOP
Package Number PW0016A
PIN DESCRIPTIONS
Pin Name Description Application Information
1 VIN Source Input Voltage Input to start-up regulator. Input range 13V to 90V, with
transient capability to 105V.
2 RAMP Modulator ramp signal An external RC circuit from Vin sets the ramp slope. This
pin is discharged at the conclusion of every cycle by an
internal FET, initiated by either the internal clock or the
V*Sec Clamp comparator.
3 CS1 Current sense input for cycle-by-cycle limiting If CS1 exceeds 0.5V the outputs will go into Cycle-by-
Cycle current limit. CS1 is held low for 50ns after OUT_A
switches high providing leading edge blanking.
4 CS2 Current sense input for soft restart If CS2 exceeds 0.5V the outputs will be disabled and a
softstart commenced. The soft-start capacitor will be fully
discharged and then released with a pull-up current of
1µA. After the first output pulse (when SS =1V), the SS
charge current will revert back to 90 µA.
5 TIME Output overlap/Deadtime control An external resistor (RSET) sets either the overlap time or
dead time for the active clamp output. An RSET resistor
connected between TIME and GND produces in-phase
OUT_A and OUT_B pulses with overlap. An RSET resistor
connected between TIME and REF produces out-of-phase
OUT_A and OUT_B pulses with deadtime.
6 REF Precision 5 volt reference output Maximum output current: 10 mA Locally decouple with a
0.1 µF capacitor. Reference stays low until the VCC UV
comparator is satisfied.
7 VCC Output from the internal high voltage start-up If an auxiliary winding raises the voltage on this pin above
regulator. The VCC voltage is regulated to 7.6V. the regulation setpoint, the internal start-up regulator will
shutdown, reducing the IC power dissipation.
8 OUT_A Main output driver Output of the main switch PWM output gate driver. Output
capability of 3A peak sink current.
9 OUT_B Active Clamp output driver Output of the Active Clamp switch gate driver. Capable of
1.25A peak sink current..
10 PGND Power ground Connect directly to analog ground.
11 AGND Analog ground Connect directly to power ground.
12 SS Soft-start control An external capacitor and an internal 90 µA current source
set the softstart ramp. The SS current source is reduced to
1 µA initially following a CS2 over-current event or an over
temperature event.
13 COMP Input to the Pulse Width Modulator An internal 5 kΩresistor pull-up is provided on this pin.
The external opto-coupler sinks current from COMP to
control the PWM duty cycle.
14 RT Oscillator timing resistor pin An external resistor connected from RT to ground sets the
internal oscillator frequency.
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LOGIC
VIN
REF
SS 90 PA
RT
LOGIC
PGND
AGND
5V
REFERENCE
OSCILLATOR
CLK
CS1
TIME
0.5V
0.5V
PWM
5k
5V
1V
R
S
Q
Q
SS
FF RAMP
CS2
RAMP
SLOPE D TO VIN
CLK + LEB
7.6V SERIES
REGULATOR
OUT_B
DRIVER
VCC
COMP
SS
SS Amp
(Sink Only)
MAX V*S
CLAMP
SYNC
UVLO
HYSTERESIS
(20 PA)
2.5V
+
-
UVLO +
-
OUT_A
DRIVER
VCC
VCC
VCC
UVLO
2.5V
89 PA
DEADTIME
OR
OVERLAP
CONTROL
+
-
+
-
+
-
ENABLE
OUTPUTS
LM5025C
SNVS568C –SEPTEMBER 2008–REVISED MARCH 2013
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PIN DESCRIPTIONS (continued)
Pin Name Description Application Information
15 SYNC Oscillator UP/DOWN synchronization input The internal oscillator can be synchronized to an external
clock with a frequency 20% lower than the internal
oscillator’s free running frequency. There is no constraint
on the maximum sync frequency.
16 UVLO Line Under-Voltage shutdown An external voltage divider from the power source sets the
shutdown comparator levels. The comparator threshold is
2.5V. Hysteresis is set by an internal current source (20
µA) that is switched on or off as the UVLO pin potential
crosses the 2.5V threshold.
Block Diagram
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1)(2)
VIN to GND -0.3V to 105V
VCC to GND -0.3V to 16V
CS1, CS2 to GND -0.3 to 1.00V
All other inputs to GND -0.3 to 7V
ESD Rating (3)
Human Body Model 2kV
Storage Temperature Range -55°C to 150°C
Junction Temperature 150°C
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For specifications and test conditions, see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3) For detailed information on soldering plastic TSSOP package, refer to the Packaging Data Book available from Texas Instruments.
Operating Ratings (1)
VIN Voltage 13 to 90V
External Voltage Applied to VCC 8 to 15V
Operating Junction Temperature -40°C to +125°C
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For specifications and test conditions, see the Electrical Characteristics.
Electrical Characteristics
Specifications with standard typeface are for TJ= 25°C, and those with boldface type apply over full Operating Junction
Temperature range. VIN = 48V, VCC = 10V, RT = 32 kΩ, RSET = 27.4 kΩ) unless otherwise stated (1)
Symbol Parameter Conditions Min Typ Max Units
Startup Regulator
VCC Reg VCC Regulation No Load 7.3 7.6 7.9 V
VCC Current Limit (2) 40 55 mA
I-VIN Startup Regulator VIN = 100V 165 500 µA
Leakage (external Vcc
Supply)
VCC Supply
VCC Under-voltage VCC Reg - VCC Reg - V
Lockout Voltage (positive 220mV 120mV
going Vcc)
VCC Under-voltage 1.0 1.5 2.0 V
Hysteresis
VCC Supply Current (ICC) Cgate = 0 4.2 mA
Reference Supply
VREF Ref Voltage IREF = 0 mA 4.85 55.15 V
Ref Voltage Regulation IREF = 0 to 10 mA 25 50 mV
Ref Current Limit 10 20 mA
Current Limit
CS1 Prop CS1 Delay to Output CS1 Step from 0 to 0.6V 40 ns
Time to onset of OUT
Transition (90%)
Cgate = 0
(1) All electrical characteristics having room temperature limits are tested during production with TA= TJ= 25°C. All hot and cold limits are
specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.
(2) Device thermal limitations may limit usable range.
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SNVS568C –SEPTEMBER 2008–REVISED MARCH 2013
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Electrical Characteristics (continued)
Specifications with standard typeface are for TJ= 25°C, and those with boldface type apply over full Operating Junction
Temperature range. VIN = 48V, VCC = 10V, RT = 32 kΩ, RSET = 27.4 kΩ) unless otherwise stated (1)
Symbol Parameter Conditions Min Typ Max Units
CS2 Prop CS2 Delay to Output CS2 Step from 0 to 0.6V 50 ns
Time to onset of OUT
Transition (90%)
Cgate = 0
Cycle by Cycle Threshold 0.45 0.5 0.55 V
Voltage (CS1)
Cycle Skip Threshold Resets SS capacitor; auto 0.45 0.5 0.55 V
Voltage (CS2) restart
Leading Edge Blanking 50 ns
Time (CS1)
CS1 Sink Impedance CS1 = 0.4V 30 50 Ω
(clocked)
CS1 Sink Impedance CS1 = 0.6V 15 30 Ω
(Post Fault Discharge)
CS2 Sink Impedance CS2 = 0.6V 55 85 Ω
(Post Fault Discharge)
CS1 and CS2 Leakage CS = CS Threshold - 100mV 1µA
Current
Soft-Start
Soft-start Current Source 65 90 115 µA
Normal
Soft-start Current Source 0.5 11.5 µA
following a CS2 event
Oscillator
Frequency1 TA= 25°C 180 200 220 kHz
TJ= Tlow to Thigh 175 225
Frequency2 RT = 10.8 kΩ510 580 650 kHz
Sync threshold 2 V
Min Sync Pulse Width 100 ns
Sync Frequency Range 160 kHz
PWM Comparator
Delay to Output COMP step 5V to 0V 40 ns
Time to onset of OUT_A
transition low
Duty Cycle Range 0 91 %
COMP to PWM Offset 0.7 11.3 V
COMP Open Circuit 4.3 5.9 V
Voltage
COMP Short Circuit COMP = 0V 0.6 11.4 mA
Current
Volt x Second Clamp
Ramp Clamp Level Delta RAMP measured from 2.4 2.5 2.6 V
onset of OUT_A to Ramp peak.
COMP = 5V
UVLO Shutdown
Undervoltage Shutdown 2.44 2.5 2.56 V
Threshold
Undervoltage Shutdown 16 20 24 µA
Hysteresis
Output Section
OUT_A High Saturation MOS Device @ Iout = -10mA, 5 10 Ω
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Electrical Characteristics (continued)
Specifications with standard typeface are for TJ= 25°C, and those with boldface type apply over full Operating Junction
Temperature range. VIN = 48V, VCC = 10V, RT = 32 kΩ, RSET = 27.4 kΩ) unless otherwise stated (1)
Symbol Parameter Conditions Min Typ Max Units
OUTPUT_A Peak Current Bipolar Device @ Vcc/2 3 A
Sink
OUT_A Low Saturation MOS Device @ Iout = 10mA, 6 9Ω
OUTPUT_A Rise Time Cgate = 2.2nF 20 ns
OUTPUT_A Fall Time Cgate = 2.2nF 15 ns
OUT_B High Saturation MOS Device @ Iout = -10mA, 10 20 Ω
OUTPUT_B Peak Current Bipolar Device @ Vcc/2 1 A
Sink
OUT_B Low Saturation MOS Device @ Iout = 10mA, 12 18 Ω
OUTPUT_B Rise Time Cgate = 1nF 20 ns
OUTPUT_B Fall Time Cgate = 1nF 15 ns
Output Timing Control
Overlap Time RSET = 38 kΩconnected to 75 105 135 ns
GND, 50% to 50% transitions
Deadtime RSET = 29.5 kΩconnected to 75 105 135 ns
REF, 50% to 50% transitions
Thermal Shutdown
TSD Thermal Shutdown 165 °C
Threshold
Thermal Shutdown 25 °C
Hysteresis
Thermal Resistance
θJA Junction to Ambient PW0016A Package 125 °C/W
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-40 25 _75 _125
TEMPERATURE (oC)
80
90
100
110
120
130
140
OVERLAP TIME (ns)
020 40 60 80 100 120
RSET (k:)
0
50
100
150
200
250
300
350
400
OVERLAP TIME (ns)
0 5 10 15 20 25
0
1
2
3
4
5
6
VREF (V)
IREF (mA)
0 2 4 6 8 10 12 14 16
VIN (V)
0
2
4
6
8
10
12
14
16
VCC (V)
VIN
VCC
0 20 30 40 50 60
0
2
4
6
8
10
VCC (V)
ICC (mA)
LM5025C
SNVS568C –SEPTEMBER 2008–REVISED MARCH 2013
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Typical Performance Characteristics
VCC Regulator Start-up Characteristics, VCC vs Vin VCC vs ICC
Figure 3. Figure 4.
VREF vs IREF Oscillator Frequency vs RT
Figure 5. Figure 6.
Overlap Time vs Temperature
Overlap Time vs RSET RSET = 38K
Figure 7. Figure 8.
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-40 25 75 125
TEMPERATURE (oC)
80
90
100
110
120
130
140
DEADTIME (ns)
020 40 60 80 100 120
RSET (k:)
0
50
100
150
200
250
300
350
400
DEADTIME (ns)
LM5025C
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SNVS568C –SEPTEMBER 2008–REVISED MARCH 2013
Typical Performance Characteristics (continued)
Dead Time vs Temperature
Dead Time vs RSET RSET = 29.5K
Figure 9. Figure 10.
SS Pin Current vs Temperature
Figure 11.
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LM5025C
SNVS568C –SEPTEMBER 2008–REVISED MARCH 2013
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DETAILED OPERATING DESCRIPTION
The LM5025C is a functional variant of the LM5025 active clamp PWM controller. The functional differences of
the LM5025C are:
The maximum duty cycle of the LM5025C is increased from 80% to 91%. The soft-start capacitor charging
current is increased from 20 µA to 90 µA. The VCC regulator current limit threshold is increased from 25 mA to 55
mA.
The CS1 and CS2 current limit thresholds have been increased to 0.5V (same as LM5025A).
The internal CS2 filter discharge device has been disabled and no longer operates each clock cycle (same as
LM5025A).
The internal VCC and VREF regulators continue to operate when the line UVLO pin is below threshold (same as
LM5025A).
The LM5025C PWM controller contains all of the features necessary to implement power converters utilizing the
Active Clamp Reset technique. The device can be configured to control either a P-Channel clamp switch or an N-
Channel clamp switch. With the active clamp technique higher efficiencies and greater power densities can be
realized compared to conventional catch winding or RDC clamp / reset techniques. Two control outputs are
provided, the main power switch control (OUT_A) and the active clamp switch control (OUT_B). The active clamp
output can be configured for either a specified overlap time (for P-Channel switch applications) or a specified
dead time (for N_Channel applications). The two internal compound gate drivers parallel both MOS and Bipolar
devices, providing superior gate drive characteristics. This controller is designed for high-speed operation
including an oscillator frequency range up to 1MHz and total PWM and current sense propagation delays less
than 100ns. The LM5025C includes a high-voltage start-up regulator that operates over a wide input range of
13V to 90V. Additional features include: Line Under Voltage Lockout (UVLO), softstart, oscillator UP/DOWN sync
capability, precision reference and thermal shutdown.
High Voltage Start-Up Regulator
The LM5025C contains an internal high voltage start-up regulator that allows the input pin (VIN) to be connected
directly to the line voltage. The regulator output is internally current limited to 55 mA. When power is applied, the
regulator is enabled and sources current into an external capacitor connected to the VCC pin. The recommended
capacitance range for the VCC regulator is 0.1 µF to 100 µF. When the voltage on the VCC pin reaches the
regulation point of 7.6V and the internal voltage reference (REF) reaches its regulation point of 5V, the controller
outputs are enabled. The outputs will remain enabled until VCC falls below 6.2V or the line Under Voltage Lock
Out detector indicates that VIN is out of range. In typical applications, an auxiliary transformer winding is
connected through a diode to the VCC pin. This winding must raise the VCC voltage above 8V to shut off the
internal start-up regulator. Powering VCC from an auxiliary winding improves efficiency while reducing the
controller power dissipation.
When the converter auxiliary winding is inactive, external current draw on the VCC line should be limited so the
power dissipated in the start-up regulator does not exceed the maximum power dissipation of the controller.
An external start-up regulator or other bias rail can be used instead of the internal start-up regulator by
connecting the VCC and the VIN pins together and feeding the external bias voltage into the two pins.
Line Under-Voltage Detector
The LM5025C contains a line Under Voltage Lock Out (UVLO) circuit. An external set-point voltage divider from
Vin to GND, sets the operational range of the converter. The divider must be designed such that the voltage at
the UVLO pin will be greater than 2.5V when Vin is in the desired operating range. If the undervoltage threshold
is not met, both outputs are disabled,all other functions of the controller remain active. UVLO hysteresis is
accomplished with an internal 20 uA current source that is switched on or off into the impedance of the set-point
divider. When the UVLO threshold is exceeded, the current source is activated to instantly raise the voltage at
the UVLO pin. When the UVLO pin voltage falls below the 2.5V threshold, the current source is turned off
causing the voltage at the UVLO pin to fall. The UVLO pin can also be used to implement a remote enable /
disable function. Pulling the UVLO pin below the 2.5V threshold disables the PWM outputs.
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VCC
PGND
CNTRL
OUT
OUT_A
OUT_B
OUT_A
OUT_B
K1 * RSET
N-Channel Active Clamp
(RSET to REF)
P-Channel Active Clamp
(RSET to GND)
K2 * RSET
K1 * RSET
K2 * RSET
LM5025C
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SNVS568C –SEPTEMBER 2008–REVISED MARCH 2013
PWM Outputs
The relative phase of the main (OUT_A) and active clamp outputs (OUT_B) can be configured for the specific
application. For active clamp configurations utilizing a ground referenced P-Channel clamp switch, the two
outputs should be in phase with the active clamp output overlapping the main output. For active clamp
configurations utilizing a high side N-Channel switch, the active clamp output should be out of phase with main
output and there should be a dead time between the two gate drive pulses. A distinguishing feature of the
LM5025C is the ability to accurately configure either dead time (both off) or overlap time (both on) of the gate
driver outputs. The overlap / deadtime magnitude is controlled by the resistor value connected to the TIME pin of
the controller. The opposite end of the resistor can be connected to either REF for deadtime control or GND for
overlap control. The internal configuration detector senses the connection and configures the phase relationship
of the main and active clamp outputs. The magnitude of the overlap/dead time can be calculated as follows:
• Overlap Time (ns) = 2.8 x RSET - 1.2
• Dead Time (ns) = 2.9 x RSET +20
• RSET in kΩ, Time in ns
Figure 12. Active Clamp Configurations
Compound Gate Drivers
The LM5025C contains two unique compound gate drivers, which parallel both MOS and Bipolar devices to
provide high drive current throughout the entire switching event. The Bipolar device provides most of the drive
current capability and provides a relatively constant sink current which is ideal for driving large power MOSFETs.
As the switching event nears conclusion and the Bipolar device saturates, the internal MOS device continues to
provide a low impedance to compete the switching event.
During turn-off at the Miller plateau region, typically around 2V - 3V, is where gate driver current capability is
needed most. The resistive characteristics of all MOS gate drivers are adequate for turn-on since the supply to
output voltage differential is fairly large at the Miller region. During turn-off however, the voltage differential is
small and the current source characteristic of the Bipolar gate driver is beneficial to provide fast drive capability.
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PWM Comparator
The PWM comparator compares the ramp signal (RAMP) to the loop error signal (COMP). This comparator is
optimized for speed in order to achieve minimum controllable duty cycles. The internal 5kΩpull-up resistor,
connected between the internal 5V reference and COMP, can be used as the pull-up for an optocoupler. The
comparator polarity is such that 0V on the COMP pin will produce a zero duty cycle on both gate driver outputs.
Volt Second Clamp
The Volt x Second Clamp comparator compares the ramp signal (RAMP) to a fixed 2.5V reference. By proper
selection of RFF and CFF, the maximum ON time of the main switch can be set to the desired duration. The ON
time set by Volt x Second Clamp varies inversely with the line voltage because the RAMP capacitor is charged
by a resistor connected to Vin while the threshold of the clamp is a fixed voltage (2.5V). An example will illustrate
the use of the Volt x Second Clamp comparator to achieve a 50% duty cycle limit, at 200 kHz, at a 48V line
input: A 50% duty cycle at a 200 kHz requires a 2.5 µs of ON time. At 48V input the Volt x Second product is
120V x µs (48V x 2.5µs). To achieve this clamp level:
RFF x CFF = VIN x TON / 2.5V
• Select CFF = 470 pF
• RFF = 102kΩ(1)
48 x 2.5µ / 2.5 = 48µ (2)
The recommended capacitor value range for CFF is 100 pF to 1000 pF.
The CFF ramp capacitor is discharged at the conclusion of every cycle by an internal discharge switch controlled
by either the internal clock or by the V x S Clamp comparator, whichever event occurs first.
Current Limit
The LM5025C contains two modes of over-current protection. If the sense voltage at the CS1 input exceeds 0.5V
the present power cycle is terminated (cycle-by-cycle current limit). If the sense voltage at the CS2 input exceeds
0.5V, the controller will terminate the present cycle, discharge the softstart capacitor and reduce the softstart
current source to 1 µA. The softstart (SS) capacitor is released after being fully discharged and slowly charges
with a 1 µA current source. When the voltage at the SS pin reaches approximately 1V, the PWM comparator will
produce the first output pulse at OUT_A. After the first pulse occurs, the softstart current source will revert to the
normal 90 µA level. Fully discharging and then slowly charging the SS capacitor protects a continuously over-
loaded converter with a low duty cycle hiccup mode.
These two modes of over-current protection allow the user great flexibility to configure the system behavior in
over-load conditions. If it is desired for the system to act as a current source during an over-load, then the CS1
cycle-by-cycle current limiting should be used. In this case the current sense signal should be applied to the CS1
input and the CS2 input should be grounded. If during an overload condition it is desired for the system to briefly
shutdown, followed by softstart retry, then the CS2 hiccup current limiting mode should be used. In this case the
current sense signal should be applied to the CS2 input and the CS1 input should be grounded. This shutdown /
soft-start retry will repeat indefinitely while the over-load condition remains. The hiccup mode will greatly reduce
the thermal stresses to the system during heavy overloads. The cycle-by-cycle mode will have higher system
thermal dissipations during heavy overloads, but provides the advantage of continuous operation for short
duration overload conditions.
It is possible to utilize both over-current modes concurrently, whereby slight overload conditions activate the CS1
cycle-by-cycle mode while more severe overloading activates the CS2 hiccup mode. Generally the CS1 input will
always be configured to monitor the main switch FET current each cycle. The CS2 input can be configured in
several different ways depending upon the system requirements.
a. The CS2 input can also be set to monitor the main switch FET current except scaled to a higher threshold
than CS1.
b. An external over-current timer can be configured which trips after a pre-determined over-current time, driving
the CS2 input high, initiating a hiccup event.
c. In a closed loop voltage regulaton system, the COMP input will rise to saturation when the cycle-by-cycle
current limit is active. An external filter/delay timer and voltage divider can be configured between the COMP
pin and the CS2 pin to scale and delay the COMP voltage. If the CS2 pin voltage reaches 0.5V a hiccup
event will initiate.
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CS2
SS 90 PA
1 PA
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A small RC filter, located near the controller, is recommended for each of the CS pins. The CS1 input has an
internal FET which discharges the current sense filter capacitor at the conclusion of every cycle, to improve
dynamic performance. This same FET remains on an additional 50ns at the start of each main switch cycle to
attenuate the leading edge spike in the current sense signal. The CS2 discharge FET only operates following a
CS2 event, UVLO and thermal shutdown.
The LM5025C CS comparators are very fast and may respond to short duration noise pulses. Layout
considerations are critical for the current sense filter and sense resistor. The capacitor associated with the CS
filter must be placed very close to the device and connected directly to the pins of the IC (CS and GND). If a
current sense transformer is used, both leads of the transformer secondary should be routed to the filter
network , which should be located close to the IC. If a sense resistor in the source of the main switch MOSFET is
used for current sensing, a low inductance type of resistor is required. When designing with a current sense
resistor, all of the noise sensitive low power ground connections should be connected together near the IC GND
and a single connection should be made to the power ground (sense resistor ground point).
Oscillator and Sync Capability
The LM5025C oscillator is set by a single external resistor connected between the RT pin and GND. To set a
desired oscillator frequency (F), the necessary RT resistor can be calculated from:
RT = (6002/F)1.0192
where
• F is in kHz
• RT in kΩ(3)
The RT resistor should be located very close to the device and connected directly to the pins of the IC (RT and
GND).
A unique feature of LM5025C is the ability to synchronize the oscillator to an external clock with a frequency that
is either higher or lower than the frequency of the internal oscillator. The lower frequency sync frequency range is
91% of the free running internal oscillator frequency. There is no constraint on the maximum SYNC frequency. A
minimum pulse width of 100 ns is required for the synchronization clock . If the synchronization feature is not
required, the SYNC pin should be connected to GND to prevent any abnormal interference . The internal
oscillator can be completely disabled by connecting the RT pin to REF. Once disabled, the sync signal will act
directly as the master clock for the controller. Both the frequency and the maximum duty cycle of the PWM
controller can be controlled by the SYNC signal (within the limitations of the Volt x Second Clamp). The
maximum duty cycle (D) will be (1-D) of the SYNC signal.
Feed-Forward Ramp
An external resistor (RFF) and capacitor (CFF) connected to VIN and GND are required to create the PWM ramp
signal. The slope of the signal at the RAMP pin will vary in proportion to the input line voltage. This varying slope
provides line feedforward information necessary to improve line transient response with voltage mode control.
The RAMP signal is compared to the error signal at the COMP pin by the pulse width modulator comparator to
control the duty cycle of the main switch output. The Volt Second Clamp comparator also monitors the RAMP pin
and if the ramp amplitude exceeds 2.5V the present cycle is terminated. The ramp signal is reset to GND at the
end of each cycle by either the internal clock or the Volt Second comparator, which ever occurs first.
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: LM5025C
LM5025C
SNVS568C –SEPTEMBER 2008–REVISED MARCH 2013
www.ti.com
Soft-Start
The softstart feature allows the power converter to gradually reach the initial steady state operating point, thus
reducing start-up stresses and surges. At power on, a 90 µA current is sourced out of the softstart pin (SS) into
an external capacitor. The capacitor voltage will ramp up slowly and will limit the COMP pin voltage and therefore
the PWM duty cycle. In the event of a fault as determined by VCC undervoltage, line undervoltage (UVLO) or
second level current limit, the output gate drivers are disabled and the softstart capacitor is fully discharged.
When the fault condition is no longer present a softstart sequence will be initiated. Following a second level
current limit detection (CS2), the softstart current source is reduced to 1 µA until the first output pulse is
generated by the PWM comparator. The current source returns to the nominal 90 µA level after the first output
pulse (~1V at the SS pin).
Thermal Protection
Internal Thermal Shutdown circuitry is provided to protect the integrated circuit in the event the maximum junction
temperature is exceeded. When activated, typically at 165°C, the controller is forced into a low power standby
state with the output drivers and the bias regulator disabled. The device will restart after the thermal hysteresis
(typically 25°C). During a restart after thermal shutdown, the softstart capacitor will be fully discharged and then
charged in the low current mode (1 µA) similar to a second level current limit event. The thermal protection
feature is provided to prevent catastrophic failures from accidental device overheating.
Application Circuit: Input 36-78V, Output 3.3V, 30A
14 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: LM5025C
LM5025C
www.ti.com
SNVS568C –SEPTEMBER 2008–REVISED MARCH 2013
REVISION HISTORY
Changes from Revision B (March 2013) to Revision C Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 14
Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LM5025C
PACKAGE OPTION ADDENDUM
www.ti.com 10-Sep-2014
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM5025CMTC/NOPB ACTIVE TSSOP PW 16 92 Green (RoHS
& no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 L5025C
MTC
LM5025CMTCE/NOPB ACTIVE TSSOP PW 16 250 Green (RoHS
& no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 L5025C
MTC
LM5025CMTCX/NOPB ACTIVE TSSOP PW 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 125 L5025C
MTC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 10-Sep-2014
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM5025CMTCE/NOPB TSSOP PW 16 250 180.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
LM5025CMTCX/NOPB TSSOP PW 16 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 6-Nov-2015
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM5025CMTCE/NOPB TSSOP PW 16 250 210.0 185.0 35.0
LM5025CMTCX/NOPB TSSOP PW 16 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 6-Nov-2015
Pack Materials-Page 2
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