General Description
The MAX13000E–MAX13005E 6-channel level transla-
tors provide the level shifting necessary to allow data
transfer in multivoltage systems. Externally applied volt-
ages, VCC and VL, set the logic levels on either side of
the device. Logic signals present on the VLside of the
device appear as higher voltage logic signals on the
VCC side of the device, and vice-versa.
The MAX13000E–MAX13005E feature a low VCC and VL
quiescent supply current less than 4µA. The
MAX13000E–MAX13005E also have ±15kV ESD protec-
tion on the I/O VCC side for greater protection in applica-
tions that route signals externally. The ESD protection is
specified using the Human Body Model (HBM). The
MAX13000E/MAX13001E/MAX13002E operate at a guar-
anteed 230kbps data rate. The MAX13003E/
MAX13004E/MAX13005E operate at a guaranteed
20Mbps data rate when VCC > +1.65V.
The MAX13000E/MAX13003E are bidirectional level
translators, allowing data translation in either direction
(VLVCC) on any single data line without a DIRECTION
input. The MAX13001E/MAX13002E/MAX13004E/
MAX13005E unidirectional level translators level shift
data in one direction (VLVCC or VCC VL) on any
single data line. The MAX13001E/MAX13002E/
MAX13004E/MAX13005E unidirectional translators’
inputs have the capability to interface with both CMOS
and open-drain (OD) outputs. For more information see
the Ordering Information, Selector Guide, and the Input-
Driver Requirements sections.
The MAX13000E–MAX13005E operate with +0.9V to
+3.6V VLvoltages and +1.5V to +3.6V VCC voltages. The
MAX13000E–MAX13005E are available in 16-bump
UCSPand 16-pin TSSOP packages, and are specified
over the extended -40°C to +85°C operating tempera-
ture range.
Applications
CMOS Logic-Level Translation
Open-Drain I/O Translation
OD-to-CMOS Signal Conversion
Low-Voltage ASIC Level Translation
Cell Phones
SPI™ and MICROWIRE®Level Translation
Smart-Card Readers
Portable POS Systems
Portable Communication Devices
Low-Cost Serial Interfaces
Telecommunications Equipment
Features
Guaranteed Data-Rate Options
230kbps (MAX13000E/MAX13001E/MAX13002E)
20Mbps (MAX13003E/MAX13004E/MAX13005E)
Bidirectional Level Translation Without a
DIRECTION Input
Operational Down to +0.9V on VLand +1.5V on VCC
±15kV ESD Protection on I/O VCC Lines per HBM
Low <4µA Quiescent Current
Enable/Shutdown Control
2mm x 2mm, 16-Bump UCSP and Lead Packaging
Options
CMOS or Open-Drain Outputs Interface Capability
MAX13000E–MAX13005E
Ultra-Low-Voltage Level Translators
________________________________________________________________ Maxim Integrated Products 1
BOTTOM VIEW
MAX13000E/MAX13003E
4 X 4 UCSP
VCC GND
I/OVCC5
I/OVCC4
I/OVCC3
1
D
C
B
A
234
I/OVCC1 I/OVCC2
I/OVL2
I/OVCC6
I/OVL1 I/OVL5 I/OVL6
I/OVL3V
LEN I/OVL4
Pin Configurations
19-3692; Rev 1; 5/11
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
UCSP is a trademark of Maxim Integrated Products, Inc.
SPI is a trademark of Motorola, Inc.
MICROWIRE is a registered trademark of National
Semiconductor Corp.
Typical Operating Circuits and Selector Guide appear at end
of data sheet.
+Denotes a lead(Pb)-free/RoHS-compliant package.
Ordering Information
PART TEMP RANGE PIN-
PACKAGE
MAX13000EEUE+ -40°C to +85°C 16 TSSOP
Pin Configurations continued at end of data sheet.
Ordering Information continued at end of data sheet.
MAX13000E–MAX13005E
Ultra-Low-Voltage Level Translators
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VCC = +1.5V to +3.6V, VL= +0.9V to VCC, CI/OVL 15pF, CI/OVCC 50pF, TA= -40°C to +85°C, unless otherwise noted. Typical val-
ues are at TA= +25°C.) (Notes 1, 4)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltages referenced to GND.
VCC ...........................................................................-0.3V to +4V
VL..............................................................................-0.3V to +4V
I/OVCC_.......................................................-0.3V to (VCC + 0.3V)
I/OVL_ ............................................................-0.3V to (VL+ 0.3V)
EN .................................................................-0.3V to (VL+ 0.3V)
Short-Circuit Duration I/OVL_, I/OVCC_ to GND ..........Continuous
Continuous Power Dissipation (TA= +70°C)
16-Pin TSSOP (derate 9.4mW/°C at +70°C) ................755mW
16-Bump UCSP (derate 8.2mW/°C at +70°C) .............659mW
Operating Temperature Range ..........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VL Supply Range VLVL VCC (Note 2) 0.9 VCC V
VCC Supply Range VCC (Note 2) 1.5 3.6 V
TA = +25°C4
Supply Current from VCC
(Note 3) IQVCC TA = +85°C40
µA
(Note 3) 1 5
TA = +25°CVL < VCC - 0.2V 2
(Note 3) 4 40
Supply Current from VL (Note 3) IQVL
TA = +85°CVL < VCC - 0.2V 20
µA
EN = GND, TA = +25°C2
VCC Shutdown Supply Current
(Note 3) ISHDN-VCC EN = GND, TA = +85°C20
µA
VL < VCC - 0.2V,
EN = GND 2
TA = +25°C
EN = GND 1 4
VL < VCC - 0.2V,
EN = GND 20
VL Shutdown Supply Current
(Note 3)
TA = +85°C
EN = GND 40
µA
TA = +25°C 0.35
I/O Tri-State Output Leakage
Current
I/O VL_, I/O VCC_,
EN = GND TA = +85°C1
µA
TA = +25°C 0.2
I/O Tri-Stated Output Leakage
Current
VL < VCC - 0.2V, I/O
VL_, I/O VCC_,
EN = GND TA = +85°C 0.5
µA
TA = +25°C 0.35
EN Input Leakage Current TA = +85°C1
µA
MAX13000E–MAX13005E
Ultra-Low-Voltage Level Translators
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +1.5V to +3.6V, VL= +0.9V to VCC, CI/OVL 15pF, CI/OVCC 50pF, TA= -40°C to +85°C, unless otherwise noted. Typical val-
ues are at TA= +25°C.) (Notes 1, 4)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
LOGIC-LEVEL THRESHOLDS
I/OVL_ Input-Voltage-High
Threshold VIHL 2/3 × VLV
I/OVL_ Input-Voltage-Low
Threshold VILL 1/3 × VLV
I/OVCC_ Input-Voltage-High
Threshold VIHC 2/3 ×
VCC V
I/OVCC_ Input-Voltage-Low
Threshold VILC 1/3 ×
VCC V
EN Input-Voltage-High Threshold VIHEN 2/3 × VLV
EN Input-Voltage-Low Threshold VILEN 1/3 × VLV
I/OVL_ Output-Voltage High VOHL I/OVL_ source current = 20µA VL -
0.25 V
MAX13002E/MAX13005E,
OVL_ sink current = 1µA 0.3
I/OVL_ Output-Voltage Low VOLL MAX13000E/MAX13001E/MAX13003E/
MAX13004E, I/OVL_ sink current = 20µA 0.25
V
I/OVCC_ Output-Voltage High VOHC I/OVCC_ source current = 20µA VCC -
0.25 V
MAX13001E/MAX13004E,
OVCC_ sink current = 1µA 0.3
I/OVCC_ Output-Voltage Low VOLC MAX13000E/MAX13002E/MAX13003E/
MAX13005E, I/OVCC_ sink current = 20µA 0.25
V
OUTPUT CURRENTS
VCC = +1.65V,
MAX13003E/MAX13004E/MAX13005E 25
Output Sink Current During
Transient (VCC Side) VCC = +1.65V,
MAX13000E/MAX13001E/MAX13002E 1
mA
VL = +1.2V, VCC = +1.65V,
MAX13003E/MAX13004E/MAX13005E 30
Output Sink Current During
Transient (VL Side) VL = +1.2V, VCC = +1.65V,
MAX13000E/MAX13001E/MAX13002E 1
mA
MAX13000E–MAX13005E
Ultra-Low-Voltage Level Translators
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +1.5V to +3.6V, VL= +0.9V to VCC, CI/OVL 15pF, CI/OVCC 50pF, TA= -40°C to +85°C, unless otherwise noted. Typical val-
ues are at TA= +25°C.) (Notes 1, 4)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VCC = +1.65V,
MAX13003E/MAX13004E/MAX13005E 22
Output Source Current During
Transient (VCC Side) VCC = +1.65V,
MAX13000E/MAX13001E/MAX13002E 1
mA
VL = +1.2V, VCC = +1.65V,
MAX13003E/MAX13004E/MAX13005E 25
Output Source Current During
Transient (VL Side) VL = +1.2V, VCC = +1.65V,
MAX13000E/MAX13001E/MAX13002E 1
mA
ESD PROTECTION
Human Body Model ±15
Air-Gap Discharge (IEC61000-4-2) ±10I/OVCC_
Contact Discharge (IEC61000-4-2) ±8
kV
TIMING CHARACTERISTICS
(VCC = +1.5V to +3.6V, VL= +0.9V to VCC, CI/OVL 15pF, CI/OVCC 50pF, TA= -40°C to +85°C, unless otherwise noted. Typical val-
ues are at TA= +25°C.) (Notes 1, 4)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CI/OVCC = 50pF,
MAX13003E/MAX13004E/MAX13005E,
VCC = +1.65V, Figures 1a, 1b
15
CI/OVCC = 50pF,
MAX13003E/MAX13004E/MAX13005E,
VCC = +1.5V, Figures 1a, 1b
15
I/OVCC_ Rise Time tRVCC
CI/OVCC = 50pF,
MAX13000E/MAX13001E/MAX13002E,
Figures 1a, 1b
400 1400
ns
CI/OVCC = 50pF,
MAX13003E/MAX13004E/MAX13005E,
VCC = +1.65V, Figures 1a, 1b
15
CI/OVCC = 50pF,
MAX13003E/MAX13004E/MAX13005E,
VCC = +1.5V, Figures 1a, 1b
15
I/OVCC_ Fall Time tFVCC
CI/OVCC = 50pF,
MAX13000E/MAX13001E/MAX13002E,
Figures 1a, 1b
400 1400
ns
MAX13000E–MAX13005E
Ultra-Low-Voltage Level Translators
_______________________________________________________________________________________ 5
TIMING CHARACTERISTICS (continued)
(VCC = +1.5V to +3.6V, VL= +0.9V to VCC, CI/OVL 15pF, CI/OVCC 50pF, TA= -40°C to +85°C, unless otherwise noted. Typical val-
ues are at TA= +25°C.) (Notes 1, 4)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CI/OVL = 50pF,
MAX13003E/MAX13004E/MAX13005E,
VCC = +1.65V, Figures 2a, 2b
15
CI/OVL = 15pF,
MAX13003E/MAX13004E/MAX13005E,
VCC = +1.5V, Figures 2a, 2b
15
I/OVL_ Rise Time tRVL
CI/OVL = 50pF,
MAX13000E/MAX13001E/MAX13002E,
Figures 2a, 2b
300 1200
ns
CI/OVL = 50pF,
MAX13003E/MAX13004E/MAX13005E,
VCC = +1.65V, Figures 2a, 2b
15
CI/OVL = 15pF,
MAX13003E/MAX13004E/MAX13005E,
VCC = +1.5V, Figures 2a, 2b
15
I/OVL_ Fall Time tFVL
CI/OVL = 50pF,
MAX13000E/MAX13001E/MAX13002E,
Figures 2a, 2b
300 1200
ns
CI/OVCC = 50pF,
MAX13003E/MAX13004E/MAX13005E,
Figures 1a, 1b
20
Propagation Delay
(Driving I/OVL_)I/OVL-VCC
CI/OVCC = 50pF,
MAX13000E/MAX13001E/MAX13002E,
Figures 1a, 1b
1000
ns
VCC > +1.65V, CI/OVL = 50pF,
MAX13003E/MAX13004E/MAX13005E,
Figures 2a, 2b
20
VCC = 1.5V, CI/OVL = 15pF,
MAX13003E/MAX13004E/MAX13005E,
Figures 2a, 2b
20
Propagation Delay
(Driving I/OVCC_)I/OVCC-VL
CI/OVL = 50pF,
MAX13000E/MAX13001E/MAX13002E,
Figures 2a, 2b
1000
ns
CI/OVCC = 50pF, CMOS output, Figure 3 2
Propagation Delay from
I/OVL to I/OVCC_ after EN
(Note 5)
tEN-VCC
CI/OVCC = 50pF, OD output, Figure 3 6
µs
Typical Operating Characteristics
(VCC = +3.3V, VL= +0.9V, TA = +25°C, MAX13003E.)
0.1
1
10
100
1000
VL SUPPLY CURRENT vs. SUPPLY VOLTAGE
(DRIVING I/O VL, VL = 0.9V)
MAX13000Etoc01
SUPPLY VOLTAGE (V)
VL SUPPLY CURRENT (μA)
1.5 2.4 2.71.8 2.1 3.0 3.3 3.6
DATA RATE = 20Mbps
DATA RATE = 230kbps
VL SUPPLY CURRENT vs. SUPPLY VOLTAGE
(DRIVING I/O VCC, VL = 0.9V)
MAX13000Etoc02
SUPPLY VOLTAGE (V)
VL SUPPLY CURRENT (mA)
3.33.02.72.42.11.8
0.01
0.1
1
0.001
1.5 3.6
DATA RATE = 20Mbps
DATA RATE = 230kbps
VCC SUPPLY CURRENT vs. SUPPLY VOLTAGE
(DRIVING I/O VL, VL = 0.9V)
MAX13000Etoc03
SUPPLY VOLTAGE (V)
VCC SUPPLY CURRENT (mA)
3.33.02.72.42.11.8
0.1
1
10
0.01
1.5 3.6
DATA RATE = 230kbps
DATA RATE = 20Mbps
MAX13000E–MAX13005E
Ultra-Low-Voltage Level Translators
6 _______________________________________________________________________________________
TIMING CHARACTERISTICS (continued)
(VCC = +1.5V to +3.6V, VL= +0.9V to VCC, CI/OVL 15pF, CI/OVCC 50pF, TA= -40°C to +85°C, unless otherwise noted. Typical val-
ues are at TA= +25°C.) (Notes 1, 4)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CI/OVL = 50pF, CMOS output, Figure 4 2
Propagation Delay from
I/OVCC to I/OVL after EN
(Note 5)
tEN-VL
CI/OVL = 50pF, OD output, Figure 4 6
µs
Each translator equally loaded,
MAX13003E/MAX13004E/MAX13005E ±5
Channel-to-Channel Skew tSKEW Each translator equally loaded,
MAX13000E/MAX13001E/MAX13002E ±250
ns
Part-to-Part Skew (Note 6) tPPSKEW
CI/OVL = 15pF, CI/OVCC = 15pF,
VL = +1.8V, VCC = +2V, ΔT = +5°C,
MAX13003E/MAX13004E/MAX13005E
10 ns
MAX13003E/MAX13004E/MAX13005E
VCC > +1.65V, CI/OVL = 50pF,
CI/OVCC = 50pF
20 Mbps
Maximum Data Rate
MAX13000E/MAX13001E/MAX13002E
CI/OVL = 50pF, CI/OVCC = 50pF 230 kbps
Note 1: All devices are 100% production tested at TA= +25°C. Limits are guaranteed by design over the entire temperature range.
Note 2: VLmust be less than or equal to VCC during normal operation. However, VLcan be greater than VCC during startup and
shutdown conditions.
Note 3: This consumption is referred to as no signal transmission.
Note 4: Guaranteed by design with an input signal full swing, rise/fall time 3ns, source resistance is 50Ω.
Note 5: Enable input signal full swing and rise/fall time 50ns.
Note 6: Guaranteed by design, not production tested.
MAX13000E–MAX13005E
Ultra-Low-Voltage Level Translators
_______________________________________________________________________________________ 7
Typical Operating Characteristics (continued)
(VCC = +3.3V, VL= +0.9V, TA = +25°C, MAX13003E.)
0.001
0.01
0.1
1.0
10
VCC SUPPLY CURRENT vs. SUPPLY VOLTAGE
(DRIVING I/OVCC, VL = +0.9V)
MAX13000Etoc04
SUPPLY VOLTAGE (V)
VCC SUPPLY CURRENT (mA)
1.5 2.4 2.71.8 2.1 3.0 3.3 3.6
DATA RATE = 230kbps
DATA RATE = 20Mbps
VL SUPPLY CURRENT vs. TEMPERATURE
(DRIVING I/OVCC, VCC = +3.3V, VL = +0.9V)
MAX13000E toc05
TEMPERATURE (°C)
VCC SUPPLY CURRENT (μA)
603510-15
300
310
320
330
340
290
-40 85
DATA RATE = 20Mbps
VCC SUPPLY CURRENT vs. TEMPERATURE
(DRIVING I/OVCC, VCC = +3.3V, VL = +0.9V)
MAX13000E toc06
TEMPERATURE (°C)
VCC SUPPLY CURRENT (mA)
603510-15
3.90
3.95
4.00
4.05
4.10
3.85
-40 85
DATA RATE = 20Mbps
0
40
20
80
60
120
100
140
10 30 4020 50 60 70 80 90 100
VL SUPPLY CURRENT vs.
CAPACITIVE LOAD ON I/O VCC
(DRIVING I/OVL, VCC = 3.3V, VL = +0.9V)
MAX31000Etoc07
CAPACITIVE LOAD (pF)
VL SUPPLY CURRENT (μA)
DATA RATE = 20Mbps
DATA RATE = 230kbps
0
2
1
4
3
7
5
8
6
9
10 30 4020 50 60 70 80 90 100
VCC SUPPLY CURRENT vs.
CAPACITIVE LOAD ON I/O VCC
(DRIVING I/OVL, VCC = 3.3V, VL = +0.9V)
MAX31000Etoc08
CAPACITIVE LOAD (pF)
VCC SUPPLY CURRENT (mA)
DATA RATE = 20Mbps
DATA RATE = 230kbps
0
2
1
4
3
7
5
8
6
9
10 30 4020 50 60 70 80 90 100
RISE/FALL TIME vs.
CAPACITIVE LOAD ON I/O VCC
(DRIVING I/OVL, VCC = 3.3V, VL = +0.9V)
MAX31000Etoc09
CAPACITIVE LOAD (pF)
RISE/FALL TIME (ns)
tF
tR
0
2
1
4
3
7
5
6
8
10 30 4020 50 60 70 80 90 100
RISE/FALL TIME vs.
CAPACITIVE LOAD ON I/O VL
(DRIVING I/OVCC, = 3.3V, VL = +0.9V)
MAX31000Etoc10
CAPACITIVE LOAD (pF)
RISE/FALL TIME (ns)
tF
tR
5.0
6.0
5.5
7.0
6.5
8.5
7.5
8.0
9.0
10 30 4020 50 60 70 80 90 100
PROPAGATION DELAY vs.
CAPACITIVE LOAD ON I/O VCC
(DRIVING I/OVL, VCC, = 3.3V, VL = +0.9V)
MAX31000Etoc11
CAPACITIVE LOAD (pF)
PROPAGATION DELAY (ns)
2.0
3.0
2.5
4.5
4.0
3.5
5.5
6.0
5.0
6.5
10 40 5020 30 60 70 80 90 100
PROPAGATION DELAY vs.
CAPACITIVE LOAD ON I/O VL
(DRIVING I/OVCC, VCC = 3.3V, VL = +0.9V)
MAX13000Etoc12
CAPACITIVE LOAD (pF)
PROPAGATION DELAY (ns)
MAX13000E–MAX13005E
Ultra-Low-Voltage Level Translators
8 _______________________________________________________________________________________
RAIL-TO-RAIL DRIVING
(DRIVING I/OVL VCC = +3.3V, VL = +0.9V,
CI/OVCC = 50pF, DATA RATE = 4Mbps)
MAX31000Etoc16
I/OVCC
2V/div
GND
I/OVL_
500mV/div
GND
40ns/div
0
6
4
2
1
5
3
7
8
9
10
11
12
13
100 84004250 12,550 16,700 20,850 25,000
VCC + VL SUPPLY CURRENT vs. FREQUENCY
(DRIVING I/OVL, VCC = +3.3V, VL = +0.9V)
MAX31000Etoc18
FREQUENCY (kHz)
VCC + VL SUPPLY CURRENT (mA)
VCC + VL
VL
VCC
I/OVL IS DRIVEN WITH A
0.9V SQUARE WAVE
0
6
4
2
1
5
3
7
8
9
10
11
12
13
100 84004250 12,550 16,700 20,850 25,000
VCC + VL SUPPLY CURRENT vs. FREQUENCY
(DRIVING I/OVCC, VCC = +3.3V, VL = +0.9V)
MAX31000Etoc19
FREQUENCY (kHz)
VCC + VL SUPPLY CURRENT (mA)
VCC + VL
VL
VCC
I/OVCC IS DRIVEN WITH A
3.3V SQUARE WAVE
0
1.5
1.0
0.5
2.0
2.5
3.0
020155 10 253035404550
VOHL vs. IOHL FOR VL SIDE
(VCC = 3.3V)
MAX13000Etoc20
IOHL (μA)
VOHL (V)
VL = +2.5V
VL = +1.8V
VL = +0.9V
0
0.15
0.10
0.05
0.20
0.25
020155 10 253035404550
VOLL vs. IOLL FOR VL SIDE
(VCC = 3.3V)
MAX13000Etoc21
IOLL (μA)
VOLL (V)
VL = +2.5V
VL = +1.8V
VL = +0.9V
OD RAIL-TO-RAIL DRIVING (MAX13005E)
(DRIVING I/OVL, VCC = +3.3V,
VL = +0.9V, CI/OVCC = 56pF,
DATA RATE = 230Mbps, RPULLUP = 1kΩ)
MAX31000Etoc13
I/OVCC
2V/div
GND
I/OVL_
500mV/div
GND
200ns/div
OD RAIL-TO-RAIL DRIVING (MAX13002E)
(DRIVING I/OVL, VCC = +3.3V,
VL = +0.9V, CI/OVCC = 56pF,
DATA RATE = 230kbps, RPULLUP = 15kΩ)
MAX31000Etoc14
I/OVCC
2V/div
GND
I/OVL_
500mV/div
GND
2μs/div
RAIL-TO-RAIL DRIVING
(DRIVING I/OVL, VCC = +3.3V, VL = +0.9V,
CI/OVCC = 50pF, DATA RATE = 230kbps)
MAX31000Etoc15
I/OVCC
2V/div
GND
I/OVL_
500mV/div
GND
1μs/div
RAIL-TO-RAIL DRIVING
(DRIVING I/OVL, VCC = +3.3V, VL = +0.9V,
CI/OVCC = 50pF, DATA RATE = 20Mbps)
MAX31000Etoc17
I/OVCC
2V/div
GND
I/OVL_
500mV/div
GND
10ns/div
Typical Operating Characteristics (continued)
(VCC = +3.3V, VL= +0.9V, TA = +25°C, MAX13003E.)
MAX13000E–MAX13005E
Ultra-Low-Voltage Level Translators
_______________________________________________________________________________________ 9
Pin Descriptions
PIN
TSSOP UCSP NAME FUNCTION
1 B1 I/OVL1 CMOS Input/Output 1, Referenced to VL
2 B2 I/OVL2 CMOS Input/Output 2, Referenced to VL
3 A1 I/OVL3 CMOS Input/Output 3, Referenced to VL
4A2 V
LLogic Input Voltage, +0.9V VL VCC. Bypass VL to GND with a 0.1µF
capacitor.
5A3 EN
Enable Input. When EN is pulled low, I/O VCC1 to I/O VCC6 and I/O VL1 to I/O
VL6 are tri-stated. Drive EN high (VL) for normal operation.
6 A4 I/OVL4 CMOS Input/Output 4, Referenced to VL
7 B3 I/OVL5 CMOS Input/Output 5, Referenced to VL
8 B4 I/OVL6 CMOS Input/Output 6, Referenced to VL
9 C4 I/OVCC6 CMOS Input/Output 6, Referenced to VCC
10 C3 I/OVCC5 CMOS Input/Output 5, Referenced to VCC
11 D4 I/OVCC4 CMOS Input/Output 4, Referenced to VCC
12 D3 GND Ground
13 D2 VCC VCC Input Voltage, +1.5V VCC 3.6V. Bypass VCC to GND with a 0.1µF
capacitor. For full ESD protection, use a 1µF bypass capacitor on VCC.
14 D1 I/OVCC3 CMOS Input/Output 3, Referenced to VCC
15 C2 I/OVCC2 CMOS Input/Output 2, Referenced to VCC
16 C1 I/OVCC1 CMOS Input/Output 1, Referenced to VCC
MAX13000E/MAX13003E
0
0.15
0.10
0.05
0.20
0.25
020155 10 253035404550
VOLC vs.
IOLC FOR VCC SIDE
MAX13000Etoc22
IOLC (μA)
VOLC (V)
VCC = +2.5V
VCC = +1.8V
VCC = +3.3V
Typical Operating Characteristics (continued)
(VCC = +3.3V, VL= +0.9V, TA = +25°C, MAX13003E.)
MAX13000E–MAX13005E
Ultra-Low-Voltage Level Translators
10 ______________________________________________________________________________________
PIN
TSSOP UCSP
NAME FUNCTION
1B1OV
L1 CMOS Output 1, Referenced to VL
2B2OV
L2 CMOS Output 2, Referenced to VL
3A1OV
L3 CMOS Output 3, Referenced to VL
4A2 V
LLogic Input Voltage, +0.9V VL VCC. Bypass VL to GND with a 0.1µF
capacitor.
5A3 EN
Enable Input. When EN is pulled low, OVCC1 to OVCC6 and IVL1 to IVL6 are
tri-stated. Drive EN high (VL) for normal operation.
6A4OV
L4 CMOS Output 4, Referenced to VL
7B3OV
L5 CMOS Output 5, Referenced to VL
8B4OV
L6 CMOS Output 6, Referenced to VL
9C4IV
CC6 Open-Drain-Compatible Input 6, Reference to VCC
10 C3 IVCC5 Open-Drain-Compatible Input 5, Referenced to VCC
11 D4 IVCC4 Open-Drain-Compatible Input 4, Referenced to VCC
12 D3 GND Ground
13 D2 VCC VCC Input Voltage, +1.5V VCC 3.6V. Bypass VCC to GND with a 0.1µF
capacitor. For full ESD protection, use a 1µF bypass capacitor on VCC.
14 D1 IVCC3 Open-Drain-Compatible Input 3, Referenced to VCC
15 C2 IVCC2 Open-Drain-Compatible Input 2, Referenced to VCC
16 C1 IVCC1 Open-Drain-Compatible Input 1, Referenced to VCC
MAX13001E/MAX13004E
Pin Descriptions (continued)
MAX13000E–MAX13005E
Ultra-Low-Voltage Level Translators
______________________________________________________________________________________ 11
PIN
TSSOP UCSP
NAME FUNCTION
1B1 IV
L1 Open-Drain-Compatible Input 1, Referenced to VL
2B2 IV
L2 Open-Drain-Compatible Input 2, Referenced to VL
3A1 IV
L3 Open-Drain-Compatible Input 3, Referenced to VL
4A2 V
LLogic Input Voltage, +0.9V VL VCC. Bypass VL to GND with a 0.1µF
capacitor.
5A3 EN
Enable Input. When EN is pulled low, OVCC1 to OVCC6 and IVL1 to IVL6 are
tri-stated. Drive EN high (VL) for normal operation.
6A4 IV
L4 Open-Drain-Compatible Input 4, Referenced to VL
7B3 IV
L5 Open-Drain-Compatible Input 5, Referenced to VL
8B4 IV
L6 Open-Drain-Compatible Input 6, Referenced to VL
9C4OV
CC6 CMOS Output 6, Referenced to VCC
10 C3 OVCC5 CMOS Output 5, Referenced to VCC
11 D4 OVCC4 CMOS Output 4, Referenced to VCC
12 D3 GND Ground
13 D2 VCC VCC Input Voltage, +1.5V VCC 3.6V. Bypass VCC to GND with a 0.1µF
capacitor. For full ESD protection, use a 1µF bypass capacitor on VCC.
14 D1 OVCC3 CMOS Output 3, Referenced to VCC
15 C2 OVCC2 CMOS Output 2, Referenced to VCC
16 C1 OVCC1 CMOS Output 1, Referenced to VCC
MAX13002E/MAX13005E
Pin Descriptions (continued)
MAX13000E–MAX13005E
Ultra-Low-Voltage Level Translators
12 ______________________________________________________________________________________
Test Circuits/Timing Diagrams
Figure 1a. Driving I/OVL Figure 1b. Timing for Driving I/OVL
MAX13000E
CI/OVCC
EN
I/OVL_
RS
SOURCE
VLVCC
I/OVCC
UNUSED I/Os ARE GROUNDED.
90%
50%
10%
I/OVCC_
I/OVL_
tRISE/FALL
I/OVL-VCC
tRVCC
tFVCC
90%
50%
10%
I/OVL-VCC
tRISE/FALL < 3ns (MAX13003E/MAX13004E/MAX13005E)
tRISE/FALL < 80ns (MAX13000E/MAX13001E/MAX13002E)
Figure 2a. Driving I/OVCC Figure 2b. Timing for Driving I/OVCC
MAX13000E
CI/OVL
EN
I/OVL_
RS
SOURCE
UNUSED I/Os ARE GROUNDED.
VLVCC
I/OVCC
90%
50%
10%
I/OVCC_
I/OVL_
tRISE/FALL
I/OVCC-VL I/OVCC-VL
tRVL
tFVL
90%
50%
10%
tRISE/FALL < 3ns (MAX13003E/MAX13004E/MAX13005E)
tRISE/FALL < 80ns (MAX13000E/MAX13001E/MAX13002E)
MAX13000E–MAX13005E
Ultra-Low-Voltage Level Translators
______________________________________________________________________________________ 13
Test Circuits/Timing Diagrams (continued)
Figure 3. Propagation Delay from I/OVLto I/OVCC After EN
MAX13000E
CI/OVCC
EN
I/OVL_
SOURCE
I/OVCC
MAX13000E
CI/OVCC
EN
I/OVL_
SOURCE
VL
I/OVCC
EN
VL
0
VL
VCC
0
0
I/OVL_
I/OVCC_
t'EN-VCC
EN
VL
0
VL
VCC
0
0
I/OVL_
tEN-VCC IS WHICH EVER IS LARGER BETWEEN t'EN-VCC AND t"EN-VCC.
I/OVCC_
VCC / 2
t"EN-VCC
VCC / 2
Figure 4. Propagation Delay from I/OVCC to I/OVLAfter EN
MAX13000E
VCC
EN
I/OVL_
SOURCE
VL
I/OVCC
CI/OVL
MAX13000E
EN
I/OVL_
SOURCE
VL
I/OVCC
CI/OVL
EN
VL
0
VCC
VL
0
0
I/OVCC_
I/OVL_ VL / 2
t'EN-VL
EN
VL
0
VCC
VL
0
0
I/OVCC_
tEN-VL IS WHICH EVER IS LARGER BETWEEN t'EN-VL AND t"EN-VL.
I/OVL_ VL / 2
t"EN-VL
MAX13000E–MAX13005E
Detailed Description
The MAX13000E–MAX13005E logic-level translators
provide the level shifting necessary to allow data trans-
fer in multivoltage systems. Externally applied voltages,
VCC and VL, set the logic levels on each side of the
device. Logic signals present on the VLside of the
device appear as higher voltage logic signals on the
VCC side of the device, and vice-versa.
The MAX13000E/MAX13003E are bidirectional level
translators allowing data translation in either direction
(VLVCC) on any single data line without the use of a
DIRECTION input. The MAX13001E/MAX13002E/
MAX13004E/MAX13005E unidirectional level translators
level shift data in one direction (VLVCC or VCC
VL) on any single data line. The MAX13001E/
MAX13002E/MAX13004E/MAX13005E unidirectional
translators’ inputs have the capability to interface with
both CMOS and open-drain (OD) outputs. For more
information, see the Ordering Information section and
the Input Driver Requirements section.
The MAX13000E–MAX13005E accept VLfrom +0.9V to
+3.6V. All devices have VCC ranging from +1.5V to
+3.6V, making them ideal for data transfer between
low-voltage ASICs/PLDs and higher voltage systems.
The MAX13000E–MAX13005E feature low VCC quies-
cent supply current of less than 4µA, and VLquiescent
supply current of less than 2µA when in shutdown. The
MAX13000E–MAX13005E have ±15kV ESD protection
on the VCC side for greater protection in applications
that route signals externally. The ESD protection is
specified using the Human Body Model (HBM).The
MAX13000E/MAX13001E/MAX13002E operate at a
guaranteed 230kbps data rate. The MAX13003E/
MAX13004E/MAX13005E operate at a guaranteed
20Mbps data rate when VCC > +1.65V.
Level Translation
For normal operation, ensure that +1.5V VCC +3.6V,
and +0.9V VLVCC. During power-up sequencing,
VLVCC does not damage the device whenever VLis
within the absolute maximum ratings (see the Absolute
Maximum Ratings section). During power-supply
sequencing, when VCC is floating and VLis powered
up, 1mA of current can be sourced to each load on the
VLside, yet the device does not latch up.
The MAX13000E–MAX13005E are designed to have
VCC VLat all times; however, if VCC is turned off, the
part will not be damaged and will not latch up. To pre-
vent excessive leakage currents in either the I/O or
supply lines, the I/O on the VLside must be left in the
high state.
The maximum data rate for the MAX13000E–
MAX13005E depends heavily on the load capacitance
(see the Typical Operating Characteristics), output
impedance of the driver, and the operational voltage
range (see the Timing Characteristics table).
Open-Drain Operation
The MAX13001E/MAX13002E/MAX13004E/MAX13005E
have input stages specifically designed to accommo-
date external open-drain drivers. When using open-
drain drivers, the MAX13001E/MAX13002E/
MAX13004E/MAX13005E operate in a unidirectional-
only mode, translating from the OD side to the CMOS
side. For improved performance, the rise- and fall-time
accelerators are present on both the CMOS and the
OD side. See the Input-Driver Requirement section. Do
not use pullup resistors greater than 15kΩfor proper
operation, and smaller pullup resistance may be need-
ed for higher speed operation.
Input-Driver Requirements
The MAX13000E–MAX13005E feature four different
architectures based on the speed of the part, as well as
on whether the translator is a CMOS-to-CMOS transla-
tor, or whether it is an OD-to-CMOS translator.
20Mbps CMOS-to-CMOS Bidirectional Translator
(MAX13003E)
The MAX13003E architecture is based on a one-shot
accelerator output stage (Figure 5). Accelerator output
stages are always in tri-state, except when there is a
transition on any of the translators on the input side,
either I/OVLor I/OVCC. A short pulse is generated dur-
ing which the one-shot output stage becomes active
and charges/discharges the capacitances at the I/Os.
Due to its bidirectional nature, the accelerator stages on
both the I/OVCC and the I/OVLbecome active during an
I/O transition from low to high or high to low. This can
lead to some current feeding into the external source
that is driving the translator. However, this behavior
helps speed up the transition on the driven side.
The type of devices that drive the inputs of the
MAX13003E is usually specified with an output drive-
current capability (IOUT). When driving the inputs of the
MAX13003E, the maximum achievable speed is con-
strained by the drive current of the external driver. To
insure the maximum possible throughput of 20Mbps, the
external driver should meet the following requirement:
IOUT 1.67 × 108 × V ×(CIN + CP)
Ultra-Low-Voltage Level Translators
14 ______________________________________________________________________________________
where, CPis the parasitic capacitance of the traces, V
is the supply voltage of the driven side (i.e., VLor VCC),
and CIN is the input capacitance of the driven side
(CIN = 10pF for VLside, CIN = 20pF for VCC side).
20Mbps OD-to-CMOS Unidirectional Translators
(MAX13004E/MAX13005E)
The MAX13004E/MAX13005E architecture is virtually the
same as that for the bidirectional CMOS-to-CMOS trans-
lators, the only difference being that the output inverter
(inverter 4) at the driving side accommodates the driving
capabilities of an open-drain output (Figure 6).
For proper operation, a pullup resistor needs to be con-
nected from the open-drain output to the power supply of
the driving side. Use pullup resistors no larger than 15kΩ.
230kbps CMOS-to-CMOS Bidirectional Translator
(MAX13000E)
The architecture of the MAX13000E lacks the one-shot
accelerator output stages since the transitions that this
device handles are limited by its data rate, 230kbps
(Figure 7).
For proper operation, the driver must meet the following
conditions: 1kΩmaximum output impedance and 1mA
minimum output current.
230kbps OD-to-CMOS Unidirectional Translators
(MAX13001E/MAX13002E)
The architecture of the MAX13001E/MAX13002E is simi-
lar to that of the 230kbps CMOS-to-CMOS part, with the
difference that it accommodates the driving capability of
an open-drain output on the driving side, and also that it
has only a single one-shot output stage (Figure 8).
For proper operation, a pullup resistor needs to be con-
nected from the open-drain output to the power supply of
the driving side. Use pullup resistors no larger than 15kΩ.
Figure 9 shows a graph of the typical input current ver-
sus input voltage for all of the above configurations.
Enable Output Mode (EN)
The MAX13000E–MAX13005E feature an enable (EN)
input. Drive EN low to set the MAX13000E–MAX13005E
I/Os in tri-state mode. Drive EN high (VL) for normal
operation.
±15kV ESD Protection
As with all Maxim devices, ESD-protection structures
are incorporated on all pins to protect against electro-
static discharges encountered during handling and
assembly. The I/OVCC lines have extra protection
against static discharge. Maxim’s engineers have
developed state-of-the-art structures to protect these
pins against ESD of ±15kV without damage. The ESD
MAX13000E–MAX13005E
Ultra-Low-Voltage Level Translators
______________________________________________________________________________________ 15
P
ONE-SHOT
VCC
VL
I/OVLI/OVCC
5kΩ
5kΩ
INVERTER 3
INVERTER 4
INVERTER 2
INVERTER 1 N
ONE-SHOT
P
ONE-SHOT
N
ONE-SHOT
Figure 5. Architecture of 20Mbps, CMOS-to-CMOS Bidirectional Translators
MAX13000E–MAX13005E
Ultra-Low-Voltage Level Translators
16 ______________________________________________________________________________________
P
ONE-SHOT
VL/VCC
VCC/VL
IVCC/IVLOVL/OVCC
5kΩ
75kΩ
INVERTER
4
5kΩ
INVERTER 3
N
ONE-SHOT
P
ONE-SHOT
N
ONE-SHOT
OPEN-DRAIN
COMPATIBLE INPUT
CMOS-
COMPATIBLE INPUT
20Mbps OPEN-DRAIN-TO-CMOS UNIDIRECTIONAL LEVEL TRANSLATOR
INVERTER 1
INVERTER 2
Figure 6. Architecture of 20Mbps, OD-to-CMOS Unidirectional Translators
VCC
VL
I/OVLI/OVCC
5kΩ
5kΩ
INVERTER 3
INVERTER 4
INVERTER 2
INVERTER 1
230kbps Bidirectional CMOS-TO-CMOS Level Translator
Figure 7. Architecture of 230kbps, CMOS-to-CMOS Bidirectional Translator
MAX13000E–MAX13005E
Ultra-Low-Voltage Level Translators
______________________________________________________________________________________ 17
structures withstand high ESD in all states: normal
operation, tri-state output mode, and power-down. After
an ESD event, Maxim’s E-versions keep working with-
out latchup, whereas competing products can latch
and must be powered-down to remove latchup.
ESD protection can be tested in various ways. The
I/OVCC lines of the MAX13000E–MAX13005E are char-
acterized for protection to ±15kV using the Human
Body Model.
ESD Test Conditions
ESD performance depends on a variety of conditions.
Contact Maxim for a reliability report that documents
test setup, test methodology, and test results.
Human Body Model
Figure 10 shows the Human Body Model and Figure 11
shows the current waveform it generates when dis-
charged into a low impedance. This model consists of
a 100pF capacitor charged to the ESD voltage of inter-
est, which is then discharged into the test device
through a 1.5kΩresistor.
VL/VCC
VCC/VL
IVCC/IVLOVL/OVCC
5kΩ
75kΩ
5kΩ
INVERTER
4
5kΩ
INVERTER 3
INVERTER 2INVERTER 1
N
ONE-SHOT
OPEN-DRAIN
COMPATIBLE INPUT
CMOS-
COMPATIBLE INPUT
230kbps OPEN-DRAIN-TO-CMOS UNIDIRECTIONAL LEVEL TRANSLATOR
VIN
WHERE, VS = VCC OR VL
VTH_IN / RIN1
(VS - VTH_IN) /
RIN2
IIN
VS
RIN1 = RIN2 = 5kΩ FOR CMOS-TO-CMOS TRANSLATORS
RIN1 = 75kΩ FOR OD-TO-CMOS TRANSLATORS
0
VTH_IN
Figure 8. Architecture of 230kbps, OD-to-CMOS Unidirectional Translator
Figure 9. Typical IIN vs. VIN
MAX13000E–MAX13005E
IEC 61000-4-2 Standard ESD Protection
The IEC 61000-4-2 standard (Figure 12) specifies ESD
tolerance for electronic systems. The IEC61000-4-2
model specifies a 150pF capacitor that is discharged
into the device through a 330Ωresistor. The
MAX13000E–MAX13005E’s I/O on the VCC side are
rated for IEC 61000-4-2 standard, (8kV Contact
Discharge and ±10kV Air-Gap Discharge).
The IEC 61000-4-2 model discharges higher peak cur-
rent and more energy than the HBM due to the lower
series resistance and larger capacitor.
Applications Information
Power-Supply Decoupling
To reduce ripple and the chance of transmitting incor-
rect data, bypass VLand VCC to ground with a 0.1µF
capacitor. To ensure full ±15kV ESD protection, bypass
VCC to ground with a 1µF capacitor. Place all capaci-
tors as close to the power-supply inputs as possible.
UCSP Package Considerations
For general UCSP package information and PC layout
considerations, please refer to Maxim application note:
Wafer-Level Chip-Scale Package.
UCSP Reliability
The chip-scale package (UCSP) represents a unique
packaging form factor that may not perform equally to a
packaged product through traditional mechanical relia-
bility tests. UCSP reliability is integrally linked to the
user’s assembly methods, circuit board material, and
usage environment. The user should closely review
these areas when considering use of a UCSP package.
Performance through Operating Life Test and Moisture
Resistance remains uncompromised as it is primarily
determined by the wafer-fabrication process.
Mechanical stress performance is a greater considera-
tion for a UCSP package. UCSPs are attached through
direct solder contact to the user’s PC board, foregoing
the inherent stress relief of a packaged product lead
frame. Solder joint contact integrity must be consid-
ered. Information on Maxim’s qualification plan, test
data, and recommendations are detailed in the UCSP
application note, which can be found on Maxim’s web-
site at www.maxim-ic.com.
Ultra-Low-Voltage Level Translators
18 ______________________________________________________________________________________
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
RC 1MΩRD 1500Ω
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
CS
100pF
Figure 10. Human Body ESD Test Model
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Cs
150pF
RC
50Ω TO 100Ω
RD
330Ω
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
Figure 12. IEC 61000-4-2 Contact Discharge Test Model
100%
90%
36.8%
tRL
tDL
TIME
CURRENT WAVEFORM
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
10%
0
0
AMPERES
IPIr
Figure 11. Human Body Current Waveform
MAX13000E–MAX13005E
Ultra-Low-Voltage Level Translators
______________________________________________________________________________________ 19
Functional Diagram
MAX13000E–MAX13005E
VLVCC
EN
I/OVL1
I/OVL2
I/OVL3
I/OVL4
I/OVL5
I/OVL6I/OVCC6
I/OVCC5
I/OVCC4
I/OVCC3
I/OVCC2
I/OVCC1
GND
MAX13000E–MAX13005E
Ultra-Low-Voltage Level Translators
20 ______________________________________________________________________________________
Typical Operating Circuits
MAX13001E
MAX13004E
+0.9V
0.1μF1μF
+2.8V
+0.9V
SYSTEM
CONTROLLER
+2.8V
SYSTEM
DATA5
DATA6
DATA1
DATA3
DATA4
DATA2
DATA6
DATA1
DATA2
DATA3
DATA4
DATA5
GND
VLVCC
IVCC_6
IVCC_5
IVCC_4
IVCC_3
IVCC_2
IVCC_1
OVL_1
OVL_2
OVL_3
OVL_4
OVL_5
OVL_6
EN
MAX13002E
MAX13005E
+0.9V
0.1μF1μF
+2.8V
+0.9V
SYSTEM
CONTROLLER
+2.8V
SYSTEM
DATA5
DATA6
DATA1
DATA3
DATA4
DATA2
DATA6
DATA1
DATA2
DATA3
DATA4
DATA5
GND
VLVCC
OVCC_6
OVCC_5
OVCC_4
OVCC_3
OVCC_2
OVCC_1
IVL_1
IVL_2
IVL_3
IVL_4
IVL_5
IVL_6
EN
MAX13000E–MAX13005E
Ultra-Low-Voltage Level Translators
______________________________________________________________________________________ 21
Typical Operating Circuits (continued)
MAX13000E
MAX13003E
+0.9V
1μF
+2.8V
+0.9V
SYSTEM
CONTROLLER
+2.8V
SYSTEM
DATA5
DATA6
DATA1
DATA3
DATA4
DATA2
DATA6
DATA1
DATA2
DATA3
DATA4
DATA5
GND
VLVCC
I/OVCC_6
I/OVCC_5
I/OVCC_4
I/OVCC_3
I/OVCC_2
I/OVCC_1
I/OVL_1
I/OVL_2
I/OVL_3
I/OVL_4
I/OVL_5
I/OVL_6
EN
0.1μF
Selector Guide
PART
DATA
RATE
(bps)
NUMBER OF
BIDIRECTIONAL
TRANSLATORS
NUMBER OF
VL VCC
TRANSLATORS
NUMBER OF
VCC VL
TRANSLATORS
TRANSLATOR
CONFIGURATION
MAX13000E 230k 6 CMOS-to-CMOS
MAX13001E 230k 6 OD-to-CMOS
MAX13002E 230k 6 OD-to-CMOS
MAX13003E 20M 6 CMOS-to-CMOS
MAX13004E 20M 6 OD-to-CMOS
MAX13005E 20M 6 OD-to-CMOS
I/OVCC3
16 I/OVCC1
15 I/OVCC2
14
I/OVCC4
13 VCC
12 GND
11
I/OVCC6
10 I/OVCC5
9
5
6
7
3
4
8
I/OVL2
I/OVL3
1I/OVL1
MAX13000E
MAX13003E
TSSOP
2
EN
I/OVL4
VL
I/OVL5
I/OVL6
TOP VIEW
IVCC3
16 IVCC1
15 IVCC2
14
IVCC4
13 VCC
12 GND
11
IVCC6
10 IVCC5
9
5
6
7
3
4
8
OVL2
OVL3
1OVL1
MAX13001E
MAX13004E
TSSOP
2
EN
OVL4
VL
OVL5
OVL6
OVCC3
16 OVCC1
15 OVCC2
14
OVCC4
13 VCC
12 GND
11
OVCC6
10 OVCC5
9
5
6
7
3
4
8
IVL2
IVL3
1IVL1
MAX13002E
MAX13005E
TSSOP
2
EN
IVL4
VL
IVL5
IVL6
MAX13000E–MAX13005E
Ultra-Low-Voltage Level Translators
22 ______________________________________________________________________________________
BOTTOM VIEW
MAX13001E/MAX13004E MAX13002E/MAX13005E
4 X 4 UCSP
VCC GND
IVCC5
IVCC4
IVCC3
1
D
C
B
A
234
IVCC1IV
CC2
OVL2
IVCC6
OVL1OV
L5OV
L6
OVL3V
LEN OVL4
4 X 4 UCSP
VCC GND
OVCC5
OVCC4
OVCC3
1
D
C
B
A
234
OVCC1OV
CC2
IVL2
OVCC6
IVL1IV
L5IV
L6
IVL3V
LEN IVL4
Pin Configurations (continued)
MAX13000E–MAX13005E
Ultra-Low-Voltage Level Translators
______________________________________________________________________________________ 23
Ordering Information (continued)
PART TEMP RANGE PIN-
PACKAGE
MAX13000EEBE+T* -40°C to +85°C 16 UCSP
(4mm × 4mm)
MAX13001EEUE+ -40°C to +85°C 16 TSSOP
MAX13001EEBE+T* -40°C to +85°C 16 UCSP
(4mm × 4mm)
MAX13002EEUE+ -40°C to +85°C 16 TSSOP
MAX13002EEBE+T* -40°C to +85°C 16 UCSP
(4mm × 4mm)
MAX13003EEUE+ -40°C to +85°C 16 TSSOP
MAX13003EEBE+T* -40°C to +85°C 16 UCSP
(4mm × 4mm)
MAX13004EEUE+ -40°C to +85°C 16 TSSOP
MAX13004EEBE+T* -40°C to +85°C 16 UCSP
(4mm × 4mm)
MAX13005EEUE+ -40°C to +85°C 16 TSSOP
MAX13005EEBE+T* -40°C to +85°C 16 UCSP
(4mm × 4mm)
Chip Information
PROCESS: BiCMOS
*Future Product—contact factory for availability.
+Denotes a lead(Pb)-free/RoHS-compliant package.
T =Tape and reel.
MAX13000E–MAX13005E
Ultra-Low-Voltage Level Translators
24 ______________________________________________________________________________________
PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
16 TSSOP U16+2 21-0066 90-0117
16 UCSP B16+1 21-0101 Refer to Application Note 1891
Package Information
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
MAX13000E–MAX13005E
Ultra-Low-Voltage Level Translators
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 25
© 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
06/05Initi al rel ease
1 5/11 Added lead-free information to the Ordering Information 1, 23