LMR12015/20
VIN PVIN
EN
BOOST
SW
FB
GND/DAP
VOUT
C2 L1
C1
C3
R1
R2
D1
SYNC
AVIN
CLK
ON
OFF
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMR12015
,
LMR12020
SNVS817B –JUNE 2012–REVISED JUNE 2019
LMR120xx 20-V
IN
, 1.5-A or 2-A Step-Down Voltage Regulator in WSON Package
1
1 Features
1• Input Voltage Range of 3 V to 20 V
• Output Voltage Range of 1 V to 18 V
• LMR12015 and LMR12020 Deliver 1.5-A and 2-A
Maximum Output Current, Respectively
• 2-MHz Switching Frequency
• Frequency Synchronization from 1 MHz to 2.35
MHz
• 70-nA Shutdown Current
• 1% Voltage-Reference Accuracy
• Peak-Current-Mode PWM Operation
• Thermal Shutdown
• Internally Compensated
• Internal Soft Start
• Tight Accuracy for Powering Digital ICs
• Extremely Easy to Use
• Tiny Overall Solution Reduces System Cost
• Space-Saving WSON (3 × 3 × 0.8 mm) Packaging
• Create a custom design using the LMR12015
WEBENCH®Power Designer or LMR12020
WEBENCH®Power Designer
2 Applications
• Point-of-Load Conversions from 3.3-V, 5-V, and
12-V Rails
• Space-Constrained Applications
3 Description
The LMR120xx regulator is a monolithic, high
frequency, PWM step-down DC/DC converter in a 10-
pin WSON package. It contains all the active
functions to provide local DC/DC conversion with fast
transient response and accurate regulation in the
smallest possible PCB area.
With a minimum of external components the
LMR12015/20 is easy to use. The ability to drive 1.5-
A or 2-A loads, with an internal 150-mΩNMOS
switch results in the best power density available.
The control circuitry allows for on-times as low as
65 ns, thus supporting exceptionally high frequency
conversion. Switching frequency is internally set to 2
MHz and synchronizable from 1 to 2.35 MHz, which
allows the use of extremely small surface mount
inductors and chip capacitors. Even though the
operating frequency is very high, efficiencies up to
90% are easy to achieve. External shutdown is
included featuring an ultra-low shutdown current of
70 nA. The LMR12015/20 utilizes peak current mode
control and internal compensation to provide high-
performance regulation over a wide range of
operating conditions. Additional features include
internal soft-start circuitry to reduce inrush current,
pulse-by-pulse current limit, thermal shutdown, and
output overvoltage protection.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
LMR12015 WSON (10) 3.00 mm × 3.00 mm
LMR12020
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Circuit
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 Recommended Operating Ratings............................ 4
6.3 Electrical Characteristics........................................... 5
6.4 Typical Performance Characteristics ........................ 6
7 Detailed Description............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram....................................... 11
7.3 Feature Description................................................. 12
7.4 Device Operation Modes ........................................ 14
8 Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Application ................................................. 16
9 Layout................................................................... 33
9.1 Layout Considerations ............................................ 33
10 Device and Documentation Support................. 35
10.1 Device Support...................................................... 35
10.2 Related Links ........................................................ 35
10.3 Receiving Notification of Documentation Updates 35
10.4 Community Resources.......................................... 35
10.5 Trademarks........................................................... 36
10.6 Electrostatic Discharge Caution............................ 36
10.7 Glossary................................................................ 36
11 Mechanical, Packaging, and Orderable
Information........................................................... 36
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (April 2013) to Revision B Page
• Editorial changes only; add WEBENCH links ........................................................................................................................ 1
Changes from Original (April 2013) to Revision A Page
• Changed layout of National Semiconductor data sheet to TI format...................................................................................... 1
2
3
47
9
8
PVIN
SW
EN
DAP AVIN
GND
BOOST
6
10
1
5
SYNC FB
SW PVIN
3
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5 Pin Configuration and Functions
DSC Package
10-Pin WSON
Top View
Pin Descriptions
PIN DESCRIPTION
NO. NAME
1,2 SW Output switch. Connects to the inductor, catch diode, and bootstrap capacitor.
3 BOOST Boost voltage that drives the internal NMOS control switch. A bootstrap capacitor is connected between
the BOOST and SW pins.
4 EN Enable control input. Logic high enables operation. Do not allow this pin to float or be greater than VIN +
0.3 V.
5 SYNC Frequency synchronization input. Drive this pin with an external clock or pulse train. Ground it to use the
internal clock.
6 FB Feedback pin. Connect FB to the external resistor divider to set output voltage.
7 GND Signal and Power Ground pin. Place the bottom resistor of the feedback network as close as possible to
this pin for accurate regulation.
8 AVIN Supply voltage for the control circuitry.
9,10 PVIN Supply voltage for output power stage. Connect a bypass capacitor to this pin.
DAP GND Signal / Power Ground and thermal connection. Tie this directly to GND (pin 7). See regarding optimum
thermal layout.
4
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(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the recommended Operating Ratings is not implied. The recommended Operating Ratings
indicate conditions at which the device is functional and should not be operated beyond such conditions.
(2) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human body model, 1.5 kΩin series with 100 pF.
6 Specifications
6.1 Absolute Maximum Ratings
See notes(1)(2)
AVIN, PVIN -0.5V to 24V
SW Voltage -0.5V to 24V
Boost Voltage -0.5V to 28V
Boost to SW Voltage -0.5V to 6V
FB Voltage -0.5V to 3V
SYNC Voltage -0.5V to 6V
EN Voltage -0.5V to (VIN + 0.3V)
Storage Temperature Range -65°C to +150°C
Junction Temperature 150°C
ESD Susceptibility(3) 2kV
Soldering Information
Infrared Reflow (5sec) 260°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the recommended Operating Ratings is not implied. The recommended Operating Ratings
indicate conditions at which the device is functional and should not be operated beyond such conditions.
(2) All numbers apply for packages soldered directly onto a 3” × 3” PC board with 2 oz. copper on 4 layers in still air.
6.2 Recommended Operating Ratings
See note(1)
AVIN, PVIN 3V to 20V
SW Voltage -0.5V to 20V
Boost Voltage -0.5V to 24V
Boost to SW Voltage 3.0V to 5.5V
Junction Temperature Range -40°C to +125°C
Thermal Resistance (θJA) WSON (DSC)(2) 33°C/W
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(1) Thermal shutdown occurs if the junction temperature exceeds 165°C. The maximum power dissipation is a function of TJ(MAX),θJA and
TA. The maximum allowable power dissipation at any ambient temperature is PD= (TJ(MAX) – TA)/θJA .
6.3 Electrical Characteristics
Specifications with standard typeface are for TJ= 25°C, and those in boldface type apply over the full Operating
Temperature Range (TJ= -40°C to 125°C). VIN = 12V, and VBOOST - VSW = 4.3V unless otherwise specified. Datasheet
min/max specification limits are ensured by design, test, or statistical analysis.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SYSTEM PARAMETERS
VFB Feedback Voltage TJ= 0°C to 85°C 0.990 1.0 1.010 V
TJ= -40°C to 125°C 0.984 1.0 1.014
ΔVFB/ΔVIN Feedback Voltage Line Regulation VIN = 3V to 20V 0.003 % / V
IFB Feedback Input Bias Current 20 100 nA
OVP Over Voltage Protection, VFB at
which PWM Halts. 1.13 V
UVLO Undervoltage Lockout VIN Rising until VSW is Switching 2.60 2.75 2.90 V
UVLO Hysteresis VIN Falling from UVLO 0.30 0.47 0.6
SS Soft Start Time 0.5 1 1.5 ms
IQ
Quiescent Current, IQ= IQ_AVIN +
IQ_PVIN VFB = 1.1 (not switching) 2.4 mA
Quiescent Current, IQ= IQ_AVIN +
IQ_PVIN VEN = 0V (shutdown) 70 nA
IBOOST Boost Pin Current fSW= 2 MHz 8.2 10 mA
fSW= 1 MHz 4.4 6
OSCILLATOR
fSW Switching Frequency SYNC = GND 1.75 22.3 MHz
VFB_FOLD FB Pin Voltage where SYNC input is
overridden. 0.53 V
fFOLD_MIN Frequency Foldback Minimum VFB = 0V 220 250 kHz
LOGIC INPUTS (EN, SYNC)
fSYNC SYNC Frequency Range 1 2.35 MHz
VIL EN, SYNC Logic low threshold Logic Falling Edge 0.4 V
VIH EN, SYNC Logic high threshold Logic Rising Edge 1.8
tSYNC_HIGH SYNC, Time Required above VIH to
Ensure a Logical High. 100 ns
tSYNC_LOW SYNC, Time Required below VIL to
Ensure a Logical Low. 100 ns
ISYNC SYNC Pin Current VSYNC < 5V 20 nA
IEN Enable Pin Current VEN = 3V 6 15 µA
VIN = VEN = 20V 50 100
INTERNAL MOSFET
RDS(ON) Switch ON Resistance 150 320 mΩ
ICL Switch Current Limit LMR12020 2.5 4.0 A
LMR12015 2.0 3.7
DMAX Maximum Duty Cycle SYNC = GND 85 93%
tMIN Minimum on time 65 ns
ISW Switch Leakage Current 40 nA
BOOST LDO
VLDO Boost LDO Output Voltage 3.9 V
THERMAL
TSHDN Thermal Shutdown Temperature(1) Junction temperature rising 165 °C
Thermal Shutdown Hysteresis Junction temperature hysteresis 15 °C
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
40
46
52
58
64
70
76
82
88
94
100
EFFICIENCY (%)
IOUT(A)
Vin = 7V
Vin = 8V
Vin = 10V
Vin = 12V
Vin = 14V
Vin = 16V
Vin = 18V
Vin = 20V
0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1
45
50
55
60
65
70
75
80
85
90
95
EFFICIENCY (%)
IOUT(A)
Vin = 5V
Vin = 7V
Vin = 9V
Vin = 12V
Vin = 14V
Vin = 16V
Vin = 18V
Vin = 20
6
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,
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6.4 Typical Performance Characteristics
All curves taken at VIN = 12 V, VBOOST – VSW = 4.3 V and TA= 25°C, unless specified otherwise.
VIN = 5 V ƒSW = 2 MHz
Refer To Figure 37
Figure 1. Efficiency vs Load Current
VIN = 3.3 V ƒSW = 2 MHz
Refer To Figure 39
Figure 2. Efficiency vs Load Current
VOUT = 1.8 V ƒSW = 2 MHz
Refer To Figure 40
Figure 3. Efficiency vs Load Current Figure 4. Short Circuit
Figure 5. Short Circuit Release Figure 6. Soft Start
7
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Typical Performance Characteristics (continued)
All curves taken at VIN = 12 V, VBOOST – VSW = 4.3 V and TA= 25°C, unless specified otherwise.
Figure 7. Soft Start With EN Tied To VIN
VIN = 12 V VOUT = 5 V L = 2.2 µH
COUT = 44 µF IOUT = 1 A
Figure 8. Magnitude vs Frequency
VIN = 12 V VOUT = 3.3 V L = 1.5 µH
COUT = 44 µF IOUT = 1 A
Figure 9. Magnitude vs Frequency
VIN = 5 V VOUT = 1.8 V L = 1 µH
COUT = 44 µF IOUT = 1 A
Figure 10. Magnitude vs Frequency
VIN = 5 V VOUT = 1.2 V L = 0.56 µH
COUT = 68 µF IOUT = 1 A
Figure 11. Magnitude vs Frequency Figure 12. Sync Functionality
8
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Typical Performance Characteristics (continued)
All curves taken at VIN = 12 V, VBOOST – VSW = 4.3 V and TA= 25°C, unless specified otherwise.
Figure 13. Loss Of Synchronization VSYNC = GND
Figure 14. Oscillator Frequency vs Temperature
VSYNC = GND
Figure 15. Oscillator Frequency vs VFB Figure 16. VFB vs Temperature
Figure 17. VFB vs VIN
VIN = 12 V
Figure 18. Current Limit vs Temperature
9
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Typical Performance Characteristics (continued)
All curves taken at VIN = 12 V, VBOOST – VSW = 4.3 V and TA= 25°C, unless specified otherwise.
Figure 19. RDSON vs Temperature
IQ= IAVIN + IPVIN
Figure 20. IQ(Shutdown) vs Temperature
Figure 21. IEN vs VEN
0
0
VIN
-VD1
tON
t
t
Inductor Current
D = tON/TSW
VSW
tOFF
TSW
iL
SW Voltage
'iL
IOUT
ILPK
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7 Detailed Description
7.1 Overview
The LMR12015/20 is a constant-frequency, peak current-mode PWM buck regulator IC that delivers a 1.5-A or 2-
A load current. The regulator has a preset switching frequency of 2 MHz. This high frequency allows the
LMR12015/20 to operate with small surface mount capacitors and inductors, resulting in a DC/DC converter that
requires a minimum amount of board space. The LMR12015/20 is internally compensated, which reduces design
time, and requires few external components.
The following operating description of the LMR12015/20 will refer to the Block Diagram and to the waveforms in
Figure 22. The LMR12015/20 supplies a regulated output voltage by switching the internal NMOS switch at a
constant frequency and varying the duty cycle. A switching cycle begins at the falling edge of the reset pulse
generated by the internal oscillator. When this pulse goes low, the output control logic turns on the internal
NMOS switch. During this on-time, the SW pin voltage (VSW) swings up to approximately VIN, and the inductor
current (iL) increases with a linear slope. The current-sense amplifier measures iL, which generates an output
proportional to the switch current typically called the sense signal. The sense signal is summed with the
regulator’s corrective ramp and compared to the error amplifier’s output, which is proportional to the difference
between the feedback voltage (VFB) and VREF. When the output of the PWM comparator goes high, the switch
turns off until the next switching cycle begins. During the switch off-time (tOFF), inductor current discharges
through the catch diode D1, which forces the SW pin (VSW) to swing below ground by the forward voltage (VD1)
of the catch diode. The regulator loop adjusts the duty cycle (D) to maintain a constant output voltage.
Figure 22. LMR12015/20 Waveforms of SW Pin Voltage and Inductor Current
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7.2 Functional Block Diagram
LMR12015/20
VIN PVIN
EN
BOOST
SW
FB
GND/DAP
VOUT
C2 L1
C1
C3
R1
R2
D1
SYNC
AVIN
CLK
ON
OFF
5V
D2
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7.3 Feature Description
7.3.1 Boost Function
Capacitor C2in , commonly referred to as CBOOST, is used to store a voltage VBOOST. When the LMR12015/20
starts up, an internal LDO charges CBOOST, using an internal diode, to a voltage sufficient to turn the internal
NMOS switch on. The gate drive voltage supplied to the internal NMOS switch is VBOOST – VSW.
During a normal switching cycle, when the internal NMOS control switch is off (tOFF) (refer to Figure 22), VBOOST
equals VLDO minus the forward voltage of the internal diode (VD2). At the same time the inductor current (iL)
forward biases the catch diode D1 forcing the SW pin to swing below ground by the forward voltage drop of the
catch diode (VD1). Therefore, the voltage stored across CBOOST is
VBOOST – VSW = VLDO – VD2 + VD1 (1)
Thus,VBOOST = VSW + VLDO – VD2 + VD1 (2)
When the NMOS switch turns on (tON), the switch pin rises to
VSW = VIN – (RDSON × IL), (3)
reverse biasing D1, and forcing VBOOST to rise. The voltage at VBOOST is then
VBOOST = VIN – (RDSON × IL)+VLDO – VD2 + VD1 (4)
which is approximately
VIN + VLDO – 0.4V (5)
VBOOST has pulled itself up by its "bootstraps", or boosted to a higher voltage.
7.3.2 Low Input Voltage Considerations
When the input voltage is below 5V and the duty cycle is greater than 75 percent, the gate drive voltage
developed across CBOOST might not be sufficient for proper operation of the NMOS switch. In this case, CBOOST
should be charged via an external Schottky diode attached to a 5-V voltage rail, see Figure 23. This ensures that
the gate drive voltage is high enough for proper operation of the NMOS switch in the triode region. Maintain
VBOOST – VSW less than the 6-V absolute maximum rating.
Figure 23. External Diode Charges CBOOST
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Feature Description (continued)
7.3.3 High Output Voltage Considerations
When the output voltage is greater than 3.3 V, a minimum load current is needed to charge CBOOST, see
Figure 24. The minimum load current forward biases the catch diode D1 forcing the SW pin to swing below
ground. This allows CBOOST to charge, ensuring that the gate drive voltage is high enough for proper operation.
The minimum load current depends on many factors including the inductor value.
Figure 24. Minimum Load Current for L = 1.5 µH
7.3.4 Frequency Synchronization
The LMR12015/20 switching frequency can be synchronized to an external clock, between 1.00 and 2.35 MHz,
applied at the SYNC pin. At the first rising edge applied to the SYNC pin, the internal oscillator is overridden and
subsequent positive edges will initiate switching cycles. If the external SYNC signal is lost during operation, the
LMR12015/20 reverts to its internal 2-MHz oscillator within 1.5 µs. To disable frequency synchronization and
utilize the internal 2-MHz oscillator, connect the SYNC pin to GND.
The SYNC pin gives the designer the flexibility to optimize their design. A lower switching frequency can be
chosen for higher efficiency. A higher switching frequency can be chosen to keep EMI out of sensitive ranges
such as the AM radio band. Synchronization can also be used to eliminate beat frequencies generated by the
interaction of multiple switching power converters. Synchronizing multiple switching power converters will result
in cleaner power rails.
The selected switching frequency (fSYNC) and the minimum on-time (tMIN) limit the minimum duty cycle (DMIN) of
the device.
DMIN= tMIN × fSYNC (6)
Operation below DMIN is not reccomended. The LMR12015/20 skips pulses to keep the output voltage in
regulation, and the current limit is not ensured. The switching is in phase but no longer at the same switching
frequency as the SYNC signal.
7.3.5 Current Limit
The LMR12015/20 use cycle-by-cycle current limiting to protect the output switch. During each switching cycle, a
current limit comparator detects if the output switch current exceeds 2 A minimum (LMR12015) or 2.5 A minimum
(LMR12020), and turns off the switch until the next switching cycle begins.
7.3.6 Frequency Foldback
The LMR12015/20 employs frequency foldback to protect the device from current run-away during output short-
circuit. Once the FB pin voltage falls below regulation, the switch frequency will smoothly reduce with the falling
FB voltage until the switch frequency reaches 220 kHz (typ). If the device is synchronized to an external clock,
synchronization is disabled until the FB pin voltage exceeds 0.53V
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Feature Description (continued)
7.3.7 Soft Start
The LMR12015/20 has a fixed internal soft start of 1 ms (typical). During soft start, the error amplifier reference
voltage ramps from 0 V to its nominal value of 1 V in approximately 1 ms. This forces the regulator output to
ramp in a controlled fashion, which helps reduce inrush current. Upon soft start the device initially is in frequency
foldback, and the frequency rises as FB rises. The regulator will gradually rise to 2 MHz. The LMR12015/20
allows synchronization to an external clock at FB > 0.53 V.
7.3.8 Output Overvoltage Protection
The overvoltage comparator turns off the internal power NFET when the FB pin voltage exceeds the internal
reference voltage by 13% (VFB > 1.13 × VREF). With the power NFET turned off the output voltage decreases
toward the regulation level.
7.3.9 Undervoltage Lockout
Undervoltage lockout (UVLO) prevents the LMR12015/20 from operating until the input voltage exceeds 2.75 V
(typical).
The UVLO threshold has approximately 470 mV of hysteresis, so the device operates until VIN drops below 2.28
V (typical). Hysteresis prevents the part from turning off during power up if VIN has finite impedance.
7.3.10 Thermal Shutdown
Thermal shutdown limits total power dissipation by turning off the internal NMOS switch when the IC junction
temperature exceeds 165°C (typ). After thermal shutdown occurs, hysteresis prevents the internal NMOS switch
from turning on until the junction temperature drops to approximately 150°C.
7.4 Device Operation Modes
7.4.1 Enable Pin / Shutdown Mode
Connect the EN pin to a voltage source greater than 1.8V to enable operation of the LMR12015/20. Apply a
voltage less than 0.4V to put the part into shutdown mode. In shutdown mode the quiescent current drops to
typically 70 nA. Switch leakage adds another 40 nA from the input supply. For proper operation, the
LMR12015/20 EN pin should never be left floating, and the voltage should never exceed VIN + 0.3 V.
The simplest way to enable the operation of the LMR12015/20 is to connect the EN pin to AVIN which allows self
start-up of the LMR12015/20 when the input voltage is applied.
When the rise time of VIN is longer than the soft-start time of the LMR12015/20 this method may result in an
overshoot in output voltage. In such applications, the EN pin voltage can be controlled by a separate logic signal,
or tied to a resistor divider, which reaches 1.8V after VIN is fully established (see Figure 25). This will minimize
the potential for output voltage overshoot during a slow VIN ramp condition. Use the lowest value of VIN , seen in
your application when calculating the resistor network, to ensure that the 1.8-V minimum EN threshold is
reached.
R3 =VIN - 1
1.8 x R4
LMR12015/20
VIN PVIN
EN
BOOST
SW
FB
GND/DAP
VOUT
C2 L1
C1
C3
R1
R2
D1
SYNC
AVIN
CLK
R4
R3
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Device Operation Modes (continued)
Figure 25. Resistor Divider on EN
(7)
LMR12015/20
VIN PVIN
EN
BOOST
SW
FB
GND/DAP
VOUT
C2 L1
C1
C3
R1
R2
D1
SYNC
AVIN
CLK
ON
OFF
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMR10530 regulator is a monolithic, high frequency, PWM step-down DC/DC converter available in a 10-pin
WSON package. It contains all the active functions to provide local DC/DC conversion with fast transient
response and accurate regulation in the smallest possible PCB area. With a minimum of external components,
the LMR10530 is easy to use. Switching frequency is internally set to 1.5 MHz or 3 MHz, allowing the use of
extremely small surface mount inductors and capacitors. Even though the operating frequency is high,
efficiencies up to 93% are easy to achieve.
8.2 Typical Application
Figure 26. Typical Application Schematic
8.2.1 Detailed Design Procedure
8.2.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LMR12015 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
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r = 'iL
lOUT
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Typical Application (continued)
8.2.1.2 Inductor Selection
Inductor selection is critical to the performance of the LMR12015/20. The selection of the inductor affects
stability, transient response and efficiency. A key factor in inductor selection is determining the ripple current (ΔiL)
(see Figure 22).
The ripple current (ΔiL) is important in many ways.
First, by allowing more ripple current, lower inductance values can be used with a corresponding decrease in
physical dimensions and improved transient response. On the other hand, allowing less ripple current will
increase the maximum achievable load current and reduce the output voltage ripple (see Output Capacitor
section for more details on calculating output voltage ripple). Increasing the maximum load current is achieved by
ensuring that the peak inductor current (ILPK) never exceeds the minimum current limit of 2 A minimum
(LMR12015) or 2.5 A minimum (LMR12020) .
ILPK = IOUT +ΔiL/ 2 (8)
Secondly, the slope of the ripple current affects the current control loop. The LMR12015/20 has a fixed slope
corrective ramp. When the slope of the current ripple becomes significantly less than the converter’s corrective
ramp (see ), the inductor pole will move from high frequencies to lower frequencies. This negates one advantage
that peak current-mode control has over voltage-mode control, which is, a single low frequency pole in the power
stage of the converter. This can reduce the phase margin, crossover frequency and potentially cause instability in
the converter. Contrarily, when the slope of the ripple current becomes significantly greater than the converter’s
corrective ramp, resonant peaking can occur in the control loop. This can also cause instability (sub-harmonic
oscillation) in the converter. For the power supply designer this means that for lower switching frequencies the
current ripple must be increased to keep the inductor pole well above crossover. It also means that for higher
switching frequencies the current ripple must be decreased to avoid resonant peaking.
With all these factors, how is the desired ripple current selected? The ripple ratio (r) is defined as the ratio of
inductor ripple current (ΔiL) to output current (IOUT), evaluated at maximum load:
(9)
A good compromise between physical size, transient response and efficiency is achieved when we set the ripple
ratio between 0.2 and 0.4. The recommended ripple ratio vs. duty cycle shown below (see Figure 27) is based
upon this compromise and control loop optimizations. Note that this is just a guideline. See Application note AN-
1197 AN-1197 Selecting Inductors for Buck Converters for further considerations.
Figure 27. Recommended Ripple Ratio vs Duty Cycle
The duty cycle (D) can be approximated quickly using the ratio of output voltage (VOUT) to input voltage (VIN):
L = VOUT + VD1
IOUT x r x fSW x (1-DMIN)
D = VOUT + VD1
VIN + VD1 - VDS
D = VOUT
VIN
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Typical Application (continued)
(10)
Use the application's lowest input voltage to calculate the ripple ratio. The catch diode forward voltage drop (VD1)
and the voltage drop across the internal NFET (VDS) must be included to calculate a more accurate duty cycle.
Calculate D by using the following formula:
(11)
VDS can be approximated by:
VDS = IOUT × RDS(ON) (12)
The diode forward drop (VD1) can range from 0.3 V to 0.5 V depending on the quality of the diode. The lower VD1
is, the higher the operating efficiency of the converter.
Now that the ripple current or ripple ratio is determined, the required inductance is calculated by:
where
• DMIN is the duty cycle calculated with the maximum input voltage
• ƒSW is the switching frequency
• IOUT is the maximum output current of 2 A (13)
Using IOUT = 2 A minimizes the inductor's physical size.
8.2.1.2.1 Inductor Calculation Example
Operating conditions for the LMR12015/20 are:
VIN = 7 – 16 V (14)
fSW = 2 MHz (15)
VOUT = 3.3 V (16)
VD1 = 0.5 V (17)
IOUT = 2 A (18)
First the maximum duty cycle is calculated.
DMAX = (VOUT + VD1) / (VIN + VD1 – VDS) = (3.3 V + 0.5 V) / (7 V + 0.5 V – 0.3 V) = 0.528 (19)
Using Figure 27 gives us a recommended ripple ratio = 0.4.
Now the minimum duty cycle is calculated.
DMIN= (VOUT + VD1) / (VIN + VD1 – VDS) = (3.3 V + 0.5 V) / (16 V + 0.5 V – 0.3 V) = 0.235 (20)
The inductance can now be calculated.
L= (1 – DMIN) x (VOUT + VD1) / (IOUT × r × ƒSW) = (1 – 0.235) × (3.3 V + 0.5 V) / (2 A × 0.4 × 2 MHz) = 1.817 µH (21)
This is close to the standard inductance value of 1.8 µH. This leads to a 1% deviation from the recommended
ripple ratio, which is now 0.4038.
Finally, we check that the peak current does not reach the minimum current limit of 2.5 A.
ILPK = IOUT × (1 + r / 2) = 2 A × (1 + 0.4038 / 2 ) = 2.404 A (22)
The peak current is less than 2.5 A, so the DC load specification can be met with this ripple ratio. To design for
the LMR12015 simply replace IOUT = 1.5 A in the equations for ILPK and see that ILPK does not exceed the
LMR12015 current limit of 2 A (min).
IRMS-IN = IOUT x D x r2
12
1 - D +
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Typical Application (continued)
8.2.1.2.2 Inductor Material Selection
When selecting an inductor, make sure that it is capable of supporting the peak output current without saturating.
Inductor saturation will result in a sudden reduction in inductance and prevent the regulator from operating
correctly. To prevent the inductor from saturating over the entire –40°C to +125°C range, pick an inductor with a
saturation current higher than the upper limit of ICL listed in Electrical Characteristics.
Ferrite core inductors are recommended to reduce AC loss and fringing magnetic flux. The drawback of ferrite
core inductors is their quick saturation characteristic. The current limit circuit has a propagation delay and so is
oftentimes not fast enough to stop a saturated inductor from going above the current limit. This has the potential
to damage the internal switch. To prevent a ferrite core inductor from getting into saturation, the inductor
saturation current rating should be higher than the switch current limit ICL. The LMR12015/20 is quite robust in
handling short pulses of current that are a few amps above the current limit. Saturation protection is provided by
a second current limit which is 30% higher than the cycle-by-cycle current limit. When the saturation protection is
triggered thedevice turns off the output switch and attempt to soft start. (When a compromise has to be made,
pick an inductor with a saturation current just above the lower limit of the ICL.) Be sure to validate the short-circuit
protection over the intended temperature range.
An inductor's saturation current is usually lower when hot. Consult the inductor vendor if the saturation current
rating is only specified at room temperature.
Soft saturation inductors such as the iron powder types can also be used. Such inductors do not saturate
suddenly and therefore are safer when there is a severe overload or even shorted output. Their physical sizes
are usually smaller than the Ferrite core inductors. The downside is their fringing flux and higher power
dissipation due to relatively high AC loss, especially at high frequencies.
8.2.1.3 Input Capacitor
An input capacitor is necessary to ensure that VIN does not drop excessively during switching transients. The
primary specifications of the input capacitor are capacitance, voltage, RMS current rating, and equivalent series
inductance (ESL). The recommended input capacitance is 10 µF, although 4.7 µF works well for input voltages
below 6 V. The input voltage rating is specifically stated by the capacitor manufacturer. Make sure to check any
recommended deratings and also verify if there is any significant change in capacitance at the operating input
voltage and the operating temperature. The input capacitor maximum RMS input current rating (IRMS-IN) must be
greater than:
where
• r is the ripple ratio defined earlier
• IOUT is the output current, and
• D is the duty cycle (23)
It can be shown from the above equation that maximum RMS capacitor current occurs when D = 0.5. Always
calculate the RMS at the point where the duty cycle, D, is closest to 0.5. The ESL of an input capacitor is usually
determined by the effective cross sectional area of the current path. A large leaded capacitor will have high ESL
and a 0805 ceramic chip capacitor will have very low ESL. At the operating frequencies of the LMR12015/20,
certain capacitors may have an ESL so large that the resulting impedance (2πfL) is higher than that required to
provide stable operation. As a result, surface mount capacitors are strongly recommended. Sanyo POSCAP,
Tantalum or Niobium, Panasonic SP or Cornell Dubilier Low ESR are all good choices for input capacitors and
have acceptable ESL. Multilayer ceramic capacitors (MLCC) have very low ESL. For MLCCs TI recommends
using X7R or X5R dielectrics. Consult the capacitor manufacturer's datasheet to see how rated capacitance
varies over operating conditions.
R1 =VOUT - 1
VREF x R2
IRMS-OUT = IOUT x r
12
'VOUT = 'iL x (RESR + 1
8 x fSW x COUT)
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Typical Application (continued)
8.2.1.4 Output Capacitor
The output capacitor is selected based upon the desired output ripple and transient response. The
LMR12015/20's loop compensation is designed for ceramic capacitors. A minimum of 22 µF is required at 2 MHz
(33 uF at 1 MHz) while 47 – 100 µF is recommended for improved transient response and higher phase margin.
The output voltage ripple of the converter is:
(24)
When using MLCCs, the ESR is typically so low that the capacitive ripple may dominate. When this occurs, the
output ripple is approximately sinusoidal and 90° phase shifted from the switching action. Another benefit of
ceramic capacitors is their ability to bypass high frequency noise. A certain amount of switching edge noise will
couple through parasitic capacitances in the inductor to the output. A ceramic capacitor will bypass this noise
while a tantalum will not.
The transient response is determined by the speed of the control loop and the ability of the output capacitor to
provide the initial current of a load transient. Capacitance can be increased significantly with little detriment to the
regulator stability. However, increasing the capacitance provides dimininshing improvement over 100 uF in most
applications, because the bandwidth of the control loop decreases as output capacitance increases. If improved
transient performance is required, add a feed forward capacitor. This becomes especially important for higher
output voltages where the bandwidth of the LMR12015/20 is lower. See Feedforward Capacitor (Optional) and
Frequency Synchronization sections.
Check the RMS current rating of the capacitor. The RMS current rating of the capacitor chosen must also meet
the following condition:
where
• IOUT is the output current, and
• r is the ripple ratio. (25)
8.2.1.5 Catch Diode
The catch diode (D1) conducts during the switch off-time. A Schottky diode is recommended for its fast switching
times and low forward voltage drop. The catch diode should be chosen so that its current rating is greater than:
ID1 = IOUT × (1-D) (26)
The reverse breakdown rating of the diode must be at least the maximum input voltage plus appropriate margin.
To improve efficiency choose a Schottky diode with a low forward voltage drop.
8.2.1.6 Boost Diode (Optional)
For circuits with input voltages VIN < 5 V and duty cycles (D) > 0.75 V. a small-signal Schottky diode is
recommended. A good choice is the BAT54 small signal diode. The cathode of the diode is connected to the
BOOST pin and the anode to a 5-V voltage rail.
8.2.1.7 Boost Capacitor
A ceramic 0.1-µF capacitor with a voltage rating of at least 6.3 V is sufficient. The X7R and X5R MLCCs provide
the best performance.
8.2.1.8 Output Voltage
The output voltage is set using Equation 27 where R2 is connected between the FB pin and GND, and R1 is
connected between VOUT and the FB pin. A good starting value for R2 is 1 kΩ.
(27)
D = VOUT + VD1
VIN + VD1 - VDS
K = POUT
POUT + PLOSS
K = POUT
PIN
CFF <= VOUT x COUT
IOUT x R1
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Typical Application (continued)
8.2.1.9 Feedforward Capacitor (Optional)
A feed forward capacitor CFF can improve the transient response of the converter. Place CFF in parallel with R1.
The value of CFF should place a zero in the loop response at, or above, the pole of the output capacitor and
RLOAD. The CFF capacitor will increase the crossover frequency of the design, thus a larger minimum output
capacitance is required for designs using CFF. CFF must only be used with an output capacitance greater than or
equal to 44 uF. Example waveforms of load transient with and without the CFF capacitorss are as shown below.
(28)
Figure 28. LMR12015/20 Load Transient With CFF
Capacitor
VOUT = 3.3 V
Figure 29. LMR12015/20 Load Transient Without CFF
Capacitor
VOUT = 3.3 V
8.2.1.10 Calculating Efficiency and Junction Temperature
The complete LMR12015/20 DC/DC converter efficiency can be calculated in the following manner.
(29)
Or
(30)
Calculations for determining the most significant power losses are following. Other losses totaling less than 2%
are not discussed.
Power loss (PLOSS) is the sum of two basic types of losses in the converter, switching and conduction.
Conduction losses usually dominate at higher output loads, where as switching losses remain relatively fixed and
dominate at lower output loads. The first step in determining the losses is to calculate the duty cycle (D).
(31)
VDS is the voltage drop across the internal NFET when it is on, and is equal to:
D = VOUT + VD1 + VDCR
VIN + VD1 - VDS
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Typical Application (continued)
VDS = IOUT x RDSON (32)
VDis the forward voltage drop across the Schottky diode. It can be obtained from the Electrical Characteristics
section of the schottky diode datasheet. If the voltage drop across the inductor (VDCR) is accounted for, the
equation becomes:
(33)
VDCR usually gives only a minor duty cycle change, and has been omitted in the examples for simplicity.
8.2.1.10.1 Schottky Diode Conduction Losses
The conduction losses in the free-wheeling Schottky diode are calculated as follows:
PDIODE = VD1 × IOUT (1 – D) (34)
Often this is the single most significant power loss in the circuit. Take care to choose a Schottky diode that has a
low forward voltage drop.
8.2.1.10.2 Inductor Conduction Losses
Another significant external power loss is the conduction loss in the output inductor. The equation can be
simplified to:
PIND = IOUT2× RDCR (35)
8.2.1.10.3 MOSFET Conduction Losses
The LMR12015/20 conduction loss is mainly associated with the internal NFET:
PCOND = IOUT2× RDSON x D (36)
8.2.1.10.4 MOSFET Switching Losses
Switching losses are also associated with the internal NFET. They occur during the switch on and off transition
periods, where voltages and currents overlap resulting in power loss. The simplest means to determine this loss
is to empirically measuring the rise and fall times (10% to 90%) of the switch at the switch node:
PSWF = 1/2(VIN × IOUT × ƒSW × tFALL) (37)
PSWR = 1/2(VIN × IOUT × ƒSW × tRISE) (38)
PSW = PSWF + PSWR (39)
Table 1. Typical Rise and Fall Times vs Input Voltage
VIN tRISE tFALL
5 V 8 ns 8 ns
10 V 9 ns 9ns
15 V 10 ns 10 ns
8.2.1.10.5 IC Quiescent Losses
Another loss is the power required for operation of the internal circuitry:
PQ= IQ× VIN (40)
IQis the quiescent operating current, and is typically around 2.4 mA.
8.2.1.10.6 MOSFET Driver Losses
The other operating power that needs to be calculated is that required to drive the internal NFET:
PBOOST = IBOOST × VBOOST (41)
VBOOST is normally between 3 VDC and 5 VDC. The IBOOST rms current is dependant on switching frequency fSW.
IBOOST is approximately 8.2 mA at 2 MHz and 4.4 mA at 1 MHz.
K = =
POUT
POUT + PLOSS
6.6 W
6.6 W + 1.499 W = 81 %
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8.2.1.10.7 Total Power Losses
Total power losses are:
PLOSS = PCOND + PSWR + PSWF + PQ+ PBOOST + PDIODE + PIND (42)
Losses internal to the LMR12015/20 are:
PINTERNAL = PCOND + PSWR + PSWF + PQ+ PBOOST (43)
8.2.1.10.8 Efficiency Calculation Example
Operating conditions are:
VIN = 12 V (44)
fSW = 2 MHz (45)
VOUT = 3.3 V (46)
VD1 = 0.5 V (47)
IOUT = 2 A (48)
RDCR = 20 mΩ(49)
Internal Power Losses are:
PCOND = IOUT2× RDSON x D= 22× 0.15 Ω× 0.314 = 188 mW (50)
PSW = (VIN x IOUT × ƒSW × tFALL) = (12 V × 2 A x 2 MHz × 10n s) = 480 mW (51)
PQ= IQ× VIN = 2.4 mA × 12 V = 29 mW (52)
PBOOST = IBOOST × VBOOST = 8.2 mA x 4.5V = 37 mW (53)
PINTERNAL = PCOND + PSW + PQ+ PBOOST = 733 mW (54)
Total power losses are:
PDIODE= VD1 × IOUT (1 – D) = 0.5 V × 2 × (1 – 0.314) = 686 mW (55)
PIND= IOUT2× RDCR = 22× 20 mΩ= 80 mW (56)
PLOSS = PINTERNAL + PDIODE + P IND = 1.499 W (57)
The efficiency can now be estimated as:
(58)
With this information we can estimate the junction temperature of the LMR12015/20.
8.2.1.10.9 Calculating the LMR2015/20 Junction Temperature
Thermal Definitions:
TJ= IC junction temperature
TA= Ambient temperature
RθJC = Thermal resistance from IC junction to device case
RθJA = Thermal resistance from IC junction to ambient air
RTJA = TJ - TA
Power
RT = 'T
Power
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Figure 30. Cross-Sectional View Of Integrated Circuit Mounted On A Printed Circuit Board.
Heat in the LMR12015/20 due to internal power dissipation is removed through conduction and/or convection.
Conduction: Heat transfer occurs through cross sectional areas of material. Depending on the material, the
transfer of heat can be considered to have poor to good thermal conductivity properties (insulator vs conductor).
Heat Transfer goes as:
Silicon→Lead Frame→PCB (59)
Convection: Heat transfer is by means of airflow. This could be from a fan or natural convection. Natural
convection occurs when air currents rise from the hot device to cooler air.
Thermal impedance is defined as:
(60)
Thermal impedance from the silicon junction to the ambient air is defined as:
(61)
This impedance can vary depending on the thermal properties of the PCB. This includes PCB size, weight of
copper used to route traces , the ground plane, and the number of layers within the PCB. The type and number
of thermal vias can also make a large difference in the thermal impedance. Thermal vias are necessary in most
applications. They conduct heat from the surface of the PCB to the ground plane. Six to nine thermal vias should
be placed under the exposed pad to the ground plane. Placing more than nine thermal vias results in only a
small reduction to RθJA for the same copper area. These vias should have 8 mil holes to avoid wicking solder
away from the DAP. See AN-1187 Leadless Leadframe Package (LLP) and AN-1520 A Guide to Board Layout
for Best Thermal Resistance for Exposed Packages for more information on package thermal performance.
To predict the silicon junction temperature for a given application, three methods can be used. The first is useful
before prototyping and the other two can more accurately predict the junction temperature within the application.
Method 1:
The first method predicts the junction temperature by extrapolating a best guess RθJA from the table or graph.
The tables and graph are for natural convection. The internal dissipation can be calculated using the efficiency
calculations. This allows the user to make a rough prediction of the junction temperature in their application.
Methods two and three can later be used to determine the junction temperature more accurately.
The table below has values of RθJA for the WSON package.
Table 2. RθJAValues for the WSON at 1-Watt Dissipation:
NUMBER OF
BOARD LAYERS SIZE OF BOTTOM LAYER
COPPER CONNECTED TO DAP SIZE OF TOP LAYER COPPER
CONNECTED TO DAP NUMBER OF 8 MIL
THERMAL VIAS RθJA
RTJC = TJ - TC
Power
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Table 2. RθJAValues for the WSON at 1-Watt Dissipation: (continued)
2 0.25 in20.05 in28 78°C/W
2 0.5625 in20.05 in28 65.6°C/W
2 1 in20.05 in28 58.6°C/W
2 1.3225 in20.05 in28 50°C/W
4 (Eval Board) 3.25 in22.25 in215 30.7°C/W
Figure 31. Estimate of Thermal Resistance vs. Ground Copper Area
Eight Thermal Vias and Natural Convection
Method 2:
The second method requires the user to know the thermal impedance of the silicon junction to case. (RθJC) is
approximately 9.1°C/W for the WSON. The case temperature should be measured on the bottom of the PCB at a
thermal via directly under the DAP of the LMR12015/20. The solder resist must be removed from this area for
temperature testing. The reading will be more accurate if it is taken midway between pins 2 and 9, where the
NMOS switch is located. Knowing the internal dissipation from the efficiency calculation given previously, and the
case temperature (TC) we have:
(62)
Therefore:
TJ= (RθJC × PLOSS)+TC(63)
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8.2.2 Application Curves
VOUT = 5 V IOUT = 100 mA – 2 A at Slew Rate = 2 A /
µs
Refer To Figure 37
Figure 32. Load Transient
VOUT = 3.3 V IOUT = 100 mA – 2 A at Slew Rate = 2 A /
µs
Refer To Figure 39
Figure 33. Load Transient
VOUT = 1.8 V IOUT = 100 mA – 2 A at Slew Rate = 2 A /
µs
Refer To Figure 40
Figure 34. Load Transient
VIN = 10 to 15 V VOUT = 3.3 V No CFF
Refer To Figure 39
Figure 35. Line Transient
VIN = 10 to 15 V VOUT = 3.3 V No CFF
Refer To Figure 38
Figure 36. Line Transient
LMR12015/20
VIN PVIN
EN
BOOST
SW
FB
GND / DAP
VOUT
C2 L1
C1
C3
R1
R2
D1
SYNC
AVIN
CLK
2 MHz
ON
OFF
C5
C4
27
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8.2.3 LMR12015/20 Circuit Examples
Figure 37. VIN =7-20V,VOUT = 5 V, ƒSW = 2 MHz,
IOUT = Full Load With CFF
Table 3. Bill Of Materials For Figure 37
PART NAME PART
ID PART VALUE PART NUMBER MANUFACTURER
Buck Regulator U1 1.5 or 2A Buck Regulator LMR12015/20 Texas Instruments
CPVIN C1 10 µF C1210C106K8PACTU Kemet
CBOOST C2 0.1 µF C0603X104K4RACTU Kemet
COUT C3 22 µF GRM32ER71C226KE18L MuRata
COUT C4 22 µF GRM32ER71C226KE18L MuRata
CFF C5 0.18 µF 0603ZC184KAT2A AVX
Catch Diode D1 Schottky Diode Vf = 0.32V CMS06 Toshiba
Inductor L1 3.3 µH 7447789003 Wurth
Feedback Resistor R1 4.02 kΩCRCW06034K02FKEA Vishay
Feedback Resistor R2 1.02 kΩCRCW06031K02FKEA Vishay
LMR12015/20
VIN PVIN
EN
BOOST
SW
FB
GND / DAP
VOUT
C2 L1
C1
C3
R1
R2
D1
SYNC
AVIN
CLK
2 MHz
ON
OFF
C5
C4
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Figure 38. VIN =5-20V,VOUT = 3.3 V, ƒSW = 2 MHz,
IOUT = Full Load With CFF
Table 4. Bill Of Materials For Figure 38
PART NAME PART
ID PART VALUE PART NUMBER MANUFACTURER
Buck Regulator U1 1.5 or 2A Buck Regulator LMR12015/20 Texas Instruments
CPVIN C1 10 µF C1210C106K8PACTU Kemet
CBOOST C2 0.1 µF C0603X104K4RACTU Kemet
COUT C3 22 µF GRM32ER71C226KE18L MuRata
COUT C4 22 µF GRM32ER71C226KE18L MuRata
CFF C5 0.18 µF 0603ZC184KAT2A AVX
Catch Diode D1 Schottky Diode Vf = 0.32V CMS06 Toshiba
Inductor L1 3.3 µH 7447789003 Wurth
Feedback Resistor R1 2.32 kΩCRCW06032K32FKEA Vishay
Feedback Resistor R2 1.02 kΩCRCW06031K02FKEA Vishay
LMR12015/20
VIN PVIN
EN
BOOST
SW
FB
GND / DAP
VOUT
C2 L1
C1
C3
R1
R2
D1
SYNC
AVIN
C4
29
LMR12015
,
LMR12020
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SNVS817B –JUNE 2012–REVISED JUNE 2019
Product Folder Links: LMR12015 LMR12020
Submit Documentation FeedbackCopyright © 2012–2019, Texas Instruments Incorporated
Figure 39. VIN =5-20V,VOUT = 3.3 V, ƒSW = 2 MHz,
IOUT = Full Load Without CFF
Table 5. Bill Of Materials For Figure 39
PART NAME PART
ID PART VALUE PART NUMBER MANUFACTURER
Buck Regulator U1 1.5 or 2A Buck Regulator LMR12015/20 Texas Instruments
CPVIN C1 10 µF C1210C106K8PACTU Kemet
CBOOST C2 0.1 µF C0603X104K4RACTU Kemet
COUT C3 22 µF GRM32ER71C226KE18L MuRata
COUT C4 22 µF GRM32ER71C226KE18L MuRata
Catch Diode D1 Schottky Diode Vf = 0.32V CMS06 Toshiba
Inductor L1 3.3 µH 7447789003 Sumida
Feedback Resistor R1 2.32 kΩCRCW06032K32FKEA Vishay
Feedback Resistor R2 1.02 kΩCRCW06031K02FKEA Vishay
LMR12015/20
VIN PVIN
EN
BOOST
SW
FB
GND / DAP
VOUT
C2 L1
C1
C3
R1
R2
D1
SYNC
AVIN
C4
30
LMR12015
,
LMR12020
SNVS817B –JUNE 2012–REVISED JUNE 2019
www.ti.com
Product Folder Links: LMR12015 LMR12020
Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated
Figure 40. VIN = 3.3 - 16 V, VOUT = 1.8 V, ƒSW = 2 MHz, IOUT = Full Load
Table 6. Bill Of Materials For Figure 40
PART NAME PART
ID PART VALUE PART NUMBER MANUFACTURER
Buck Regulator U1 1.5 or 2A Buck Regulator LMR12015/20 Texas Instruments
CPVIN C1 10 µF GRM32DR71E106KA12L Murata
CBOOST C2 0.1 µF GRM188R71C104KA01D Murata
COUT C3 22 µF C3225X7R1C226K TDK
COUT C4 22 µF C3225X7R1C226K TDK
Catch Diode D1 Schottky Diode Vf = 0.32V CMS06 Toshiba
Inductor L1 1.0 µH CDRH5D18BHPNP Sumida
Feedback Resistor R1 12 kΩCRCW060312K0FKEA Vishay
Feedback Resistor R2 15 kΩCRCW060315K0FKEA Vishay
LMR12015/20
VIN PVIN
EN
BOOST
SW
FB
GND / DAP
VOUT
C2 L1
C1
C3
R1
R2
D1
SYNC
AVIN
CLK
1 MHz
ON
OFF
C5
C4
31
LMR12015
,
LMR12020
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SNVS817B –JUNE 2012–REVISED JUNE 2019
Product Folder Links: LMR12015 LMR12020
Submit Documentation FeedbackCopyright © 2012–2019, Texas Instruments Incorporated
Figure 41. VIN = 3.3 - 16 V, VOUT = 1.8 V, ƒSW = 1 MHz, IOUT = Full Load
Table 7. Bill Of Materials For Figure 41
PART NAME PART
ID PART VALUE PART NUMBER MANUFACTURER
Buck Regulator U1 1.5 or 2A Buck Regulator LMR12015/20 Texas Instruments
CPVIN C1 10 µF GRM32DR71E106KA12L Murata
CBOOST C2 0.1 µF GRM188R71C104KA01D Murata
COUT C3 22 uF C3225X7R1C226K TDK
COUT C4 22 uF C3225X7R1C226K TDK
CFF C5 3.9 nF GRM188R71H392KA01D Murata
Catch Diode D1 Schottky Diode Vf = 0.32V CMS06 Toshiba
Inductor L1 1.8 µH CDRH5D18BHPNP Sumida
Feedback Resistor R1 12 kΩCRCW060312K0FKEA Vishay
Feedback Resistor R2 15 kΩCRCW060315K0FKEA Vishay
LMR12015/20
VIN PVIN
EN
BOOST
SW
FB
GND / DAP
VOUT
C2 L1
C1
C3
R1
R2
D1
SYNC
AVIN
CLK
2 MHz
ON
OFF
C5
C4
32
LMR12015
,
LMR12020
SNVS817B –JUNE 2012–REVISED JUNE 2019
www.ti.com
Product Folder Links: LMR12015 LMR12020
Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated
Figure 42. VIN =3.3-9V,VOUT = 1.2 V, ƒSW = 2 MHz, IOUT = Full Load
Table 8. Bill Of Materials For Figure 42
PART NAME PART
ID PART VALUE PART NUMBER MANUFACTURER
Buck Regulator U1 1.5 or 2A Buck Regulator LMR12015/20 Texas Instruments
CPVIN C1 10 µF GRM32DR71E106KA12L Murata
CBOOST C2 0.1 µF GRM188R71C104KA01D Murata
COUT C3 47 µF GRM32ER61A476KE20L Murata
COUT C4 22 µF C3225X7R1C226K TDK
CFF C5 NOT MOUNTED
Catch Diode D1 Schottky Diode Vf = 0.32V CMS06 Toshiba
Inductor L1 0.56 µH CDRH2D18/HPNP Sumida
Feedback Resistor R1 1.02 kΩCRCW06031K02FKEA Vishay
Feedback Resistor R2 5.10 kΩCRCW06035K10FKEA Vishay
+
-
33
LMR12015
,
LMR12020
www.ti.com
SNVS817B –JUNE 2012–REVISED JUNE 2019
Product Folder Links: LMR12015 LMR12020
Submit Documentation FeedbackCopyright © 2012–2019, Texas Instruments Incorporated
9 Layout
9.1 Layout Considerations
9.1.1 Compact Layout
The performance of any switching converter depends as much upon the layout of the PCB as the component
selection. The following guidelines will help the user design a circuit with maximum rejection of outside EMI and
minimum generation of unwanted EMI.
Parasitic inductance can be reduced by keeping the power path components close together and keeping the
area of the loops small, on which high currents travel. Short, thick traces or copper pours (shapes) are best. In
particular, the switch node (where L1, D1, and the SW pin connect) should be just large enough to connect all
three components without excessive heating from the current it carries. The LMR12015/20 operates in two
distinct cycles (see Figure 22) whose high current paths are shown below in Figure 43:
Figure 43. Buck Converter Current Loops
The dark grey, inner loop represents the high current path during the MOSFET on-time. The light grey, outer loop
represents the high current path during the off-time.
9.1.2 Ground Plane and Shape Routing
The diagram of Figure 43 is also useful for analyzing the flow of continuous current vs. the flow of pulsating
currents. The circuit paths with current flow during both the on-time and off-time are considered to be continuous
current, while those that carry current during the on-time or off-time only are pulsating currents. Preference in
routing should be given to the pulsating current paths, as these are the portions of the circuit most likely to emit
EMI. The ground plane of a PCB is a conductor and return path, and it is susceptible to noise injection just like
any other circuit path. The path between the input source and the input capacitor and the path between the catch
diode and the load are examples of continuous current paths. In contrast, the path between the catch diode and
the input capacitor carries a large pulsating current. This path should be routed with a short, thick shape,
preferably on the component side of the PCB. Multiple vias in parallel should be used right at the pad of the input
capacitor to connect the component side shapes to the ground plane. A second pulsating current loop that is
often ignored is the gate drive loop formed by the SW and BOOST pins and boost capacitor CBOOST. To minimize
this loop and the EMI it generates, keep CBOOST close to the SW and BOOST pins.
9.1.3 FB Loop
The FB pin is a high-impedance input, and the loop created by R2, the FB pin and ground should be made as
small as possible to maximize noise rejection. R2 should therefore be placed as close as possible to the FB and
GND pins of the IC.
9.1.4 PCB Summary
1. Minimize the parasitic inductance by keeping the power path components close together and keeping the
area of the high-current loops small.
34
LMR12015
,
LMR12020
SNVS817B –JUNE 2012–REVISED JUNE 2019
www.ti.com
Product Folder Links: LMR12015 LMR12020
Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated
Layout Considerations (continued)
2. The most important consideration when completing the layout is the close coupling of the GND connections
of the CIN capacitor and the catch diode D1. These ground connections must be immediately adjacent, with
multiple vias in parallel at the pad of the input capacitor connected to GND. Place CIN and D1 as close to the
IC as possible.
3. Next in importance is the location of the GND connection of the COUT capacitor, which should be near the
GND connections of CIN and D1.
4. There should be a continuous ground plane on the copper layer directly beneath the converter. This reduces
parasitic inductance and EMI.
5. The FB pin is a high impedance node — take care to make the FB trace short to avoid noise pickup and
inaccurate regulation. Place the feedback resistors as close as possible to the IC, with the GND of R2 placed
as close as possible to the GND of the IC. The VOUT trace to R1 should be routed away from the inductor
and any other traces that are switching.
6. High AC currents flow through the VIN, SW and VOUT traces, so they must be as short and wide as possible.
However, making the traces wide increases radiated noise, so the layout designer must make this trade-off.
Radiated noise can be decreased by choosing a shielded inductor.
Place the remaining components as close as possible to the IC. See AN-2279 LMR12020 Evaluation Module for
further considerations and the LMR12015/20 eval board as an example of a four-layer layout.
35
LMR12015
,
LMR12020
www.ti.com
SNVS817B –JUNE 2012–REVISED JUNE 2019
Product Folder Links: LMR12015 LMR12020
Submit Documentation FeedbackCopyright © 2012–2019, Texas Instruments Incorporated
10 Device and Documentation Support
10.1 Device Support
10.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
10.1.2 Development Support
10.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LMR12015 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
10.2 Related Links
Table 9 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to order now.
Table 9. Related Links
PARTS PRODUCT FOLDER ORDER NOW TECHNICAL
DOCUMENTS TOOLS &
SOFTWARE SUPPORT &
COMMUNITY
LMR12015 Click here Click here Click here Click here Click here
LMR12020 Click here Click here Click here Click here Click here
10.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
10.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
36
LMR12015
,
LMR12020
SNVS817B –JUNE 2012–REVISED JUNE 2019
www.ti.com
Product Folder Links: LMR12015 LMR12020
Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated
10.5 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
10.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
10.7 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMR12015XSD/NOPB ACTIVE WSON DSC 10 1000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 L285B
LMR12015XSDX/NOPB ACTIVE WSON DSC 10 4500 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 L285B
LMR12020XSD/NOPB ACTIVE WSON DSC 10 1000 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 L284B
LMR12020XSDX/NOPB ACTIVE WSON DSC 10 4500 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 L284B
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMR12015XSD/NOPB WSON DSC 10 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1
LMR12015XSDX/NOPB WSON DSC 10 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1
LMR12020XSD/NOPB WSON DSC 10 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1
LMR12020XSDX/NOPB WSON DSC 10 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jun-2019
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMR12015XSD/NOPB WSON DSC 10 1000 210.0 185.0 35.0
LMR12015XSDX/NOPB WSON DSC 10 4500 367.0 367.0 35.0
LMR12020XSD/NOPB WSON DSC 10 1000 210.0 185.0 35.0
LMR12020XSDX/NOPB WSON DSC 10 4500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jun-2019
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
1.2±0.1
10X 0.3
0.2
10X 0.5
0.4
0.8 MAX
0.05
0.00
2±0.1
2X
2
8X 0.5
A
3.1
2.9
B3.1
2.9
(0.2) TYP
WSON - 0.8 mm max heightDSC0010B
PLASTIC SMALL OUTLINE - NO LEAD
4214926/A 07/2014
PIN 1 INDEX AREA
0.08 SEATING PLANE
(OPTIONAL)
PIN 1 ID
1
6
10
5
0.1 C A B
0.05 C
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
0.08
0.1 C A B
0.05 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
(1.2)
(2)
10X (0.65)
10X (0.25)
(0.35) TYP
(0.75) TYP
(2.75)
() TYP
VIA
0.2
8X (0.5)
WSON - 0.8 mm max heightDSC0010B
PLASTIC SMALL OUTLINE - NO LEAD
4214926/A 07/2014
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:20X
1
56
10
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
SOLDER MASK
OPENING
METAL
UNDER
SOLDER MASK
SOLDER MASK
DEFINED
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
www.ti.com
EXAMPLE STENCIL DESIGN
(1.13)
(0.89)
10X (0.65)
10X (0.25)
8X (0.5)
(2.75)
(0.55)
WSON - 0.8 mm max heightDSC0010B
PLASTIC SMALL OUTLINE - NO LEAD
4214926/A 07/2014
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SYMM
SYMM
METAL
TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
84% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
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