LTC2600/LTC2610/LTC2620 Octal 16-/14-/12-Bit Rail-to-Rail DACs in 16-Lead SSOP DESCRIPTION FEATURES n n n n n n n n n n Smallest Pin-Compatible Octal DACs: LTC2600: 16 Bits LTC2610: 14 Bits LTC2620: 12 Bits Guaranteed 16-Bit Monotonic Over Temperature Wide 2.5V to 5.5V Supply Range Low Power Operation: 250A per DAC at 3V Individual Channel Power-Down to 1A, Max Ultralow Crosstalk Between DACs (<10V) High Rail-to-Rail Output Drive (15mA, Min) Double-Buffered Digital Inputs Pin-Compatible 10-/8-Bit Versions (LTC1660/LTC1665) Tiny 16-Lead Narrow SSOP and 20-Lead 4mm x 5mm QFN Packages n n n These parts establish new board-density benchmarks for 16- and 14-bit DACs and advance performance standards for output drive, crosstalk and load regulation in single-supply, voltage-output multiples. The parts use a simple SPI/MICROWIRE compatible 3-wire serial interface which can be operated at clock rates up to 50MHz. Daisychain capability and a hardware CLR function are included. The LTC2600/LTC2610/LTC2620 incorporate a power-on reset circuit. During power-up, the voltage outputs rise less than 10mV above zero-scale; and after power-up, they stay at zero-scale until a valid write and update take place. APPLICATIONS n The LTC(R)2600/LTC2610/LTC2620 are octal 16-, 14- and 12-bit, 2.5V-to-5.5V rail-to-rail voltage-output DACs in 16-lead narrow SSOP and 20-lead 4mm x 5mm QFN packages. They have built-in high performance output buffers and are guaranteed monotonic. Mobile Communications Process Control and Industrial Automation Instrumentation Automatic Test Equipment L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. BLOCK DIAGRAM DAC A REGISTER 2 REGISTER (1) VOUTA 16 VCC REGISTER 1 REGISTER GND (20) DAC H (17) 15 VOUTH (16) REGISTER DAC B REGISTER 3 REGISTER (2) VOUTB REGISTER Differential Nonlinearity (LTC2600) DAC G 1.0 14 VOUTG (15) VCC = 5V VREF = 4.096V 0.8 REF 6 DAC D REGISTER DAC E 13 VOUTF 12 VOUTE (14) (13) DNL (LSB) REGISTER REGISTER 0.4 DAC F REGISTER 5 REGISTER (4) V OUTD DAC C REGISTER 4 REGISTER (3) VOUTC REGISTER 0.6 0.2 0 -0.2 -0.4 -0.6 -0.8 (5) (7) CS/LD 7 (8) 8 SCK POWER-ON RESET CONTROL LOGIC 11 CLR (11) 10 SDO (10) SDI (9) DECODE 32-BIT SHIFT REGISTER 9 -1.0 0 16384 32768 CODE 49152 65535 2600 G21 2600 BD NOTE: NUMBERS IN PARENTHESIS REFER TO THE UFD PACKAGE 2600fe 1 LTC2600/LTC2610/LTC2620 ABSOLUTE MAXIMUM RATINGS (Note 1) Any Pin to GND ........................................... -0.3V to 6V Any Pin to VCC ............................................ -6V to 0.3V Operating Temperature Range LTC2600C/LTC2610C/LTC2620C ............. 0C to 70C LTC2600I/LTC2610I/LTC2620I............. -40C to 85C Storage Temperature Range.................. -65C to 150C Maximum Junction Temperature........................... 125C Lead Temperature (Soldering, 10 sec) ................. 300C PIN CONFIGURATION VCC DNC TOP VIEW DNC GND TOP VIEW 20 19 18 17 GND 1 16 VCC VOUTA 2 15 VOUTH VOUTB 3 14 VOUTG VOUTC 4 13 VOUTF VOUTD 5 12 VOUTE REF 5 12 DNC REF 6 11 CLR DNC 6 11 CLR CS/LD 7 10 SDO SCK 8 9 VOUTA 1 16 VOUTH VOUTB 2 15 VOUTG VOUTC 3 8 9 10 SDI SDO 7 SCK GN PACKAGE 16-LEAD PLASTIC SSOP TJMAX = 125C, JA = 150C/W 13 VOUTE CS/LD SDI 14 VOUTF 21 VOUTD 4 UFD PACKAGE 20-LEAD (4mm s 5mm) PLASTIC QFN TJMAX = 150C, JA = 43C/W EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2600CUFD#PBF LTC2600CUFD#TRPBF 2600 20-Lead (4mm x 5mm) Plastic DFN 0C to 70C LTC2600IUFD#PBF LTC2600IUFD#TRPBF 2600 20-Lead (4mm x 5mm) Plastic DFN -40C to 85C LTC2600CGN#PBF LTC2600CGN#TRPBF 2600 16-Lead Plastic SSOP 0C to 70C LTC2600IGN#PBF LTC2600IGN#TRPBF 2600I 16-Lead Plastic SSOP -40C to 85C LTC2610CUFD#PBF LTC2610CUFD#TRPBF 2610 20-Lead (4mm x 5mm) Plastic DFN 0C to 70C LTC2610IUFD#PBF LTC2610IUFD#TRPBF 2610 20-Lead (4mm x 5mm) Plastic DFN -40C to 85C LTC2610CGN#PBF LTC2610CGN#TRPBF 2610 16-Lead Plastic SSOP 0C to 70C LTC2610IGN#PBF LTC2610IGN#TRPBF 2610I 16-Lead Plastic SSOP -40C to 85C LTC2620CUFD#PBF LTC2620CUFD#TRPBF 2620 20-Lead (4mm x 5mm) Plastic DFN 0C to 70C LTC2620IUFD#PBF LTC2620IUFD#TRPBF 2620 20-Lead (4mm x 5mm) Plastic DFN -40C to 85C LTC2620CGN#PBF LTC2620CGN#TRPBF 2620 16-Lead Plastic SSOP 0C to 70C LTC2620IGN#PBF LTC2620IGN#TRPBF 2620I 16-Lead Plastic SSOP -40C to 85C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 2600fe 2 LTC2600/LTC2610/LTC2620 ELECTRICAL CHARACTERISTICS The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 2.5V to 5.5V, VREF VCC, VOUT unloaded, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN LTC2620 TYP MAX MIN LTC2610 TYP MAX MIN LTC2600 TYP MAX UNITS DC Performance Resolution l 12 14 16 12 14 16 Monotonicity VCC = 5V, VREF = 4.096V (Note 2) l DNL Differential Nonlinearity VCC = 5V, VREF = 4.096V (Note 2) l INL Integral Nonlinearity VCC = 5V, VREF = 4.096V (Note 2) l 0.75 Load Regulation VREF = VCC = 5V, Mid-Scale IOUT = 0mA to 15mA Sourcing IOUT = 0mA to 15mA Sinking l l VREF = VCC = 2.5V, Mid-Scale IOUT = 0mA to 7.5mA Sourcing IOUT = 0mA to 7.5mA Sinking l l Bits Bits 1 LSB 3 16 12 64 LSB 0.025 0.125 0.025 0.125 0.1 0.1 0.5 0.5 0.3 0.3 2 2 LSB/mA LSB/mA 0.05 0.05 0.25 0.25 0.2 0.2 1 1 0.8 0.8 4 4 LSB/mA LSB/mA 0.5 1 4 ZSE Zero-Scale Error VCC = 5V, VREF = 4.096V Code = 0 1 9 1 9 1 9 mV VOS Offset Error VCC = 5V, VREF = 4.096V (Note 7) 1 9 1 9 1 9 mV VOS Temperature Coefficient GE Gain Error 3 VCC = 5V, VREF = 4.096V Gain Temperature Coefficient 0.2 6.5 3 0.7 0.2 V/C 3 0.7 0.2 6.5 0.7 %FSR ppm/C 6.5 The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 2.5V to 5.5V, VREF VCC, VOUT unloaded, unless otherwise noted. SYMBOL PARAMETER CONDITIONS LTC2600/LTC2610/LTC2620 MIN TYP MAX PSR Power Supply Rejection VCC = 10% -80 ROUT DC Output Impedance l VREF = VCC = 5V, Mid-Scale; -15mA IOUT 15mA VREF = VCC = 2.5V, Mid-Scale; -7.5mA IOUT 7.5mA l 0.025 0.030 DC Crosstalk (Note 4) Due to Full-Scale Output Change (Note 5) Due to Load Current Change Due to Powering Down (per Channel) 10 3.5 7.3 Short-Circuit Output Current VCC = 5.5V, VREF = 5.6V Code: Zero-Scale; Forcing Output to VCC Code: Full-Scale; Forcing Output to GND l l 15 15 34 34 60 60 mA mA VCC = 2.5V, VREF = 5.6V Code: Zero-Scale; Forcing Output to VCC Code: Full-Scale; Forcing Output to GND l l 7.5 7.5 18 24 50 50 mA mA Input Voltage Range l 0 VCC V Resistance l 11 20 k ISC UNITS dB 0.15 0.15 V V/mA V Reference Input Normal Mode Capacitance IREF Reference Current, Power-Down Mode 16 90 All DACs Powered Down l 0.001 pF 1 A 2600fe 3 LTC2600/LTC2610/LTC2620 ELECTRICAL CHARACTERISTICS The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 2.5V to 5.5V, VREF VCC, VOUT unloaded, unless otherwise noted. SYMBOL PARAMETER LTC2600/LTC2610/LTC2620 MIN TYP MAX CONDITIONS UNITS Power Supply l VCC Positive Supply Voltage 2.5 ICC Supply Current VCC = 5V (Note 3) VCC = 3V (Note 3) All DACs Powered Down (Note 3) VCC = 5V All DACs Powered Down (Note 3) VCC = 3V l l l l VIH Digital Input High Voltage VCC = 2.5V to 5.5V VCC = 2.5V to 3.6V l l VIL Digital Input Low Voltage VCC = 4.5V to 5.5V VCC = 2.5V to 5.5V l l VOH Digital Output High Voltage Load Current = -100A l VCC - 0.4 VOL Digital Output Low Voltage Load Current = +100A l 0.4 V 1 A 8 pF 2.6 2.0 0.35 0.10 5.5 V 4 3.2 1 1 mA mA A A Digital I/O ILK Digital Input Leakage VIN = GND to VCC l CIN Digital Input Capacitance (Note 6) l 2.4 2.0 V V 0.8 0.6 V V V The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 2.5V to 5.5V, VREF VCC, VOUT unloaded, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN LTC2620 TYP MAX MIN LTC2610 TYP MAX MIN LTC2600 TYP MAX UNITS AC Performance tS Settling Time (Note 8) 7 9 7 9 10 s s 2.7 2.7 4.8 2.7 4.8 5.2 s s s Voltage Output Slew Rate 0.80 0.80 0.80 V/s Capacitive Load Driving 1000 1000 1000 pF At Mid-Scale Transition 12 12 12 180 180 180 kHz Output Voltage Noise Density At f = 1kHz At f = 10kHz 120 100 120 100 120 100 nV/Hz nV/Hz Output Voltage Noise 0.1Hz to 10Hz 15 15 15 VP-P Settling Time for 1LSB Step (Note 9) Glitch Impulse 0.024% (1LSB at 12 Bits) 0.006% (1LSB at 14 Bits) 0.0015% (1LSB at 16 Bits) 7 0.024% (1LSB at 12 Bits) 0.006% (1LSB at 14 Bits) 0.0015% (1LSB at 16 Bits) Multiplying Bandwidth en nV * s 2600fe 4 LTC2600/LTC2610/LTC2620 TIMING CHARACTERISTICS The l denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (See Figure 1) (Note 6) SYMBOL PARAMETER LTC2600/LTC2610/LTC2620 MIN TYP MAX CONDITIONS UNITS VCC = 2.5V to 5.5V t1 SDI Valid to SCK Setup l 4 ns t2 SDI Valid to SCK Hold l 4 ns t3 SCK High Time l 9 ns t4 SCK Low Time l 9 ns t5 CS/LD Pulse Width l 10 ns t6 LSB SCK High to CS/LD High l 7 ns t7 CS/LD Low to SCK High l 7 ns t8 SDO Propagation Delay from SCK Falling Edge CLOAD = 10pF VCC = 4.5V to 5.5V VCC = 2.5V to 5.5V l l 20 45 ns ns t9 CLR Pulse Width l 20 ns t10 CS/LD High to SCK Positive Edge l 7 ns SCK Frequency 50% Duty Cycle Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Linearity and monotonicity are defined from code kL to code 2N - 1, where N is the resolution and kL is given by kL = 0.016(2N/VREF), rounded to the nearest whole code. For VREF = 4.096V and N = 16, kL = 256 and linearity is defined from code 256 to code 65,535. Note 3: Digital inputs at 0V or VCC. Note 4: DC crosstalk is measured with VCC = 5V and VREF = 4.096V, with the measured DAC at mid-scale, unless otherwise noted. l 50 MHz Note 5: RL = 2k to GND or VCC. Note 6: Guaranteed by design and not production tested. Note 7: Inferred from measurement at code 256 (LTC2600), code 64 (LTC2610) or code 16 (LTC2620), and at full-scale. Note 8: VCC = 5V, VREF = 4.096V. DAC is stepped 1/4-scale to 3/4-scale and 3/4-scale to 1/4-scale. Load is 2k in parallel with 200pF to GND. Note 9: VCC = 5V, VREF = 4.096V. DAC is stepped 1LSB between halfscale and half-scale - 1. Load is 2k in parallel with 200pF to GND. 2600fe 5 LTC2600/LTC2610/LTC2620 TYPICAL PERFORMANCE CHARACTERISTICS LTC2600 Integral Nonlinearity (INL) 32 Differential Nonlinearity (DNL) 1.0 VCC = 5V VREF = 4.096V 24 INL vs Temperature 32 VCC = 5V VREF = 4.096V 0.8 VCC = 5V VREF = 4.096V 24 0.6 16 0 -8 0.2 INL (LSB) DNL (LSB) 8 INL (LSB) 16 0.4 0 -0.2 INL (POS) 8 0 -8 INL (NEG) -0.4 -16 -0.6 -24 -32 -16 -24 -0.8 16384 0 32768 CODE 49152 -1.0 65535 0 16384 32768 CODE 49152 DNL vs Temperature VCC = 5V VREF = 4.096V 90 1.5 VCC = 5.5V 24 VCC = 5.5V 1.0 16 0.2 0 -0.2 0 -8 DNL (NEG) -0.4 0.5 INL (POS) 8 DNL (LSB) DNL (POS) INL (LSB) DNL (LSB) 70 DNL vs VREF 32 0.4 INL (NEG) DNL (POS) 0 DNL (NEG) -0.5 -16 -0.6 -1.0 -24 -0.8 -1.0 -50 -10 10 30 50 TEMPERATURE (C) 2600 G22 INL vs VREF 1.0 0.6 -30 2600 G21 2600 G20 0.8 -32 -50 65535 -30 -10 10 30 50 TEMPERATURE (C) 70 90 -32 0 1 2 3 VREF (V) 4 2600 G23 5 -1.5 0 1 2 3 VREF (V) 2600 G24 Settling to 1LSB 4 5 2600 G25 Settling of Full-Scale Step VOUT 100V/DIV VOUT 100V/DIV 9.7s 12.3s CS/LD 2V/DIV CS/LD 2V/DIV 2s/DIV VCC = 5V, VREF = 4.096V 1/4-SCALE TO 3/4-SCALE STEP RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS 2600 G26 5s/DIV 2600 G27 SETTLING TO 1LSB VCC = 5V, VREF = 4.096V CODE 512 TO 65535 STEP RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS 2600fe 6 LTC2600/LTC2610/LTC2620 TYPICAL PERFORMANCE CHARACTERISTICS LTC2610 Differential Nonlinearity (DNL) Integral Nonlinearity (INL) 8 1.0 VCC = 5V VREF = 4.096V 6 VCC = 5V VREF = 4.096V 0.8 0.6 4 0.4 2 DNL (LSB) INL (LSB) Settling to 1LSB 0 -2 VOUT 100V/DIV 0.2 0 CS/LD 2V/DIV -0.2 -0.4 -4 8.9s -0.6 -6 -0.8 -8 -1.0 0 4096 8192 CODE 12288 16383 2600 G30 2s/DIV 0 4096 8192 CODE 12288 2600 G28 VCC = 5V, VREF = 4.096V 1/4-SCALE TO 3/4-SCALE STEP RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS 16383 2600 G29 LTC2620 Integral Nonlinearity (INL) 2.0 Differential Nonlinearity (DNL) 1.0 VCC = 5V VREF = 4.096V 1.5 0.6 6.8s 0.4 0.5 DNL (LSB) INL (LSB) VCC = 5V VREF = 4.096V 0.8 1.0 0 -0.5 VOUT 1mV/DIV 0.2 0 CS/LD 2V/DIV -0.2 -0.4 -1.0 -0.6 -1.5 -2.0 Settling to 1LSB 2s/DIV -0.8 0 1024 2048 CODE 3072 -1.0 4095 0 1024 2048 CODE 3072 2600 G31 2600 G33 VCC = 5V, VREF = 4.096V 1/4-SCALE TO 3/4-SCALE STEP RL = 2k, CL = 200pF AVERAGE OF 2048 EVENTS 4095 2600 G32 LTC2600/LTC2610/LTC2620 Load Regulation Current Limiting 0.06 $VOUT (V) 0.04 CODE = MIDSCALE -0.06 0.4 VREF = VCC = 3V 0.2 0 -0.2 VREF = VCC = 5V -0.4 VREF = VCC = 5V 1 0 -1 VREF = VCC = 3V -0.6 -0.08 -0.10 10 -40 -30 -20 -10 0 IOUT (mA) 2 0.6 VREF = VCC = 3V 0 -0.04 CODE = MIDSCALE 0.8 VREF = VCC = 5V 0.02 -0.02 Offset Error vs Temperature 3 OFFSET ERROR (mV) 0.08 1.0 $VOUT (mV) 0.10 -2 -0.8 20 30 40 2600 G01 -1.0 -35 -25 -15 -5 5 IOUT (mA) 15 25 35 2600 G02 -3 -50 -30 -10 10 30 50 TEMPERATURE (C) 70 90 2600 G03 2600fe 7 LTC2600/LTC2610/LTC2620 TYPICAL PERFORMANCE CHARACTERISTICS LTC2600/LTC2610/LTC2620 Gain Error vs Temperature Zero-Scale Error vs Temperature 3 3 0.3 2.0 1.5 1.0 2 0.2 OFFSET ERROR (mV) GAIN ERROR (%FSR) 2.5 ZERO-SCALE ERROR (mV) Offset Error vs VCC 0.4 0.1 0 -0.1 0 -1 -0.2 0.5 -2 -0.3 0 -50 -30 -10 10 30 50 TEMPERATURE (C) 70 90 -0.4 -50 -30 -10 10 30 50 TEMPERATURE (C) 70 2600 G04 0.4 -3 2.5 90 3.5 3 4 VCC (V) 4.5 5 2600 G05 Gain Error vs VCC 5.5 2600 G06 ICC Shutdown vs VCC Large-Signal Response 450 0.3 400 0.2 350 0.1 300 ICC (nA) GAIN ERROR (%FSR) 1 0 -0.1 VOUT 0.5V/DIV 250 200 VREF = VCC = 5V 1/4-SCALE TO 3/4-SCALE 150 -0.2 100 -0.3 2.5s/DIV 50 -0.4 2.5 3 3.5 4 VCC (V) 4.5 5 5.5 0 2.5 3 3.5 4 VCC (V) 4.5 2600 G07 5 2600 G09 5.5 2600 G08 Mid-Scale Glitch Impulse Headroom at Rails vs Output Current Power-On Reset Glitch 5.0 5V SOURCING 4.5 4.0 VOUT 10mV/DIV 3.5 12nV-s TYP VOUT (V) VCC 1V/DIV 4mV 4mVPEAK PEAK CS/LD 5V/DIV VOUT 10mV/DIV 2.5s/DIV 2600 G10 3V SOURCING 3.0 2.5 2.0 1.5 5V SINKING 1.0 250s/DIV 3V SINKING 2600 G11 0.5 0 0 1 2 3 4 5 6 IOUT (mA) 7 8 9 10 2600 G12 2600fe 8 LTC2600/LTC2610/LTC2620 TYPICAL PERFORMANCE CHARACTERISTICS LTC2600/LTC2610/LTC2620 VCC = 5V SWEEP SCK, SDI AND CS/LD 0V TO VCC 2.3 2.2 VCC = 5V VREF = 2V VOUT 0.5V/DIV 2.1 2.0 VOUT 1V/DIV DACs A TO G IN POWER-DOWN MODE 1.9 CS/LD 5V/DIV 1.8 CLR 5V/DIV 1.7 2.5s/DIV 1.6 0.5 1 1.5 2 2.5 3 3.5 LOGIC VOLTAGE (V) 4 4.5 1s/DIV 2600 G14 2600 G15 5 2600 G13 Output Voltage Noise, 0.1Hz to 10Hz Multiplying Bandwidth 0 -3 -6 -9 -12 VOUT 10V/DIV -15 -18 -21 -24 VCC = 5V VREF (DC) = 2V VREF (AC) = 0.2VP-P CODE = FULL SCALE -27 -30 -33 -36 1k 10k 100k FREQUENCY (Hz) 0 1 2 3 4 5 6 SECONDS 7 8 9 10 2600 G17 1M 2600 G16 Short-Circuit Output Current vs VOUT (Sourcing) Short-Circuit Output Current vs VOUT (Sinking) 0mA 10mA/DIV 0 dB 1.5 10mA/DIV ICC (mA) Hardware CLR Exiting Power-Down to Mid-Scale Supply Current vs Logic Voltage 2.4 0mA VCC = 5.5V 1V/DIV VREF = 5.6V CODE = 0 VOUT SWEPT 0V TO VCC 2600 G18 1V/DIV VCC = 5.5V VREF = 5.6V CODE = FULL SCALE VOUT SWEPT VCC TO 0V 2600 G19 2600fe 9 LTC2600/LTC2610/LTC2620 PIN FUNCTIONS (GN/UFD) GND (Pin 1/Pin 20): Analog Ground. VOUTA to VOUTH (Pins 2-5 and 12-15/Pins 1-48 and 13-16): DAC Analog Voltage Outputs. The output range is 0 - VREF. REF (Pin 6/Pin 5): Reference Voltage Input. 0V VREF VCC. CS/LD (Pin 7/Pin 7): Serial Interface Chip Select/Load Input. When CS/LD is low, SCK is enabled for shifting data on SDI into the register. When CS/LD is taken high, SCK is disabled and the specified command (see Table 1) is executed. SCK (Pin 8/Pin 8): Serial Interface Clock Input. CMOS and TTL compatible. SDI (Pin 9/Pin 9): Serial Interface Data Input. Data is applied to SDI for transfer to the device at the rising edge of SCK. The LTC2600, LTC2610 and LTC2620 accept input word lengths of either 24 or 32 bits. SDO (Pin 10/Pin 10): Serial Interface Data Output. This pin is used for daisychain operation. The serial output of the shift register appears at the SDO pin. The data transferred to the device via the SDI pin is delayed 32 SCK rising edges before being output at the next falling edge. SDO is an active output and does not go high impedance, even when CS/LD is taken to a logic high level. CLR (Pin 11/Pin 11): Asynchronous Clear Input. A logic low at this level-triggered input clears all registers and causes the DAC voltage outputs to drop to 0V. CMOS and TTL compatible. VCC (Pin 16/Pin 17): Supply Voltage Input. 2.5V VCC 5.5V. DNC (Pins 6, 12, 18, 19 UFD Only): Do Not Connect. Exposed Pad (Pin 21 UFD Only): Ground. The exposed pad must be soldered to the PCB. 2600fe 10 LTC2600/LTC2610/LTC2620 VOUTA 2 DAC A DAC REGISTER INPUT REGISTER INPUT REGISTER (2) VOUTB 3 DAC B DAC REGISTER INPUT REGISTER INPUT REGISTER (3) VOUTC 4 DAC C DAC REGISTER INPUT REGISTER INPUT REGISTER (4) VOUTD 5 DAC D INPUT REGISTER INPUT REGISTER (5) REF 6 (7) CS/LD 7 (8) SCK 8 (17) DAC REGISTER (1) 16 VCC DAC H 15 VOUTH (16) DAC REGISTER 1 DAC G 14 VOUTG (15) DAC REGISTER GND DAC F 13 VOUTF (14) DAC REGISTER (20) DAC REGISTER BLOCK DIAGRAM DAC E 12 VOUTE (13) POWER-ON RESET CONTROL LOGIC 11 CLR (11) 10 SDO (10) 9 SDI (9) DECODE 32-BIT SHIFT REGISTER 2600 BD02 NOTE: NUMBERS IN PARENTHESIS REFER TO THE UFD PACKAGE TIMING DIAGRAM t1 t2 SCK t3 1 t6 t4 2 3 23 24 t10 SDI t5 t7 CS/LD t8 SDO 2600 F01 2600fe 11 LTC2600/LTC2610/LTC2620 OPERATION Power-On Reset Serial Interface The LTC2600/LTC2610/LTC2620 clear the outputs to zero-scale when power is first applied, making system initialization consistent and repeatable. The CS/LD input is level triggered. When this input is taken low, it acts as a chip-select signal, powering on the SDI and SCK buffers and enabling the input shift register. Data (SDI input) is transferred at the next 24 rising SCK edges. The 4-bit command, C3-C0, is loaded first; then the 4-bit DAC address, A3-A0; and finally the 16-bit data word. The data word comprises the 16-, 14- or 12-bit input code, ordered MSB-to-LSB, followed by 0, 2 or 4 don't-care bits (LTC2600, LTC2610 and LTC2620 respectively). Data can only be transferred to the device when the CS/LD signal is low.The rising edge of CS/LD ends the data transfer and causes the device to carry out the action specified in the 24-bit input word. The complete sequence is shown in Figure 2a. For some applications, downstream circuits are active during DAC power-up, and may be sensitive to nonzero outputs from the DAC during this time. The LTC2600/2610/2620 contain circuitry to reduce the power-on glitch: the analog outputs typically rise less than 10mV above zero-scale during power on if the power supply is ramped to 5V in 1ms or more. In general, the glitch amplitude decreases as the power supply ramp time is increased. See Power-On Reset Glitch in the Typical Performance Characteristics section. Power Supply Sequencing The voltage at REF (Pin 6) should be kept within the range -0.3V VREF VCC + 0.3V (see Absolute Maximum Ratings). Particular care should be taken to observe these limits during power supply turn-on and turn-off sequences, when the voltage at VCC (Pin 16) is in transition. Transfer Function The digital-to-analog transfer function is: k VOUT(IDEAL) = N VREF 2 The command (C3-C0) and address (A3-A0) assignments are shown in Table 1. The first four commands in the table consist of write and update operations. A write operation loads a 16-bit data word from the 32-bit shift register into the input register of the selected DAC, n. An update operation copies the data word from the input register to the DAC register. Once copied into the DAC register, the data word becomes the active 16-, 14- or 12-bit input code, and is converted to an analog voltage at the DAC output. The update operation also powers up the selected DAC if it had been in power-down mode. The data path and registers are shown in the Block Diagram. where k is the decimal equivalent of the binary DAC input code, N is the resolution and VREF is the voltage at REF (Pin 6). While the minimum input word is 24 bits, it may optionally be extended to 32 bits. To use the 32-bit word width, 8 don't-care bits are transferred to the device first, followed by the 24-bit word as just described. Figure 2b shows the Table 1. ADDRESS (n)* COMMAND* A3 A2 A1 A0 C3 C2 C1 C0 0 0 0 0 DAC A 0 0 0 0 Write to Input Register n 0 0 0 1 DAC B 0 0 0 1 Update (Power Up) DAC Register n 0 0 1 0 DAC C 0 0 1 0 Write to Input Register n, Update (Power Up) All n 0 0 1 1 DAC D 0 0 1 1 Write to and Update (Power Up) n 0 1 0 0 DAC E 0 1 0 0 Power Down n 0 1 0 1 DAC F 1 1 1 1 No Operation 0 1 1 0 DAC G 0 1 1 1 DAC H 1 1 1 1 All DACs *Command and address codes not shown are reserved and should not be used. 2600fe 12 LTC2600/LTC2610/LTC2620 OPERATION INPUT WORD (LTC2600) COMMAND C3 C2 C1 C0 ADDRESS A3 A2 A1 DATA (16 BITS) A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB 2600 TBL01 INPUT WORD (LTC2610) COMMAND C3 C2 C1 C0 ADDRESS A3 A2 A1 DATA (14 BITS + 2 DON'T-CARE BITS) A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MSB X X LSB 2600 TBL02 INPUT WORD (LTC2620) COMMAND C3 C2 C1 C0 ADDRESS A3 A2 A1 DATA (12 BITS + 4 DON'T-CARE BITS) A0 D11 D10 D9 D8 D7 D6 D5 MSB D4 D3 D2 D1 D0 X X X X LSB 2600 TBL03 32-bit sequence. The 32-bit word is required for daisychain operation, and is also available to accommodate microprocessors which have a minimum word width of 16 bits (2 bytes). Daisychain Operation The serial output of the shift register appears at the SDO pin. Data transferred to the device from the SDI input is delayed 32 SCK rising edges before being output at the next SCK falling edge. The SDO output can be used to facilitate control of multiple serial devices from a single 3-wire serial port (i.e., SCK, SDI and CS/LD). Such a "daisychain" series is configured by connecting SDO of each upstream device to SDI of the next device in the chain. The shift registers of the devices are thus connected in series, effectively forming a single input shift register which extends through the entire chain. Because of this, the devices can be addressed and controlled individually by simply concatenating their input words; the first instruction addresses the last device in the chain and so forth. The SCK and CS/LD signals are common to all devices in the series. In use, CS/LD is first taken low. Then the concatenated input data is transferred to the chain, using SDI of the first device as the data input. When the data transfer is complete, CS/LD is taken high, completing the instruction sequence for all devices simultaneously. A single device can be controlled by using the no-operation command (1111) for the other devices in the chain. 2600fe 13 LTC2600/LTC2610/LTC2620 OPERATION Power-Down Mode Voltage Outputs For power-constrained applications, power-down mode can be used to reduce the supply current whenever less than eight outputs are needed. When in power-down, the buffer amplifiers and reference inputs are disabled, and draw essentially zero current. The DAC outputs are put into a high impedance state, and the output pins are passively pulled to ground through individual 90k resistors. When all eight DACs are powered down, the master bias generation circuit is also disabled. Input- and DAC-register contents are not disturbed during power-down. Each of the 8 rail-to-rail amplifiers contained in these parts has guaranteed load regulation when sourcing or sinking up to 15mA at 5V (7.5mA at 3V). Any channel or combination of channels can be put into power-down mode by using command 0100b in combination with the appropriate DAC address, (n). The 16-bit data word is ignored. The supply and reference currents are reduced by approximately 1/8 for each DAC powered down; the effective resistance at REF (Pin 6) rises accordingly, becoming a high impedance input (typically > 1G) when all eight DACs are powered down. Normal operation can be resumed by executing any command which includes a DAC update, as shown in Table 1. The selected DAC is powered up as its voltage output is updated. There is an initial delay as the DAC powers up before it begins its usual settling behavior. If less than eight DACs are in a powered-down state prior to the update command, the power-up delay is 5s. If, on the other hand, all eight DACs are powered down, then the master bias generation circuit is also disabled and must be restarted. In this case, the power-up delay is greater: 12s for VCC = 5V, 30s for VCC = 3V. Load regulation is a measure of the amplifier's ability to maintain the rated voltage accuracy over a wide range of load conditions. The measured change in output voltage per milliampere of forced load current change is expressed in LSB/mA. DC output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from LSB/mA to Ohms. The amplifiers' DC output impedance is 0.025 when driving a load well away from the rails. When drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 25 typical channel resistance of the output devices; e.g., when sinking 1mA, the minimum output voltage = 25 * 1mA = 25mV. See the graph Headroom at Rails vs Output Current in the Typical Performance Characteristics section. The amplifiers are stable driving capacitive loads of up to 1000pF. Board Layout The excellent load regulation and DC crosstalk performance of these devices is achieved in part by keeping "signal" and "power" grounds separated internally and by reducing shared internal resistance to just 0.005. 2600fe 14 LTC2600/LTC2610/LTC2620 OPERATION The GND pin functions both as the node to which the reference and output voltages are referred and as a return path for power currents in the device. Because of this, careful thought should be given to the grounding scheme and board layout in order to ensure rated performance. The PC board should have separate areas for the analog and digital sections of the circuit. This keeps digital signals away from sensitive analog signals and facilitates the use of separate digital and analog ground planes which have minimal capacitive and resistive interaction with each other. Digital and analog ground planes should be joined at only one point, establishing a system star ground as close to the device's ground pin as possible. Ideally, the analog ground plane should be located on the component side of the board, and should be allowed to run under the part to shield it from noise. Analog ground should be a continuous and uninterrupted plane, except for necessary lead pads and vias, with signal traces on another layer. The GND pin of the part should be connected to analog ground. Resistance from the GND pin to system star ground should be as low as possible. Resistance here will add directly to the effective DC output impedance of the device (typically 0.025), and will degrade DC crosstalk. Note that the LTC2600/LTC2610/LTC2620 are no more susceptible to these effects than other parts of their type; on the contrary, they allow layout-based performance improvements to shine rather than limiting attainable performance with excessive internal resistance. Rail-to-Rail Output Considerations In any rail-to-rail voltage output device, the output is limited to voltages within the supply range. Since the analog outputs of the device cannot go below ground, they may limit for the lowest codes as shown in Figure 3b. Similarly, limiting can occur near full scale when the REF pin is tied to VCC. If VREF = VCC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC as shown in Figure 3c. No full-scale limiting can occur if VREF is less than VCC - FSE. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur. 2600fe 15 16 X X SDI SDO SCK CS/LD 1 X X 2 X X 3 X 4 X X X DON'T CARE 5 C3 SDI C2 2 C1 3 X X 6 X X 7 C3 C2 10 C1 11 C2 C1 COMMAND WORD 9 C3 A1 7 ADDRESS WORD A2 6 A0 8 D15 9 D14 10 D12 12 D11 13 D10 14 24-BIT INPUT WORD D13 11 D9 15 D7 17 DATA WORD D8 16 D6 18 D5 C0 C0 A3 A3 A2 14 A1 15 A2 A1 ADDRESS WORD 13 A0 A0 16 17 D15 D15 PREVIOUS 32-BIT INPUT WORD 12 D14 D14 18 t2 t8 D9 D9 t4 23 PREVIOUS D15 t3 17 D10 D10 22 SDO t1 D11 D11 21 D15 D12 D12 20 SDI SCK D13 D13 19 25 18 D7 PREVIOUS D14 D14 D8 DATA WORD D6 D5 D4 D3 D2 D2 30 YYYY F02a 29 D3 24 D0 28 D4 23 D1 27 D5 22 D2 26 D6 21 D3 D7 20 D4 24 D8 19 Figure 2a. LTC2600 24-Bit Load Sequence (Minimum Input Word). LTC2610 SDI Data Word: 14-Bit Input Code + 2 Don't-Care Bits; LTC2620 SDI Data Word: 12-Bit Input Code + 4 Don't-Care Bits A3 5 D1 D1 31 YYYY F02b CURRENT 32-BIT INPUT WORD D0 D0 32 OPERATION Figure 2b. LTC2600 32-Bit Load Sequence (Required for Daisy-Chain Operation). LTC2610 SDI/SDO Data Word: 14-Bit Input Code + 2 Don't-Care Bits; LTC2620 SDI/SDO Data Word: 12-Bit Input Code + 4 Don't-Care Bits X X 4 C0 8 COMMAND WORD 1 SCK CS/LD LTC2600/LTC2610/LTC2620 2600fe LTC2600/LTC2610/LTC2620 OPERATION VREF = VCC VREF = VCC POSITIVE FSE OUTPUT VOLTAGE OUTPUT VOLTAGE INPUT CODE (c) OUTPUT VOLTAGE 0 0V NEGATIVE OFFSET 32, 768 INPUT CODE (a) 65, 535 INPUT CODE (b) 2600 F03 Figure 3. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative Offset for Codes Near Zero-Scale (c) Effect of Positive Full-Scale Error for Codes Near Full Scale PACKAGE DESCRIPTION GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .189 - .196* (4.801 - 4.978) .045 .005 16 15 14 13 12 11 10 9 .254 MIN .009 (0.229) REF .150 - .165 .229 - .244 (5.817 - 6.198) .0165 .0015 .150 - .157** (3.810 - 3.988) .0250 BSC RECOMMENDED SOLDER PAD LAYOUT 1 .015 .004 x 45 (0.38 0.10) .007 - .0098 (0.178 - 0.249) .0532 - .0688 (1.35 - 1.75) 2 3 4 5 6 7 8 .004 - .0098 (0.102 - 0.249) 0 - 8 TYP .016 - .050 (0.406 - 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) .008 - .012 (0.203 - 0.305) TYP .0250 (0.635) BSC GN16 (SSOP) 0204 3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 2600fe 17 LTC2600/LTC2610/LTC2620 PACKAGE DESCRIPTION UFD Package 20-Lead Plastic QFN (4mm x 5mm) (Reference LTC DWG # 05-08-1711 Rev B) 0.70 p 0.05 4.50 p 0.05 1.50 REF 3.10 p 0.05 2.65 p 0.05 3.65 p 0.05 PACKAGE OUTLINE 0.25 p 0.05 0.50 BSC 2.50 REF 4.10 p 0.05 5.50 p 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 p 0.10 (2 SIDES) 0.75 p 0.05 PIN 1 NOTCH R = 0.20 OR C = 0.35 1.50 REF R = 0.05 TYP 19 20 0.40 p 0.10 PIN 1 TOP MARK (NOTE 6) 1 2 5.00 p 0.10 (2 SIDES) 2.50 REF 3.65 p 0.10 2.65 p 0.10 (UFD20) QFN 0506 REV B 0.200 REF 0.00 - 0.05 R = 0.115 TYP 0.25 p 0.05 0.50 BSC BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 2600fe 18 LTC2600/LTC2610/LTC2620 REVISION HISTORY (Revision history begins at Rev D) REV DATE DESCRIPTION PAGE NUMBER D 03/10 Revise GN Part Markings in Order Information E 05/10 Changed "No Connect" pins to "Do Not Connect" in Pin Configuration and Pin Functions sections 2 2, 10 2600fe Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC2600/LTC2610/LTC2620 TYPICAL APPLICATION Schematic for LTC2600 Demonstration Circuit DC579. The Outputs Are Measured by an Onboard LTC2428 1 4 3 2 1 VSS SDA A2 SCL A1 WP A0 VCC VREF VCC 1 TP1 TP2 5 R1, R3, R4 R1 are 4.99k, 1% 6 R3 R2 7.5k R4 11 7 C3 0.1F 8 C2 0.1F 6 REF CLR VCC VOUTA U1 24LC025 VOUTB 14 12 10 8 6 4 2 5V VCC C1 0.1F + + + + + + + + + + + + + + 13 11 9 7 5 3 1 SCK 8 CS 7 9 10 MOSI MISO VOUTC SCK VOUTD LS/LD VOUTE VOUTF SDI VOUTG SDO VOUTH 16 2 1 TP16 VIN TP3 DAC A 1 TP14 GND 4 1 TP4 DAC B 1 TP15 GND 1 TP5 DAC C 1 TP6 DAC D 1 TP7 DAC E 1 TP8 DAC F 1 TP9 DAC G 5 12 13 14 15 GND 1 1 3 U2 LTC2600CGN J1 HD2X7 1 VIN TP10 DAC H VREF VOUT VIN 6 9 1 C6 0.1F 1 5V 4.096V 2 3 JP2 TP11 VREF C7 4.7F 6.3V VREF U5 LT1461ACS8-4 2 3 C9 0.1F VIN VOUT 6 VCC 1 SHDN GND 4 C5 0.1F R8 22 C10 100pF 7 4 MUXOUT ADCIN 3 3 2 2 8 1 JP1 ON/OFF DISABLE ADC VCC VCC FSSET VREF GND 4 VCC C4 0.1F R5 7.5k U4 LT1236ACS8-5 2 VCC 1 5VREF C8 REGULATOR 1F 16V 2 3 JP3 1 VCC TP12 VCC TP13 GND CH0 10 CH1 11 CH2 12 CH3 13 CH4 14 CH5 15 CH6 17 CH7 5 ZSSET CSADC CSMUX 4-/8-CHANNEL MUX + 20-BIT ADC SCK CLK DIN - LTC2424/LTC2428 SD0 FO GND GND GND GND GND GND GND 1 U3 LTC2428CG 6 16 18 22 27 28 23 20 R6 7.5k CS 25 19 SCK 21 24 26 R7 7.5k 5V RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1458/LTC1458L Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.096V LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1654 Dual 14-Bit Rail-to-Rail VOUT DAC Programmable Speed/Power, 3.5s/750A, 8s/450A LTC1655/LTC1655L Single 16-Bit VOUT DAC with Serial Interface in SO-8 VCC = 5V(3V), Low Power, Deglitched LTC1657/LTC1657L Parrallel 5V/3V 16-Bit VOUT DAC Low Power, Deglitched, Rail-to-Rail VOUT LTC1660/LTC1665 Octal 10/8-Bit VOUT DAC in 16-Pin Narrow SSOP VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output LTC1821 Parallel 16-Bit Voltage Output DAC Precision 16-Bit Settling in 2s for 10V Step 2600fe 20 Linear Technology Corporation LT 0510 REV E * PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 www.linear.com (c) LINEAR TECHNOLOGY CORPORATION 2003