AUSTIN SEMICONDUCTOR. ING MTS5C2568 883C 32K x 8 SRAM SRAM 32K x 8 SRAM AVAILABLE AS MILITARY SPECIFICATIONS * SMD 5962-88662 MIL-STD-883 FEATURES Ultra high speed 12, 15ns High speed: 20, 25, 35 and 45ns Battery backup: 2V data retention Low power standby High-performance, low-power, CMOS double-metal process Single +5V (+10%) power supply e Easy memory expansion with CE. Allinputs and outputs are TTL compatible OPTIONS MARKING Timing 12ns access (Contact factory) -12 15ns access -15 20ns access -20 25ns access -25 35ns access -35 45ns access -45 55ns access ~-55* 7Ons access -70* Packages Ceramic DIP (300 mil} C No. 108 Ceramic DIP (600 mil) CW No. 110 Ceramic LCC (28 leads) EC No. 204 Ceramic LCC (32 leads) ECW No. 208 Ceramic Flat Pack F No. 302 Ceramic SOJ DJC No.500 e 2V data retention, low power standby L Radiation Tolerant (EPI) E *Electrical characteristics identical to those provided tor the 45ns access devices. GENERAL DESCRIPTION The Austin Semiconductor SRAM family employs high- speed, low-power CMOS designs using a four-transistor memory cell. Austin Serniconductor SRAMSs are fabricated using double-layer metal, double-layer polysilicon tech- nology. For flexibility in high-speed memory applications, Aus- tin Semiconductor offers chip enable (CE) and output en- able (OE) capability. These enhancements can place the PIN ASSIGNMENT (Top View) 28-PIN SOU ; 28-Pin DIP 32-Pin LCC (D15/D10) (C-12) Z ee aes AI401 2801 Vcc A122 270 WE ef < A713 26f A13 s E AG 44 250 A8 * = A505 240 a9 = # ber A406 230 At yereaee A347 22p 0E A248 211 A10 ; A109 200 CE 28-Pin Lcc A010 19) Das (C-11) Dai 411 182 Da7 eae 8 DQ2 412 17) DA wet dae ats DO3 413 16% DOS Sek moo vss 414 151 DO4 tel 2H Mate oa 32358 28-Pin Flat Pack outputs in High-Z for additional flexibility in system de- sign. Writing to these devices is accomplished when write enable (WE) and CE inputs are both LOW. Reading is accomplished when WE remains HIGH and CE and OE go LOW. The device offers a reduced power standby mode when disabled. This allows system designs to achieve low standby power requirements. MT5C2568 8830 REV 397 GSocooOT 1-73 Austin Semiconductor. Inc . reserves the night to change products or specificanons without noticeAUSTIN SEMICONDUCTOR. INC MT5C2568 883C Yan asl aT Y) The L version provides an approximate 50 percent reduction in CMOS standby current (Isc2) over the standard version. All devices operate from a single +5V power supply and all inputs and outputs are fully TTL compatible. FUNCTIONAL BLOCK DIAGRAM Vec GND ' | DQ8 262,144-BIT > MEMORY ARRAY @ , LL, DQ VO CONTROL area O90 ROW DECODER A | (LSB) OE WE ys COLUMN DECODER (LSB) POWER r t t ft t ft ot _ A A A A A A A TRUTH TABLE MODE OE cE WE pa POWER STANDBY x H x HIGH-Z STANDBY READ L L H Q ACTIVE READ H L H HIGH-Z ACTIVE WRITE x L L D ACTIVE MT5C2568 883C 1-74 Austin Semiconductor. Inc . reserves the ngnt to change orcaucts or specitcalians without note REV 397 - ps900007AUSTIN SEMICONDUCTOR. INC WITSC2568 883C 32K x 8 SRAM ABSOLUTE MAXIMUM RATINGS* *Stresses greater than those listed under Absolute Maxi- Voltage on Any Input or DQ Relative to Vss.... -2V to +7V mum Ratings may cause permanent damage to the device. Voltage on Vcc Supply Relative to VS... This is a stress rating only and functional operation of the Storage Temperature ......c.csccsscsescsesseesieneen device at these or any other conditions above those indi- Power Dissipation cated in the operational sections of this specification is not Short Circuit Output Current ...0.0. eee ese implied. Exposure to absolute maximum rating conditions Lead Temperature (soldering 10 seconds) for extended periods may affect reliability. Junction Temperature oo... eee teeeseee sete reneeeneeee ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (-55C < T, < 125C; Vcc = 5V + 10%) DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES Input High (Logic 1} Voltage Vin 2.2 Vcc+1.0 v 1 Input Low (Logic 0) Voltage ViL -0.5 0.8 Vv 1,2 Input Leakage Current OV < Vin < Vec Hu 5 5 pA Output Leakage Current Outputs Disabled ILo 5 5 HA OV < Vout < Vcc Output High Voltage loH = -4.0mA Vou 2.4 Vv 1 Output Low Voltage lo. = 8.0MA VoL 0.4 Vv 1 MAX DESCRIPTION CONDITIONS SYMBOL) -12 |-15 | -20 | -25 | -35 | -45 UNITS NOTES Power Supply CE < Vit; Vec = MAX Current: Operating f = MAX = 1/'RC (MIN) lec 190 |}165 | 150 | 140 | 135 | 130 mA 3 Output Open Power Supply CE 2 Vin; Vcc = MAX Current: Standby f = MAX = 1/'RC (MIN) | Isett 60 | 50 45 40 | 40 | 40 mA Output Open CE 2 Vin, All Other inputs < Vit or 2 Vin, Voc = MAX] Isat 25 | 25 25 25 25 25 mA f=OHz CE 2 Vec -0.2V; Voc = MAX Vit < Vss +0.2V Isacz 5 5 5 5 5 5 mA Vin 2 Vcc -0.2V; f = 0 Hz L Version Only|_ Isac2 4 4 4 4 4 4 mA CAPACITANCE DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES Input Capacitance Ty = 25C, f= IMHz Ci 8 pF 4 Output Capacitance Vcc = 5V Co 8 pF 4 ee BE3C 1 -75 Austin Semiconductor inc reserves the nght tc chanje products or specificanons vtnout notice Ds000007AUSTIN SEMICONDUCTOR, IN Rr 32K x 8 SRAM ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Note 5) (-55C < Tg < 125C; Voc = 5V + 10%) -12 -15 -20 -25 -35 45 DESCRIPTION SYM | MIN | MAX | MIN | MAX | MIN|MAX | MIN] MAX | MIN | MAX | MIN | MAX |UNTTS |NOTES READ Cycle READ cycle time 'RC 12 15 20: 25 35 45 ns Address access time AA 12 15 20 25 35 45 ns Chip Enable access time ACE 12 15 20 25 35 45 | ns Output hold from address change | OH | 2 2 2 2 2 2 ns Enable to output in Low-Z LZCE] 2 2 2 2 2 2 ns | 7 disable to output in Hig1-Z 'HZCE! 7 8 9 10 14 15 | ns |6,7 Chip Enable to power-up time 'PU 0 0 0 0 0 0 ns | 4 Chip disable to power-down time} 'PD 12 15 20 25 35 45 ns | 4 Output Enable access time AOE 6 8 9 10 14 15 ns Output Enable to output in Low-Z ['LZOE] 0 0 0 0 0 0 ns Output disable to output in High-Z | 'HZOE 4 6 8 10 14 15 | ns | 6 WRITE Cycle WRITE cycle time wc 12 15 20 25 35 45 ns Chip Enable to end of write cw} 10 12 15 18 20 25 ns Address valid to end of write AW | 10 12 15 18 20 25 ns Address setup time tAS 0 0 0 0 0 0 ns Address hold from end of write AH 2 2 2 2 2 2 ns WRITE pulse width we 10 12 15 17 20 25 ns Data setup time ps 6 7 10 12 15 20 ns Data hold time DH 0 a) OQ 0 0 0 ns Write disable to output in Low-Z|"LZWE| 2 2 2 2 2 2 ns | 7 Write Enable to output in High-Z} 'HZWE| 0 6 0 7 0 10 0 11 0 14 0 15 | ns 16,7 MT5C2568 883C 1 -76 Ausbn Semconguctor. Inc reserves the aght lo change products or specitications without noheewae MT5C2568 883C 32K x 8 SRAM AC TEST CONDITIONS Input pulse levels ...............ccecseteeeeeeerees Vss to 3V Input rise and fall times ...0....... eee eeeeeeeteree 5ns Input timing reference level ......00..00 ee 1.5V Output reference level... eee eeeeeteee 1.5V Output load .0....... eee eeeeesereeeeee See figures 1 and 2 NOTES 1. All voltages referenced to Vss (GND). 2. -3V for pulse width < 20ns. 3. Icc is dependent on output loading and cycle rates. The specified value applies with the outputs unloaded, and f = 1 'RC (MIN) 4, This parameter is guaranteed but not tested. 5. Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted. 6. tHZCE, 'HZOE and HZWE are specified with CL = 5 pF as in Fig. 2. Transition is measured + 500mV typical from steady state voltage, allowing for actual tester RC time constant. +5V 480 255 30 pF = Fig. 1 OUTPUT LOAD EQUIVALENT Fig. 2 OUTPUT LOAD EQUIVALENT 7. Atany given temperature and voltage condition, HZCE is less than LZCE and HZWE is less than 'LZWE. 8. WE is HIGH for READ cycle. 9. Device is continuously selected. Chip enable and output enable are held in their active state. 10. Address valid prior to or coincident with latest occurring chip enable. 11. RC = READ cycle time. 12. Chip enable (CE) and write enable (WE) can initiate and terminate a WRITE cycle. DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only) DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES Vec for Retention Data Vor 2 _ Vv Data Retention Current CE 2 (Vcc - 0.2V)|Vcc = 2V|_ Iccor 500 pA Vin > (Vcc - 0.2V) or<0.2V Vcc = 3V 800 pA Chip Deselect to Data CDR 0 ns 4 Retention Time Operation Recovery Time 'R 'RC ns 4,14 LOW Vcc DATA RETENTION WAVEFORM DATA RETENTION MODE 4.5V ~~ N icpR Vcc kK Yor >2Vv 7 45VY tR v eT DOR / WY, DON'T CARE B34 UNDEFINED MT5C2568 883C. REV 3a? Dscoo007 Austin Semiconductor. Inc , reserves the ngnt to change products or specificalons without notice 1-77z AUSTIN SEMICONDL C TOR. INC ne pekch ce 32K x 8 SRAM READ CYCLE NO. 18 tac | ADDR } VALID Y TAA tou Q PREVIOUS DATA VALID DATA VALID READ CYCLE NO. 27.810 tac _ \ CE K A Xe) tLZ0E | 'HZOE OE X } 'ACE tL2CcE tHZCE pq HIGH-z is DATA VALID =-_ tpb teu [oe i lec | DON'T CARE RY) UNDEFINED MT5C2568 883C 1 -78 Austin Semconductor inc. reserves the ngnl to change products of specifications without notice REV 397 dDso000ce7AUSTEN SEMICONDUCTOR, INC. IT5C 2568 883C 32K x 8 SRAM NOTE: WRITE CYCLE NO. 1 '2 (Chip Enable Controlled) two ADDR taw tas \ tow tay oc | { we we WLLL | CUM ps 'bH D DATA VALID Q HiGH-Z WRITE CYCLE NO. 27. 72 (Write Enable Controlled) two ADDR taw | cw tad | tas 1 we a /\ i tos DH D DATA VALID Q HIGH-Z Output enable (OE) is inactive (HIGH). DON'T CARE RM] UNDEFINED MT5C2568 883C REV. 397 Dso00007 1 -79 Austin Semiconductor, inc. reserves the nght to change products or specications without noticeAUSTIN SEMICONDUCTOR, EN MTSC2568 883C 32K x 8 SRAM | | ELECTRICAL TEST REQUIREMENTS SUBGROUPS MIL-STD-883 TEST REQUIREMENTS (per Method 5005, Table !) INTERIM ELECTRICAL (PRE-BURN-IN) TEST PARAMETERS 2, BA, 10 (Method 5004) FINAL ELECTRICAL TEST PARAMETERS 1*, 2,3, 7*, 8,9, 10, 11 (Method 5004) GROUP A TEST REQUIREMENTS 1,2, 3, 4**, 7,8, 9, 10, 11 (Method 5005) GROUP C AND D END-POINT ELECTRICAL PARAMETERS 1, 2,3, 7, 8,9, 10, 11 (Method 5005) * PDA applies to subgroups 1 and 7. ** Subgroup 4 shall be measured only for initial qualification and after process or design changes. which may affect input or output capacitance. MT5C2568 883C 1 -80 Austin Semiconductor. inc reserves tne right to change products or specificabons without notice REV 397 DSo00007