1
Features
•Compatible with an Embedded ARM®Processor
•Three 16-bit Timer/Counter Channels
•A Wide Range of Functions Including:
– Frequency Measurement
– Event Counting
– Interval Measurement
– Pulse Generation
– Delay Timing
– Pulse Width Modulation
– Up/down Capabilities
•Each Channel Contains Three External Clock Inputs, Five Internal Clock Inputs and
Two Multi-purpose Input/Output Signals, All User-configurable
•Internal Interrupt Signal
•Two Global Registers That Act on All Three TC1 Channels
•Fully Scan Testable Up to 99% Fault Coverage
•Can be Directly Connected to the Atmel Implementation of the AMBA™Peripheral Bus
(APB)
Description
The Timer/Counter 1 (TC1) includes three identical 16-bit timer/counter channels.
Each channel can be independently programmed to perform a wide range of functions
including frequency measurement, event counting, interval measurement, pulse gen-
eration, delay timing and pulse width modulation.
Each channel has three external clock inputs, five internal clock inputs and two multi-
purpose input/output signals which can be configured by the user. Each channel
drives an internal interrupt signal which can be programmed to generate processor
interrupts.
The Timer/Counter 1 block has two global registers which act upon all three TC1
channels. The Block Control Register allows the three channels to be started simulta-
neously with the same instruction. The Block Mode Register defines the external clock
inputs for each channel, allowing them to be chained.
The TC1 can be used with any 32-bit microcontroller core if the timing diagram shown
on page 6 is respected. When using an ARM7TDMI™as the core, the Atmel Bridge
must be used to provide the correct bus interface to the peripheral.
Scan Test Configuration
The fault coverage is maximum if all non-scan inputs can be controlled and all non-
scan outputs can be observed. In order to achieve this, the ATPG vectors must be
generated on the entire circuit (top-level) which includes the Timer/Counter 1 or all
TC1 I/Os must have a top level access and ATPG vectors must be applied to these
pins.
32-bit
Embedded ASIC
Core Peripheral
Timer/Counter 1
(TC1)
Rev. 1753B–CASIC–02/02
2Timer/Counter 1 (TC1)
1753B–CASIC–02/02
Figure 1. Timer/Counter 1 Pin Configuration
P_D_IN[31:0]
NRESET_R
P_A[13:0]
P_WRITE
P_STB
NRESET_F
P_SEL_TIMER
SCAN_TEST_MODE
TIMER_INT0
TIMER_INT1
TEST_SO[5:1]
P_D_OUT[31:0]
Timer/
Counter 1
Functional
Functional
TEST_SE
TEST_SI[5:1]
Test Scan
Test Scan
P_STB_RISING
CLOCK_CH1
CLOCK_CH2
CLOCK_CH0
TIMER_DIV1_CLOCK
TIMER_DIV3_CLOCK
TIMER_DIV2_CLOCK
TIMER_DIV5_CLOCK
TIMER_DIV4_CLOCK
TIMER_CLK0
TIMER_CLK2
TIMER_CLK1
TIMER_INT2
TIMER_EXT_OUT_A0
TIMER_EXT_OUT_B0
TIMER_EXT_OUT_A1
TIMER_EXT_OUT_B1
TIMER_EXT_OUT_A2
TIMER_EXT_OUT_B2
NTIMER_OUT_ENABLE_A0
NTIMER_OUT_ENABLE_B0
NTIMER_OUT_ENABLE_A1
NTIMER_OUT_ENABLE_B1
NTIMER_OUT_ENABLE_A2
NTIMER_OUT_ENABLE_B2
TIMER_EXT_IN_A0
TIMER_EXT_IN_A1
TIMER_EXT_IN_B0
TIMER_EXT_IN_A2
TIMER_EXT_IN_B1
TIMER_EXT_IN_B2
SLCLK_EQ_SYSCLK
3
Timer/Counter 1 (TC1)
1753B–CASIC–02/02
Table 1. Timer/Counter 1 Pin Description
Name Function Type
Active
Level Comments
Functional
NRESET_R Reset system Input Low Resets all the counters and signals on rising
edge of master clock
NRESET_F Reset system Input Low Resets all the counters and signals on falling
edge of master clock
CLOCK_CH0 Channel clock Input –Master clock of channel 0
CLOCK_CH1 Channel clock Input –Master clock of channel 1
CLOCK_CH2 Channel clock Input –Master clock of channel 2
SLCLK_EQ_SYSCLK ARM Core operation Input –
P_A[13:0] Address bus Input –Theaddresstakesintoaccountthe2LSBs
[1:0], but the macrocell does not take these bits
into account (left unconnected).
P_D_IN[31:0] Input data bus Input –From host (bridge)
P_D_OUT[31:0] Output data bus Output –To host (bridge)
P_WRITE Write enable Input High From host (bridge)
P_STB Peripheral strobe Input High From host (bridge)
P_STB_RISING User interface clock
signal
Input From host (bridge). Clock for all DFFs
controlling the configuration registers.
P_SEL_TIMER Selection of the block Input High From host (bridge)
TIMER_INT0 Interrupt 0 Output High Programmable from alarm and/or event
TIMER_INT1 Interrupt 1 Output High Programmable from alarm and/or event
TIMER_INT2 Interrupt 2 Output High Programmable from alarm and/or event
TIMER_DIV1_CLOCK Clock enable Input System clock (CLOCK_CHx) divided
TIMER_DIV2_CLOCK Clock enable Input System clock (CLOCK_CHx) divided
TIMER_DIV3_CLOCK Clock enable Input System clock (CLOCK_CHx) divided
TIMER_DIV4_CLOCK Clock enable Input System clock (CLOCK_CHx) divided
TIMER_DIV5_CLOCK Clock enable Input System clock (CLOCK_CHx) divided
TIMER_CLK0 External master clock Input User-defined external clock, comes from pad
TIMER_CLK1 External master clock Input User-defined external clock, comes from pad
TIMER_CLK2 External master clock Input User-defined external clock, comes from pad
TIMER_EXT_IN_A0,
TIMER_EXT_IN_A1,
TIMER_EXT_IN_A2
External input A Input User-defined external input for receiving
waveforms. Can be connected to a bidir pad.
TIMER_EXT_IN_B0,
TIMER_EXT_IN_B1,
TIMER_EXT_IN_B2
External input B Input User-defined external input for receiving
waveforms. Can be connected to a bidir pad.
4Timer/Counter 1 (TC1)
1753B–CASIC–02/02
TIMER_EXT_OUT_A0,
TIMER_EXT_OUT_A1,
TIMER_EXT_OUT_A2
External output A Output User-defined external output for transmitting
waveforms. Can be connected to a bidir pad.
TIMER_EXT_OUT_B0,
TIMER_EXT_OUT_B1,
TIMER_EXT_OUT_B2
External output B Output User-defined external output for transmitting
waveforms. Can be connected to a bidir pad.
NTIMER_OUT_ENABLE_A0,
NTIMER_OUT_ENABLE_A1,
NTIMER_OUT_ENABLE_A2
Output enable A Output Low Can be connected to a BIDIR enable pin to
define the direction.
NTIMER_OUT_ENABLE_B0,
NTIMER_OUT_ENABLE_B1,
NTIMER_OUT_ENABLE_B2
Output enable B Output Low Can be connected to a BIDIR enable pin to
define the direction.
Test Scan
SCAN_TEST_MODE Clock selection for
test purposes
Input High All sequential cells are driven with the same
clock phase (CLK32768)
TEST_SE Scan test enable Input High/low Scan shift /scan capture
TEST_SI[5:1] Scan test input Input High Entry of scan chain
TEST_SO[5:1] Scan test output Output –Ouput of scan chain
Table 1. Timer/Counter 1 Pin Description (Continued)
Name Function Type
Active
Level Comments
5
Timer/Counter 1 (TC1)
1753B–CASIC–02/02
Figure 2. Connecting the Timer/Counter 1 to an ARM®-based Microcontroller
32-bit
Core
(ARM)
Atmel Bridge
P_WRITE
P_D_FRBR / P_D_IN[31:0](1)
P_D_TOBR / P_D_OUT[31:0](2)
P_STB
P_A[13:0]
P_SEL_TIMER
Atmel Bus Interface
ASB
Timer/Counter 1
NRESET_R
To Advanced
Interrupt
Controller (AIC)
TIMER_INT0
NRESET_R
TIMER_INT1
TIMER_INT2
CLOCK_CH0
Power
Management/
Clock Generator
CLOCK_CH1
CLOCK_CH2
TIMER_DIV1_CLOCK
TIMER_DIV2_CLOCK
TIMER_DIV3_CLOCK
TIMER_DIV4_CLOCK
TIMER_DIV5_CLOCK
Pad
or
PIO
TIMER_EXT_IN_A0 - 2,
TIMER_EXT_IN_B0 - 2
TIMER_EXT_OUT_A0 - 2,
TIMER_EXT_OUT_B0 - 2
NTIMER_OUT_ENABLE_A0 - 2
NTIMER_OUT_ENABLE_B0 - 2
NRESET_F
P_STB_RISING
Pad
or
PIO
TIMER_CLK0
TIMER_CLK1
TIMER_CLK2
TIOA0 - 2
TIOB0 - 2
TCLK0 - 2
6Timer/Counter 1 (TC1)
1753B–CASIC–02/02
Figure 3. Timer/Counter 1 Timing Diagram
CLOCK_CH0 - 2
Valid
P_STB
P_A[13:0]
P_D_IN[31:0]
P_WRITE
P_D_OUT[31:0]
tPD1 tPD2
tPD_OUT, tPD_INT,
tSU_WRITE tHOLD_WRITE
tHOLD_DIN
tSU_DIN
tPD_NTIMER
tSU_DIV, tSU_IN tHOLD_DIV, tHOLD_IN
TIMER_EXT_OUT_A0 - 2,
TIMER_INT0 - 2
NTIMER_OUT_ENABLE_A0 - 2,
NTIMER_OUT_ENABLE_B0 - 2
TIMER_DIVX_CLOCK
TIMER_EXT_IN_A0 - 2,
TIMER_EXT_IN_B0 - 2
P_STB_RISING
tSU_A tHOLD_A
7
Timer/Counter 1 (TC1)
1753B–CASIC–02/02
Figure 4. Timer/Counter 1 Block Diagram
Notes: 1. DIVx = TIMER_DIVx_CLOCK where x = 1, 2, 3, 4 or 5
2. TIOA = TIMER_EXT_IN_Ax, TIMER_EXT_OUT_Ax
TIOB = TIMER_EXT_IN_Bx, TIMER_EXT_OUT_Bx
3. TCLK0 - 2 = TIMER_CLK0 - 2
Timer/Counter 1
Channel 0
Timer/Counter 1
Channel 1
Timer/Counter 1
Channel 2
SYNC
Parallel I/O
Controller
TC1XC1S
TC0XC0S
TC2XC2S
INT0
INT1
INT2
TIOA0
TIOA1
TIOA2
TIOB0
TIOB1
TIOB2
XC0
XC1
XC2
XC0
XC1
XC2
XC0
XC1
XC2
TCLK0
TCLK1
TCLK2
TCLK0
TCLK1
TCLK2
TCLK0
TCLK1
TCLK2
TIOA1
TIOA2
TIOA0
TIOA2
TIOA0
TIOA1
Advanced
Interrupt
Controller
TCLK0
TCLK1
TCLK2
TIOA0
TIOB0
TIOA1
TIOB1
TIOA2
TIOB2
Timer Counter Block
TIOA
TIOB
TIOA
TIOB
TIOA
TIOB
SYNC
SYNC
DIV2(1)
DIV3(1)
DIV4(1)
DIV5(1)
DIV1(1)
8Timer/Counter 1 (TC1)
1753B–CASIC–02/02
Signal Name
Description Block/Channel Signal Name Description
Channel Signal
XC0, XC1, XC2 External Clock Inputs
TIOA Capture Mode: General-purpose Input
Waveform Mode: General-purpose Output
TIOB Capture Mode: General-purpose Input
Waveform Mode: General-purpose Input/output
INT Interrupt Signal Output
SYNC Synchronization Input Signal
Block Signal
TCLK0, TCLK1, TCLK2 External Clock Inputs
TIOA0 TIOA Signal for Channel 0
TIOB0 TIOB Signal for Channel 0
TIOA1 TIOA Signal for Channel 1
TIOB1 TIOB Signal for Channel 1
TIOA2 TIOA Signal for Channel 2
TIOB2 TIOB Signal for Channel 2
9
Timer/Counter 1 (TC1)
1753B–CASIC–02/02
Timer/Counter 1
Description
The three channels of the Timer/Counter 1 are independent and identical in operation. The
registers for channel programming are listed in Table 3 on page 22.
Counter Each channel is organized around a 16-bit counter. The value of the counter is incremented at
each positive edge of the selected clock. When the counter has reached the value 0xFFFF
and passes to 0x0000, an overflow occurs and the bit COVFS in TC1_SR (Status Register) is
set.
The current value of the counter is accessible in real time by reading the Counter Value Regis-
ter, TC1_CV. The counter can be reset by a trigger. In this case, the counter value passes to
0x0000 on the next valid edge of the selected clock.
Clock Selection At block level, input clock signals of each channel can either be connected to the external
inputs TCLK0, TCLK1 or TCLK2, or be connected to the configurable I/O signals TIOA0,
TIOA1 or TIOA2 for chaining by programming the TC1_BMR (Block Mode). See Figure 5.
Each channel can independently select an internal or external clock source for its counter:
•Internal clock signals: TIMER_DIV1_CLOCK, TIMER_DIV2_CLOCK,
TIMER_DIV3_CLOCK, TIMER_DIV4_CLOCK, TIMER_DIV5_CLOCK
•External clock signals: XC0, XC1 or XC2
This selection is made by the TCCLKS bits in the TC1 Channel Mode Register (Capture
Mode).
The selected clock can be inverted with the CLKI bit in TC1_CMR (Capture Mode). This allows
counting on the opposite edges of the clock.
The burst function allows the clock to be validated when an external signal is high. The
BURST parameter in the Mode Register defines this signal (none, XC0, XC1, XC2).
Note: In all cases, if an external clock is used, the duration of each of its levels must be longer than the
master clock (CLOCK_CHx) period. The external clock frequency must be at least 2.5 times
lower than the master clock (CLOCK_CHx).
Figure 5. Clock Selection
TIMER_DIV1_CLOCK
TIMER_DIV2_CLOCK
TIMER_DIV3_CLOCK
TIMER_DIV4_CLOCK
TIMER_DIV5_CLOCK
XC0
XC1
XC2
TCCLKS
CLKI
BURST
1
Selected
Clock
10 Timer/Counter 1 (TC1)
1753B–CASIC–02/02
Clock Control The clock of each counter can be controlled in two different ways: it can be enabled/disabled
and started/stopped. See Figure 6.
•The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS
commands in the Control Register. In Capture Mode it can be disabled by an RB load
event if LDBDIS is set to 1 in TC1_CMR. In Waveform Mode, it can be disabled by an RC
Compare event if CPCDIS is set to 1 in TC1_CMR. When disabled, the start or the stop
actions have no effect: only a CLKEN command in the Control Register can re-enable the
clock. When the clock is enabled, the CLKSTA bit is set in the Status Register.
•Theclockcanalsobestarted or stopped: a trigger (software, synchro, external or
compare) always starts the clock. The clock can be stopped by an RB load event in
Capture Mode (LDBSTOP = 1 in TC1_CMR) or a RC compare event in Waveform Mode
(CPCSTOP = 1 in TC1_CMR). The start and the stop commands have effect only if the
clock is enabled.
Figure 6. Clock Control
Timer/Counter 1
Operating Modes
Each channel can independently operate in two different modes:
•Capture Mode allows measurement on signals.
•Waveform Mode allows wave generation.
The Timer/Counter 1 Operating Mode is programmed with the WAVE bit in the TC1 Channel
Mode Register. In Capture Mode, TIOA and TIOB are configured as inputs. In Waveform
Mode, TIOA is always configured to be an output and TIOB is an output if it is not selected to
be the external trigger.
QS
R
S
R
Q
CLKSTA CLKEN CLKDIS
Stop
Event
Disable
Event
Counter
Clock
Selected
Clock Trigger
11
Timer/Counter 1 (TC1)
1753B–CASIC–02/02
Trigg er A trigger resets the counter and starts the counter clock. Three types of triggers are common
to both modes, and a fourth external trigger is available to each mode.
The following triggers are common to both modes:
•Software Trigger: Each channel has a software trigger, available by setting SWTRG in
TC1_CCR.
•SYNC: Each channel has a synchronization signal SYNC. When asserted, this signal has
the same effect as a software trigger. The SYNC signals of all channels are asserted
simultaneously by writing TC1_BCR (Block Control) with SYNC set.
•Compare RC Trigger: RC is implemented in each channel and can provide a trigger when
the counter value matches the RC value if CPCTRG is set in TC1_CMR.
The channel can also be configured to have an external trigger. In Capture Mode, the external
trigger signal can be selected between TIOA and TIOB. In Waveform Mode, an external event
can be programmed on one of the following signals: TIOB, XC0, XC1 or XC2. This external
event can then be programmed to perform a trigger by setting ENETRG in TC1_CMR.
If an external trigger is used, the duration of the pulses must be longer than the master clock
(CLOCK_CHx) period in order to be detected.
Whatever the trigger used, it will be taken into account at the following active edge of the
selected clock. This means that the counter value can be read different from zero just after a
trigger, especially when a low frequency signal is selected as the clock.
12 Timer/Counter 1 (TC1)
1753B–CASIC–02/02
Capture Operating
Mode
This mode is entered by clearing the WAVE parameter in TC1_CMR (Channel Mode
Register).
Capture Mode allows the TC1 channel to perform measurements such as pulse timing, fre-
quency, period, duty cycle and phase on TIOA and TIOB signals which are considered as
input.
Figure 7 shows the configuration of the TC1 channel when programmed in Capture Mode.
Capture Registers
A and B (RA and RB)
Registers A and B are used as capture registers. This means that they can be loaded with the
counter value when a programmable event occurs on the signal TIOA.
The parameter LDRA in TC1_CMR defines the TIOA edge for the loading of register A, and
the parameter LDRB defines the TIOA edge for the loading of Register B.
RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since
the last loading of RA.
RB is loaded only if RA has been loaded since the last trigger or the last loading of RB.
Loading RA or RB before the read of the last value loaded sets the Overrun Error Flag
(LOVRS) in TC1_SR (Status Register). In this case, the old value is overwritten.
Trigger Conditions In addition to the SYNC signal, the software trigger and the RC compare trigger, an external
trigger can be defined.
Bit ABETRG in TC1_CMR selects input signal TIOA or TIOB as an external trigger. Parameter
ETRGEDG defines the edge (rising, falling or both) detected to generate an external trigger. If
ETRGEDG = 0 (none), the external trigger is disabled.
Status Register The following bits in the Status Register are significant in Capture Operating Mode.
•CPAS, CPBS, CPCS: RC Compare Status
There has been an RC Compare match at least once since the last read of the status.
•COVFS: Counter Overflow Status
The counter has attempted to count past $FFFF since the last read of the status.
•LOVRS: Load Overrun Status
RA or RB has been loaded at least twice without any read of the corresponding register,
since the last read of the status.
•LDRAS: Load RA Status
RA has been loaded at least once without any read, since the last read of the status.
•LDRBS: Load RB Status
RB has been loaded at least once without any read, since the last read of the status.
•ETRGS: External Trigger Status
An external trigger on TIOA or TIOB has been detected since the last read of the status.
13
Timer/Counter 1 (TC1)
1753B–CASIC–02/02
Figure 7. Capture Mode
TIMER_DIV1_CLOCK
TIMER_DIV2_CLOCK
TIMER_DIV3_CLOCK
TIMER_DIV4_CLOCK
TIMER_DIV5_CLOCK
XC0
XC1
XC2
TCCLKS
CLKI
QS
R
S
R
Q
CLKSTA CLKEN CLKDIS
BURST
TIOB
Register C
Capture
Register A
Capture
Register B Compare RC =
16-bit Counter
ABETRG
SWTRG
ETRGEDG CPCTRG
TC1_IMR
Trig
LDRBS
LDRAS
ETRGS
TC1_SR
LOVRS
COVFS
SYNC
1
MTIOB
TIOA
MTIOA
LDRA
LDBSTOP
If RA is not loaded
or RB is loaded If RA is loaded
LDBDIS
CPCS
INT
Edge
Detector
Edge
Detector
LDRB
Edge
Detector
CLK
OVF
RESET
Timer/Counter 1 Channel
CLK_CH to all flip-flops
14 Timer/Counter 1 (TC1)
1753B–CASIC–02/02
Waveform
Operating Mode
This mode is entered by setting the WAVE parameter in TC1_CMR (Channel Mode Register).
Waveform Operating Mode allows the TC1 channel to generate 1 or 2 PWM signals with the
same frequency and independently programmable duty cycles, or to generate different types
of one-shot or repetitive pulses.
In this mode, TIOA is configured as output and TIOB is defined as output if it is not used as an
external event (EEVT parameter in TC1_CMR).
Figure 8 on page 15 shows the configuration of the TC1 channel when programmed in Wave-
form Operating Mode.
Waveform Selection Depending on the parameter WAVSEL in TC1_CMR (Channel Mode Register), the behavior
of TC1_CV varies.
With any selection, RA, RB and RC can all be used as compare registers.
RA Compare may be used to control the TIOA output, RB Compare may be used to control
the TIOB output (if correctly configured) and RC Compare may be used to control TIOA and/or
TIOB outputs.
15
Timer/Counter 1 (TC1)
1753B–CASIC–02/02
Figure 8. Waveform Mode
TCCLKS
CLKI
QS
R
S
R
Q
CLKSTA CLKEN CLKDIS
CPCDIS
BURST
TIOB
Register A Register B Register C
Compare RA = Compare RB = Compare RC =
CPCSTOP
16-bit Counter
EEVT
EEVTEDG
SYNC
SWTRG
ENETRG
WAVSEL
TC1_IMR
Trig
ACPC
ACPA
AEEVT
ASWTRG
BCPC
BCPB
BEEVT
BSWTRG
TIOA
MTIOA
TIOB
MTIOB
CPAS
COVFS
ETRGS
TC1_SR
CPCS
CPBS
CLK
OVF
RESET
Output Controller
Output Controller
INT
1
Edge
Detector
Timer/Counter 1 Channel
CLK_CH to all flip-flops
TIMER_DIV1_CLOCK
TIMER_DIV2_CLOCK
TIMER_DIV3_CLOCK
TIMER_DIV4_CLOCK
TIMER_DIV5_CLOCK
XC0
XC1
XC2
WAVSEL
16 Timer/Counter 1 (TC1)
1753B–CASIC–02/02
WAVSEL = 00 When WAVSEL = 00, the value of TC1_CV is incremented from 0 to 0xFFFF. Once 0xFFFF
has been reached, the value of TC1_CV is reset. Incrementation of TC1_CV starts again and
the cycle continues. See Figure 9.
A trigger such as an external event or a software trigger can reset the value of TC1_CV. It is
important to note that the trigger may occur at any time. See Figure 10. RC Compare cannot
be programmed to generate a trigger in this configuration. At the same time, RC Compare can
stop the counter clock (CPCSTOP = 1 in TC1_CMR) and/or disable the counter clock (CPC-
DIS=1inTC1_CMR).
Figure 9. WAVSEL = 00 Without Trigger
Figure 10. WAVSEL = 00 With Trigger
Time
Counter Value
RC
RB
RA
TIOB
TIOA
Counter cleared by compare match with 0xFFFF
0xFFFF
Waveform Examples
Time
Counter Value
RC
RB
RA
TIOB
TIOA
Counter cleared by compare match with 0xFFFF
0xFFFF
Waveform Examples
Counter cleared by trigger
17
Timer/Counter 1 (TC1)
1753B–CASIC–02/02
WAVSEL = 10 When WAVSEL = 10, the value of TC1_CV is incremented from 0 to the value of RC, then
automatically reset on an RC Compare. Once the value of TC1_CV has been reset, it is then
incremented and so on. See Figure 11. It is important to note that at any time TC1_CV can be
reset by an external event or a software trigger if both are programmed correctly. See Figure
12. In addition, RC Compare can stop the counter clock (CPCSTOP = 1 in TC1_CMR) and/or
disable the counter clock (CPCDIS = 1 in TC1_CMR).
Figure 11. WAVSEL = 10 Without Trigger
Figure 12. WAVSEL = 10 With Trigger
Time
Counter Value
RC
RB
RA
TIOB
TIOA
Counter cleared by compare match with RC
0xFFFF
Waveform Examples
Time
Counter Value
RC
RB
RA
TIOB
TIOA
Counter cleared by compare match with RC
0xFFFF
Waveform Examples
Counter cleared by trigger
18 Timer/Counter 1 (TC1)
1753B–CASIC–02/02
WAVSEL = 01 When WAVSEL = 01, the value of TC1_CV is incremented from 0 to 0xFFFF. Once 0xFFFF is
reached, the value of TC1_CV is decremented to 0, then re-incremented to 0xFFFF and so
on. See Figure 13. A trigger such as an external event or a software trigger can modify
TC1_CV at any time. If a trigger occurs while TC1_CV is incrementing, TC1_CV then decre-
ments. If a trigger is received while TC1_CV is decrementing, TC1_CV then increments. See
Figure 14.
RC Compare cannot be programmed to generate a trigger in this configuration.
At the same time, RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the
counter clock (CPCDIS = 1).
Figure 13. WAVSEL= 01 Without Trigger
Figure 14. WAVSEL = 01 With Trigger
Time
Counter Value
RC
RB
RA
TIOB
TIOA
Counter decremented by compare match with 0xFFFF
0xFFFF
Waveform Examples
Time
Counter Value
TIOB
TIOA
Counter decremented by compare match with 0xFFFF
0xFFFF
Waveform Examples
Counter decremented
by trigger
Counter incremented
by trigger
RC
RB
RA
19
Timer/Counter 1 (TC1)
1753B–CASIC–02/02
WAVSEL = 11 When WAVSEL = 11, the value of TC1_CV is incremented from 0 to RC. Once RC is reached,
the value of TC1_CV is decremented to 0, then re-incremented to RC and so on. See Figure
15. A trigger such as an external event or a software trigger can modify TC1_CV at any time. If
a trigger occurs while TC1_CV is incrementing, TC1_CV then decrements. If a trigger is
received while TC1_CV is decrementing, TC1_CV then increments. See Figure 16.
RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock
(CPCDIS = 1).
Figure 15. WAVSEL = 11 Without Trigger
Figure 16. WAVSEL = 11 With Trigger
Time
Counter Value
RC
RB
RA
TIOB
TIOA
Counter decremented by compare match with RC
0xFFFF
Waveform Examples
Time
Counter Value
TIOB
TIOA
Counter decremented by compare match with RC
0xFFFF
Waveform Examples
Counter decremented
by trigger
Counter incremented
by trigger
RC
RB
RA
20 Timer/Counter 1 (TC1)
1753B–CASIC–02/02
External Event/Trigger
Conditions
An external event can be programmed to be detected on one of the clock sources (XC0, XC1,
XC2) or TIOB. The external event selected can then be used as a trigger.
The parameter EEVT in TC1_CMR selects the external trigger. The parameter EEVTEDG
defines the trigger edge for each of the possible external triggers (rising, falling or both). If
EEVTEDG is cleared (none), no external event is defined.
If TIOB is defined as an external event signal (EEVT = 0), TIOB is no longer used as output
and the TC1 channel can only generate a waveform on TIOA.
When an external event is defined, it can be used as a trigger by setting bit ENETRG in
TC1_CMR.
As in Capture Mode, the SYNC signal and the software trigger are also available as triggers.
RC Compare can also be used as a trigger depending on the parameter WAVSEL.
Output Controller The output controller defines the output level changes on TIOA and TIOB following an event.
TIOB control is used only if TIOB is defined as output (not as an external event).
The following events control TIOA and TIOB: software trigger, external event and RC com-
pare. RA compare controls TIOA and RB compare controls TIOB. Each of these events can
be programmed to set, clear or toggle the output as defined in the corresponding parameter in
TC1_CMR.
The tables below show which parameter in TC1_CMR is used to define the effect of each
event.
If two or more events occur at the same time, the priority level is defined as follows:
1. Software trigger
2. External event
3. RC compare
4. RA or RB compare
Status The following bits in the Status Register TC1_SR are significant in Waveform Mode:
•CPAS: RA Compare Status
There has been a RA Compare match at least once since the last read of the status
•CPBS: RB Compare Status
There has been a RB Compare match at least once since the last read of the status
Parameter TIOA Event
ASWTRG Software trigger
AEEVT External event
ACPC RC compare
ACPA RA compare
Parameter TIOB Event
BSWTRG Software trigger
BEEVT External event
BCPC RC compare
BCPB RB compare
21
Timer/Counter 1 (TC1)
1753B–CASIC–02/02
•CPCS: RC Compare Status
There has been a RC Compare match at least once since the last read of the status
•COVFS: Counter Overflow
Counter has attempted to count past $FFFF since the last read of the status
•ETRGS: External Trigger
External trigger has been detected since the last read of the status
22 Timer/Counter 1 (TC1)
1753B–CASIC–02/02
TC1 User Interface
TC1_BCR (Block Control Register) and TC1_BMR (Block Mode Register) control the whole
TC1 block. TC1 channels are controlled by the registers listed in Table 3. The offset of each of
the channel registers in Table 3 is in relation to the offset of the corresponding channel as
mentioned in Table 2.
Notes: 1. Read only if WAVE = 0
2. If the user selects an address which is not defined in the above tables, the value of
P_D_OUT[31:0] is 0x00000000.
Table 2. Timer/Counter 1 Global Memory Map
Offset Channel/Register Name Access Reset State
0x00 TC1 Channel 0 See Table 3
0x40 TC1 Channel 1 See Table 3
0x80 TC1 Channel 2 See Table 3
0xC0 TC1 Block Control Register TC1_BCR Write-only –
0xC4 TC1 Block Mode Register TC1_BMR Read/write 0
Table 3. Timer/Counter 1 Channel Memory Map
Offset Register Name Access Reset State
0x00 Channel Control Register TC1_CCR Write-only –
0x04 Channel Mode Register TC1_CMR Read/write 0
0x08 Reserved –
0x0C Reserved –
0x10 Counter Value TC1_CV Read 0
0x14 Register A TC1_RA Read/write(1) 0
0x18 Register B TC1_RB Read/write(1) 0
0x1C Register C TC1_RC Read/write 0
0x20 Status Register TC1_SR Read-only –
0x24 Interrupt Enable Register TC1_IER Write-only –
0x28 Interrupt Disable Register TC1_IDR Write-only –
0x2C Interrupt Mask Register TC1_IMR Read-only 0
23
Timer/Counter 1 (TC1)
1753B–CASIC–02/02
TC1 Block Control Register
Register Name: TC1_BCR
Access Type: Write-only
•SYNC: Synchro Command
0=Noeffect.
1 = Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.
TC1 Block Mode Register
Register Name: TC1_BMR
Access Type: Read/write
•TC0XC0S: External Clock Signal 0 Selection
•TC1XC1S: External Clock Signal 1 Selection
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––––SYNC
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–– TC2XC2S TC1XC1S TC0XC0S
TC0XC0S Signal Connected to XC0
00TCLK0
0 1 none
10TIOA1
11TIOA2
TC1XC1S Signal Connected to XC1
00TCLK1
0 1 none
10TIOA0
11TIOA2
24 Timer/Counter 1 (TC1)
1753B–CASIC–02/02
•TC2XC2S: External Clock Signal 2 Selection
TC1 Channel Control Register
Register Name: TC1_CCR
Access Type: Write-only
•CLKEN: Counter Clock Enable Command
0=Noeffect.
1 = Enables the clock if CLKDIS is not 1.
•CLKDIS: Counter Clock Disable Command
0=Noeffect.
1 = Disables the clock.
•SWTRG: Software Trigger Command
0=Noeffect.
1 = A software trigger is performed: the counter is reset and clock is started.
TC2XC2S Signal Connected to XC2
00TCLK2
0 1 none
10TIOA0
11TIOA1
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
–––––SWTRG CLKDIS CLKEN
25
Timer/Counter 1 (TC1)
1753B–CASIC–02/02
TC1 Channel Mode Register: Capture Mode
Register Name: TC1_CMR
Access Type: Read/write
•TCCLKS: Clock Selection
•CLKI: Clock Invert
0 = Counter is incremented on rising edge of the clock.
1 = Counter is incremented on falling edge of the clock.
•BURST: Burst Signal Selection
•LDBSTOP: Counter Clock Stopped with RB Loading
0 = Counter clock is not stopped when RB loading occurs.
1 = Counter clock is stopped when RB loading occurs.
•LDBDIS: Counter Clock Disable with RB Loading
0 = Counter clock is not disabled when RB loading occurs.
1 = Counter clock is disabled when RB loading occurs.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––– LDRB LDRA
15 14 13 12 11 10 9 8
WAVE = 0 CPCTRG –––ABETRG ETRGEDG
76543210
LDBDIS LDBSTOP BURST CLKI TCCLKS
TCCLKS Clock Selected
0 0 0 TIMER_DIV1_CLOCK
0 0 1 TIMER_DIV2_CLOCK
0 1 0 TIMER_DIV3_CLOCK
0 1 1 TIMER_DIV4_CLOCK
1 0 0 TIMER_DIV5_CLOCK
101XC0
110XC1
111XC2
BURST
0 0 The clock is not gated by an external signal.
0 1 XC0 is ANDed with the selected clock.
1 0 XC1 is ANDed with the selected clock.
1 1 XC2 is ANDed with the selected clock.
26 Timer/Counter 1 (TC1)
1753B–CASIC–02/02
•ETRGEDG: External Trigger Edge Selection
•ABETRG: TIOA or TIOB External Trigger Selection
0 = TIOB is used as an external trigger.
1 = TIOA is used as an external trigger.
•CPCTRG: RC Compare Trigger Enable
0 = RC Compare has no effect on the counter and its clock.
1 = RC Compare resets the counter and starts the counter clock.
•WAVE
0 = Capture Mode is enabled.
1 = Capture Mode is disabled (Waveform Mode is enabled).
•LDRA: RA Loading Selection
•LDRB: RB Loading Selection
ETRGEDG Edge
0 0 none
0 1 rising edge
1 0 falling edge
1 1 each edge
LDRA Edge
0 0 none
0 1 rising edge of TIOA
1 0 falling edge of TIOA
1 1 each edge of TIOA
LDRB Edge
0 0 none
0 1 rising edge of TIOA
1 0 falling edge of TIOA
1 1 each edge of TIOA
27
Timer/Counter 1 (TC1)
1753B–CASIC–02/02
TC1 Channel Mode Register: Waveform Mode
Register Name: TC1_CMR
Access Type: Read/write
•TCCLKS: Clock Selection
•CLKI: Clock Invert
0 = Counter is incremented on rising edge of the clock.
1 = Counter is incremented on falling edge of the clock.
•BURST: Burst Signal Selection
•CPCSTOP: Counter Clock Stopped with RC Compare
0 = Counter clock is not stopped when counter reaches RC.
1 = Counter clock is stopped when counter reaches RC.
•CPCDIS: Counter Clock Disable with RC Compare
0 = Counter clock is not disabled when counter reaches RC.
1 = Counter clock is disabled when counter reaches RC.
31 30 29 28 27 26 25 24
BSWTRG BEEVT BCPC BCPB
23 22 21 20 19 18 17 16
ASWTRG AEEVT ACPC ACPA
15 14 13 12 11 10 9 8
WAVE = 1 WAVSEL ENETRG EEVT EEVTEDG
76543210
CPCDIS CPCSTOP BURST CLKI TCCLKS
TCCLKS Clock Selected
0 0 0 TIMER_DIV1_CLOCK
0 0 1 TIMER_DIV2_CLOCK
0 1 0 TIMER_DIV3_CLOCK
0 1 1 TIMER_DIV4_CLOCK
1 0 0 TIMER_DIV5_CLOCK
101XC0
110XC1
111XC2
BURST
0 0 The clock is not gated by an external signal.
0 1 XC0 is ANDed with the selected clock.
1 0 XC1 is ANDed with the selected clock.
1 1 XC2 is ANDed with the selected clock.
28 Timer/Counter 1 (TC1)
1753B–CASIC–02/02
•EEVTEDG: External Event Edge Selection
•EEVT: External Event Selection
Note: 1.
If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms
.
•ENETRG: External Event Trigger Enable
0 = The external event has no effect on the counter and its clock. In this case, the selected external event only controls the
TIOA output.
1 = The external event resets the counter and starts the counter clock.
•WAVSEL: Waveform Selection
•WAVE = 1
0 = Waveform Mode is disabled (Capture Mode is enabled).
1 = Waveform Mode is enabled.
•ACPA: RA Compare Effect on TIOA
•ACPC: RC Compare Effect on TIOA
EEVTEDG Edge
0 0 none
0 1 rising edge
1 0 falling edge
1 1 each edge
EEVT Signal selected as external event TIOB Direction
0 0 TIOB input(1)
0 1 XC0 output
1 0 XC1 output
1 1 XC2 output
WAVSEL Effect
0 0 UP mode without automatic trigger on RC Compare
1 0 UP mode with automatic trigger on RC Compare
0 1 UPDOWN mode without automatic trigger on RC Compare
1 1 UPDOWN mode with automatic trigger on RC Compare
ACPA Effect
0 0 none
01set
1 0 clear
11toggle
ACPC Effect
0 0 none
01set
1 0 clear
11toggle
29
Timer/Counter 1 (TC1)
1753B–CASIC–02/02
•AEEVT: External Event Effect on TIOA
•ASWTRG: Software Trigger Effect on TIOA
•BCPB: RB Compare Effect on TIOB
•BCPC: RC Compare Effect on TIOB
•BEEVT: External Event Effect on TIOB
•BSWTRG: Software Trigger Effect on TIOB
AEEVT Effect
0 0 none
01set
1 0 clear
11toggle
ASWTRG Effect
0 0 none
01set
1 0 clear
11toggle
BCPB Effect
0 0 none
01set
1 0 clear
11toggle
BCPC Effect
0 0 none
01set
1 0 clear
11toggle
BEEVT Effect
0 0 none
01set
1 0 clear
11toggle
BSWTRG Effect
0 0 none
01set
1 0 clear
11toggle
30 Timer/Counter 1 (TC1)
1753B–CASIC–02/02
TC1 Counter Value Register
Register Name: TC1_CV
Access Type: Read-only
•CV: Counter Value
CV contains the counter value in real time.
TC1 Register A
Register Name: TC1_RA
Access Type: Read-only if WAVE = 0, Read/write if WAVE = 1
•RA: Register A
RA contains the Register A value in real time.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
CV
76543210
CV
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
RA
76543210
RA
31
Timer/Counter 1 (TC1)
1753B–CASIC–02/02
TC1 Register B
Register Name: TC1_RB
Access Type: Read-only if WAVE = 0, Read/write if WAVE = 1
•RB: Register B
RB contains the Register B value in real time.
TC1 Register C
Register Name: TC1_RC
Access Type: Read/write
•RC: Register C
RC contains the Register C value in real time.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
RB
76543210
RB
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
RC
76543210
RC
32 Timer/Counter 1 (TC1)
1753B–CASIC–02/02
TC1StatusRegister
Register Name: TC1_SR
Access Type: Read/write
•COVFS: Counter Overflow Status
0 = No counter overflow has occurred since the last read of the Status Register.
1 = A counter overflow has occurred since the last read of the Status Register.
•LOVRS: Load Overrun Status
0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1.
1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Sta-
tus Register, if WAVE = 0.
•CPAS: RA Compare Status
0 = RA Compare has not occurred since the last read of the Status Register or WAVE = 0.
1 = RA Compare has occurred since the last read of the Status Register, if WAVE = 1.
•CPBS: RB Compare Status
0 = RB Compare has not occurred since the last read of the Status Register or WAVE = 0.
1 = RB Compare has occurred since the last read of the Status Register, if WAVE = 1.
•CPCS: RC Compare Status
0 = RC Compare has not occurred since the last read of the Status Register.
1 = RC Compare has occurred since the last read of the Status Register.
•LDRAS: RA Loading Status
0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1.
1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0.
•LDRBS: RB Loading Status
0 = RB Load has not occurred since the last read of the Status Register or WAVE = 1.
1 = RB Load has occurred since the last read of the Status Register, if WAVE = 0.
•ETRGS: External Trigger Status
0 = External trigger has not occurred since the last read of the Status Register.
1 = External trigger has occurred since the last read of the Status Register.
•CLKSTA: Clock Enabling Status
0 = Clock is disabled.
1 = Clock is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––––MTIOB MTIOA CLKSTA
15 14 13 12 11 10 9 8
––––––––
76543210
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS
33
Timer/Counter 1 (TC1)
1753B–CASIC–02/02
•MTIOA: TIOA Mirror
0 = TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low.
1 = TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high.
•MTIOB: TIOB Mirror
0 = TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low.
1 = TIOB is high. If WAVE = 0, this means that TIOB pin is high. If WAVE = 1, this means that TIOB is driven high.
TC1 Interrupt Enable Register
Register Name: TC1_IER
Access Type: Write-only
•COVFS: Counter Overflow
0=Noeffect.
1 = Enables the Counter Overflow Interrupt.
•LOVRS: Load Overrun
0=Noeffect.
1 = Enables the Load Overrun Interrupt.
•CPAS: RA Compare
0=Noeffect.
1 = Enables the RA Compare Interrupt.
•CPBS: RB Compare
0=Noeffect.
1 = Enables the RB Compare Interrupt.
•CPCS: RC Compare
0=Noeffect.
1 = Enables the RC Compare Interrupt.
•LDRAS: RA Loading
0=Noeffect.
1 = Enables the RA Load Interrupt.
•LDRBS: RB Loading
0=Noeffect.
1 = Enables the RB Load Interrupt.
•ETRGS: External Trigger
0=Noeffect.
1 = Enables the External Trigger Interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS
34 Timer/Counter 1 (TC1)
1753B–CASIC–02/02
TC1 Interrupt Disable Register
Register Name: TC1_IDR
Access Type: Write-only
•COVFS: Counter Overflow
0=Noeffect.
1 = Disables the Counter Overflow Interrupt.
•LOVRS: Load Overrun
0=Noeffect.
1 = Disables the Load Overrun Interrupt (if WAVE = 0).
•CPAS: RA Compare
0=Noeffect.
1 = Disables the RA Compare Interrupt (if WAVE = 1).
•CPBS: RB Compare
0=Noeffect.
1 = Disables the RB Compare Interrupt (if WAVE = 1).
•CPCS: RC Compare
0=Noeffect.
1 = Disables the RC Compare Interrupt.
•LDRAS: RA Loading
0=Noeffect.
1 = Disables the RA Load Interrupt (if WAVE = 0).
•LDRBS: RB Loading
0=Noeffect.
1 = Disables the RB Load Interrupt (if WAVE = 0).
•ETRGS: External Trigger
0=Noeffect.
1 = Disables the External Trigger Interrupt.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS
35
Timer/Counter 1 (TC1)
1753B–CASIC–02/02
TC1 Interrupt Mask Register
Register Name: TC1_IMR
Access Type: Read-only
•COVFS: Counter Overflow
0 = The Counter Overflow Interrupt is disabled.
1 = The Counter Overflow Interrupt is enabled.
•LOVRS: Load Overrun
0 = The Load Overrun Interrupt is disabled.
1 = The Load Overrun Interrupt is enabled.
•CPAS: RA Compare
0 = The RA Compare Interrupt is disabled.
1 = The RA Compare Interrupt is enabled.
•CPBS: RB Compare
0 = The RB Compare Interrupt is disabled.
1 = The RB Compare Interrupt is enabled.
•CPCS: RC Compare
0 = The RC Compare Interrupt is disabled.
1 = The RC Compare Interrupt is enabled.
•LDRAS: RA Loading
0 = The Load RA Interrupt is disabled.
1 = The Load RA Interrupt is enabled.
•LDRBS: RB Loading
0 = The Load RB Interrupt is disabled.
1 = The Load RB Interrupt is enabled.
•ETRGS: External Trigger
0 = The External Trigger Interrupt is disabled.
1 = The External Trigger Interrupt is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS
Printed on recycled paper.
© Atmel Corporation 2002.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
whichisdetailedinAtmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.
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1753B–CASIC–02/02 0M
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