SLLS177H − MARCH 1994 − REVISED JANUARY 2006
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DProgrammable Auto-RTS and Auto-CTS
DIn Auto-CTS Mode, CTS Controls
Transmitter
DIn Auto-RTS Mode, RCV FIFO Contents and
Threshold Control RTS
DSerial and Modem Control Outputs Drive a
RJ11 Cable Directly When Equipment Is on
the Same Power Drop
DCapable of Running With All Existing
TL16C450 Software
DAfter Reset, All Registers Are Identical to
the TL16C450 Register Set
DUp to 16-MHz Clock Rate for up to 1-Mbaud
Operation
DIn the TL16C450 Mode, Hold and Shift
Registers Eliminate the Need for Precise
Synchronization Between the CPU and
Serial Data
DProgrammable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1
to (216 −1) and Generates an Internal 16×
Clock
DStandard Asynchronous Communication
Bits (Start, Stop, and Parity) Added to or
Deleted From the Serial Data Stream
D5-V and 3.3-V Operation
DIndependent Receiver Clock Input
DTransmit, Receive, Line Status, and Data
Set Interrupts Independently Controlled
DFully Programmable Serial Interface
Characteristics:
− 5-, 6-, 7-, or 8-Bit Characters
− Even-, Odd-, or No-Parity Bit Generation
and Detection
− 1-, 1 1/2-, or 2-Stop Bit Generation
− Baud Generation (dc to 1 Mbit/s)
DFalse-Start Bit Detection
DComplete Status Reporting Capabilities
D3-State Output TTL Drive Capabilities for
Bidirectional Data Bus and Control Bus
DLine Break Generation and Detection
DInternal Diagnostic Capabilities:
− Loopback Controls for Communications
Link Fault Isolation
− Break, Parity, Overrun, and Framing
Error Simulation
DFully Prioritized Interrupt System Controls
DModem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)
description
The TL16C550C and the TL16C550CI are functional upgrades of the TL16C550B asynchronous
communications element (ACE), which in turn is a functional upgrade of the TL16C450. Functionally equivalent
to the TL16C450 on power up (character or TL16C450 mode), the TL16C550C and the TL16C550CI, like the
TL16C550B, can be placed in an alternate FIFO mode. This relieves the CPU of excessive software overhead
by buffering received and transmitted characters. The receiver and transmitter FIFOs store up to 16 bytes
including three additional bits of error status per byte for the receiver FIFO. In the FIFO mode, there is a
selectable autoflow control feature that can significantly reduce software overload and increase system
efficiency by automatically controlling serial data flow using RTS output and CTS input signals.
The TL16C550C and TL16C550CI perform serial-to-parallel conversions on data received from a peripheral
device or modem and parallel-to-serial conversion on data received from its CPU. The CPU can read the ACE
status at any time. The ACE includes complete modem control capability and a processor interrupt system that
can be tailored to minimize software management of the communications link.
Both the TL16C550C and the TL16C550CI ACE include a programmable baud rate generator capable of
dividing a reference clock by divisors from 1 to 65535 and producing a 16× reference clock for the internal
transmitter logic. Provisions are included to use this 16× clock for the receiver logic. The ACE accommodates
a 1-Mbaud serial rate (16-MHz input clock) so that a bit time is 1 µs and a typical character time is 10 µs (start
bit, 8 data bits, stop bit).
Two of the TL16C450 terminal functions on the TL16C550C and the TL16C550CI have been changed to
TXRDY and RXRDY, which provide signaling to a DMA controller.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
! " #$%! " &$'(#! )!%*
)$#!" # ! "&%##!" &% !+% !%" %," "!$%!"
"!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)%
!%"!/ (( &%!%"*
Copyright 1994 − 2006, Texas Instruments Incorporated
SLLS177H − MARCH 1994 − REVISED JANUARY 2006
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D0
D1
D2
D3
D4
D5
D6
D7
RCLK
SIN
SOUT
CS0
CS1
CS2
BAUDOUT
XIN
XOUT
WR1
WR2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
RI
DCD
DSR
CTS
MR
OUT1
DTR
RTS
OUT2
INTRPT
RXRDY
A0
A1
A2
ADS
TXRDY
DDIS
RD2
RD1
N PACKAGE
(TOP VIEW)
MR
OUT1
DTR
RTS
OUT2
NC
INTRPT
RXRDY
A0
A1
A2
39
38
37
36
35
34
33
32
31
30
29
1819
7
8
9
10
11
12
13
14
15
16
17
D5
D6
D7
RCLK
SIN
NC
SOUT
CS0
CS1
CS2
BAUDOUT 20 21 22 23
RI
DCD
DSR
CTS
54 321644
D4
D3
D2
D1
D0
NC
V
RD2
DDIS
TXRDY
ADS
XIN
XOUT
WR1
WR2
NC
RD1
42 41 4043
24 25 26 27 28
NC−No internal connection
CC
VSS
FN PACKAGE
(TOP VIEW)
14 15
NC
MR
OUT1
DTR
RTS
OUT2
INTRPT
RXRDY
A0
A1
A2
NC
36
35
34
33
32
31
30
29
28
27
26
25
16
1
2
3
4
5
6
7
8
9
10
11
12
NC
D5
D6
D7
RCLK
NC
SIN
SOUT
CS0
CS1
CS2
BAUDOUT
17 18 19 20
PT/PFB PACKAGE
(TOP VIEW)
RI
DCD
DSR
CTS
47 46 45 44 4348 42
NC
D4
D3
D2
D1
D0
DDIS
TXRDY
ADS
XOUT
WR1
WR2
RD1
RD2
NC
40 39 3841
21 22 23 24
37
13
NC
NC
VCC
XIN
VSS
NOTE: 40-pin DIP (N package) will be
obsoleted as of 7/30/2006. Please
contact your local distributor or TI Sales
Office for more information.
SLLS177H − MARCH 1994 − REVISED JANUARY 2006
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description
autoflow control (see Figure 1)
Autoflow control is comprised of auto-CTS and auto-RTS. With auto-CTS, the CTS input must be active before
the transmitter FIFO can emit data. With auto-RTS, RTS becomes active when the receiver needs more data
and notifies the sending serial device. When RTS is connected to CTS, data transmission does not occur unless
the receiver FIFO has space for the data; thus, overrun errors are eliminated using ACE1 and ACE2 from a
TLC16C550C with the autoflow control enabled. If not, overrun errors occur when the transmit data rate exceeds
the receiver FIFO read latency.
RCV
FIFO
Serial to
Parallel
Flow
Control
XMT
FIFO
Parallel
to Serial
Flow
Control
Parallel
to Serial
Flow
Control
Serial to
Parallel
Flow
Control
XMT
FIFO
RCV
FIFO
ACE1 ACE2
D7−D0
SIN SOUT
RTS CTS
SOUT SIN
CTS RTS
D7−D0
Figure 1. Autoflow Control (Auto-RTS and Auto-CTS) Example
auto-RTS (see Figure 1)
Auto-RTS data flow control originates in the receiver timing and control block (see functional block diagram)
and is linked to the programmed receiver FIFO trigger level. When the receiver FIFO level reaches a trigger level
of 1, 4, or 8 (see Figure 3), RTS is deasserted. With trigger levels of 1, 4, and 8, the sending ACE may send
an additional byte after the trigger level is reached (assuming the sending ACE has another byte to send)
because it may not recognize the deassertion of RTS until after it has begun sending the additional byte. RTS
is automatically reasserted once the RCV FIFO is emptied by reading the receiver buffer register.
When the trigger level is 14 (see Figure 4), RTS is deasserted after the first data bit of the 16th character is
present on the SIN line. RTS is reasserted when the RCV FIFO has at least one available byte space.
auto-CTS (see Figure 1)
The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, it sends the next
byte. To stop the transmitter from sending the following byte, CTS must be released before the middle of the
last stop bit that is currently being sent (see Figure 2). The auto-CTS function reduces interrupts to the host
system. When flow control is enabled, CTS level changes do not trigger host interrupts because the device
automatically controls its own transmitter. Without auto-CTS, the transmitter sends any data present in the
transmit FIFO and a receiver overrun error may result.
enabling autoflow control and auto-CTS
Autoflow control is enabled by setting modem control register bits 5 (autoflow enable or AFE) and 1 (RTS) to
a 1. Autoflow incorporates both auto-RTS and auto-CTS. When only auto-CTS is desired, bit 1 in the modem
control register should be cleared (this assumes that a control signal is driving CTS).
SLLS177H − MARCH 1994 − REVISED JANUARY 2006
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
auto-CTS and auto-RTS functional timing
Start Bits 0−7 Start Bits 0−7 Start Bits 0−7
Stop Stop Stop
S
OUT
CTS
NOTES: A. When CTS is low, the transmitter keeps sending serial data out.
B. If CT S goes high before the middle of the last stop bit of the current byte, the transmitter finishes sending the current byte but it does
not send the next byte.
C. When CTS goes from high to low, the transmitter begins sending data again.
Figure 2. CTS Functional Timing Waveforms
The receiver FIFO trigger level can be set to 1, 4, 8, or 14 bytes. These are described in Figures 3 and 4.
Start Byte N Start Byte N+1 Start Byte
Stop Stop Stop
SIN
RTS
RD
(RD RBR) 12 N N+1
NOTES: A. N = RCV FIFO trigger level (1, 4, or 8 bytes)
B. The two blocks in dashed lines cover the case where an additional byte is sent as described in the preceding auto-RTS section.
Figure 3. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 1,4, or 8 Bytes
Byte 14 Byte 15
SIN
RTS
RD
(RD RBR)
Start Byte 18 StopStart Byte 16 Stop
RTS Released After the
First Data Bit of Byte 16
NOTES: A. RTS is deasserted when the receiver receives the first data bit of the sixteenth byte. The receive FIFO is full after finishing the
sixteenth byte.
B. RTS is asserted again when there is at least one byte of space available and no incoming byte is in processing or there is more th an
one byte of space available.
C. When the receive FIFO is full, the first receive buffer register read reasserts RTS.
Figure 4. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 14 Bytes
SLLS177H − MARCH 1994 − REVISED JANUARY 2006
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
Receiver
Buffer
Register
Divisor
Latch (LS)
Divisor
Latch (MS)
Baud
Generator
Receiver
FIFO
Line
Status
Register
Transmitter
Holding
Register
Modem
Control
Register
Modem
Status
Register
Line
Control
Register
Transmitter
FIFO
Interrupt
Enable
Register
Interrupt
Identification
Register
FIFO
Control
Register
Select
and
Control
Logic
Interrupt
Control
Logic
S
e
l
e
c
t
Data
Bus
Buffer
BAUDOU
T
SIN
RCLK
SOUT
CTS
DTR
DSR
DCD
RI
OUT1
OUT2
INTRP
T
A0
D(7−0)
Internal
Data Bus
A1
A2
CS0
CS1
CS2
ADS
MR
RD1
RD2
WR1
WR2
DDIS
TXRDY
XIN
XOUT
R
XRDY
S
e
l
e
c
t
Receiver
Shift
Register
Receiver
Timing and
Control
Transmitter
Timing and
Control
Transmitter
Shift
Register
Modem
Control
Logic
8
VCC
VSS Power
Supply
RTS
Autoflow
Control
(AFE)
8
8
8
8
8
8
8
SLLS177H − MARCH 1994 − REVISED JANUARY 2006
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME NO.
N†NO.
FN NO.
PT I/O DESCRIPTION
A0
A1
A2
28
27
26
31
30
29
28
27
26
IRegister select. A0−A2 are used during read and write operations to select the ACE register to read
from or write to. Refer to Table 1 for register addresses and refer to ADS description.
ADS 25 28 24 I Address strobe. When ADS is active (low), A0, A1, and A2 and CS0, CS1, and CS2 drive the internal
select logic directly; when ADS is high, the register select and chip select signals are held at the logic
levels they were in when the low-to-high transition of ADS occurred.
BAUDOUT 15 17 12 O Baud out. BAUDOUT is a 16× clock signal for the transmitter section of the ACE. The clock rate is
established by the reference oscillator frequency divided by a divisor specified by the baud generator
divisor latches. BAUDOUT may also be used for the receiver section by tying this output to RCLK.
CS0
CS1
CS2
12
13
14
14
15
16
9
10
11
I Chip select. When CS0 and CS1 are high and CS2 is lo w, these three inputs select the ACE. When any
of these inputs are inactive, the ACE remains inactive (refer to ADS description).
CTS 36 40 38 I Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of
the modem status register. Bit 0 (∆CTS) of the modem status register indicates that CTS has changed
states since the last read from the modem status register. If the modem status interrupt is enabled when
CTS changes levels and the auto-CTS mode is not enabled, an interrupt is generated. CTS is also used
in the auto-CTS mode to control the transmitter.
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
9
43
44
45
46
47
2
3
4
I/O Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, and status
information between the ACE and the CPU.
DCD 38 42 40 I Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD)
of the modem status register. Bit 3 (∆DCD) of the modem status register indicates that DCD has
changed states since the last read from the modem status register. If the modem status interrupt is
enabled when DCD changes levels, an interrupt is generated.
DDIS 23 26 22 O Driver disable. DDIS is active (high) when the CPU is not reading data. When active, DDIS can disable
an external transceiver.
DSR 37 41 39 I Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of
the modem status register. Bit 1 (∆DSR) of the modem status register indicates DSR has changed
levels since the last read from the modem status register. If the modem status interrupt is enabled when
DSR changes levels, an interrupt is generated.
DTR 33 37 33 O Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to
establish communication. DTR is placed in the active level by setting the DTR bit of the modem control
register. DTR is placed in the inactive level either as a result of a master reset, during loop mode
operation, or clearing the DTR bit.
INTRPT 30 33 30 O Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced.
Four conditions that cause an interrupt to be issued are: a receiver error, received data that is available
or timed out (FIFO mode only), an empty transmitter holding register, or an enabled modem status
interrupt. INTRPT is reset (deactivated) either when the interrupt is serviced or as a result of a master
reset.
MR 35 39 35 I Master reset. When active (high), MR clears most ACE registers and sets the levels of various output
signals (refer to Table 2).
The N package is Not Recommended for New Designs.
SLLS177H − MARCH 1994 − REVISED JANUARY 2006
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
NAME NO.
N†NO.
FN NO.
PT I/O DESCRIPTION
OUT1
OUT2 34
31 38
35 34
31 O Outputs 1 and 2. These are user-designated output terminals that are set to the active (low) level by
setting respective modem control register (MCR) bits (OUT1 and OUT2). OUT1 and OUT2 are set to
inactive the (high) level as a result of master reset, during loop mode operations, or by clearing bit 2
(OUT1) or bit 3 (OUT2) of the MCR.
RCLK 9 10 5 I Receiver clock. RCLK is the 16× baud rate clock for the receiver section of the ACE.
RD1
RD2 21
22 24
25 19
20 IRead inputs. When either RD1 or RD2 is active (low or high respectively) while the ACE is selected,
the CPU is allowed to read status information or data from a selected ACE register. Only one of these
inputs is required for the transfer of data during a read operation; the other input should be tied to its
inactive level (i.e., RD2 tied low or RD1 tied high).
RI 39 43 41 I Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the
modem status register. Bit 2 (TERI) of the modem status register indicates that RI has transitioned from
a low to a high level since the last read from the modem status register. If the modem status interrupt
is enabled when this transition occurs, an interrupt is generated.
RTS 32 36 32 O Request to send. When active, RTS informs the modem or data set that the ACE is ready to receive
data. RTS is set to the active level by setting the RTS modem control register bit and is set to the inactive
(high) level either as a result of a master reset or during loop mode operations or by clearing bit 1 (R TS)
of the MCR. In the auto-RTS mode, RTS is set to the inactive level by the receiver threshold control logic.
RXRDY 29 32 29 O Receiver ready. Receiver direct memory access (DMA) signalling is available with RXRDY. When
operating i n the FIFO mode, one of two types of DMA signalling can be selected using the FIFO control
register bit 3 (FCR3). When operating in the TL16C450 mode, only DMA mode 0 is allowed. Mode 0
supports single-transfer DMA in which a transfer is made between CPU bus cycles. Mode 1 supports
multitransfer DMA in which multiple transfers are made continuously until the receiver FIFO has been
emptied. In DMA mode 0 (FCR0 = 0 or FCR0 = 1, FCR3 = 0), when there is at least one character in
the receiver FIFO or receiver holding register, RXRDY is active (low). When RXRDY has been active
but there are no characters in the FIFO or holding register , RXRDY goes inactive (high). In DMA mode 1
(FCR0 = 1, FCR3 = 1), when the trigger level or the time-out has been reached, RXRDY goes active
(low); when it has been active but there are no more characters in the FIFO or holding register, it goes
inactive (high).
SIN 10 11 7 I Serial data input. SIN is serial data input from a connected communications device
SOUT 11 13 8 O Serial data output. SOUT is composite serial data output to a connected communication device. SOUT
is set to the marking (high) level as a result of master reset.
TXRDY 24 27 23 O Transmitter ready. Transmitter DMA signalling is available with TXRDY. When operating in the FIFO
mode, one of two types of DMA signalling can be selected using FCR3. When operating in the
TL16C450 mode, only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer
is made between CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple transfers are
made continuously until the transmit FIFO has been filled.
VCC 40 44 42 5-V supply voltage
VSS 20 22 18 Supply common
WR1
WR2 18
19 20
21 16
17 IWrite inputs. When either WR1 or WR2 is active (low or high respectively) and while the ACE is
selected, the CPU is allowed to write control words or data into a selected ACE register. Only one of
these inputs is required to transfer data during a write operation; the other input should be tied to its
inactive level (i.e., WR2 tied low or WR1 tied high).
XIN
XOUT 16
17 18
19 14
15 I/O External clock. XIN and XOUT connect the ACE to the main timing reference (clock or crystal).
The N package is Not Recommended for New Designs.
SLLS177H − MARCH 1994 − REVISED JANUARY 2006
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range at any input, VI −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA, TL16C550C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TL16C550CI −40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Case temperature for 10 seconds, TC: FN package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N† or PT package 260°C. . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The N package is Not Recommended for New Designs.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
low voltage (3.3 V nominal)
MIN NOM MAX UNIT
Supply voltage, VCC 3 3.3 3.6 V
Input voltage, VI0 VCC V
High-level input voltage, VIH (see Note 2) 0.7 VCC V
Low-level input voltage, VIL (see Note 2) 0.3 VCC V
Output voltage, VO (see Note 3) 0 VCC V
High-level output current, IOH (all outputs) 1.8 mA
Low-level output current, IOL (all outputs) 3.2 mA
Input capacitance 1 pF
Operating free-air temperature, TA0 25 70 °C
Junction temperature range, TJ (see Note 4) 0 25 115 °C
Oscillator/clock speed 14.9 MHz
NOTES: 2. Meets TTL levels, VIHmin = 2 V and VILmax = 0.8 V on nonhysteresis inputs
3. Applies for external output buffers
4. These junction temperatures reflect simulated conditions. Absolute maximum junction temperature is 150°C. The customer is
responsible for verifying junction temperature.
standard voltage (5 V nominal)
MIN NOM MAX UNIT
Supply voltage, VCC 4.75 5 5.25 V
Input voltage, VI0 VCC V
High-level input voltage, VIH
Except XIN 2
V
High-level input voltage, VIH XIN 0.7 VCC V
Low-level input voltage, VIL
Except XIN 0.8
V
Low-level input voltage, VIL XIN 0.3 VCC V
Output voltage, VO (see Note 5) 0 VCC V
High-level output current, IOH (all outputs) 4 mA
Low-level output current, IOL (all outputs) 4 mA
Input capacitance 1 pF
Operating free-air temperature, TA0 25 70 °C
NOTE 5: Applies for external output buffers
SLLS177H − MARCH 1994 − REVISED JANUARY 2006
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
standard voltage (5 V nominal) (continued)
MIN NOM MAX UNIT
Junction temperature range, TJ
(see Note 6) 0 25 115 °C
Oscillator/clock speed 16 MHz
NOTE 6: These junction temperatures reflect simulated conditions. Absolute maximum junction temperature is 150°C. The customer is
responsible for verifying junction temperature.
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
low voltage (3.3 V nominal)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VOH‡High-level output voltage IOH = −1 mA 2.4 V
VOL‡Low-level output voltage IOL = 1.6 mA 0.5 V
Il
Input current
VCC = 3.6 V,
VSS = 0,
10
A
IlInput current
VCC = 3.6 V,
VI = 0 to 3.6 V,
VSS = 0,
All other terminals floating 10 µA
VCC = 3.6 V, VSS = 0,
IOZ
High-impedance-state output current
VCC = 3.6 V, VSS = 0,
V
O
= 0 to 3.6 V, ±
20
µA
IOZ
High-impedance-state output current
VO = 0 to 3.6 V,
Chip selected in write mode or chip deselect
±20
µA
VCC = 3.6 V, TA = 25
°
C,
V
CC
= 3.6 V, T
A
= 25
°
C,
SIN, DSR, DCD, CTS, and RI at 2 V,
ICC
Supply current
CC A
SIN, DSR, DCD, CTS, and RI at 2 V,
All other inputs at 0.8 V, XTAL1 at 4 MHz,
8
mA
ICC
Supply current
SIN, DSR, DCD, CTS, and RI at 2 V,
All other inputs at 0.8 V, XTAL1 at 4 MHz,
No load on outputs, Baud rate = 50 kbit/s
8
mA
All other inputs at 0.8 V, XTAL1 at 4 MHz,
No load on outputs, Baud rate = 50 kbit/s
Ci(CLK) Clock input capacitance
V = 0, V = 0,
15 20 pF
Co(CLK) Clock output capacitance VCC = 0, VSS = 0,
f = 1 MHz, TA = 25°C,
20 30 pF
CiInput capacitance
CC SS
f = 1 MHz, T
A
= 25
°
C,
All other terminals grounded
6 10 pF
CoOutput capacitance
All other terminals grounded
10 20 pF
†All typical values are at VCC = 3.3 V and TA = 25°C.
‡These parameters apply for all outputs except XOUT.
standard voltage (5 V nominal)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VOH‡High-level output voltage IOH = −1 mA 2.4 V
VOL‡Low-level output voltage IOL = 1.6 mA 0.4 V
Il
Input current
VCC = 5.25 V,
VSS = 0,
10
A
IlInput current
VCC = 5.25 V,
VI = 0 to 5.25 V,
VSS = 0,
All other terminals floating 10 µA
VCC = 5.25 V, VSS = 0,
IOZ
High-impedance-state output current
VCC = 5.25 V, VSS = 0,
V
O
= 0 to 5.25 V, ±
20
µA
IOZ
High-impedance-state output current
VO = 0 to 5.25 V,
Chip selected in write mode or chip deselect
±20
µA
VCC = 5.25 V, TA = 25
°
C,
V
CC
= 5.25 V, T
A
= 25
°
C,
SIN, DSR, DCD, CTS, and RI at 2 V,
ICC
Supply current
CC A
SIN, DSR, DCD, CTS, and RI at 2 V,
All other inputs at 0.8 V, XTAL1 at 4 MHz,
10
mA
ICC
Supply current
SIN, DSR, DCD, CTS, and RI at 2 V,
All other inputs at 0.8 V, XTAL1 at 4 MHz,
No load on outputs, Baud rate = 50 kbit/s
10
mA
All other inputs at 0.8 V, XTAL1 at 4 MHz,
No load on outputs, Baud rate = 50 kbit/s
Ci(CLK) Clock input capacitance
V = 0, V = 0,
15 20 pF
Co(CLK) Clock output capacitance VCC = 0, VSS = 0,
f = 1 MHz, TA = 25°C,
20 30 pF
CiInput capacitance
CC SS
f = 1 MHz, T
A
= 25
°
C,
All other terminals grounded
6 10 pF
CoOutput capacitance
All other terminals grounded
10 20 pF
†All typical values are at VCC = 5 V and TA = 25°C.
‡These parameters apply for all outputs except XOUT.
SLLS177H − MARCH 1994 − REVISED JANUARY 2006
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
system timing requirements over recommended ranges of supply voltage and operating free-air
temperature
ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT
tcR Cycle time, read (tw7 + td8 + td9) RC 87 ns
tcW Cycle time, write (tw6 + td5 + td6) WC 87 ns
tw1 Pulse duration, clock high tXH
5
f = 16 MHz Max,
V = 5 V
25
ns
tw2 Pulse duration, clock low tXL 5
f = 16 MHz Max,
VCC = 5 V 25 ns
tw5 Pulse duration, ADS low tADS 6, 7 9 ns
tw6 Pulse duration, WR tWR 6 40 ns
tw7 Pulse duration, RD tRD 7 40 ns
tw8 Pulse duration, MR tMR 1µs
tsu1 Setup time, address valid before ADS↑tAS
6, 7
8
ns
tsu2 Setup time, CS valid before ADS↑tCS 6, 7 8 ns
tsu3 Setup time, data valid before WR1↑ or WR2↓tDS 6 15 ns
tsu4 Setup time, CTS↑ before midpoint of stop bit 17 10 ns
th1 Hold time, address low after ADS↑tAH
6, 7
0
ns
th2 Hold time, CS valid after ADS↑tCH 6, 7 0 ns
th3 Hold time, CS valid after WR1↑ or WR2↓tWCS
6
10
ns
th4 Hold time, address valid after WR1↑ or WR2↓tWA 6 10 ns
th5 Hold time, data valid after WR1↑ or WR2↓tDH 6 5 ns
th6 Hold time, chip select valid after RD1↑ or RD2↓tRCS 7 10 ns
th7 Hold time, address valid after RD1↑ or RD2↓tRA 7 20 ns
td4†Delay time, CS valid before WR1↓ or WR2↑tCSW
6
7
ns
td5†Delay time, address valid before WR1↓ or WR2↑tAW 6 7 ns
td6†Delay time, write cycle, WR1↑ or WR2↓to ADS↓tWC 6 40 ns
td7†Delay time, CS valid to RD1↓ or RD2↑tCSR
7
7
ns
td8†Delay time, address valid to RD1↓ or RD2↑tAR 7 7 ns
td9 Delay time, read cycle, RD1↑ or RD2↓to ADS↓tRC 7 40 ns
td10 Delay time, RD1↓ or RD2↑to data valid tRVD 7 CL = 75 pF 45 ns
td11 Delay time, RD1↑ or RD2↓to floating data tHZ 7 CL = 75 pF 20 ns
†Only applies when ADS is low
system switching characteristics over recommended ranges of supply voltage and operating
free-air temperature (see Note 7)
PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT
tdis(R) Disable time, RD1↓↑ or RD2↑↓ to DDIS↑↓ tRDD 7 CL = 75 pF 20 ns
NOTE 7: Charge and discharge times are determined by VOL, VOH, and external loading.
baud generator switching characteristics over recommended ranges of supply voltage and
operating free-air temperature, CL = 75 pF
PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT
tw3 Pulse duration, BAUDOUT low tLW 5
f = 16 MHz, CLK
÷
2,
V = 5 V
50
ns
tw4 Pulse duration, BAUDOUT high tHW 5
f = 16 MHz, CLK ÷ 2,
VCC = 5 V 50 ns
td1 Delay time, XIN↑ to BAUDOUT↑tBLD 5 45 ns
td2 Delay time, XIN↑↓ to BAUDOUT↓tBHD 5 45 ns
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11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
receiver switching characteristics over recommended ranges of supply voltage and operating
free-air temperature (see Note 8)
PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT
td12 Delay time, RCLK to sample tSCD 8 10 ns
td13 Delay time, stop to set INTRPT or read
RBR to LSI interrupt or stop to RXRDY↓tSINT 8, 9, 10,
11, 12 1RCLK
cycle
td14 Delay time, read RBR/LSR to reset INTRPT tRINT 8, 9, 10,
11, 12 CL = 75 pF 70 ns
NOTE 8: In the FIFO mode, the read cycle (RC) = 425 ns (min) between reads of the receive FIFO and the status registers (interrupt identification
register or line status register).
transmitter switching characteristics over recommended ranges of supply voltage and operating
free-air temperature
PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT
td15 Delay time, initial write to transmit start tIRS 13 8 24 baudout
cycles
td16 Delay time, start to INTRPT tSTI 13 8 10 baudout
cycles
td17 Delay time, WR (WR THR) to reset INTRPT tHR 13 CL = 75 pF 50 ns
td18 Delay time, initial write to INTRPT (THRE†) tSI 13 16 34 baudout
cycles
td19 Delay time, read IIR† to reset INTRPT
(THRE†)tIR 13 CL = 75 pF 35 ns
td20 Delay time, write to TXRDY inactive tWXI 14,15 CL = 75 pF 35 ns
td21 Delay time, start to TXRDY active tSXA 14,15 CL = 75 pF 9baudout
cycles
†THRE = transmitter holding register empty; IIR = interrupt identification register.
modem control switching characteristics over recommended ranges of supply voltage and
operating free-air temperature, CL = 75 pF
PARAMETER ALT. SYMBOL FIGURE MIN MAX UNIT
td22 Delay time, WR MCR to output tMDO 16 50 ns
td23 Delay time, modem interrupt to set INTRPT tSIM 16 35 ns
td24 Delay time, RD MSR to reset INTRPT tRIM 16 40 ns
td25 Delay time, CTS low to SOUT↓17 24 baudout
cycles
td26 Delay time, RCV threshold byte to RTS↑18 2 baudout
cycles
td27 Delay time, read of last byte in receive FIFO to RTS↓18 2 baudout
cycles
td28 Delay time, first data bit of 16th character to RTS↑19 2 baudout
cycles
td29 Delay time, RBRRD low to RTS↓19 2 baudout
cycles
SLLS177H − MARCH 1994 − REVISED JANUARY 2006
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
BAUDOUT
(1/1)
XIN
BAUDOUT
(1/2)
BAUDOUT
(1/3)
BAUDOUT
(1/N)
(N > 3) 2 XIN Cycles (N−2) XIN Cycles
tw3 tw4
td2
td1 td2
N
tw1 tw2
td1
Figure 5. Baud Generator Timing Waveforms
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PARAMETER MEASUREMENT INFORMATION
ADS
tw5
th1
tsu1
th2
tsu2
tsu3 th5
th3
tw6
td4
td5 td6
th4†
Valid Data
Valid Valid†
Valid Valid†
Active
A0−A2
CS0, CS1, CS2
WR1, WR2
D7−D0
50%50%
50% 50%50%
50% 50%
50% 50%
50%
†Applicable only when ADS is low
Figure 6. Write Cycle Timing Waveforms
SLLS177H − MARCH 1994 − REVISED JANUARY 2006
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
ADS
tw5
th1
tsu1
th2
tsu2
td10 td11
th6
tw7
td7†
td8†td9
th7†
Valid Data
Valid Valid†
Valid Valid†
Active
A0−A2
CS0, CS1, CS2
RD1, RD2
D7−D0
tdis(R)
tdis(R)
DDIS
50%50% 50%
50%
50%
50% 50%
50% 50%
50% 50%
50% 50%
†Applicable only when ADS is low
Figure 7. Read Cycle Timing Waveforms
SLLS177H − MARCH 1994 − REVISED JANUARY 2006
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
td13
Active
Active
RD1, RD2
(read RBR)
RCLK
td14
td14
8 CLKs td12
Parity StopStart Data Bits 5−8
Sample Clock
TL16C450 Mode:
Sample Clock
SIN
INTRPT
(data ready)
INTRPT
(RCV error)
RD1, RD2
(read LSR)
50%50%
50%
50% 50%
50%
Figure 8. Receiver Timing Waveforms
SLLS177H − MARCH 1994 − REVISED JANUARY 2006
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
td13
(see Note A) td14
Stop
Data Bits 5−8
Sample Clock
SIN
Trigger Level
INTRPT
(FCR6, 7 = 0, 0)
INTRPT
Line Status
Interrupt (LSI) td14
RD1
(RD LSR)
RD1
(RD RBR)
Active
Active
(FIFO at or above
trigger level)
(FIFO below
trigger level)
50%50%
50%
50%
50% 50%
NOTE A: For a time-out interrupt, td13 = 9 RCLKs.
Figure 9. Receive FIFO First Byte (Sets DR Bit) Waveforms
td13
(see Note A) td14
Stop
Top Byte of FIFO
Sample Clock
SIN
Time-Out or
Trigger Level
Interrupt
Line Status
Interrupt (LSI)
td13
(FIFO at or above
trigger level)
(FIFO below
trigger level)
RD1, RD2
(RD LSR)
RD1, RD2
(RD RBR) Active Active
td14
Previous Byte
Read From FIFO
50%
50%
50%50%
50%
50% 50%
NOTE A: For a time-out interrupt, td13 = 9 RCLKs.
Figure 10. Receive FIFO Bytes Other Than the First Byte (DR Internal Bit Already Set) Waveforms
SLLS177H − MARCH 1994 − REVISED JANUARY 2006
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
td13
(see Note B) td14
Stop
Sample Clock
SIN
(first byte)
Active
RD
(RD RBR)
RXRDY
See Note A
50%
50%
50%
NOTE A: This is the reading of the last byte in the FIFO.
Figure 11. Receiver Ready (RXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0)
td13
(see Note B) td14
Sample Clock
SIN
(first byte that reaches
the trigger level)
Active
RD
(RD RBR)
RXRDY
See Note A
50%
50%50%
NOTES: A. This is the reading of the last byte in the FIFO.
B. For a time-out interrupt, td13 = 9 RCLKs.
Figure 12. Receiver Ready (RXRDY) Waveforms, FCR0 = 1 and FCR3 = 1 (Mode 1)
SLLS177H − MARCH 1994 − REVISED JANUARY 2006
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
td16
Parity Stop
Start Data Bits
SOUT Start
td15
td17 td17
td18
td19
INTRPT
(THRE)
WR
(WR THR)
RD IIR
50% 50% 50% 50% 50%
50%
50%
50%
50%
50%
50%
Figure 13. Transmitter Timing Waveforms
td20
WR
(WR THR)
td21
Parity Stop
Data Start
Byte #1
SOUT
TXRDY
50%
50%
50%
50%
Figure 14. Transmitter Ready (TXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0)
WR
(WR THR)
Parity Stop
Data Start
Byte #16
SOUT
TXRDY FIFO Full
td20 td21
50%
50%
50%
50%
Figure 15. Transmitter Ready (TXRDY) Waveforms, FCR0 = 1 and FCR3 = 1 (Mode 1)
SLLS177H − MARCH 1994 − REVISED JANUARY 2006
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
td22 td22
WR
(WR MCR)
RTS, DTR,
OUT1, OUT2
CTS, DSR, DCD
td23
td24
td23
INTRPT
(modem)
RD2
(RD MSR)
RI
50% 50%
50% 50%
50%
50% 50%
50%
50%
50%
Figure 16. Modem Control Timing Waveforms
Midpoint of Stop Bit
td25
tsu4
CTS
SOUT
50% 50%
50%
Figure 17. CTS and SOUT Autoflow Control Timing (Start and Stop) Waveforms
td27
SIN
50%
td26
50%
50%
Midpoint of Stop Bit
RTS
RBRRD
Figure 18. Auto-RTS Timing for RCV Threshold of 1, 4, or 8 Waveforms
SLLS177H − MARCH 1994 − REVISED JANUARY 2006
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
td29
SIN
50%
td28
50%
50%
Midpoint of Data Bit 0
RTS
RBRRD
15th Character 16th Character
Figure 19. Auto-RTS Timing for RCV Threshold of 14 Waveforms
APPLICATION INFORMATION
D7−D0
MEMR or I/OR
MEMW or I/ON
INTR
RESET
A0
A1
A2
CS L
H
EIA
232-D Drivers
and Receivers
XOUT
XIN
RCLK
BAUDOUT
RI
CTS
DCD
DSR
DTR
RTS
SOUT
SIN
INTRPT
D7−D0
RD1
WR1
MR
A0
A1
A2
ADS
WR2
RD2
CS2
CS1
CS0
TL16C550C
(ACE)
3.072 MHz
C
P
U
B
u
s
Figure 20. Basic TL16C550C Configuration
SLLS177H − MARCH 1994 − REVISED JANUARY 2006
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Receiver Disable
Microcomputer
System Data Bus Data Bus
Driver Disable
8-Bit
Bus Transceiver
WR WR1
D7−D0
DDIS
TL16C550C
(ACE)
Figure 21. Typical Interface for a High Capacity Data Bus
SLLS177H − MARCH 1994 − REVISED JANUARY 2006
22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Buffer
Address
Decoder
A16−A23
ADS
AD0−AD15
RSI/ABT
PHI1 PHI2
PHI1 PHI2 ADS
ADS
CPU
RSTO
A16−A23
CS0
CS1
CS2
MR
A0−A2
D0−D7
AD0−AD7
RD1
WR1
AD0−AD15
RD2
WR2
XIN
XOUT
BAUDOUT
RCLK
DTR
RTS
OUT1
OUT2
RI
DCD
DSR
CTS
SIN
SOUT
INTRPT
TXRDY
DDIS
RXRDY
GND
(VSS)5 V
(VCC)
Alternate
Crystal Control
TL16C550C
EIA-232-D
Connector
20
1
8
6
5
2
3
7
1
TCU WR
RD
Figure 22. Typical TL16C550C Connection to a CPU
SLLS177H − MARCH 1994 − REVISED JANUARY 2006
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
Table 1. Register Selection
DLAB†A2 A1 A0 REGISTER
0 L L L Receiver buffer (read), transmitter holding register (write)
0 L L H Interrupt enable register
X L H L Interrupt identification register (read only)
X L H L FIFO control register (write)
X L H H Line control register
X H L L Modem control register
X H L H Line status register
X H H L Modem status register
X H H H Scratch register
1 L L L Divisor latch (LSB)
1 L L H Divisor latch (MSB)
†The divisor latch access bit (DLAB) is the most significant bit of the line control register . The DLAB signal
is controlled by writing to this bit location (see Table 4).
Table 2. ACE Reset Functions
REGISTER/SIGNAL RESET CONTROL RESET STATE
Interrupt enable register Master reset All bits cleared (0−3 forced and 4−7 permanent)
Interrupt identification register Master reset Bit 0 is set, bits 1, 2, 3, 6, and 7 are cleared, and bits 4−5 are
permanently cleared
FIFO control register Master reset All bits cleared
Line control register Master reset All bits cleared
Modem control register Master reset All bits cleared (6−7 permanent)
Line status register Master reset Bits 5 and 6 are set; all other bits are cleared
Modem status register Master reset Bits 0−3 are cleared; bits 4−7 are input signals
SOUT Master reset High
INTRPT (receiver error flag) Read LSR/MR Low
INTRPT (received data available) Read RBR/MR Low
INTRPT (transmitter holding register empty) Read IR/write THR/MR Low
INTRPT (modem status changes) Read MSR/MR Low
OUT2 Master reset High
RTS Master reset High
DTR Master reset High
OUT1 Master reset High
Scratch register Master reset No effect
Divisor latch (LSB and MSB) registers Master reset No effect
Receiver buffer register Master reset No effect
Transmitter holding register Master reset No effect
RCVR FIFO MR/FCR1−FCR0/∆FCR0 All bits cleared
XMIT FIFO MR/FCR2−FCR0/∆FCR0 All bits cleared
SLLS177H − MARCH 1994 − REVISED JANUARY 2006
24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
accessible registers
The system programmer, using the CPU, has access to and control over any of the ACE registers that are
summarized in Table 2. These registers control ACE operations, receive data, and transmit data. Descriptions
of these registers follow Table 3.
Table 3. Summary of Accessible Registers
REGISTER ADDRESS
0DLAB=0 0DLAB = 0 1DLAB=0 2 2 3 4 5 6 7 0DLAB =1 1DLAB=1
BIT
NO.
Receiver
Buffer
Register
(Read
Only)
Transmitter
Holding
Register
(Write
Only)
Interrupt
Enable
Register
Interrupt
Ident.
Register
(Read
Only)
FIFO
Control
Register
(Write
Only)
Line
Control
Register
Modem
Control
Register
Line
Status
Register
Modem
Status
Register
Scratch
Register
Divisor
Latch
(LSB)
Latch
(MSB)
RBR THR IER IIR FCR LCR MCR LSR MSR SCR DLL DLM
0Data Bit 0†Data Bit 0
Enable
Received
Data
Available
Interrupt
(ERBI)
0 if
Interrupt
Pending
FIFO
Enable
Word
Length
Select
Bit 0
(WLS0)
Data
Terminal
Ready
(DTR)
Data
Ready
(DR)
Delta
Clear
to Send
(∆CTS)
Bit 0 Bit 0 Bit 8
1Data Bit 1 Data Bit 1
Enable
Transmitter
Holding
Register
Empty
Interrupt
(ETBEI)
Interrupt
ID
Bit 1
Receiver
FIFO
Reset
Word
Length
Select
Bit 1
(WLS1)
Request
to Send
(RTS)
Overrun
Error
(OE)
Delta
Data
Set
Ready
(∆DSR)
Bit 1 Bit 1 Bit 9
2Data Bit 2 Data Bit 2
Enable
Receiver
Line Status
Interrupt
(ELSI)
Interrupt
ID
Bit 2
Transmitter
FIFO
Reset
Number
of
Stop Bits
(STB)
OUT1 Parity
Error
(PE)
Trailing
Edge Ring
Indicator
(TERI) Bit 2 Bit 2 Bit 10
3Data Bit 3 Data Bit 3
Enable
Modem
Status
Interrupt
(EDSSI)
Interrupt
ID
Bit 3
(see
Note 9)
DMA
Mode
Select
Parity
Enable
(PEN) OUT2 Framing
Error
(FE)
Delta
Data
Carrier
Detect
(∆DCD)
Bit 3 Bit 3 Bit 11
4Data Bit 4 Data Bit 4 0 0 Reserved
Even
Parity
Select
(EPS)
Loop Break
Interrupt
(BI)
Clear
to
Send
(CTS)
Bit 4 Bit 4 Bit 12
5Data Bit 5 Data Bit 5 0 0 Reserved Stick
Parity
Autoflow
Control
Enable
(AFE)
Transmitter
Holding
Register
(THRE)
Data
Set
Ready
(DSR)
Bit 5 Bit 5 Bit 13
6Data Bit 6 Data Bit 6 0
FIFOs
Enabled
(see
Note 9)
Receiver
Trigger
(LSB)
Break
Control 0Transmitter
Empty
(TEMT)
Ring
Indicator
(RI) Bit 6 Bit 6 Bit 14
7Data Bit 7 Data Bit 7 0
FIFOs
Enabled
(see
Note 9)
Receiver
Trigger
(MSB)
Divisor
Latch
Access
Bit
(DLAB)
0
Error in
RCVR
FIFO
(see
Note 9)
Data
Carrier
Detect
(DCD)
Bit 7 Bit 7 Bit 15
†Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
NOTE 9: These bits are always 0 in the TL16C450 mode.
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
FIFO control register (FCR)
The FCR is a write-only register at the same location as the IIR, which is a read-only register. The FCR enables
and clears the FIFOs, sets the receiver FIFO trigger level, and selects the type of DMA signalling.
DBit 0: This bit, when set, enables the transmitter and receiver FIFOs. Bit 0 must be set when other FCR
bits are written to or they are not programmed. Changing this bit clears the FIFOs.
DBit 1: This bit, when set, clears all bytes in the receiver FIFO and clears its counter. The shift register is not
cleared. The 1 that is written to this bit position is self clearing.
DBit 2: This bit, when set, clears all bytes in the transmit FIFO and clears its counter. The shift register is not
cleared. The 1 that is written to this bit position is self clearing.
DBit 3: When FCR0 is set, setting FCR3 causes RXRDY and TXRDY to change from level 0 to level 1.
DBits 4 and 5: These two bits are reserved for future use.
DBits 6 and 7: These two bits set the trigger level for the receiver FIFO interrupt (see Table 4).
Table 4. Receiver FIFO Trigger Level
BIT 7 BIT 6 RECEIVER FIFO
TRIGGER LEVEL (BYTES)
0 0 01
0 1 04
1 0 08
1 1 14
FIFO interrupt mode operation
When the receiver FIFO and receiver interrupts are enabled (FCR0 = 1, IER0 = 1, IER2 = 1), a receiver interrupt
occurs as follows:
1. The received data available interrupt is issued to the microprocessor when the FIFO has reached its
programmed trigger level. It is cleared when the FIFO drops below its programmed trigger level.
2. The IIR receive data available indication also occurs when the FIFO trigger level is reached, and like the
interrupt, it is cleared when the FIFO drops below the trigger level.
3. The receiver line status interrupt (IIR = 06) has higher priority than the received data available (IIR = 04)
interrupt.
4. The data ready bit (LSR0) is set when a character is transferred from the shift register to the receiver FIFO.
It is cleared when the FIFO is empty.
SLLS177H − MARCH 1994 − REVISED JANUARY 2006
26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
FIFO interrupt mode operation (continued)
When the receiver FIFO and receiver interrupts are enabled:
1. FIFO time-out interrupt occurs if the following conditions exist:
a. At least one character is in the FIFO.
b. The most recent serial character was received more than four continuous character times ago (if two
stop bits are programmed, the second one is included in this time delay).
c. The most recent microprocessor read of the FIFO has occurred more than four continuous character
times before. This causes a maximum character received command to interrupt an issued delay of 160
ms at a 300 baud rate with a 12-bit character.
2. Character times are calculated by using the RCLK input for a clock signal (makes the delay proportional
to the baud rate).
3. When a time-out interrupt has occurred, it is cleared and the timer is cleared when the microprocessor reads
one character from the receiver FIFO.
4. When a time-out interrupt has not occurred, the time-out timer is cleared after a new character is received
or after the microprocessor reads the receiver FIFO.
When the transmitter FIFO and THRE interrupt are enabled (FCR0 = 1, IER1 = 1), transmit interrupts occur as
follows:
1. The transmitter holding register empty interrupt [IIR (3−0) = 2] occurs when the transmit FIFO is empty. It
is cleared [IIR (3−0) = 1] when the THR is written to (1 to 16 characters may be written to the transmit FIFO
while servicing this interrupt) or the IIR is read.
2. The transmitter holding register empty interrupt is delayed one character time minus the last stop bit time
when there have not been at least two bytes in the transmitter FIFO at the same time since the last time
that the FIFO was empty. The first transmitter interrupt after changing FCR0 is immediate if it is enabled.
FIFO polled mode operation
With FCR0 = 1 (transmitter and receiver FIFOs enabled), clearing IER0, IER1, IER2, IER3, or all four to 0 puts
the ACE in the FIFO polled mode of operation. Since the receiver and transmitter are controlled separately,
either one or both can be in the polled mode of operation.
In this mode, the user program checks receiver and transmitter status using the LSR. As stated previously:
DLSR0 is set as long as there is one byte in the receiver FIFO.
DLSR1 − LSR4 specify which error(s) have occurred. Character error status is handled the same way as
when in the interrupt mode; the IIR is not affected since IER2 = 0.
DLSR5 indicates when the THR is empty.
DLSR6 indicates that both the THR and TSR are empty.
DLSR7 indicates whether there are any errors in the receiver FIFO.
There is n o trigger level reached or time-out condition indicated in the FIFO polled mode. However, the receiver
and transmitter FIFOs are still fully capable of holding characters.
SLLS177H − MARCH 1994 − REVISED JANUARY 2006
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PRINCIPLES OF OPERATION
interrupt enable register (IER)
The IER enables each of the five types of interrupts (refer to Table 5) and enables INTRPT in response to an
interrupt generation. The IER can also disable the interrupt system by clearing bits 0 through 3. The contents
of this register are summarized in Table 3 and are described in the following bullets.
DBit 0: When set, this bit enables the received data available interrupt.
DBit 1: When set, this bit enables the THRE interrupt.
DBit 2: When set, this bit enables the receiver line status interrupt.
DBit 3: When set, this bit enables the modem status interrupt.
DBits 4 through 7: These bits are not used (always cleared).
interrupt identification register (IIR)
The ACE has an on-chip interrupt generation and prioritization capability that permits a flexible interface with
most popular microprocessors.
The ACE provides four prioritized levels of interrupts:
DPriority 1 − Receiver line status (highest priority)
DPriority 2 − Receiver data ready or receiver character time-out
DPriority 3 − Transmitter holding register empty
DPriority 4 − Modem status (lowest priority)
When an interrupt is generated, the IIR indicates that an interrupt is pending and encodes the type of interrupt
in its three least significant bits (bits 0, 1, and 2). The contents of this register are summarized in Table 3 and
described in Table 5. Detail on each bit is as follows:
DBit 0: This bit is used either in a hardwire prioritized or polled interrupt system. When bit 0 is cleared, an
interrupt is pending If bit 0 is set, no interrupt is pending.
DBits 1 and 2: These two bits identify the highest priority interrupt pending as indicated in Table 3
DBit 3: This bit is always cleared in TL16C450 mode. In FIFO mode, bit 3 is set with bit 2 to indicate that a
time-out interrupt is pending.
DBits 4 and 5: These two bits are not used (always cleared).
DBits 6 and 7: These bits are always cleared in TL16C450 mode. They are set when bit 0 of the FIFO control
register is set.
SLLS177H − MARCH 1994 − REVISED JANUARY 2006
28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
interrupt identification register (IIR) (continued)
Table 5. Interrupt Control Functions
INTERRUPT
IDENTIFICATION REGISTER PRIORITY
LEVEL
INTERRUPT TYPE
INTERRUPT SOURCE
INTERRUPT RESET
METHOD
BIT 3 BIT 2 BIT 1 BIT 0
LEVEL
INTERRUPT TYPE
INTERRUPT SOURCE
METHOD
0 0 0 1 None None None None
0 1 1 0 1 Receiver line status Overrun error, parity error,
framing error, or break interrupt Read the line status register
0 1 0 0 2 Received data available Receiver data available in the
TL16C450 mode or trigger level
reached in the FIFO mode Read the receiver buf fer register
1 1 0 0 2 Character time-out
indication
No characters have been
removed from or input to the
receiver FIFO during the last four
character times, and there is at
least one character in it during
this time
Read the receiver buf fer register
0 0 1 0 3 Transmitter holding
register empty Transmitter holding register
empty
Read the interrupt identification
register (if source of interrupt) or
writing into the transmitter
holding register
0 0 0 0 4 Modem status Clear to send, data set ready,
ring indicator, or data carrier
detect Read the modem status register
line control register (LCR)
The system programmer controls the format of the asynchronous data communication exchange through the
LCR. In addition, the programmer is able to retrieve, inspect, and modify the contents of the LCR; this eliminates
the need for separate storage of the line characteristics in system memory. The contents of this register are
summarized in Table 3 and described in the following bulleted list.
DBits 0 and 1: These two bits specify the number of bits in each transmitted or received serial character.
These bits are encoded as shown in Table 6.
Table 6. Serial Character Word Length
BIT 1 BIT 0 WORD LENGTH
0 0 5 bits
0 1 6 bits
1 0 7 bits
1 1 8 bits
DBit 2: This bit specifies either one, one and one-half, or two stop bits in each transmitted character. When
bit 2 is cleared, one stop bit is generated in the data. When bit 2 is set, the number of stop bits generated
is dependent on the word length selected with bits 0 and 1. The receiver clocks only the first stop bit
regardless of th e n umber of stop bits selected. The number of stop bits generated in relation to word length
and bit 2 are shown in Table 7.
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
line control register (LCR) (continued)
Table 7. Number of Stop Bits Generated
BIT 2 WORD LENGTH SELECTED
BY BITS 1 AND 2 NUMBER OF STOP
BITS GENERATED
0Any word length 1
15 bits 1 1/2
16 bits 2
17 bits 2
18 bits 2
DBit 3: This bit is the parity enable bit. When bit 3 is set, a parity bit is generated in transmitted data between
the last data word bit and the first stop bit. In received data, if bit 3 is set, parity is checked. When bit 3 is
cleared, no parity is generated or checked.
DBit 4: This bit is the even parity select bit. When parity is enabled (bit 3 is set) and bit 4 is set even parity
(an even number of logic 1s in the data and parity bits) is selected. When parity is enabled and bit 4 is
cleared, odd parity (an odd number of logic 1s) is selected.
DBit 5: This bit is the stick parity bit. When bits 3, 4, and 5 are set, the parity bit is transmitted and checked
as cleared. When bits 3 and 5 are set and bit 4 is cleared, the parity bit is transmitted and checked as set.
If bit 5 is cleared, stick parity is disabled.
DBit 6: This bit is the break control bit. Bit 6 is set to force a break condition; i.e., a condition where SOUT
is forced to the spacing (cleared) state. When bit 6 is cleared, the break condition is disabled and has no
affect on the transmitter logic; it only effects SOUT.
DBit 7: This bit is the divisor latch access bit (DLAB). Bit 7 must be set to access the divisor latches of the
baud generator during a read or write. Bit 7 must be cleared during a read or write to access the receiver
buffer, the THR, or the IER.
line status register (LSR)†
The LSR provides information to the CPU concerning the status of data transfers. The contents of this register
are summarized in Table 3 and described in the following bulleted list.
DBit 0: This bit is the data ready (DR) indicator for the receiver. DR is set whenever a complete incoming
character has been received and transferred into the RBR or the FIFO. DR is cleared by reading all of the
data in the RBR or the FIFO.
DBit 1‡: This bit is the overrun error (OE) indicator. When OE is set, it indicates that before the character in
the RBR was read, it was overwritten by the next character transferred into the register. OE is cleared every
time the CPU reads the contents of the LSR. If the FIFO mode data continues to fill the FIFO beyond the
trigger level, an overrun error occurs only after the FIFO is full and the next character has been completely
received in the shift register. An overrun error is indicated to the CPU as soon as it happens. The character
in the shift register is overwritten, but it is not transferred to the FIFO.
†The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testing environment.
‡Bits 1 through 4 are the error conditions that produce a receiver line status interrupt.
SLLS177H − MARCH 1994 − REVISED JANUARY 2006
30 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
line status register (LSR) (continued)†
DBit 2‡: This bit is the parity error (PE) indicator. When PE is set, it indicates that the parity of the received
data character does not match the parity selected in the LCR (bit 4). PE is cleared every time the CPU reads
the contents of the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO
to which it applies. This error is revealed to the CPU when its associated character is at the top of the FIFO.
DBit 3‡: This bit is the framing error (FE) indicator. When FE is set, it indicates that the received character
did not have a valid (set) stop bit. FE is cleared every time the CPU reads the contents of the LSR. In the
FIFO mode, this error is associated with the particular character in the FIFO to which it applies. This error
is revealed to the CPU when its associated character is at the top of the FIFO. The ACE tries to
resynchronize after a framing error. To accomplish this, it is assumed that the framing error is due to the
next start bit. The ACE samples this start bit twice and then accepts the input data.
DBit 4‡: This bit is the break interrupt (BI) indicator. When BI is set, it indicates that the received data input
was held low for longer than a full-word transmission time. A full-word transmission time is defined as the
total ti m e t o t r a nsmit the start, data, parity, and stop bits. BI is cleared every time the CPU reads the contents
of the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO to which it
applies. This error is revealed to the CPU when its associated character is at the top of the FIFO. When a
break occurs, only one 0 character is loaded into the FIFO. The next character transfer is enabled after SIN
goes to the marking state for at least two RCLK samples and then receives the next valid start bit.
DBit 5: This bit is the THRE indicator. THRE is set when the THR is empty, indicating that the ACE is ready
to accept a new character. If the THRE interrupt is enabled when THRE is set, an interrupt is generated.
THRE is set when the contents of the THR are transferred to the TSR. THRE is cleared concurrent with the
loading of the THR by the CPU. In the FIFO mode, THRE is set when the transmit FIFO is empty; it is cleared
when at least one byte is written to the transmit FIFO.
DBit 6: This bit is the transmitter empty (TEMT) indicator. TEMT bit is set when the THR and the TSR are
both empty. When either the THR or the TSR contains a data character, TEMT is cleared. In the FIFO mode,
TEMT is set when the transmitter FIFO and shift register are both empty.
DBit 7: In the TL16C550C mode, this bit is always cleared. In the TL16C450 mode, this bit is always cleared.
In the FIFO mode, LSR7 is set when there is at least one parity, framing, or break error in the FIFO. It is
cleared when the microprocessor reads the LSR and there are no subsequent errors in the FIFO.
modem control register (MCR)
The MCR is an 8-bit register that controls an interface with a modem, data set, or peripheral device that is
emulating a modem. The contents of this register are summarized in Table 3 and are described in the following
bulleted list.
DBit 0: This bit (DTR) controls the DTR output.
DBit 1: This bit (RTS) controls the RTS output.
DBit 2: This bit (OUT1) controls OUT1, a user-designated output signal.
DBit 3: This bit (OUT2) controls OUT2, a user-designated output signal.
When any of bits 0 through 3 are set, the associated output is forced low. When any of these bits are cleared,
the associated output is forced high.
†The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testing environment.
‡Bits 1 through 4 are the error conditions that produce a receiver line status interrupt.
SLLS177H − MARCH 1994 − REVISED JANUARY 2006
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PRINCIPLES OF OPERATION
modem control register (MCR) (continued)
DBit 4: This bit (LOOP) provides a local loop back feature for diagnostic testing of the ACE. When LOOP
is set, the following occurs:
− The transmitter SOUT is set high.
− The receiver SIN is disconnected.
− The output of the TSR is looped back into the receiver shift register input.
− The four modem control inputs (CTS, DSR, DCD, and RI) are disconnected.
− The four modem control outputs (DTR, RTS, OUT1, and OUT2) are internally connected to the four
modem control inputs.
− The four modem control outputs are forced to the inactive (high) levels.
DBit 5: This bit (AFE) is the autoflow control enable. When set, the autoflow control as described in the
detailed description is enabled.
In the diagnostic mode, data that is transmitted is immediately received. This allows the processor to verify
the transmit and receive data paths to the ACE. The receiver and transmitter interrupts are fully operational.
The modem control interrupts are also operational, but the modem control interrupt’s sources are now the
lower four bits of the MCR instead of the four modem control inputs. All interrupts are still controlled by the
IER.
The ACE flow can be configured by programming bits 1 and 5 of the MCR as shown in Table 8.
Table 8. ACE Flow Configuration
MCR BIT 5
(AFE) MCR BIT 1
(RTS) ACE FLOW CONFIGURATION
1 1 Auto-RTS and auto-CTS enabled (autoflow control enabled)
1 0 Auto-CTS only enabled
0 X Auto-RTS and auto-CTS disabled
modem status register (MSR)
The MSR is an 8-bit register that provides information about the current state of the control lines from the
modem, data set, or peripheral device to the CPU. Additionally, four bits of this register provide change
information; when a control input from the modem changes state, the appropriate bit is set. All four bits are
cleared when the CPU reads the MSR. The contents of this register are summarized in Table 3 and are
described in the following bulleted list.
DBit 0: This bit is the change in clear-to-send (∆CTS) indicator. ∆CTS indicates that the CTS input has
changed state since the last time it was read by the CPU. When ∆CTS is set (autoflow control is not enabled
and the modem status interrupt is enabled), a modem status interrupt is generated. When autoflow control
is enabled (∆CTS is cleared), no interrupt is generated.
DBit 1: This bit is the change in data set ready (∆DSR) indicator. ∆DSR indicates that the DSR input has
changed state since the last time it was read by the CPU. When ∆DSR is set and the modem status interrupt
is enabled, a modem status interrupt is generated.
DBit 2: This bit is the trailing edge of the ring indicator (TERI) detector. TERI indicates that the RI input to
the chip has changed from a low to a high level. When TERI is set and the modem status interrupt is enabled,
a modem status interrupt is generated.
SLLS177H − MARCH 1994 − REVISED JANUARY 2006
32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
modem status register (MSR) (continued)
DBit 3: This bit is the change in data carrier detect (∆DCD) indicator. ∆DCD indicates that the DCD input to
the chip has changed state since the last time it was read by the CPU. When ∆DCD is set and the modem
status interrupt is enabled, a modem status interrupt is generated.
DBit 4: This bit is the complement of the clear-to-send (CTS) input. When the ACE is in the diagnostic test
mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 1 (RTS).
DBit 5: This bit is the complement of the data set ready (DSR) input. When the ACE is in the diagnostic test
mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 0 (DTR).
DBit 6: This bit is the complement of the ring indicator (RI) input. When the ACE is in the diagnostic test mode
(LOOP [MCR4] = 1), this bit is equal to the MCR bit 2 (OUT1).
DBit 7: This bit is the complement of the data carrier detect (DCD) input. When the ACE is in the diagnostic
test mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 3 (OUT2).
programmable baud generator
The ACE contains a programmable baud generator that takes a clock input in the range between dc and 16 MHz
and divides it by a divisor in the range between 1 and (216−1). The output frequency of the baud generator is
sixteen times (16×) the baud rate. The formula for the divisor is:
divisor = XIN frequency input ÷ (desired baud rate × 16)
Two 8-bit registers, called divisor latches, store the divisor in a 16-bit binary format. These divisor latches must
be loaded during initialization of the ACE in order to ensure desired operation of the baud generator. When either
of the divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long counts on initial load.
Tables 9 and 10 illustrate the use of the baud generator with crystal frequencies of 1.8432 MHz and 3.072 MHz
respectively. For baud rates of 38.4 kbits/s and below, the error obtained is very small. The accuracy of the
selected baud rate is dependent on the selected crystal frequency (refer to Figure 23 for examples of typical
clock circuits).
SLLS177H − MARCH 1994 − REVISED JANUARY 2006
33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
programmable baud generator (continued)
Table 9. Baud Rates Using a 1.8432-MHz Crystal
DESIRED
BAUD RATE
DIVISOR USED
TO GENERATE
16 × CLOCK
PERCENT ERROR
DIFFERENCE BETWEEN
DESIRED AND ACTUAL
50 2304
75 1536
110 1047 0.026
134.5 857 0.058
150 768
300 384
600 192
1200 96
1800 64
2000 58 0.69
2400 48
3600 32
4800 24
7200 16
9600 12
19200 6
38400 3
56000 2 2.86
Table 10. Baud Rates Using a 3.072-MHz Crystal
DESIRED
BAUD RATE
DIVISOR USED
TO GENERATE
16 × CLOCK
PERCENT ERROR
DIFFERENCE BETWEEN
DESIRED AND ACTUAL
50 3840
75 2560
110 1745 0.026
134.5 1428 0.034
150 1280
300 640
600 320
1200 160
1800 107 0.312
2000 96
2400 80
3600 53 0.628
4800 40
7200 27 1.23
9600 20
19200 10
38400 5
SLLS177H − MARCH 1994 − REVISED JANUARY 2006
34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
programmable baud generator (continued)
Driver
Optional
Driver
External
Clock
Optional
Clock
Output
Oscillator Clock
to Baud Generator
Logic
XIN
XOUT
VCC
Crystal
XIN
RX2
VCC
XOUT
C1
RP
C2
Oscillator Clock
to Baud Generator
Logic
TYPICAL CRYSTAL OSCILLATOR NETWORK
CRYSTAL RPRX2 C1 C2
3.072 MHz 1 MΩ1.5 kΩ10−30 pF 40−60 pF
1.8432 MHz 1 MΩ1.5 kΩ10−30 pF 40−60 pF
Figure 23. Typical Clock Circuits
receiver buffer register (RBR)
The ACE receiver section consists of a receiver shift register (RSR) and a RBR. The RBR is actually a 16-byte
FIFO. Timing is supplied by the 16× receiver clock (RCLK). Receiver section control is a function of the ACE
line control register.
The ACE RSR receives serial data from SIN. The RSR then concatenates the data and moves it into the RBR
FIFO. In the TL16C450 mode, when a character is placed in the RBR and the received data available interrupt
is enabled (IER0 = 1), an interrupt is generated. This interrupt is cleared when the data is read out of the RBR.
In the FIFO mode, the interrupts are generated based on the control setup in the FIFO control register.
scratch register
The scratch register is an 8-bit register that is intended for the programmer’s use as a scratchpad in the sense
that it temporarily holds the programmer’s data without affecting any other ACE operation.
transmitter holding register (THR)
The ACE transmitter section consists of a THR and a transmitter shift register (TSR). The THR is actually a
16-byte FIFO. Timing is supplied by BAUDOUT. Transmitter section control is a function of the ACE line control
register.
The ACE THR receives data off the internal data bus and when the shift register is idle, moves it into the TSR.
The TSR serializes the data and outputs it at SOUT. In the TL16C450 mode, if the THR is empty and the
transmitter holding register empty (THRE) interrupt is enabled (IER1 = 1), an interrupt is generated. This
interrupt is cleared when a character is loaded into the register. In the FIFO mode, the interrupts are generated
based on the control setup in the FIFO control register.
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TL16C550CFN ACTIVE PLCC FN 44 26 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TL16C550CFNG4 ACTIVE PLCC FN 44 26 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TL16C550CFNR ACTIVE PLCC FN 44 500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TL16C550CFNRG4 ACTIVE PLCC FN 44 500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TL16C550CIFN ACTIVE PLCC FN 44 26 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TL16C550CIFNG4 ACTIVE PLCC FN 44 26 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TL16C550CIFNR ACTIVE PLCC FN 44 500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TL16C550CIFNRG4 ACTIVE PLCC FN 44 500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TL16C550CIPT ACTIVE LQFP PT 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TL16C550CIPTG4 ACTIVE LQFP PT 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TL16C550CIPTR ACTIVE LQFP PT 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TL16C550CIPTRG4 ACTIVE LQFP PT 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TL16C550CN OBSOLETE PDIP N 40 TBD Call TI Call TI
TL16C550CPFB ACTIVE TQFP PFB 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TL16C550CPFBG4 ACTIVE TQFP PFB 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TL16C550CPFBR ACTIVE TQFP PFB 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TL16C550CPFBRG4 ACTIVE TQFP PFB 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TL16C550CPT ACTIVE LQFP PT 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TL16C550CPTG4 ACTIVE LQFP PT 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TL16C550CPTR ACTIVE LQFP PT 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TL16C550CPTRG4 ACTIVE LQFP PT 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
PACKAGE OPTION ADDENDUM
www.ti.com 6-Jul-2009
Addendum-Page 1
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 6-Jul-2009
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TL16C550CIPTR LQFP PT 48 1000 330.0 16.4 9.6 9.6 1.9 12.0 16.0 Q2
TL16C550CPFBR TQFP PFB 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2
TL16C550CPTR LQFP PT 48 1000 330.0 16.4 9.6 9.6 1.9 12.0 16.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TL16C550CIPTR LQFP PT 48 1000 367.0 367.0 38.0
TL16C550CPFBR TQFP PFB 48 1000 367.0 367.0 38.0
TL16C550CPTR LQFP PT 48 1000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MPLC004A – OCTOBER 1994
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER
4040005/B 03/95
20 PIN SHOWN
0.026 (0,66)
0.032 (0,81)
D2/E2
0.020 (0,51) MIN
0.180 (4,57) MAX
0.120 (3,05)
0.090 (2,29)
D2/E2
0.013 (0,33)
0.021 (0,53)
Seating Plane
MAX
D2/E2
0.219 (5,56)
0.169 (4,29)
0.319 (8,10)
0.469 (11,91)
0.569 (14,45)
0.369 (9,37)
MAX
0.356 (9,04)
0.456 (11,58)
0.656 (16,66)
0.008 (0,20) NOM
1.158 (29,41)
0.958 (24,33)
0.756 (19,20)
0.191 (4,85)
0.141 (3,58)
MIN
0.441 (11,20)
0.541 (13,74)
0.291 (7,39)
0.341 (8,66)
18
19
14
13
D
D1
13
9
E1E
4
8
MINMAXMIN
PINS
**
20
28
44
0.385 (9,78)
0.485 (12,32)
0.685 (17,40)
52
68
84 1.185 (30,10)
0.985 (25,02)
0.785 (19,94)
D/E
0.395 (10,03)
0.495 (12,57)
1.195 (30,35)
0.995 (25,27)
0.695 (17,65)
0.795 (20,19)
NO. OF D1/E1
0.350 (8,89)
0.450 (11,43)
1.150 (29,21)
0.950 (24,13)
0.650 (16,51)
0.750 (19,05)
0.004 (0,10)
M
0.007 (0,18)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
MECHANICAL DATA
MTQF003A – OCTOBER 1994 – REVISED DECEMBER 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PT (S-PQFP-G48) PLASTIC QUAD FLATPACK
4040052/C 11/96
0,13 NOM
0,17
0,27
25
24
SQ
12
13
36
37
6,80
7,20
1
48
5,50 TYP
0,25
0,45
0,75
0,05 MIN
SQ
9,20
8,80
1,35
1,45
1,60 MAX
Gage Plane
Seating Plane
0,10
0°–7°
0,50 M
0,08
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
D. This may also be a thermally enhanced plastic package with leads conected to the die pads.
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK
4073176/B 10/96
Gage Plane
0,13 NOM
0,25
0,45
0,75
Seating Plane
0,05 MIN
0,17
0,27
24
25
13
12
SQ
36
37
7,20
6,80
48
1
5,50 TYP
SQ
8,80
9,20
1,05
0,95
1,20 MAX 0,08
0,50 M
0,08
0°–7°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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