CY2544 CY2546 PRELIMINARY Quad PLL Programmable Clock Generator with Spread Spectrum Features Benefits * Four fully integrated phase-locked loops (PLLs) * Input Frequency range: -- External crystal: 8 to 48 MHz -- External reference: 8 to 166 MHz clock * Wide operating output frequency range -- 3 to 166 MHz * Programmable Spread Spectrum with Center and Down Spread option and Lexmark modulation profile * Two VDD core voltage options: -- 2.5V, 3.0V, and 3.3V for CY2544 -- 1.8V for CY2546 * Selectable output voltages: -- 2.5V, 3.0V, and 3.3V for CY2544 * * * * * * * -- 1.8V for CY2546 Frequency Select feature with option to select eight different frequencies Low jitter, high accuracy outputs Up to nine clock outputs Programmable output drive strength Glitch-free outputs while frequency switching 24-pin QFN package Commercial and Industrial temperature ranges * Multiple high-performance PLLs allow synthesis of unrelated frequencies * Nonvolatile programming for customized PLL frequencies, spread spectrum characteristics, drive strength, crystal load capacitance, and output frequencies * Two Spread Spectrum capable PLLs with Linear or Lexmark profile for maximum EMI reduction * Spread Spectrum PLLs can be disabled or enabled separately * PLLs can be programmed for system frequency margin tests * Meets critical timing requirements in complex system designs * Suitable for PC, consumer, and networking applications * Ability to synthesize standard frequencies with ease * Application compatibility in standard and low-power systems Block Diagram EXCLKIN 4 of 6 Crossbar Switch CLK1 Bank 1 XIN XOUT OSC Output PLL1 CLK3 Dividers and FS0 FS1 FS2 CLK4 Bank 2 Drive PLL2 CLK2 CLK5 CLK6 Strength MUX and Control Logic CLK7 Control Bank 3 PLL3 (SS) CLK8 CLK9 PLL4 (SS) PD#/OE SSON Cypress Semiconductor Corporation Document #: 001-12563 Rev. *A * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised February 28, 2007 [+] Feedback CY2544 CY2546 PRELIMINARY XIN XOUT VDD EXCLKIN CLK9 GND XIN XOUT VDD_CORE EXCLKIN CLK9 GND Pin Configuration 24 23 22 21 20 19 24 23 22 21 20 19 GND 1 18 GND GND 1 18 GND CLK1 2 17 CLK8 CLK1 2 17 CLK8 VDD_CLK_B1 3 16 VDD_CLK_B3 VDD_CLK_B1 3 16 VDD_CLK_B3 4 15 CLK7/SSON PD#OE 4 15 CLK7/SSON 5 14 VDD_CLK_B2 VDD_CORE 5 14 VDD_CLK_B2 6 13 CLK6 CLK2 6 13 CLK6 CY2546 9 10 11 CLK5 12 GND 8 CLK4/FS2 7 PD#/OE/FS1 12 CLK3/FS0 11 24LD QFN GND 10 GND 9 CLK5 8 CLK4/FS2 7 PD#/OE/FS1 CLK2 CLK3/FS0 NC GND PD#OE CY2544 24LD QFN Pin Description - CY2544 (2.5V, 3.0V or 3.3V VDD) Pin Number Name I/O Description 1 GND Power Power Supply Ground for Core 2 CLK1 Output Programmable Output Clock 3 VDD_CLK_B1 Power 2.5V/3.0V/3.3V Power Supply for Output Bank1 (CLK1, CLK2, CLK3) output 4 PD#/OE Input Power Down or Output Enable 5 NC NC No Connect 6 CLK2 Output Programmable Output Clock 7 GND Power Power Supply Ground for Output Bank 1 8 CLK3/FS0 Output/Input Multifunction Programmable pin,CLK3 Output Clock or Frequency Select pin FS0 9 PD#/OE/FS1 Input Multifunction Programmable pin, Power Down, Output Enable or Frequency Select pin FS1 10 CLK4/FS2 Output/Input Multifunction Programmable pin, CLK4 Output or Frequency Select input pin FS2 11 CLK5 Output Programmable Output Clock 12 GND Power Power Supply Ground for Output Bank 2 13 CLK6 Output Programmable Output Clock 14 VDD_CLK_B2 Power 2.5V/3.0V/3.3V Power Supply for Output Bank2 (CLK4, CLK5, CLK6) output 15 CLK7/SSON Output/Input Multifunction Programmable pin, CLK7 Output or SSON input 16 VDD_CLK_B3 Power 2.5V/3.0V/3.3V Power Supply for Output Bank3 (CLK7, CLK8, CLK9) output 17 CLK8 Output Programmable Output Clock 18 GND Power Power Supply Ground for Output Bank 3 Document #: 001-12563 Rev. *A Page 2 of 11 [+] Feedback CY2544 CY2546 PRELIMINARY Pin Description - CY2544 (2.5V, 3.0V or 3.3V VDD) (continued) Pin Number 19 Name I/O Description GND Power Power Supply Ground for Core 20 CLK9 Output Programmable Output Clock 21 EXCLKIN Input External Clock Input 22 VDD Power 2.5V/3.0V/3.3V Power Supply 23 XOUT Output Crystal Output 24 XIN Input Crystal Input Pin Description - CY2546 (1.8V VDD_CORE) Pin Number Name 1 GND 2 3 I/O Description Power Power Supply Ground for Core CLK1 Output Programmable Output Clock VDD_CLK_B1 Power 1.8V Power Supply for Output Bank1 (CLK1, CLK2, CLK3) output 4 PD#/OE Input Power Down or Output Enable 5 VDD_CORE Power Supply 1.8V Power Supply for Core 6 CLK2 Output Programmable Output Clock 7 GND Power Power Supply Ground For Output Bank 1 8 CLK3/FS0 Output/Input Multifunction Programmable pin,CLK3 Output Clock or Frequency Select pin FS0 9 PD#/OE/FS1 Input Multifunction Programmable pin, Power Down, Output Enable or Frequency Select pin FS1 10 CLK4/FS2 Output/Input Multifunction Programmable pin, CLK4 Output or Frequency Select input pin FS2 11 CLK5 Output Programmable Output Clock 12 GND Power Power Supply Ground for Output Bank 2 13 CLK6 Output Programmable Output Clock 14 VDD_CLK_B2 Power 1.8V Power Supply for Output Bank2 (CLK4, CLK5, CLK6) output 15 CLK7/SSON Output/Input Multifunction Programmable pin, CLK4 Output or SSON input 16 VDD_CLK_B3 Power 1.8V Power Supply for Output Bank3 (CLK7, CLK8, CLK9) output 17 CLK8 Output Programmable Output Clock 18 GND Power Power Supply Ground for Output Bank 3 19 GND Power Power Supply Ground for Core 20 CLK9 Output Programmable Output Clock 21 EXCLKIN Input External Low Voltage Reference Clock Input 22 VDD_CORE Power 1.8V Power Supply for Core 23 XOUT Output Crystal Output 24 XIN Input Crystal Input Document #: 001-12563 Rev. *A Page 3 of 11 [+] Feedback CY2544 CY2546 PRELIMINARY General Description The CY2544 and CY2546 are four-PLL programmable Spread Spectrum Clock Generators used to reduce EMI found in high-speed digital electronic systems. Two of the four PLLs have Spread Spectrum capability. The spread spectrum feature is turned on or off using the control pin SSON. The advantage of having four PLLs is that a single device can generate up to four independent families of frequencies from a single crystal or reference input frequency. Generally, a design requires up to four oscillators to achieve the same result as a single CY2544 or CY2546. The device uses Cypress proprietary PLL and Spread Spectrum Clock (SSC) technology to synthesize and modulate the frequency of the input clock. Frequency modulating the clock greatly reduces the measured EMI at the fundamental and harmonic frequencies. This reduction in radiated energy significantly reduces the cost of complying with regulatory agency (EMC) requirements and improves time-to-market without degrading the system performance. The CY2544 and CY2546 use a factory/field-programmable configuration memory array to provide customization for output frequencies, frequency select options, spread characteristics like spread percentage and modulation frequency, output drive strength and crystal load capacitance. Customized devices are configured using CyberClocksTM software or by contacting the factory. The spread percentage is programmed to either center spread or down spread with various spread percentages. The range for center spread is from 0.125% to 2.50%. The range for down spread is from -0.25% to -5.0%. Contact the factory for smaller or larger spread percentage amounts, if required. Document #: 001-12563 Rev. *A The input to the CY2544 and CY2546 is either a crystal or a clock signal. The input frequency range for crystals is 8 MHz to 48 MHz, and for clock signals is 8 MHz to 166 MHz. In addition, there is a separate input for a clock reference. The CY2544 and CY2546 have nine clock outputs and each output has four possible input sources. There are three frequency select lines FS(2:0) that provide an option to select eight different sets of frequencies among each of the four PLLs. Each output has programmable output divider options. Output 1 has eight possible divider values and outputs 2-9 have four possible divider values for maximum flexibility. The 2-bit or 3-bit output dividers are programmable, providing a wide output frequency range. The outputs are glitch-free when frequency is switched using output dividers. The outputs can have a predictable phase relationship, if the clock source is the same PLL and divider values are 2, 3, 4, or 6. The output banking feature allows the three sets of frequencies to operate at three different voltages. Selectable output voltage options are 2.5V, 3.0V, or 3.3V for CY2544 and 1.8V for CY2546 part. The CY2544 and CY2546 are available in 24-pin QFN packages with commercial and industrial operating temperature ranges. Table 1. Supply Voltage Options Device VDD Supply Voltage CY2544 CY2546 2.5V, 3.0V or 3.3V 1.8V Page 4 of 11 [+] Feedback CY2544 CY2546 PRELIMINARY Absolute Maximum Conditions Parameter Description Condition Min. Max. Unit VDD Supply Voltage for CY2544 -0.5 4.5 V VDD_CORE Supply Voltage for CY2546 -0.5 2.6 V Supply Voltage for CY2544 -0.5 4.5 V Supply Voltage for CY2546 -0.5 2.6 V VDD_CLK_BX VIN Input Voltage Relative to VSS -0.5 TS Temperature, Storage Non Functional -65 ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 UL-94 Flammability Rating @1/8 in. MSL Moisture Sensitivity Level QFN package VDD + 0.5 VDC +150 C - Volts 2000 V-0 3 Recommended Operating Conditions Min. Typ. VDD Parameter VDD Operating at 3.3V for CY2544 Description 3.00 - Max. Unit 3.60 V VDD VDD Operating at 3.0V for CY2544 2.70 - 3.30 V VDD VDD Operating at 2.5V for CY2544 2.25 - 2.75 V VDD_CORE VDD_CORE Operating at 1.8V for CY2546 1.65 - 1.95 V VDD_CLK_BX Output Driver Voltage for Bank 1, 2 and 3 Operating at 3.3V (CY2544) 3.00 - 3.60 V VDD_CLK_BX Output Driver Voltage for Bank 1, 2 and 3 Operating at 3.0V (CY2544) 2.70 - 3.30 V VDD_CLK_BX Output Driver Voltage for Bank 1, 2 and 3 Operating at 2.5V (CY2544) 2.25 - 2.75 V VDD_CLK_BX Output Driver Voltage for Bank 1, 2 and 3 Operating at 1.8V (CY2546) 1.65 - 1.95 V TAC Commercial Ambient Temperature 0 - +70 C TAI Industrial Ambient Temperature -40 - +85 C CLOAD Maximum Load Capacitance - - 15 pF tPU Power-up time for all VDD pins to reach minimum specified voltage (power ramps must be monotonic) 0.05 - 500 ms DC Electrical Specifications Parameter Description Conditions VOL Output Low Voltage, All CLK pins All VDD levels, IOL = 8 mA VOH Output High Voltage, All CLK pins All VDD levels, IOH = -8 mA VIL All Inputs except XIN All VDD levels VIH All Inputs except XIN All VDD levels VILX Input Low Voltage, clock input to XIN pin All VDD levels All VDD levels Min. Typ. Max. Unit - - 0.4 V VDD - 0.4 - - V -0.3 - 0.2 * VDD V 0.8 * VDD - VDD + 0.3 V -0.3 - 0.36 V VIHX Input High Voltage, clock input to XIN pin 1.44 - 2.0 V IILPDOE Input Low Current, PD#/OE and FS0,1,2 pins VIN = VSS (No Internal pull up) - - 1 A IIHPDOE Input High Current, PD#/OE and FS0,1,2 pins VIN = VDD (No Internal pull up) - - 1 A IILSR Input Low Current, SSON pin VIN = VSS (Internal pull down = 160k typical) - - 1 A IIHSR Input High Current, SSON pin VIN = VDD (Internal pull down = 160k typical) - - 25 A IDD[1] Supply Current All clocks running, No load - 15 - mA IDDS Standby Current All output power down - 50 - A CIN Input Capacitance - All inputs except XIN SSON, OE, PD# or FS inputs - - 7 pF Document #: 001-12563 Rev. *A Page 5 of 11 [+] Feedback CY2544 CY2546 PRELIMINARY AC Electrical Specifications Parameter Description Conditions Min. Typ. Max. Unit FIN (crystal) Crystal Frequency 8 - 48 MHz FIN (clock) Input Clock Frequency (XIN or EXCLKIN) 8 - 166 MHz FOUT Output Clock Frequency 3 - 166 MHz DC Output Duty Cycle All Clocks except Ref Out Duty Cycle is defined in Figure 2, "Duty Cycle Definition," on page 8; t1/t2, 50% of VDD 45 50 55 % DC Ref Out Duty Cycle Ref In Min 45%, Max 55% 40 ER CLK1-9 Rising Edge Rate VDD = All, 20% to 80% VDD 0.8 EF CLK1-9 Falling Edge Rate VDD = All, 20% to 80% VDD 0.8 TCCJ1 Cycle-to-cycle Jitter Configuration dependent. See Table 2, "Configuration Example for Jitter," on page 6 - TLTJ Long Term Jitter (1000 cycle period jitter) Configuration dependent. See Table 2, "Configuration Example for Jitter," on page 6 - T10 PLL Lock Time - 60 % - V/ns - - V/ns - - ps - - ns 1 3 ms - Table 2. Configuration Example for Jitter Reference Description Max Jitter (ps) on Output 1(48MHz) Max Jitter (ps) on Output 2 (27 MHz) Max Jitter (ps) on Max Jitter (ps) on Output 3 (166 MHz) Output 4 (74.25 MHz) Cycle-to-Cycle Jitter 27MHz TCCJ1 155 255 170 195 48 MHz TCCJ1 135 225 100 125 Long Term Jitter 27MHz TLTJ 770 580 630 1105 48 MHz TLTJ 535 575 520 795 Note 1. Configuration dependent. Document #: 001-12563 Rev. *A Page 6 of 11 [+] Feedback CY2544 CY2546 PRELIMINARY Recommended Crystal Specification for SMD Package Parameter Description Range 1 Range 2 Range 3 Unit Fmin Minimum Frequency 8 14 28 MHz Fmax Maximum Frequency 14 28 48 MHz R1(max) Maximum Motional Resistance (ESR) 135 50 30 C0(max) Maximum Shunt Capacitance 4 4 2 pF CL(max) Maximum Parallel Load Capacitance 18 14 12 pF DL(max) Maximum Crystal Drive Level 300 300 300 W Recommended Crystal Specification for Thru-Hole Package Parameter Description Range 1 Range 2 Range 3 Unit Fmin Minimum Frequency 8 14 24 MHz Fmax Maximum Frequency 14 24 32 MHz R1(max) Maximum Motional Resistance (ESR) 90 50 30 C0(max) Maximum Shunt Capacitance 7 7 7 pF CL(max) Maximum Parallel Load Capacitance DL(max) Maximum Crystal Drive Level Document #: 001-12563 Rev. *A 18 12 12 pF 1000 1000 1000 W Page 7 of 11 [+] Feedback CY2544 CY2546 PRELIMINARY Test and Measurement Setup Figure 1. Test and Measurement Setup V DDs 0.1 F Outputs C LOAD DUT GND Voltage and Timing Definitions Figure 2. Duty Cycle Definition t1 t2 VDD 50% of VDD Clock Output 0V Figure 3. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4 t3 t4 V DD 80% of VDD Clock Output Document #: 001-12563 Rev. *A 20% of VDD 0V Page 8 of 11 [+] Feedback CY2544 CY2546 PRELIMINARY Ordering Information Part Number[2] Type VDD(V) Temperature Range Lead-free CY2544Cxxx 24-pin QFN 3.3, 3.0 or 2.5 Commercial, 0C to 70C CY2544CxxxT 24-pin QFN -Tape & Reel 3.3, 3.0 or 2.5 Commercial, 0C to 70C CY2544FC 24-pin QFN 3.3, 3.0 or 2.5 Commercial, 0C to 70C CY2544FCT 24-pin QFN - Tape & Reel 3.3, 3.0 or 2.5 Commercial, 0C to 70C CY2546Cxxx 24-pin QFN 1.8 Commercial, 0C to 70C CY2546CxxxT 24-pin QFN -Tape & Reel 1.8 Commercial, 0C to 70C CY2546FC 24-pin QFN 1.8 Commercial, 0C to 70C CY2546FCT 24-pin QFN -Tape & Reel 1.8 Commercial, 0C to 70C CY2544IxxxT 24-pin QFN -Tape & Reel 3.3, 3.0 or 2.5 Industrial, -40C to +85C CY2544FI 24-pin QFN 3.3, 3.0 or 2.5 Industrial, -40C to +85C CY2544FIT 24-pin QFN - Tape & Reel 3.3, 3.0 or 2.5 Industrial, -40C to +85C CY2546Ixxx 24-pin QFN 1.8 Industrial, -40C to +85C CY2546IxxxT 24-pin QFN -Tape & Reel 1.8 Industrial, -40C to +85C CY2546FI 24-pin QFN 1.8 Industrial, -40C to +85C CY2546FIT 24-pin QFN -Tape & Reel 1.8 Industrial, -40C to +85C Note 2. xxx Indicates Factory Programmable are factory programmed configurations. For more details, contact your local Cypress FAE or Cypress Sales Representative. F in the part number indicates field programmable using CyberClocks Online software. Document #: 001-12563 Rev. *A Page 9 of 11 [+] Feedback CY2544 CY2546 PRELIMINARY Package Drawing and Dimensions Figure 4. 24-Lead QFN 4x4 mm (Subcon Punch Type Pkg with 2.49x2.49 EPAD) LF24A SIDE VIEW TOP VIEW BOTTOM VIEW 0.05 3.90 4.10 1.00 MAX. 0.230.05 0.05 MAX. 3.70 3.80 ?0.50 C 0.80 MAX. PIN1 ID 0.20 R. 2.49 0.20 REF. N N 1 2 2.45 2.55 3.90 4.10 3.70 3.80 1 2 2.49 0.45 SOLDERABLE EXPOSED PAD 0.30-0.50 0.420.18 (4X) 0-12 C SEATING PLANE 0.50 2.45 2.55 NOTES: 1. HATCH IS SOLDERABLE EXPOSED METAL. 2. REFERENCE JEDEC#: MO-220 51-85203-*A 3. PACKAGE WEIGHT: 0.042g 4. ALL DIMENSIONS ARE IN MM [MIN/MAX] 5. PACKAGE CODE PART # DESCRIPTION LF24A LY24A STANDARD LEAD FREE CyberClocks is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 001-12563 Rev. *A Page 10 of 11 (c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY2544 CY2546 PRELIMINARY Document History Page Document Title: CY2544/CY2546 Quad PLL Programmable Clock Generator with Spread Spectrum Document Number: 001-12563 REV. ECN NO. Issue Date Orig. of Change ** 690257 See ECN RGL New Data Sheet *A 790516 See ECN RGL Separated the Pin Configuration drawing into two to show the difference between CY2544 and CY2546 pin outs. Changed the IDD from 22mA maximum to 25mA typical Changed IILSR Internal pull down from 100K to 160K Changed IIHSR Internal pull down from 100k to 160K and changed the maximum value from 10A to 25A Changed IILPDOE to No Internal pull up and changed the maximum value from 10A to 1A Changed IIHPDOE to no Internal pull up Document #: 001-12563 Rev. *A Description of Change Page 11 of 11 [+] Feedback