Semiconductor Components Industries, LLC, 2000
November, 2000 – Rev. 3 1Publication Order Number:
MMBF170LT1/D
MMBF170LT1
Power MOSFET
500 mAmps, 60 Volts
N–Channel SOT–23
MAXIMUM RATINGS
Rating Symbol Value Unit
Drain–Source Voltage VDSS 60 Vdc
Drain–Gate Voltage VDGS 60 Vdc
Gate–Source Voltage
– Continuous
– Non–repetitive (tp ≤ 50 s) VGS
VGSM ±20
±40 Vdc
Vpk
Drain Current – Continuous
– Pulsed ID
IDM 0.5
0.8 Adc
THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
Total Device Dissipation FR–5 Board
(Note 1.) TA = 25°C
Derate above 25°C
PD225
1.8 mW
mW/°C
Thermal Resistance, Junction to Ambient RJA 556 °C/W
Junction and Storage Temperature TJ, Tstg –55 to
+150 °C
1. FR–5 = 1.0 0.75 0.062 in.
3
1
2
Device Package Shipping
ORDERING INFORMATION
MMBF170LT1 SOT–23 3000 Tape & Reel
N–Channel
SOT–23
CASE 318
STYLE 21
http://onsemi.com
W
MARKING
DIAGRAM
6Z
W = Work Week
PIN ASSIGNMENT
3
21
Drain
Gate
2
1
3
Source
MMBF170LT3 SOT–23 10,000 Tape & Reel
500 mAMPS
60 VOLTS
RDS(on) = 5
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ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)
Characteristic Symbol Min Max Unit
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage (VGS = 0, ID = 100 A) V(BR)DSS 60 – Vdc
Gate–Body Leakage Current, Forward (VGSF = 15 Vdc, VDS = 0) IGSS – 10 nAdc
ON CHARACTERISTICS (Note 2.)
Gate Threshold Voltage (VDS = VGS, ID = 1.0 mA) VGS(th) 0.8 3.0 Vdc
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 200 mA) rDS(on) – 5.0
On–State Drain Current (VDS = 25 Vdc, VGS = 0) ID(off) – 0.5 A
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 10 Vdc, VGS = 0 V, f = 1.0 MHz) Ciss – 60 pF
SWITCHING CHARACTERISTICS (Note 2.)
Turn–On Delay Time (VDD = 25 Vdc, ID = 500 mA, R
g
en = 50 )td(on) – 10 ns
Turn–Of f Delay Time
(VDD
25
Vdc
,
ID
500
mA
,
Rgen
50
)
Figure 1 td(off) – 10
2. Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%.
Figure 1. Switching Test Circuit Figure 2. Switching Waveform
20 dB 50
ATTENUATOR
PULSE
GENERATOR
50
50 1 M
Vout
125
+25 V
40 pF
Vin
TO SAMPLING
SCOPE
50 INPUT
PULSE WIDTH
50%
90%
50%
10%
10%
90% 90%
Vin
OUTPUT
INVERTED
INPUT
(Vin AMPLITUDE 10 VOLTS)
Vout
toff
tf
td(off)
ton
td(on) tr
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TYPICAL ELECTRICAL CHARACTERISTICS
ID, DRAIN CURRENT (AMPS)
rDS(on), STATIC DRAIN-SOURCE ON-RESISTANCE
(NORMALIZED)
VGS(th), THRESHOLD VOLTAGE (NORMALIZED) ID, DRAIN CURRENT (AMPS)
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0100 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0
VDS, DRAIN SOURCE VOLTAGE (VOLTS)
Figure 3. Ohmic Region
1.0
0.8
0.6
0.4
0.2
100 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0
VGS, GATE SOURCE VOLTAGE (VOLTS)
Figure 4. Transfer Characteristics
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
1.2
1.05
1.1
1.10
1.0
0.95
0.9
0.85
0.8
0.75
0.7
-60 -20 +20 +60 +100 +140 -60 -20 +20 +60 +100 +140
T, TEMPERATURE (°C)
Figure 5. Temperature versus Static
Drain–Source On–Resistance
T, TEMPERATURE (°C)
Figure 6. Temperature versus Gate
Threshold Voltage
TA = 25°C
VGS = 10 V
9 V
8 V
7 V
6 V
4 V
3 V
5 V
VDS = 10 V -55°C25°C
125°C
VGS = 10 V
ID = 200 mA
VDS = VGS
ID = 1.0 mA
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INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to insure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
mm
inches
0.037
0.95
0.037
0.95
0.079
2.0
0.035
0.9
0.031
0.8
SOT–23 POWER DISSIPATION
The power dissipation of the SOT–23 is a function of the
pad size. This can vary from the minimum pad size for
soldering to a pad size given for maximum power
dissipation. Power dissipation for a surface mount device is
determined by TJ(max), the maximum rated junction
temperature of the die, RθJA, the thermal resistance from
the device junction to ambient, and the operating
temperature, TA. Using the values provided on the data
sheet for the SOT–23 package, PD can be calculated as
follows:
PD = TJ(max) – TA
RθJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values
into the equation for an ambient temperature TA of 25°C,
one can calculate the power dissipation of the device which
in this case is 225 milliwatts.
PD = 150°C – 25°C
556°C/W = 225 milliwatts
The 556°C/W for the SOT–23 package assumes the use
of the recommended footprint on a glass epoxy printed
circuit board to achieve a power dissipation of 225
milliwatts. There are other alternatives to achieving higher
power dissipation from the SOT–23 package. Another
alternative would be to use a ceramic substrate or an
aluminum core board such as Thermal Clad. Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
•Always preheat the device.
•The delta temperature between the preheat and
soldering should be 100°C or less.*
•When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.
•The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
•When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
•After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
•Mechanical stress or shock should not be applied
during cooling.
* Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
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PACKAGE DIMENSIONS
STYLE 21:
PIN 1. GATE
2. SOURCE
3. DRAIN
DJ
K
L
A
C
BS
H
GV
3
12
DIM
A
MIN MAX MIN MAX
MILLIMETERS
0.1102 0.1197 2.80 3.04
INCHES
B0.0472 0.0551 1.20 1.40
C0.0350 0.0440 0.89 1.11
D0.0150 0.0200 0.37 0.50
G0.0701 0.0807 1.78 2.04
H0.0005 0.0040 0.013 0.100
J0.0034 0.0070 0.085 0.177
K0.0140 0.0285 0.35 0.69
L0.0350 0.0401 0.89 1.02
S0.0830 0.1039 2.10 2.64
V0.0177 0.0236 0.45 0.60
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE
MATERIAL.
SOT–23 (TO–236)
CASE 318–08
ISSUE AF
MMBF170LT1
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Notes
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Notes
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MMBF170LT1/D
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