JA AALWVI CMOS 12-Bit Serial Input Multiplying D/A Converter General Description The MAX543 is a 12-bit current-output multiplying digital-to-analog converter (DAC) that is packaged in a space-saving 8-pin DIP or 16-pin surface mount SO. Its 3-wire serial interface saves additional circuit board space and also results in low power dissipation. When used with microprocessors (uP) with a seriat port, the MAX543 minimizes the digital noise feed- through from its input pins to its output. The serial port can be used as a dedicated analog bus and kept inactive while the MAX543 is in use. Serial interfacing also reduces the complexity of opto- or transformer- isolated applications. The MAX543 contains a 12-bit R-2R type DAC, a serial-in paraliel-out shift register, a DAC register and control logic. On the rising edge of the clock (CLK) pulse the serial input (SRI) data is shifted into the MAX543. When all the data is clocked in_it is trans- ferred into the DAC register by taking the LOAD input low. The MAX543 is specified both with a single +5V and +15V power supply. With a +5V supply, the digital inputs are TTL and +5V CMOS compatible. High voltage CMOS compatibility is maintained with a +15V supply. Maxim's MAX543 uses low tempco thin-film resistors laser trimmed to +1/4 LSB linearity and better than +1 LSB gain accuracy. The digital inputs are protected against electrostatic discharge (ESD) damage and can typically withstand over 5,000V of ESD valtages. Applications Automatic Calibration Motion Control Systems uP Controlled Systems Programmable Amplifiers/Attenuators Digitally Controlled Filters Functional Block Diagram Vrer Arp 12-BiT p Ree D/A CONVERTER tour MAXIM MAX543 12-BIT Ly, DAC REGISTER DD ZS 12-BIT = SHIFT REGISTER ] T CLK SAI onal LOAD MAKI Features @ 12-Bit Accuracy in 8-Pin Mini-DIP Fast 3-Wire Serial Interface @ Low INL and DNL (+1/2 LSB Max) @ Gain Accuracy to +1 LSB Max @ Low Gain Tempco (Sppm/C Max) @ Operates with +5V or +15V Supplies @ TTL/CMOS Compatible @ ESD Protected Ordering information PART TEMP. RANGE PACKAGE LINEARITY MAXS43ACPA -0C to +70C.- Plastic DIP. +1/2 LSB MAX543BCPA 0C to +70C ~Plastic DIP +1 LSB MAX543ACWE 0C to +70C ~=Wide SO +1/2 LSB MAX543BCWE 0C to +70C_ ~=Wide SO +1 LSB MAX543AEWE -40C to +85C ~WideSO = +1/2 LSB MAX543BEWE -40C to +85C WideSO +1 LSB MAX543BC/D _0C to +70C_ Dice +1 LSB MAX543AEJA -40C to +85C CERDIP +1/2 LSB MAXS43BEJA -40C to +85C CERDIP +1 LSB MAX543AMJA -55C to +125C ~CERDIP +1/2 LSB MAX543BMJA -55C to +125C CERDIP +1 LSB All DiP packages are 8 leads; ail SO packages are 16 leads. Pin Configurations Top View pip NC. ve 8) N.C. nec. 8) N.C. Veer CO a) Yoo MAXIM on a MAX543 = om ann [@] 7] LOAD and [71 N.C. N.C. N.C. so * Leads 6 and 7 must be connected together as close to the package as possible. maxi is aregistered trademark of Maxim Integrated Products Maxim Integrated Products 9-31 : O ~ GMAX543 CMOS 12-Bit Serial Input Multiplying D/A Converter ABSOLUTE MAXIMUM RATINGS Vop to GND 2... cece e eect n eee renee +17V Operating Temperature Ranges Vacr tO GND 2... cece cece eee ecto n cere et eeees +25V MAXS43AC/BC 2... eee eee eee ee eee ee 0C to 70C Vare to GND... . ccc e ccc n eee e rennet nee eeens +25V MAX543AE/BE .......... eee eee .- ~40C to +85C Digital Input Voltage to GND .. -0.3V, Vpp + 0.3V MAX543AM/BM ..........-000006 . 755C ta +126C Viout to GND 2.0... ccc cee eee ~0.3V, Vpp + 0.3V Storage Temperature ~-B5C to +150C Power dissipation to +75C (any package) ....... 470mW Lead Temperature (soldering 10 seconds) ........ +300C Derate above +75C by .......... cc cece eee 6mW?PC Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (Vop = +5V, +12V or +15V; Vaer = +10V; Viour = GND = OV; over specified temperature range unless otherwise noted.) PARAMETER | SYMBOL | CONDITIONS MIN TYP MAX [UNITS STATIC PERFORMANCE Resolution N 12 Bits Integral Nonlinearity INL MA eteR #2 | .sB Guaranteed monotonic Differential Nonlinearity DNL |to 12 bits Maxease e LSB over temperature MAX543A +1 i Ta = 425C Gain Error Fse | Using 4 MAX543B +2 | tsB internal Reg Ta = Twin to Twax| All +2 Gain Tempco ae AGain/ATemp (Note 1) TCFS | Using internal Rea 1 +5 = |ppm/C DC Supply Rejection PSR AVop = +5%. +0.001 | %/% DYNAMIC PERFORMANCE (Note 1) To 1/2LSB. lour load is 100Q]| Current Settling Time ts 13pF. DAC register alternately {Ts = +25C 0.25 1 BS loaded with alt 1s and all Os. Vrer= OV. lout load is 1000||13pF. Digital to Analog Glitch Q DAC register alternately loaded with 2 20 nv-s all 1s and all Os. Vaer = +10Vp-p at 10kHz. AC Feedthrough at lour FTE | DAC register loaded with all Os. 0.4 1 | mVp-p : . . Varner = 6Vims at 1kKHz. Total Harmonic Distortion THD DAC register loaded with all 1s. -85 dB Output Noise 10Hz to 100kHz. Voltage Density en Measured between Reg and Jour. 3 5 nWHz REFERENCE INPUT input Resistance RREF | Veer pin to tour 7 11 15 kQ Input Resistance Tempco TCR -200 ppm/C 9-32 MAXIMCMOS 12-Bit Serial Input Multiplying D/A Converter ELECTRICAL CHARACTERISTICS (Continued) (Von = +5V, +12V or +15V; Vaer = +10V; Viour = GND = OV; over specified temperature range unless otherwise noted.) = PARAMETER | SYMBOL | CONDITIONS | MIN TYP = MAX | UNITS > ANALOG OUTPUT >< Ta = +25C +05 +5 ft lout Leakage Current Ike Ae ean Os. | Ta = Twin MA EBAC/BC/ +25 nA a 0 Twax AHAXS43AM/BM 100 . DAC register loaded with all Os. 55 80 lout Capacitance (Note 1) Cout 7 = pF DAC register loaded with all 1s. 85 110 DIGITAL INPUTS input High Voltage Vis Wee EBV 24 v Input Low Voltage Vit ve - oe se Vv Input Leakage Current lin Digital Inputs at OV or Vop +1 HA input Capacitance (Note 1) Cin Digital Inputs at OV or Vop 8 pF SWITCHING CHARACTERISTICS (Note 2) CLK Pulse Width High tcH 90 ns CLK Pulse Width Low ter 120 ns SRI Data to CLK Setup tos 40 ns SRI Data to CLK Hold tou 80 ns LOAD Pulse Width tip 120 ns LSB CLK to LOAD ter 0 ns LOAD High to CLK tie 0 ns POWER SUPPLY voo Fare Wo wore [ER All digital inputs at Vic or Vin 500 Ipp Range too _ HA All digital inputs at OV or Voo 5 100 Note 1: Guaranteed by design and not subject to test. Note 2: Sample tested at +25C to ensure compliance. MAKIM 0-33MAX543 CMOS 12-Bit Serial Input Multiplying D/A Converter GAIN vs FREQUENCY {OUTPUT AMPLIFIER: MAX400} 0 12 DIGITAL INPUT = 11 1411 1111 -24 -36 Gm} pratt ao = Zz -60 6 -72 -84 -96 ~108 caer 10k = 100k 1M 10M FREQUENCY (Hz) LOGIC THRESHOLD VOLTAGE vs SUPPLY VOLTAGE 4 5 3 9 = 24 g 2 a =f 3 1 E 1 3 5 7 9 1 13 15 Voo (VOLTS) LINEARITY ERROR (LSB) vs FREQUENCY (MULTIPLYING MODE) Vop = +5V Ta = 25C THD (dB) 10 100 1k 10k FREQUENCY (Hz) 100k LINEARITY ERROR vs DIGITAL CODE 1.00 T Ta = 425C 0.75 |-Vper = +10V 0.50 0.25 erent A > R & 8 -0.75 -1.00 Q 24 2048 3072 4096 DIGITAL INPUT CODE (DECIMAL) DNL ERROR vs REFERENCE VOLTAGE 05 2 4 6 8 10 Vrer (VOLTS) lop (mA) iNL (LSB) b B Typical Operating Characteristics TOTAL HARMONIC DISTORTION SUPPLY CURRENT vs LOGIC INPUT VOLTAGE a 1 2 3 4 Yin (VOLTS) LINEARITY ERROR vs REFERENCE VOLTAGE S a 8 o oy 2 4 6 8 10 Vrer (VOLTS) MAXI S/VICMOS 12-Bit Serial input Multiplying D/A Converter Detailed Description D/A Converter The MAX543 DAC circuit consists of a laser trimmed, thin-film R-2R resistor array with NMOS current switches as shown in Figure 1. Binary weighted currents are switched to either lo; or GND depend- ing on the status of each input data bit. Although the current at Ioyr and GND depends on the digital input code, the sum of the two output currents are always equal to the input current at Vper. The current output Ioy7 can be converted into a volt- age by adding an external output amplifier (Figure 3). The Vper input accepts a wide range of signals includ- ing fixed and time varying voltage or current inputs. If a current source is used for the reference input, then a low tempco external resistor should be used for Reg to minimize gain variation with temperature. The internal feedback resistor Rep is compensated with an NMOS switch that matches the NMOS switches used in the R-2R array. This results in excellent supply rejection and gain temperature coefficient. The loyy pin output capacitance, Coyz, is code de- pendent and is typically 55pF with all switches to GND and 85pF with all switches to Igur- Digital Circuit Figure 2 shows the timing diagram for the MAX543. The MSB is always loaded first on the rising edge of clock. When ail the data is shifted into the MAX543, the DAC register is loaded by taking the LOAD signa! low. The DAC register is_ transparent when LOAD is low and latched when LOAD is high. If the LOAD signal is taken low before the LSB bit is fully shifted into the shift register, the DAC output can produce a glitch. If this is undesirable, the LOAD signal can be delayed 30ns after the rising edge of the LSB clock edge to avoid this condition. lour oO GND | ! I \ DB11 DB10 OB9 (MSB) Figure 1. Simplitied D/A Circuit of MAX543 The input buffer inverters of the MAX543 act as level shifters converting TTL levels into CMOS logic levels. These input buffers are TTL and +5V-CMOS compat- ible (0.8V and 2.4V) at Vpp = +5V. For Vpp = +15V the input buffers are CMOS compatible (1.5V and 13.5V). At this supply voltage the input buffers are in their linear region when the input voltages are between 1V and 6V. Therefore to minimize men supply currents, the digital input voltages should be kept as close to the supply and ground voltages (Vpp and GND) as possible. Circuit Configurations Unipolar Operation Basic application of the MAX543 is shown in Figure 3. This circuit is used for unipolar operation or 2- quadrant multiplication. The code table for this mode is given in Table 1. Note that the polarity of the output is the inverse of the reference voltage, Veer. SRI MSsB** BIT 10 BIT 4 ne | tos >! tou | [int | fi to { <a 1 | | ** DATA LOADED MSB FIRST i 2 ah] CLK INPUT > tcH } ! __,| LOAD SERIAL DATA | INTO INPUT REGISTER tec ts. >} Le nc TOAD Figure 2. Write Cycle Timing Diagram MAAISZVI EPSXVNMAX543 CMOS 12-Bit Serial Input Multiplying D/A Converter +5V Veer R1 1 is 1002 Vaer Ypo R2 sriJ Ree Ay x MAXLM 3 T PF 2 cuk J lour 5 MAX543 4 LOAD J GND we > : s Figure 3. Unipolar Operation R2 500 20kQ 1 WA-VREF VAX YL ent Vaer R1 | MAX543 GND, rm Py, 1007) | CLK LOAD SRI MAX400 Vout lr Ts 6 MAX400 Figure 4. Bipolar Operation Table 2. Offset Binary Code Table for Circuit of Figure 4 Table 1. Unipolar Binary Code Table for Circuit of DIGITAL INPUT Figure 3 MSB sp ANALOG OUTPUT use eT se ANALOG OUTPUT 1444 4444 49419 Voge (ee | 1494 4447 4111 Voce 1000 0000 0001 Veer saa | 1000 0000 0000 -Vaer { 3k = Tae 1000 0000 0000 0 0000 0000 0001 Veer {agg | 0141 11117 11191 Veer {sans | 0000 0000 cooo] o 0000 0000 0000 Veer {Sea | In many applications gain adjustment will not be necessary since the gain accuracy of the part is suf- ficient, or the gain is trimmed at the reference source. In these cases, resistors R1 and R2 in Figure 3 can be omitted. When trimming is used, and the DAC is Operated over a wide temperature range, then low tempco iS 300ppm/C) resistors should be used for R1 and R2. The capacitor C1 provides phase compensation and reduces overshoot and ringing when fast amplifiers are used at the output of the DAC. Bipolar Operation Figure 4 shows the MAX543 operating in the bipolar, or 4-quadrant multiplying mode. A second amplifier and three matched resistors (R3, R4 and R5) are required. These resistors must be of the same material (preferably metal film or wire-wound) for good tem- perature tracking characteristics (<15ppm/C), and should match to 0.01% for 12-bit performance. The Output code is offset binary and is listed in Table 2. tn 9-36 Table 3. 2s Complement Code Table DIGITAL INPUT Mss LsB ANALOG OUTPUT 7 O1ty 4444 4499 Veer {Seas | 1 0000 0000 oo01 ae (so. 0000 0000 0000 0 144d anda tidd Veer | so REF | 2048 04 1000 0000 0000 Veer {Seg SVUAXILsvICMOS 12-Bit Serial Input Multiplying D/A Converter multiplying applications, the MSB determines output polarity while the other 11 bits control the amplitude. The MSB can be inverted in software using an exclusive-OR instruction to make the MAX543 work with 2's complement coding. Table 3 shows the code relationships to output voltage for the 2s complement operation. To adjust the circuit, load the DAC with a code of 1000 0000 0000 and trim R1 for a OV output. With R1 and R2 omitted, an alternative zero trim is to adjust the ratio of R3 and R4 for OV out. Full scale can be trimmed by loading the DAC with all zeros or all ones and adjusting the amplitude of Veer or varying R5 untif the desired positive or negative output is obtained. In many applications the gain adjustment will not be necessary, especially when using parts with a guaranteed maximum +1 LSB gain error. In these cases, the gain can be trimmed at the reference source and resistors R1 and R2 in Figure 4 omitted. However, if the trims are desired and the DAC is operated over a wide temperature range, then low tempco (<300ppm/C) resistors should be used for R1 and R2. Single Supply Operation __. (Voltage Mode) The MAX543 can be conveniently used in single supply (voltage mode) operation with Igy; biased at any voltage between GND and Vpp. loy7 must not be allowed to go 0.3V lower than the @ND or 0.3V higher than Vpp. Otherwise, internal diodes would turn on causing a high current flow from the supply which could damage the device. Figure 5 shows the MAX543 connected as a voltage output DAC. | is connected to the reference voltage source and Nb is grounded. The DAC output, now appears at the Vace pin which has a constant im- pedance equal to the reference input resistance (typ- ically 11kQ). This output should be buffered with an op amp when a lower output impedance is required. Rep pin is not used in this mode. The input impedance of the reference input (Iqu7) for this mode is code dependent, and the response time of the circuit depends on the behavior of the reference source with changing load conditions. +15V Voo lout ~naAximn REF MAX543 GND SRI CLK LOAD REFERENCE 1 Lo , VOLTAGE ouT 15 VOLT CMOS DIGITAL INPUTS Figure 5. Single Supply Operation Using Voltage Switching Mode MIAAISVI Two advantages of the voltage mode operation are single supply operation and that a negative reference is not required for a positive output. It should also be noted that the reference input (lo.j7) must always be positive and is limited to no more than 2.5V when Vpp is 15V. If the reference voltage is greater than 2.5V or Vop is reduced, resistance mismatches in the DACs internal NMOS switches result in degraded integral (INL) and differentia! nonlinearity (DNL). The unipolar and bipolar circuits in Figures 3 and 4 can all be converted to voltage output mode. MAX543 Opto-isolated Application Figure 6A shows the MAX543 interface to optocoup- lers for isolated barrier applications. Three optocoup- lers (OC1 thru OC3) carry the serial data and clocking signals across the isolation barrier. Isolated power sources, V* and V~, supply the MAX543, the output amplifier and optocouplers. If data word updates are infrequent, and large analog output transitions can be tolerated while serial data is being clocked in, then parts count can be reduced by eliminating optocoup- ler OC3 and tying LOAD (pin 5) of the MAX543 low. Using type 6N136 optocouplers this circuit accepts serial data at a maximum clock rate of 100kHz, or 130us per data word. The SERIAL DATA and LOAD signals should change coincident with the falling edge of CLOCK, as shown in the timing diagram (Figure 68). A positive CLOCK cycle is masked during the time that LOAD is low. The MAX543 will also work with +5V isolated supplies using the optocoupler circuit of Figure 6A. The values of R1 through R3 should be changed to 3kQ to main- tain switching speed with the lower value of V*. Current drawn from V~ for the MAX543 and opto- coupler is 3.5mA at 100kHz clock rate when ail data bits are set to zero. V* current drops to zero (exclud- ing reference and op amp current) when no new data is being loaded and CLOCK, SERIAL DATA, and LOAD are static high. Microprocessor interfacing interfacing to the 8085 Figure 7 shows the MAX543 interfacing to the 8085 microprocessor. The SOD line from the 8085 is used to send serial data to the DAC. This data is clocked into the MAX543 by executing memory write instruc- tions. The CLK input for the DAC can _be generated by decoding address 8000 and the WR signal. The data is transferred into the DAC register with a memory write instruction to address A000 which brings LOAD low. The data for the MAX543 is stored in the right- justified format in registers H and L of the 8085. 9-37 EvPSXVNMAX543 CMOS 12-Bit Serial Input Multiplying D/A Converter | | SERIAL DATA NON-ISOLATED | ISOLATED * TTL OR CMOS LOGIC DEVICE *eyt = +15V. FOR Vt = +5V USE 3kQ FOR Rt, R2, R3 Figure 6A. MAX543 Opto-coupled Application pata _xx X xx X 81 X B2 X B3 X 84 X Bs X 86 X 87 X Ba X Bo X Bio X Bit X B12 X xx _X BI (MSB) (L88) LOAD a IDLE WORD N WORD N+1 Figure 68. MAX543 Opto-lsolated Timing 9-38 MAXAI/VICMOS 12-Bit Serial Input Multiplying D/A Converter (8) ADDRESS BUS (16) Ao-45 E; Ap Ae ALE 8212 = 808s = 74L8138 __ +5VO1E3 ADDRESS WR E, DECODER (8) ADo.7 DATA S soD SRI LOAD CLK MAXIM MAX543 *ANALOG CIRCUITRY OMITTED FOR SIMPLICITY Figure 7, MAX543 - 8085 Interface interfacing to the MC6800 Figure 8 shows the MAX543 interfacing to the MC6B00 microprocessor. The data is transferred into the MAX543 by executing successive memory WRITE instructions while changing the data between WRITEs to construct the serial data to the DAC. The DB7 data line is used for the SRI signal. The lower half of the memory location 0000 holds the four MSB data bits, and the 0001 location holds the eight LSB data bits. The memory address 2000, R/W, and 02 are decoded to generate the CLK signal for the DAC with each memory WRITE. Similarly, a memory WRITE to address 4000 transfers data into the DAC register by bringing the MAX543s LOAD input low. Application Information Output Amplifier Offset For best linearity, |g; and GND should be terminated at exactly OV. In most applications Igy7 is connected to the summing junction of an inverting op amp. The input offset voltage of the amplifier can degrade the linearity of the DAC by causing Igy7 to be terminated to a non-zero voltage. The resulting error is: Error Voltage = Vog (1 + Reg/Ro) where Vog is the op amp's offset voltage and Ro is the output resistance of the DAC. Ro is a function of the digital input code, and varies from approximately 11k9 to 33kQ. The error voltage range is then typically 4/3V og to 2Vog, a Change of 2/3Vos. An amplifier with 3mvV of offset will, therefore, degrade the linearity by 2mvV, almost a full LSB with a 10V reference voltage. For best linearity, a low-offset amplifier such as the MAX400 should be used, or the amplifier offset must be trimmed to zero. A good rule of thumb is that Vos should be no more than 1/10LSB. MVAXIVI 16-BIT DATA BUS Ats Aa A2 Es 7aLS138 , ADDRESS DECODER mc6s00 DBo 8-BIT DATA BUS DB; r j LOAD CLK ise) /MAXKI/VI MAX543 ANALOG CIRCUITRY OMITTED FOR SIMPLICITY Figure 8. MAX543 - MC6800 Interface The output amplifier input bias current (Ig) can also limit performance since I, < Reg generates an offset error. |g should, therefore, be much less than the DAC output current for 1 LSB, typically 250nA with Vper = 10V. One tenth of this value, 25nA, is recommended Offset and linearity can also be impaired if the output amplifier noninverting input is grounded through a bias current compensation resistor. This resistor adds to the offset at this pin and should not be used. Best performance is obtained when the noninverting input is directly connected to ground. Dynamic Considerations In static or DC applications, the AC characteristics of the output amplifier are not critical. In higher speed applications, where either the reference input Is an AC signal or the DAC output must quickly settle to a new programmed value, the AC parameters of the output op amp must be considered. Another error source in dynamic applications is para- sitic coupling of signal from the Vaer pin to lout. This normally is a function of board layout and lead- to-lead package capacitance. Noise signals can also be injected into the DAC outputs when the digital inputs are switched. This digital feedthrough is usually dependent on circuit board layout and on-chip capac- itive coupling. Layout induced feedthrough can be minimized with guard traces between digital inputs, Veer and lout pins. The DAC output follows the digital inputs when the LOAD pin is low. In this mode invalid outputs and voltage glitches can appear at the DAC output. Keep- ing the LOAD input high until all the data is shifted into the MAX543 eliminates this problem. 9-39 : O A GMAX543 CMOS 12-Bit Serial Input Multiplying D/A Converter Compensation A compensation capacitor, C1, may be required when the DAC is used with a high speed output amplifier. The purpose of the capacitor is to cancel the pole formed by the DAC output capacitance, Coy, and the internal feedback resistor, Rep. Its value depends on the type of op amp used but typically ranges from 10pF to 33pF. Too small a value causes output ringing while excess capacitance overdamps the output. The size of C1 can be minimized and the output voltage settling time improved by keeping the circuit board trace and stray capacitance at Igyy as low as possible. Grounding and Bypassing Since loy7 and the noninverting input of the output amplifier are sensitive to offset voltages, nodes that are to be grounded should be connected directly to single point ground through a separate, low resis- tance (less than 0.20) connection. The current at louy and GND varies with input code, creating a code lependent error if these terminals are connected to ground (or a virtual ground) through a resistive path. A 1puF bypass capacitor, in parallel with a 0.01pF ceramic capacitor, should be connected across the DAC Vpp and GND as close to the pins as possible. The MAX543 has high impedance digital inputs. To minimize noise pick-up, they should be tied to either Vpp or GND when not used. It is good practice to connect active inputs to Vop or GND through high valued resistors (1MQ) to prevent static charge accumulation if the pins are left floating, such as when a circuit card is left unconnected. Chip Topography Voo CLK SAI LOAD areas Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embadied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice aft any time. 9-40 MAXIM