1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology.
1.2 Features
1.3 Applications
nLinear regulator for Double-Data Rate (DDR) memory
1.4 Quick reference data
2. Pinning information
[1] It is not possible to make a connection to pin 2.
PHD38N02LT
N-channel TrenchMOS logic level FET
Rev. 02 — 2 February 2007 Product data sheet
nLow on-state resistance n2.5 V gate drive
nVDS 20 V nID44.7 A
nRDSon 16 mnPtot 57.6 W
Table 1. Pinning
Pin Description Simplified outline Symbol
1 gate (G)
SOT428 (DPAK)
2 drain (D) [1]
3 source (S)
mb mounting base; connected to drain (D)
3
2
mb
1
S
D
G
mbb076
PHD38N02LT_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 2 February 2007 2 of 12
NXP Semiconductors PHD38N02LT
N-channel TrenchMOS logic level FET
3. Ordering information
4. Limiting values
Table 2. Ordering information
Type number Package
Name Description Version
PHD38N02LT DPAK plastic single-ended surface-mounted package; 3 leads
(one lead cropped) SOT428
Table 3. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDS drain-source voltage 25 °CTj175 °C - 20 V
VDGR drain-gate voltage (DC) 25 °CTj175 °C; RGS =20k-20V
VGS gate-source voltage - ±12 V
IDdrain current Tmb =25°C; VGS = 5 V; see Figure 2 and 3- 44.7 A
Tmb = 100 °C; VGS = 5 V; see Figure 2 - 31.6 A
IDM peak drain current Tmb =25°C; pulsed; tp10 µs; see Figure 3 - 179 A
Ptot total power dissipation Tmb =25°C; see Figure 1 - 57.6 W
Tstg storage temperature 55 +175 °C
Tjjunction temperature 55 +175 °C
Source-drain diode
ISsource current Tmb =25°C - 44.7 A
ISM peak source current Tmb =25°C; pulsed; tp10 µs - 179 A
PHD38N02LT_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 2 February 2007 3 of 12
NXP Semiconductors PHD38N02LT
N-channel TrenchMOS logic level FET
Fig 1. Normalized total power dissipation as a
function of mounting base temperature Fig 2. Normalized continuous drain current as a
function of mounting base temperature
Tmb =25°C; IDM is single pulse; VGS =5V
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
03aa16
0
40
80
120
0 50 100 150 200
Tmb (°C)
Pder
(%)
03aa24
0
40
80
120
0 50 100 150 200
Tmb (°C)
Ider
(%)
Pder Ptot
Ptot 25°C()
------------------------100 %×=Ider ID
ID25°C()
-------------------- 100 %×=
003aab706
1
10
102
103
1 10 102
VDS (V)
ID
(A)
DC
10 ms
Lim it RDSon = VDS / ID
1 ms
tp = 10 µs
100 µs
PHD38N02LT_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 2 February 2007 4 of 12
NXP Semiconductors PHD38N02LT
N-channel TrenchMOS logic level FET
5. Thermal characteristics
[1] Mounted on a printed-circuit board; vertical in still air.
Table 4. Thermal characteristics
Symbol Parameter Conditions Min Typ Max Unit
Rth(j-mb) thermal resistance from junction to mounting base see Figure 4 - - 2.6 K/W
Rth(j-a) thermal resistance from junction to ambient
SOT428 minimum footprint - 75 - K/W
SOT404 minimum footprint [1] - 50 - K/W
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration
003aab707
10-2
10-1
1
10
10-5 10-4 10-3 10-2 10-1 1
tp (s)
Zth(j-mb)
(K/W)
single pulse
δ = 0.5
0.2
0.1
0.05
0.02
tpT
P
t
tp
T
δ =
PHD38N02LT_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 2 February 2007 5 of 12
NXP Semiconductors PHD38N02LT
N-channel TrenchMOS logic level FET
6. Characteristics
Table 5. Characteristics
T
j
=25
°
C unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Static characteristics
V(BR)DSS drain-source breakdown
voltage ID= 250 µA; VGS =0V
Tj=25°C 20--V
Tj=55 °C 18--V
VGS(th) gate-source threshold voltage ID= 250 µA; VDS =V
GS; see Figure 9 and 10
Tj=25°C 0.5 1.0 1.5 V
Tj= 175 °C 0.3 - - V
Tj=55 °C - - 1.8 V
IDSS drain leakage current VDS =20V; V
GS =0V
Tj=25°C - 0.05 1.0 µA
Tj= 175 °C - - 500 µA
IGSS gate leakage current VGS =±12 V; VDS = 0 V - 10 100 nA
RDSon drain-source on-state
resistance VGS =5V; I
D= 25 A; see Figure 6 and 8
Tj=25°C - 13.5 16 m
Tj= 175 °C - 24.3 28.8 m
Dynamic characteristics
QG(tot) total gate charge ID= 25 A; VDS =10V; V
GS =5V;
see Figure 11 and 12 - 15.1 - nC
QGS gate-source charge - 4.5 - nC
QGD gate-drain charge - 4.2 - nC
Ciss input capacitance VGS =0V; V
DS = 20 V; f = 1 MHz;
see Figure 14 - 800 - pF
Coss output capacitance - 260 - pF
Crss reverse transfer capacitance - 190 - pF
td(on) turn-on delay time VDS =10V; I
D= 25 A; VGS =10V;
RG= 5.6 -4-ns
trrise time - 12.5 - ns
td(off) turn-off delay time - 30 - ns
tffall time -23-ns
Source-drain diode
VSD source-drain voltage IS= 25 A; VGS = 0 V; see Figure 13 - 0.98 1.2 V
PHD38N02LT_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 2 February 2007 6 of 12
NXP Semiconductors PHD38N02LT
N-channel TrenchMOS logic level FET
Tj=25°CT
j=25°C
Fig 5. Output characteristics: drain current as a
function of drain-source voltage; typical values Fig 6. Drain-source on-state resistance as a function
of drain current; typical values
Tj=25°C and 175 °C; VDS >I
D×RDSon
Fig 7. Transfer characteristics: drain current as a
function of gate-source voltage; typical values Fig 8. Normalized drain-source on-state resistance
factor as a function of junction temperature
003aab708
0
10
20
30
0 0.2 0.4 0.6 0.8 1
VDS (V)
ID
(A)
1. 8 V
Tj = 25 °C
VGS = 1. 6 V
10 V 5 V 3 V
2. 4 V
2. 2 V
2 V
2. 6 V
003aab710
0
10
20
30
0 102030
ID (A)
RDSon
(m)2.6 V
Tj = 25 °C
3 V
10 V
5 V
VGS = 2. 4 V
003aab709
0
5
10
15
20
25
0123
VGS (V)
ID
(A)
Tj = 25 °C
175 °C
03af18
0
0.5
1
1.5
2
-60 0 60 120 180
T
j
(°C)
a
aRDSon
RDSon 25°C()
------------------------------
=
PHD38N02LT_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 2 February 2007 7 of 12
NXP Semiconductors PHD38N02LT
N-channel TrenchMOS logic level FET
ID= 0.25 mA; VDS =V
GS Tj=25°C; VDS =5V
Fig 9. Gate-source threshold voltage as a function of
junction temperature Fig 10. Sub-threshold drain current as a function of
gate-source voltage
ID= 25 A; VDS =10V
Fig 11. Gate-source voltage as a function of gate
charge; typical values Fig 12. Gate charge waveform definitions
03al82
0
0.5
1
1.5
2
-60 0 60 120 180
(V)
min
max
typ
V
GS(th)
T
j
(°C)
03an65
10
-6
10
-5
10
-4
10
-3
0 0.4 0.8 1.2 1.6
(A)
min maxtyp
V
GS
(V)
I
D
003aab713
0
2
4
6
8
10
0102030
QG (nC)
VGS
(V) ID = 25 A
Tj = 25 °C
VDS = 10 V
003aaa508
V
GS
V
GS(th)
Q
GS1
Q
GS2
Q
GD
V
DS
Q
G(tot)
I
D
Q
GS
V
GS(pl)
PHD38N02LT_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 2 February 2007 8 of 12
NXP Semiconductors PHD38N02LT
N-channel TrenchMOS logic level FET
Tj=25°C and 175 °C; VGS =0V V
GS = 0 V; f = 1 MHz
Fig 13. Source current as a function of source-drain
voltage; typical values Fig 14. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
003aab712
0
5
10
15
20
25
0 0.3 0.6 0.9 1.2
VSD (V)
IS
(A)
Tj = 25 °C
175 °C
VGS = 0 V
003aab711
102
103
104
10-1 1 10 102
VDS (V)
C
(pF)
Ciss
Coss
Crss
PHD38N02LT_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 2 February 2007 9 of 12
NXP Semiconductors PHD38N02LT
N-channel TrenchMOS logic level FET
7. Package outline
Fig 15. Package outline SOT428 (DPAK)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT428 SC-63
TO-252
SOT428
06-02-14
06-03-16
DIMENSIONS (mm are the original dimensions)
Plastic single-ended surface-mounted package (DPAK); 3 leads (one lead cropped)
A
2
13
E1
D2
D1HD
LL1
L2
e1
e
mounting
base
wA
M
b
E
b2
b1c
A1
y
0 5 10 mm
scale
UNIT
mm 0.93
0.46 5.46
5.00 0.56
0.20 6.22
5.98 6.73
6.47 10.4
9.6 2.95
2.55
A1
2.38
2.22
Ab
2
1.1
0.9
b1e1
0.89
0.71
bcD
1
0.9
0.5
L2
Ee
2.285 4.57
4.0
D2
min
4.45
E1
min
0.5
L1
min
HDLw
0.2
y
max
0.2
A
PHD38N02LT_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 2 February 2007 10 of 12
NXP Semiconductors PHD38N02LT
N-channel TrenchMOS logic level FET
8. Revision history
Table 6. Revision history
Document ID Release date Data sheet status Change notice Supersedes
PHD38N02LT_2 20070202 Product data sheet - PHB_PHD38N02LT-01
Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
Legal texts have been adapted to the new company name where appropriate.
PHB38N02LT has been discontinued.
PHB_PHD38N02LT-01
(9397 750 11614) 20030630 Product data - -
PHD38N02LT_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 2 February 2007 11 of 12
NXP Semiconductors PHD38N02LT
N-channel TrenchMOS logic level FET
9. Legal information
9.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
9.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
9.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
9.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
TrenchMOS — is a trademark of NXP B.V.
10. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
NXP Semiconductors PHD38N02LT
N-channel TrenchMOS logic level FET
© NXP B.V. 2007. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 2 February 2007
Document identifier: PHD38N02LT_2
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
11. Contents
1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 General description. . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.4 Quick reference data. . . . . . . . . . . . . . . . . . . . . 1
2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Thermal characteristics. . . . . . . . . . . . . . . . . . . 4
6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5
7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
8 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10
9 Legal information. . . . . . . . . . . . . . . . . . . . . . . 11
9.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11
9.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
9.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
9.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
10 Contact information. . . . . . . . . . . . . . . . . . . . . 11
11 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12