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NDS331N

N-Channel Logic Level Enhancement Mode Field Effect Transistor

General Description Features

_______________________________________________________________________________

Absolute Maximum Ratings TA = 25°C unless otherwise noted

Symbol Parameter NDS331N Units

VDSS Drain-Source Voltage 20 V

VGSS Gate-Source Voltage - Continuous 8V

IDMaximum Drain Current - Continuous (Note 1a) 1.3 A

- Pulsed 10

PDMaximum Power Dissipation (Note 1a)0.5 W

(Note 1b) 0.46

TJ,TSTG Operating and Storage Temperature Range -55 to 150 °C

THERMAL CHARACTERISTICS

RθJA Thermal Resistance, Junction-to-Ambient

(Note 1a)

250°C/W

RθJC Thermal Resistance, Junction-to-Case (Note 1) 75 °C/W

1.3 A, 20 V. RDS(ON) = 0.21 Ω @ VGS= 2.7 V

RDS(ON) = 0.16 Ω @ VGS= 4.5 V.

Industry standard outline SOT-23 surface mount package

using poprietary SuperSOTTM-3 design for superior thermal

and electrical capabilities.

High density cell design for extremely low RDS(ON).

Exceptional on-resistance and maximum DC current

capability.

These N-Channel logic level enhancement mode power field

effect transistors are produced using Fairchild's proprietary,

high cell density, DMOS technology. This very high density

process is especially tailored to minimize on-state resistance.

These devices are particularly suited for low voltage

applications in notebook computers, portable phones, PCMCIA

cards, and other battery powered circuits where fast

switching, and low in-line power loss are needed in a very

small outline surface mount package.

NDS331N N-Channel Logic Level Enhancement Mode Field Effect Transistor

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Semiconductor Components Industries, LLC, 2017 Publication Order Number:

January, 2017, Rev. E NDS331N

ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)

Symbol Parameter Conditions Min Typ Max Units

OFF CHARACTERISTICS

BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 20 V

IDSS Zero Gate Voltage Drain Current VDS = 16 V, VGS= 0 V 1µA

TJ =125°C 10 µA

IGSSF Gate - Body Leakage, Forward VGS = 8 V, VDS = 0 V 100 nA

IGSSR Gate - Body Leakage, Reverse VGS = -8 V, VDS= 0 V -100 nA

ON CHARACTERISTICS (Note 2)

VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA0.5 0.7 1V

TJ =125°C 0.3 0.53 0.8

RDS(ON) Static Drain-Source On-Resistance VGS = 2.7 V, ID = 1.3 A0.15 0.21 Ω

TJ =125°C 0.24 0.4

VGS = 4.5 V, ID = 1.5 A0.11 0.16

ID(ON) On-State Drain Current VGS = 2.7 V, VDS = 5 V 3A

VGS = 4.5 V, VDS = 5 V 4

gFS Forward Transconductance VDS = 5 V, ID = 1.3 A, 3.5 S

DYNAMIC CHARACTERISTICS

Ciss Input Capacitance VDS = 10 V, VGS = 0 V,

f = 1.0 MHz

162 pF

Coss Output Capacitance 85 pF

Crss Reverse Transfer Capacitance 28 pF

SWITCHING CHARACTERISTICS (Note 2)

tD(on)Turn - On Delay Time VDD = 5 V, ID = 1 A,

VGS = 5 V, RGen = 6 Ω5 20 ns

trTurn - On Rise Time 25 40 ns

tD(off) Turn - Off Delay Time 10 20 ns

tfTurn - Off Fall Time 5 20 ns

QgTotal Gate Charge VDS = 5 V, ID = 1.3 A,

VGS = 4.5 V

3.5 5nC

Qgs Gate-Source Charge 0.3 nC

Qgd Gate-Drain Charge 1nC

NDS331N N-Channel Logic Level Enhancement Mode Field Effect Transistor

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Electrical Characteristics (TA = 25°C unless otherwise noted)

Symbol Parameter Conditions Min Typ Max Units

DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS

ISMaximum Continuous Drain-Source Diode Forward Current 0.42 A

ISM Maximum Pulsed Drain-Source Diode Forward Current 10 A

VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = 0.42 A (Note 2)0.8 1.2 V

Notes:

1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by

design while RθCA is determined by the user's board design.

PD(t)=TJ−TA

RθJA

(t)=TJ−TA

RθJC

+RθCA

(t)=ID

2(t)×RDS(ON)TJ

Typical RθJA using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:

a. 250oC/W when mounted on a 0.02 in2 pad of 2oz copper.

b. 270oC/W when mounted on a 0.001 in2 pad of 2oz copper.

Scale 1 : 1 on letter size paper

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.

1a 1b

NDS331N N-Channel Logic Level Enhancement Mode Field Effect Transistor

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Figure 1. On-Region Characteristics.

0 1 2 3

V , DRAIN-SOURCE VOLTAGE (V)

I , DRAIN-SOURCE CURRENT (A)

3.0 2.7

V =4.5V

2.5

1.5

2.0

Figure 2. On-Resistance Variation

with Drain Current and Gate Voltage.

00.5 11.5 22.5 3

0.5

0.75

1.25

1.5

1.75

I , DRAIN CURRENT (A)

DRAIN-SOURCE ON-RESISTANCE

T = 125°C

25°C

V = 2.7 V

-55°C

R , NORMALIZED

DS(on)

Figure 4. On-Resistance Variation

with Drain Current and Temperature.

-50 -25 025 50 75 100 125 150

0.6

0.8

1.2

1.4

1.6

1.8

T , JUNCTION TEMPERATURE (°C)

DRAIN-SOURCE ON-RESISTANCE

V = 2.7V

I = 1.3A

R , NORMALIZED

DS(ON)

Figure 3. On-Resistance Variation

with Temperature.

00.5 11.5 22.5 3

V , GATE TO SOURCE VOLTAGE (V)

I , DRAIN CURRENT (A)

25°C

125°C

V = 5.0V

T = -55°C

Figure 5. Transfer Characteristics.

-50 -25 025 50 75 100 125 150

0.5

0.6

0.7

0.8

0.9

1.1

1.2

1.3

T , JUNCTION TEMPERATURE (°C)

GATE-SOURCE THRESHOLD VOLTAGE

I = 250µA

V = V

DS GS

V , NORMALIZED

Figure 6. Gate Threshold Variation

with Temperature.

00.5 11.5 22.5 3

0.5

0.75

1.25

1.5

1.75

I , DRAIN CURRENT (A)

DRAIN-SOURCE ON-RESISTANCE

V = 2.0V

R , NORMALIZED

DS(on)

3.5

4.5

2.7 3.0

2.5

Typical Electrical Characteristics

NDS331N N-Channel Logic Level Enhancement Mode Field Effect Transistor

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Typical Electrical Characteristics (continued)

-50 -25 0 25 50 75 100 125 150

0.92

0.96

1.04

1.08

1.12

T , JUNCTION TEMPERATURE (°C)

DRAIN-SOURCE BREAKDOWN VOLTAGE

I = 250µA

BV , NORMALIZED

DSS

Figure 7. Breakdown Voltage Variation with

Temperature.

0.1 0.2 0.5 1 2 5 10 20

100

200

400

600

V , DRAIN TO SOURCE VOLTAGE (V)

CAPACITANCE (pF)

iss

f = 1 MHz

V = 0V

oss

rss

Figure 9. Capacitance Characteristics.

00.2 0.4 0.6 0.8 11.2

0.0001

0.001

0.01

0.1

V , BODY DIODE FORWARD VOLTAGE (V)

I , REVERSE DRAIN CURRENT (A)

T = 125°C

25°C

-55°C

V = 0V

Figure 8. Body Diode Forward Voltage Variation with

Source Current and Temperature.

0 1 2 3 4 5

Q , GATE CHARGE (nC)

V , GATE-SOURCE VOLTAGE (V)

I = 1.3A

D10V

15V

V = 5V

Figure 10. Gate Charge Characteristics.

VDD

OUT

VGS

DUT

RGEN

Figure 11. Switching Test Circuit.Figure 12. Switching Waveforms.

10%

50%

90%

10%

90%

50%

VIN

VOUT

on off

d(off) f

d(on)

t t

ttt

INVERTED

10%

PULSE WIDTH

NDS331N N-Channel Logic Level Enhancement Mode Field Effect Transistor

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Typical Electrical Characteristics (continued)

01234

I , DRAIN CURRENT (A)

g , TRANSCONDUCTANCE (SIEMENS)

T = -55°C

25°C

V = 5.0V

125°C

Figure 13. Transconductance Variation with Drain

Current and Temperature.

00.1 0.2 0.3 0.4

0.2

0.4

0.6

0.8

2oz COPPER MOUNTING PAD AREA (in )

STEADY-STATE POWER DISSIPATION (W)

4.5"x5" FR-4 Board

T = 25 C

Still Air

Figue 15. SuperSOTTM _ 3 Maximum

Steady-State Power Dissipation. versus Copper

Mounting Pad Area.

Figure 14. Maximum Safe Operating Area.

00.1 0.2 0.3 0.4

1.2

1.4

1.6

1.8

2oz COPPER MOUNTING PAD AREA (in )

I , STEADY-STATE DRAIN CURRENT (A)

4.5"x5" FR-4 Board

T = 25 C

Still Air

V = 2.7V

Figure 16. Maximum Steady-State Drain

Current versus Copper Mounting Pad. Area

Figure 17. Transient Thermal Response Curve.

Note : Thermal characterization performed using the conditions described in note 1b.

response will change depending on the circuit board design.

NDS331N N-Channel Logic Level Enhancement Mode Field Effect Transistor

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0.1 1 10 60

0.01

0.1

CURVE BENT TO

MEASURED DATA

100 μs

10 ms

100 ms

1 ms

ID, DRAIN CURRENT (A)

VDS, DRA IN to SOURCE VOLTAGE (V)

THIS AREA IS

LIMITED BY rDS(on)

SINGLE PULSE

TJ = MA X RA TED

RθJA = 270 oC/W

TA = 25 oC

10-4 10-3 10-2 10-1 110

100 1000

0.001

0.01

0.1

SINGLE PULSE

DUTY CYCLE-DESCENDING ORDER

NORMALIZED THERMAL

IMPEDANCE, ZθJA

t, RECTANGULAR PULSE DURATION (sec)

D = 0.5

0 .2

0 .1

0.05

0.02

0.01

PDM

t1t2

NOTES:

ZθJA(t) = r(t) x RθJA

RθJA = 270 oC/W

Duty Cycle, D = t1 / t2

Peak TJ = PDM x ZθJA(t) + TA

NOTES: UNLESS OTHERWISE SPECIFIED

A) NO JEDEC REFERENCE AS OF AUGUST 2003

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS ARE EXCLUSIVE OF BURRS,

MOLD FLASH AND TIE BAR EXTRUSIONS.

D) DIMENSIONING AND TOLERANCING PER

ASME Y14.5M - 2009.

E) DRAWING FILE NAME: MKT-MA03BREV3

(0.29)

SCALE: 50:1

0.178

0.102

(0.56)

0.43

0.33

0.20

SEATING

PLANE

1.40

LAND PATTERN RECOMMENDATION

SEE DETAIL A

1.90

0.95

GAGE PLANE

(0.94)

1.12 MAX

0.10 MC

0.10

0.508

0.382

1.40±0.12

0.10

0.00

2.92±0.12 A

1.90

2.51±0.20

2.20

1.00

0.95

www.onsemi.com

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent

coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.

ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,

regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer

application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not

designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification

in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized

application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and

expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such

claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This

literature is subject to all applicable copyright laws and is not for resale in any manner.

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