SPICE Device Model SUM110P06-07L
Vishay Siliconix
P-Channel 60-V (D-S) 175° MOSFET
CHARACTERISTICS
• P-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the p-channel vertical DMOS. The subcircuit
mode is extracted and optimized over the −55 to 125°C temperature
ranges under the pulsed 0-to-10V gate drive. The saturated output
impedance is best fit at the gate bias near the threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched Cgd model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 72665 www.vishay.com
14-Nov-03 1
SPICE Device Model SUM110P06-07L
Vishay Siliconix
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Parameter Symbol Test Conditions
Simulated
Data
Measured
Data Unit
Static
Gate Threshold Voltage VGS(th) VDS = VGS, ID = − 250µA 1.8 V
On-State Drain Currenta ID(on) VDS = − 5V, VGS = − 10V 858 A
VGS = − 10V, ID = − 30A 0.0055 0.0055
VGS = − 10V, ID = − 30A, TJ = 125°C 0.0080
VGS = − 10V, ID = − 30A, TJ = 175°C 0.0094
Drain-Source On-State Resistancea r
DS(on)
VGS = − 4.5V, ID = − 20A 0.0067 0.0070
Ω
Forward Transconductancea g
fs VDS = − 15V, ID = − 110A 120 S
Diode Forward Voltagea V
SD IS = − 85A, VGS = 0V - 0.92 - 1 V
Dynamicb
Input Capacitance Ciss 11170 11400
Output Capacitance Coss 1248 1200
Reverse Transfer Capacitance Crss
VGS = 0V, VDS = − 25V, f = 1MHz
860 900
pF
Total Gate Chargec Qg 241 230
Gate-Source Chargec Qgs 50 50
Gate-Drain Chargec Qgd
VDS = − 30V, VGS = − 10V, ID = − 110A
60 60
nC
Turn-On Delay Timec td(on) 40 20
Rise Timec tr 29 160
Turn-Off Delay Timec td(off) 235 200
Fall Timec tf
VDD = − 30V, RL = 0.27Ω
ID ≅ − 110A, VGEN = − 10V, RG = 2.5Ω
119 240
ns
Notes
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.
b. Guaranteed by design, not subject to production testing.
c. Independent of operating temperature.
www.vishay.com Document Number: 72665
2 14-Nov-03
SPICE Device Model SUM110P06-07L
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
Document Number: 72665 www.vishay.com
14-Nov-03 3
