MM74HC148N - Fairchild Semiconductor

October 1987

Revised February 1999

MM74HC148 8-3 Line Priority Encoder

MM74HC148

8-3 Line Priority Encoder

General Descript ion

The MM74HC148 priority encoder utilizes advanced sili-

con-gate C MO S techno log y. It has the hig h noise immu ni ty

and low power consumption typical of CMOS circuits, as

wel l as th e speeds and output drive similar to LB -TTL.

This prio ri ty enco de r accepts 8 i n put re que st l ine s 0–7 and

outputs 3 lines A0–A2. The priority encoding ensures that

only the highest order data li ne is e ncoded . Cascad ing c ir-

cuitry (enable input EI and enable output EO) has been

provided to allow octal expansion without the need for

external circuitry. All data inputs and o utputs are active at

the low logic level.

All inputs are protected from damage due to static dis-

charge by internal d iode clamps to VCC and ground.

Features

■Typical propagation delay: 13 ns

■Wide supply voltage range: 2V–6V

Ordering Code:

Devices also available in Tape and R eel. Speci fy by append ing the suffix let t er “X” to the o rdering code.

Connection Diagram

Pin Assignments for DIP, SOIC and TSSOP

Truth Ta ble

H = HIGH

L = LOW

X = Irrelevant

Order Number Package Number Package Description

MM74HC148M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow

MM74HC148MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

MM74HC148N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Inputs Outputs

EI01234567A2A1A0GSEO

HXXXXXXXXH H H H H

LHHHHHHHH H H H H L

LXXXXXXXL L L L L H

LXXXXXXLH L L H L H

LXXXXXLHH L H L L H

LXXXXLHHH L H H L H

LXXXLHHHHH L L L H

L XXLHHHHH H L H L H

L XLHHHHHH H H L L H

L LHHHHHHH H H H L H

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MM74HC148

Schematic Diagram

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MM74HC148

Logic Diagram

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MM74HC148

Absolute Maximum Ratings(No te 1)

(Note 2) Recommended Operation

Conditions

Note 1: Absolute Maximum Ratings are those values beyond which dam-

age to the device may occur.

Note 2: Unle s s ot herwise specified all voltag es are referenced to ground.

Note 3: Powe r D issipat ion tem perature derating—plastic “N” p ac k age: −12

mW/°C from 65°C to 85°C.

DC Electrical Characteristics (Note 4)

Note 4: For a po wer s upply of 5 V ±10% t he worst case ou tput volt ages ( VOH, and VOL) occur f or HC at 4.5V. Thus t he 4.5V values s hould be used w hen

designing with this supply. Worst case VIH and VIL occu r at VCC = 5. 5V and 4.5V resp ec t iv ely. (The VIH value at 5.5V is 3.85V.) The worst case leakage cur-

rent (IIN, ICC, and IOZ) occur fo r C M OS at the higher volt age and so th e 6. 0V valu es s hould be used.

Supply Voltage (VCC)−0.5 to +7.0V

DC Input Voltage (VIN)−1.5 to VCC +1.5V

DC Output Voltage (VOUT)−0.5 to VCC +0.5V

Clamp Diode Current (IIK, IOK)±20 mA

DC Output Current, per pin (IOUT)±25 mA

DC VCC or GND Current, per pin (ICC)±50 mA

Storage Temperature Range (TSTG)−65°C to +150°C

Power Dissipation (PD)

(Note 3) 600 mW

S.O. Package only 500 mW

Lead Temperature (TL)

(Soldering 10 seconds) 26 0°C

Min Max Units

Supply Voltage (VCC)26V

DC Input or Output Voltage

(VIN, VOUT)0V

CC V

Operating Temperature Range (TA)−40 +85 °C

Input Rise or Fall Times

(tr, tf) VCC = 2.0V 1000 ns

VCC = 4.5V 500 ns

VCC = 6.0V 400 ns

Symbol Parameter Conditions VCC TA = 25°CT

A = −40 to 85°CT

A = −55 to 125°CUnits

Typ Guaranteed Limits

VIH Minimum HIGH Level 2.0V 1.5 1.5 1.5 V

Input Voltage 4.5V 3.15 3.15 3.15 V

6.0V 4.2 4.2 4.2 V

VIL Maximum LOW Level 2.0 V 0.5 0.5 0.5 V

Input Voltage 4.5V 1.35 1.35 1.35 V

6.0V 1.8 1.8 1.8 V

VOH Minimum HIGH Level VIN = VIH or VIL

Output Vo ltage |IOUT| ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 V

4.5V 4.5 4.4 4.4 4.4 V

6.0V 6.0 5.9 5.9 5.9 V

VIN = VIH or VIL

|IOUT| ≤ 4.0 mA 4.5V 4.7 3.96 3.84 3.7 V

|IOUT| ≤ 5.2 mA 6.0V 5.2 5.48 5.34 5.2 V

VOL Maximum LOW Level VIN = VIH or VIL

Output Vo ltage |IOUT| ≤ 20 µA 2.0V 0 0.1 0.1 0.1 V

4.5V 0 0.1 0.1 0.1 V

6.0V 0 0.1 0.1 0.1 V

VIN = VIH or VIL

|IOUT| ≤ 4.0 mA 4.5V 0.2 0.26 0.33 0.4 V

|IOUT| ≤ 5.2 mA 6.0V 0.2 0.26 0.33 0.4 V

IIN Maximum Input VIN = VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA

Current

ICC Maximum Quiescent VIN = VCC or GND 6.0V 8.0 80 160 µA

Supply Current IOUT = 0 µA

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MM74HC148

AC Electrical Characteristics

VCC = 2.0V to 6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified)

Note 5: Cpd determines the no load dynamic pow er cons um ption, an d t he no load d y namic cu rrent consumptio n.

Symbol Parameter Conditions Typ Guaranteed

Limits Units

tPHL, tPLH Maximum Propagation Delay, 14 ns

Any Input to Any Output

Symbol Parameter Conditions VCC TA = 25°CT

A = −40°C to +85°CT

A = −55°C to +125°CUnits

Typ Guaranteed Limits

tPHL, tPLH Inputs 0–7 2.0V 140 175 210 ns

to Outputs 4.5V 14 28 35 42 ns

A0, A1, A2 6.0V 24 30 36 ns

tPHL, tPLH Inputs 0–7 2.0V 140 175 210 ns

to 4.5V 15 28 35 42 ns

Output EO 6.0V 24 30 36 ns

tPHL, tPLH Inputs 0–7 2.0V 160 200 240 ns

to 4.5V 17 32 40 48 ns

Output GS 6.0V 27 34 41 ns

tPHL, tPLH Input EI 2.0V 160 200 240 ns

to Outputs 4.5V 17 32 40 48 ns

A0, A1, A2 6.0V 27 34 41 ns

tPHL, tPLH Input EI 2.0V 100 125 150 ns

to 4.5V 12 20 25 30 ns

Output GS 6.0V 17 21 26 ns

tPHL, tPLH Input EI 2.0V 100 125 150 ns

to 4.5V 12 20 25 30 ns

Output EO 6.0V 17 21 26 ns

tf, trMaximum 2.0V 75 95 110 ns

Output Rise 4.5V 7 15 19 22 ns

and Fall Time 6.0V 13 16 19 ns

Cpd Power Dissipation 52 pF

Capacitance (Note 5)

Cin Maximum Input 5 10 10 10 pF

Capacitance

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MM74HC148

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow

Package Number M16A

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MM74HC148

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Packag e Num be r MTC 16

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

MM74HC148 8-3 Line Priority Encoder

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support de vices o r systems a re devices or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical com ponent in any com ponen t of a life supp ort

device or system whose failure to perform can be rea-

sonabl y ex pect ed to ca use the fa i lure of the life su pp ort

device or system, or to affect its safety or effectiveness.

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N16E