AT49F002A(N)(T) - N/A

3354D– FLAS H– 8/0 3

Features

•Single-volt age Operation

–5V Read

– 5V Reprogramming

•Fast Re ad Ac cess Time – 55 ns

•Internal Program Control and Timer

•Sector A rchi tecture

– One 16K Bytes Boot Block with Programming Lockout

– Two 8K Bytes Parameter Blocks

– Four Main Memory Blocks (One 32K Bytes, Three 64K Bytes)

•Fast Erase Cycle Time – 4 Seconds

•Byte-by-Byte Programming – 20 µs/Byte Typical

•Hardware Data Protection

•DATA Polling for End of Program Detection

•Low Power Dissipation

– 25 mA Active Current

– 100 µA CMOS Standby Current

•Typical 10,000 Write Cycles

Description

The AT49F002A(N)(T ) is a 5-volt only in-system re programmable Flash memor y. Its

2 megab its of mem or y is orga nized as 262, 144 words by 8 bits. Manufactured w ith

Atmel’s advanced nonvolatile CMOS technology, the device offers access times to

55 ns with power dissipation of just 137 mW ov er the industrial temperature range.

2-megabit

(256K x 8)

5-volt Only

Flash Memory

AT49F002A

AT49F002AN

AT49F002AT

AT49F002ANT

PLCC Top View

Pin Configurations

Pin Name Function

A0 - A17 Addresses

CE Chip Enable

OE Out put Enable

WE Write Enable

RESET RESET

I/O0 - I/O7 Data Inputs/O utpu ts

I/O0

A14

A13

A11

A10

I/O7

I/O1

I/O2

GND

I/O3

I/O4

I/O5

I/O6

A12

A15

A16

RESET *

VCC

A17

DIP Top View

VSOP Top View (8 x 14 mm) or

TSOP Top View (8 x 20 mm)

Type 1

* RESET

A16

A15

A12

I/O0

I/O1

I/O2

GND

VCC

A17

A14

A13

A11

A10

I/O7

I/O6

I/O5

I/O4

I/O3

A11

A13

A14

A17

VCC

* RESET

A16

A15

A12

A10

I/O7

I/O6

I/O5

I/O4

I/O3

GND

I/O2

I/O1

I/O0

Note: *This pin is a NC on the AT49F002AN(T).

2AT49F002A(N)(T) 3354D–FLASH–8/03

When the device is deselected, the CMOS standby current is less than 100 µA. For the

AT49F002AN(T) pin 1 f or the DIP and PLCC packages and pin 9 f or the TSOP package are no

connect pins.

To al low fo r sim ple i n-sy stem re prog rammabi lity, the A T49F0 02A( N)(T) does not r equi re hig h

input voltages for programmi ng. Five-volt-only commands determine the read and program-

ming operation of the device. Reading data out of the device is similar to reading from an

EPROM; it has standard CE, OE, and WE inputs to avoid bus contention. Reprogramming the

AT49F002A(N)(T) is performed by erasing a block of data and then programming on a byte by

byte bas is. The byte pro gramming tim e is a fast 20 µs. Th e end of a program c ycle can be

option ally detec ted by th e DATA po lling feature. Once the end of a byte program cyc le has

been detected, a new access for a read or program can begin. The typical number of program

and erase cycles is in excess of 10,000 cycles.

The device is erased by executing the erase command sequence; the device internally con-

trols the erase operations. There are two 8K byte parameter block sections, four main memory

blocks, and one boot block.

The devi ce has the c apa bil ity to pr ot ec t the da ta in th e boo t blo ck; thi s fe atur e is en abl ed by a

command sequence. The 16K-byte boot block section includes a reprogramming lock out fea-

ture to pr ovide data int egrity. The boot sector is designe d to contain user se cure code , and

when the feature is enabled, the boot sector is protected from being reprogrammed.

In the A T49F002 A(N)(T), o nce the bo ot block pro grammin g lockout feature i s enabled , the

contents of the boot block are permanent and cannot be changed. In the AT49F002A(T), once

the boot b lock p rogra mming lock out fe ature is en abled , the con tents of th e boot b lock canno t

be changed with input voltage levels of 5.5 volts or less.

Block Diag ram

CONTROL

LOGIC

Y DECODER

PARAMETER

BLOCK 1

(8K BYTES)

BOOT BLOCK

(16K BYTES)

RESET

ADDRESS

INPUTS

VCC

GND

AT49F002A(N)

DATA INPUTS/OUTPUTS

I/O7 - I/O0

X DECODER

PARAMETER

BLOCK 2

(8K BYTES)

MAIN MEMORY

BLOCK 1

(32K BYTES)

MAIN MEMORY

BLOCK 2

(64K BYTES)

MAIN MEMORY

BLOCK 3

(64K BYTES)

MAIN MEMORY

BLOCK 4

(64K BYTES)

PROGRAM

DATA LATCHES

Y-GATING

INPUT/OUTPUT

BUFFERS

1FFFF

10000

0FFFF

08000

3FFFF

30000

2FFFF

20000

07FFF

06000

05FFF

04000

03FFF

00000

PARAMETER

BLOCK 1

(8K BYTES)

BOOT BLOCK

(16K BYTES)

AT49F002A(N)T

DATA INPUTS/OUTPUTS

I/O7 - I/O0

PARAMETER

BLOCK 2

(8K BYTES)

MAIN MEMORY

BLOCK 1

(32K BYTES)

MAIN MEMORY

BLOCK 2

(64K BYTES)

PROGRAM

DATA LATCHES

Y-GATING

INPUT/OUTPUT

BUFFERS

3FFFF

3C000

3BFFF

3A000

39FFF

38000

37FFF

30000

2FFFF

20000

MAIN MEMORY

BLOCK 3

(64K BYTES)

MAIN MEMORY

BLOCK 4

(64K BYTES)

1FFFF

10000

0FFFF

00000

AT49F002A(N)(T)

3354D–FLASH–8/03

Device

Operation READ: The AT49F002A(N)(T) is accessed like an EPROM. When CE and O E are low and

WE is high, the data stored at the memory location determined by the address pins is asserted

on the outputs. The outputs are put in the high impedance state whenever CE or OE is high.

This dual-line control gives designers flexibility in preventing bus contention.

COMMAND S EQUENCES: W hen the d evi ce is first powe red on i t wil l be r ese t to the r ead or

standby mode depending upon the state of th e control line inputs. In or der to perform other

device fu nctio n s, a s er i es o f com mand se que nces are enter ed i nto th e dev ic e. The c om man d

sequences are shown in the Command Definitions table. The command sequences are written

by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high.

The addres s is la tched on th e falling edge of CE or WE, w hichever occu rs last. T he data is

latched b y the firs t rising edge of CE or W E. Stand ard micr opr ocess or write timing s are u sed.

The addres s lo ca tions used in the co mm and s equ enc es are not affe cted by enter ing the c om-

mand sequences.

RESET: A RESET input pin is provided to ease some system applications. When RESET is at

a logic high level, the device is in its standard operating mode. A low level on the RESET input

halts the present device operation and puts the outputs of the device in a high impedance

state. If the RESET pin m ake s a hi gh t o lo w tr ansi tio n dur in g a pr ogra m or er ase o per ati on, the

operatio n may n ot be suc cessfu lly c omple ted and th e opera tion wi ll have to b e repea ted after

a high level is applied to the RESET p in. When a high level is reas serte d on the RES ET pin,

the device returns to the read or standby mode, depending upon the state of the control inputs.

By applying a 12V ± 0.5V input signal to the RESET pin, the boot bl ock array can be repro-

grammed even if the boot block lockout feature has been enabled (see Boot Block

Programming Lockout Override section). The RESET feature is not available for the

AT49F002AN(T).

ERASURE: Befo re a byte can b e repro gramm ed, th e main memo ry b lock or param eter block

which c ontains the by te must be era sed. The erased stat e of the memor y bits is a lo gical “1”.

The entire device can be erased at one time by using a 6-byte software code. The software

chip erase code consists of 6-byte load commands to specific address locations with a specific

data pattern (please refer to the Chip Erase Cycle Waveforms).

After the software chip erase has been initiated, the device will internally time the erase opera-

tion so that no external clocks are requ ired. The maximu m time ne eded to e rase the w hole

chip is tEC. If t he bo ot bl ock l ockou t feat ure has been enab led, the data in the b oot sec tor will

not be erased.

CHIP ERASE : If the boot block lockout has been enabled, the Chip Erase function will erase

Parameter Block 1, Parameter Block 2, Main Memory Block 1-4 but not the boot block. If the

Boot Block Lockout has not been enabled, the Chip Erase function will erase the entire chip.

After the full chip erase the device will return back to read mode. Any command during c hip

erase will be ignored.

4AT49F002A(N)(T) 3354D–FLASH–8/03

SECTOR ERASE: As an alternative to a full chip erase, the device is organized into sectors

that can be individually erased. There are two 8K-byte parameter block sections and four main

memory blocks . T he 8K-b yte paramet er bl ock sect ions and th e fo ur main me mory b locks can

be independently erased and reprogrammed. The Sector Erase command is a six bus cycle

operation. The sector ad dress is l atched on the falling WE edge of the sixth cy cle while t he

30H data in put co mma nd is lat che d at the ris ing edge of WE. The se ct or erase s tar ts after the

rising edge of WE of the sixth cycle. The erase operation is internally c ontrolled; it will auto-

matically time to completion.

BYTE PROGRAMMING: Once the memory array is erased, the device is programmed (to a

logical “0”) on a byte-by-byte basis. Please note that a data “0” cannot be programmed back to

a “1” ; only erase op eratio ns can conve rt “0”s t o “1”s . Prog ramming is ac compli shed v ia the

internal device command register and is a 4 bus cycle operation (please refer to the Command

Definitions table). The device will automatically generate the required internal program pulses.

The prog ram cycle has add resses latch ed on the fal ling edge of WE or CE, whic hever oc curs

last, and the data l atched on the rising edge of WE or CE, whichever occurs fir st. Program-

ming is completed after the specified tBP cycle time. The DATA polling feature may also be

used to indicate the end of a program cycle.

BOOT BLOCK PROGRAMMING LOCKOUT: The devic e has one desi gnated bl ock that has

a progra mmin g lockou t feature. This fe ature pre vents pr ogrammi ng of data in the des ignate d

block once the feature has been enabled. The size of the block is 16K bytes. This block,

refer red to as th e boot block , can cont ain secur e code that i s used to bri ng up the s ystem.

Enabling the lockout feature will allow the boot code to stay in the device while data in the rest

of the device is updated. This feature does not have to be activated; the boot block’s usage as

a write pr otected reg ion is opt ional to the use r. The addr ess range of the boot block is 00000

to 03FFF for the AT49F002A(N) while the address range of the boot block is 3C000 to 3FFFF

for the AT49F002A(N)T.

Once the feature is enabled, the data in the boot block can no longer be erased or pro-

grammed with inp ut volt age level s of 5.5V or less . Data in th e main m emory bl ock can s till be

changed through the regular programming method. To activate the lockout feature, a series of

six pro gram commands to specific addresses with specific data must b e performed. Pl ease

refer to the Command Definitions table.

BOOT BLOCK LO CKOUT DETECTIO N: A software method is available to determine if pro-

gramm ing of th e boot bl ock sec tion i s locke d out. Wh en th e device is in th e softwa re produ ct

identification mode (see Software Product Identification Entry and Exit sections) a read from

address location 00002H will show if programming the boot block is locked out for the

AT49F0 02A(N), an d a read from ad dress loc ation 3C0 02H will sho w if program ming the boo t

block is locked out for AT49F002A(N)T. If the data on I/O0 is low, the boot block can be pro-

grammed ; if t he dat a on I /O0 i s high , the p rogram loc kout featu re h as be en acti vated and th e

block c annot be prog ramme d. The softwa re produc t identi fica tion exit co de shou ld be use d to

return to standard operation.

AT49F002A(N)(T)

3354D–FLASH–8/03

BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE: The user can override the boot

block progr ammi ng lock out by taking the RES ET pin to 12 v olts. By doi ng thi s, p ro tec ted bo ot

block d ata ca n be al ter ed through a ch ip erase, s ec tor e rase or word pr ogr am mi ng. Whe n th e

RESET pin i s b rough t back to T TL le ve ls the bo ot bl oc k progr am mi ng l ock out featu re is a gai n

active. This feature is not available on the AT49F002AN(T).

PRODUCT IDENTIFICATION: The pr odu ct identific atio n mo de i dent ifi es the de vi ce and m an-

ufacturer as Atmel. It may be accessed by hardware or software operation. The hardware

operation mode can be used by an external programmer to identify the correct programming

algorithm for the Atmel product.

For deta ils, see Ope rating Mod es (for hardwar e operation) or Software Pr oduct Ide ntificatio n.

The manufacturer and device code is the same for both modes.

DATA POLLING: The AT49F 002A(N)(T) features DATA poll ing to indicate the end of a pr o-

gram cycl e. Du ring a p ro gr am cyc le an att empted rea d of the last by te l oade d wil l res ult in the

complem ent of the loaded d ata on I/O 7. Once the program cycle h as been completed, true

data is val id on al l ou tput s and the n ext c ycle may begin. DATA polling may begin at any time

during the program cycle.

TOGGLE BIT: In addition to DATA polli ng the AT49F 002A(N)(T ) provid es another me thod for

determining the end of a program or erase cycle. During a program or erase operation, suc-

cessive attempts to read data from the device will result in I/O6 toggling between one and

zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be

read. Examining the toggle bit may begin at any time during a program cycle.

HARDWARE DATA PROTECTION : Hardware featur es pr otect agai nst inad verte nt pro grams

to the AT49F002A(N)(T) in the following ways: (a) VCC sense: if VCC is below 3.8V (typical), the

program function is inhibited. (b) Program inhibit: holding any one of OE low, CE high or WE

high inhibits program cycles. (c) Noise filter: pulses of less than 15 ns (typical) on the WE or

CE inputs will not initiate a program cycle.

6AT49F002A(N)(T) 3354D–FLASH–8/03

Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O7 - I/O0 (Hex). The address format in each bus cycle is as follows:

A11 - A0 (Hex); A11 - A17 (don’t care).

2. Since A11 is don’t care, AAA can be replaced wi th 2AA.

3. The 16K byte boot sector has the address range 00000H to 03FFFH for the AT49F002A(N) and 3C000H to 3FFFFH for the

AT49F002A(N)T

4. Either one of the Product ID Exit commands can be used.

5. SA = sector addresses:

For the AT49F002A(N ):

SA = 00000 to 03FFF for BOOT BLOCK

SA = 04000 to 05FFF for PARAMETER BLOCK 1

SA = 06000 to 07FFF for PARAMETER BLOCK 2

SA = 08000 to FFFF for MAIN MEMORY ARRAY BLOCK 1

SA = 10000 to 1FFFF for MAIN MEMORY ARRAY BLOCK 2

SA = 20000 to 2FFFF for MAIN MEMORY ARRAY BLOCK 3

SA = 30000 to 3FFFF for MAIN MEMORY ARRAY BLOCK 4

For the AT49F002A(N )T:

SA = 3C000 to 3FFFF for BOOT BLOCK

SA = 3A000 to 3BFFF for PARAMETER BLOCK 1

SA = 38000 to 39FFF for PARAMETER BLOCK 2

SA = 30000 to 37FFF for MAIN MEMORY ARRAY BLOCK 1

SA = 20000 to 2FFFF for MAIN MEMORY ARRAY BLOCK 2

SA = 10000 to 1FFFF for MAIN MEMORY ARRAY BLOCK 3

SA = 00000 to 0FFFF for MAIN MEMORY ARRAY BLOCK 4

Command Definition (in Hex )(1)

Command

Sequence Bus

Cycles

1st Bus

Cycle 2nd Bus

Cycle 3rd Bus

Cycle 4th Bus

Cycle 5th Bus

Cycle 6th Bus

Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read 1Addr DOUT

Chip Erase 6555 AA AAA(2) 55 555 80 555 AA AAA 55 555 10

Sector Erase 6555 AA AAA 55 555 80 555 AA AAA 55 SA(5) 30

Byte Program 4555 AA AAA 55 555 A0 Addr DIN

Boot Block Lockout(3) 6555 AA AAA 55 555 80 555 AA AAA 55 555 40

Prod u ct ID En try 3555 AA AAA 55 555 90

Prod u ct ID Exi t(4) 3555 AA AAA 55 555 F0

Prod u ct ID Exi t(4) 1XXXX F0

Absolute Maxim u m Ratings*

Temperature Under Bias................................ -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute Maxi-

mum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional

operation of the device at these or any other condi-

tions beyond those indicated in the operational sec-

tions of this specification is not implied. Exposure to

absolute maximum rating conditions for extended

periods may affect device rel iab ili ty.

Storage Temperature..................................... -65°C to +150°C

All Input Voltages

(including NC Pins)

with Respect to Ground...................................-0.6V to +6.25V

All Output Voltages

with Respect to Ground.............................-0.6V to VCC + 0.6V

Voltage on OE

with Respect to Ground...................................-0.6V to +13.5V

AT49F002A(N)(T)

3354D–FLASH–8/03

Notes: 1. X can be VIL or VIH.

2. Refer to AC P rogramming Waveforms.

3. VH = 12.0V ± 0.5V.

4. Manufacturer Code: 1FH, Device Code: 07H - AT49F002A(N), 08H - AT49F002A(N)T

5. See details under Software Product Identification Entry/Exit.

6. This pin is not a vailable on the AT49F00 2AN(T).

Note: 1. In the erase mode, ICC is 90 mA.

DC and AC Operating Range

AT49F002A(N)(T)-55

Operating

Temperature (Case) Ind. -40°C - 85°C

VCC Power Supply 5V ± 10%

Operating Modes

Mode CE OE WE RESET(6) Ai I/O

Read VIL VIL VIH VIH Ai DOUT

Program/Erase(2) VIL VIH VIL VIH Ai DIN

Standby/Write Inhibit VIH X(1) X VIH XHigh Z

Program Inhibit X X VIH VIH

X VIL X VIH

Output Disable X VIH X VIH High Z

Reset X X X VIL XHigh Z

Product Identification

Hardware VIL VIL VIH A1 - A17 = VIL, A9 = VH,(3) A0 = VIL Manufacturer Code(4)

A1 - A17 = VIL, A9 = VH,(3) A0 = VIH Device Code(4)

Software(5) A0 = VIL, A1 - A17=VIL Manufacturer Code(4)

A0 = VIH, A1 - A17=VIL Device Code(4)

DC Characteristics

Symbol Parameter Condition Min Max Units

ILI Input Load Current VIN = 0V to V CC 10 µA

ILO Output Leakage Current VI/O = 0V to VCC 10 µA

ISB1 VCC Standby Current CMOS CE = V CC - 0.3V to VCC 100 µA

ISB2 VCC Standby Current TTL CE = 2.0V to VCC 3mA

ICC(1) VCC Active Current f = 5 MHz; IOUT = 0 mA 25 mA

VIL Input Low Voltage 0.8 V

VIH Input High Voltage 2.0 V

VOL Output Low Vo ltage IOL = 2.1 mA 0.45 V

VOH1 Output High Voltage IOH = -400 µA 2.4 V

VOH2 Output High Voltage CMOS IOH = -100 µA; VCC = 4.5V 4.2 V

8AT49F002A(N)(T) 3354D–FLASH–8/03

AC Read Waveforms (1)(2)(3)(4)

Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.

2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on t CE or by tACC - tOE after an address change

without impact on tACC.

3. tDF is specifie d f ro m OE or CE whichever occurs first (CL = 5 pF).

4. This parameter is characterized and is not 100% tested.

AC Read Characteristics

Symbol Parameter

AT49F002A(N)(T)-55

UnitsMin Max

tACC Address to Output Delay 55 ns

tCE(1) CE to Output Delay 55 ns

tOE(2) OE to Output Delay 030 ns

tDF(3)(4) CE or OE to Output Float 025 ns

tOH Output Hold from OE, CE or Address, whichever

occurred firs t 0ns

ADDRESS

OUTPUT

HIGH Z

OUTPUT

ACC

VALID

ADDRESS VALID

AT49F002A(N)(T)

3354D–FLASH–8/03

Input Test W aveform and Measurement Level

tR, tF < 5 ns

Output Load Test

Note: 1. This parameter is characterized and is not 100% tested.

55 ns

5.0V

1.8K

30 pF

OUTPUT

1.3K

Pin Capacitance

f = 1 MHz, T = 25°C(1)

Symbol Typ Max Units Conditions

CIN 4 6 pF VIN = 0V

COUT 812 pF VOUT = 0V

10 AT49F002A(N)(T) 3354D–FLASH–8/03

AC Byte Load Waveforms

WE Controlled

CE Controlled

AC Byte Load Characteristics

Symbol Parameter Min Max Units

tAS, tOES Address, OE Set-up Time 0ns

tAH Address H old Time 25 ns

tCS Chip Select Set-up Time 0ns

tCH Chip Select Hold Time 0ns

tWP Write Pulse Width (WE or CE)25 ns

tDS Data Set-up Time 25 ns

tDH, tOEH Data, OE Hold Time 0ns

tWPH Write Pulse Width High 20 ns

tDH

tDS

tAS tAH

tWP

ADDRESS

DATA IN

OE tOES tOEH

WE tCS

tCH

tWPH

tDH

tDS

tAS tAH

tWP

ADDRESS

DATA IN

OE tOES tOEH

CE tCS

tCH

tWPH

AT49F002A(N)(T)

3354D–FLASH–8/03

Program Cycle Waveforms

Sector or Chip Erase Cycle Waveforms

Notes: 1. OE must be hi gh only when WE and CE are both low.

2. For chip erase, the address should be 555. For sector erase, the address depends on what sector is to be erased.

(See note 4 under command definitions.)

3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.

Program Cycle Characteristics

Symbol Parameter Min Typ Max Units

tBP Byte Progr am ming Time 20 50 µs

tAS Address Set-u p Time 0ns

tAH Address H old Time 25 ns

tDS Data Set-up Time 25 ns

tDH Data Hold Time 0ns

tWP Write Pulse Widt h 25 ns

tWPH Write Pulse Width High 20 ns

tEC Erase Cyc le Tim e 4 8 seconds

12 AT49F002A(N)(T) 3354D–FLASH–8/03

Notes: 1. These parameters are characterized and not 100% tested.

2. See t OE spec i n AC Read C haracteristics.

Data Polling Wavef orms

Notes: 1. These parameters are characterized and not 100% tested.

2. See t OE spec i n AC Read C haracteristics.

Toggle Bit Waveforms(1)(2)(3)

Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling

input(s).

2. Beginning and ending state of I/O6 will vary.

3. Any address location may be used but the address should not vary.

Data Polling Characteristics(1)

Symbol Parameter Min Typ Max Units

tDH Data Hold Time 10 ns

tOEH OE Hold Time 10 ns

tOE OE to Output Delay(2) ns

tWR Write Recovery Time 0ns

HIGH Z

An An An An An

I/O7

A0-A17

OEH

Toggle Bit Characteristic s (1)

Symbol Parameter Min Typ Max Units

tDH Data Hold Time 10 ns

tOEH OE Hold Time 10 ns

tOE OE to Output Delay(2) ns

tOEHP OE High Pulse 50 ns

tWR Write Recovery Time 0 ns

I/O6

tOEH

HIGH Z

tDH tOE

tWR

tOEHP

AT49F002A(N)(T)

3354D–FLASH–8/03

Software Product Identification

Entry(1)

Software Product Identification Exit(1)

Notes: 1. Data Format: I/O7 - I/O0 (Hex);

Address Format: A14 - A0 (Hex).

2. A1 - A17 = VIL.

Manufa cture Code is read for A0 = VIL;

Device Code is read for A0 = VIH.

Additional Device Co de is read for address 0003H

3. The device does not remain in identification mode

if powered down.

4. The device returns to standard operation mode.

5. Manufacturer Code: 1FH

Device Code: 07H - AT49F002A(N)

08H - AT49F002A(N)T

Additional Device Code: 0FH - AT49F002A (N)(T)

LOAD DATA AA

ADDRESS 555

LOAD DATA 55

ADDRESS AAA

LOAD DATA 90

ADDRESS 555

ENTER PRODUCT

IDENTIFICATION

MODE

(2)(3)(5)

LOAD DATA AA

ADDRESS 555

LOAD DATA 55

ADDRESS AAA

LOAD DATA F0

ADDRESS 555

EXIT PRODUCT

IDENTIFICATION

MODE(4)

LOAD DATA F0

ANY ADDRESS

EXIT PRODUCT

IDENTIFICATION

MODE(4)

Boot Block Lockout Feature Enable

Algorithm(1)

Notes: 1. Data Format: I/O7 - I/O0 (Hex);

Address Format: A14 - A0 (Hex).

2. Boot block lockout feature enabled.

LOAD DATA AA

ADDRESS 555

LOAD DATA 55

ADDRESS AAA

LOAD DATA 80

ADDRESS 555

LOAD DATA AA

ADDRESS 555

LOAD DATA 55

ADDRESS AAA

LOAD DATA 40

ADDRESS 555

PAUSE 1 second

(2)

14 AT49F002A(N)(T) 3354D–FLASH–8/03

AT49F002A Ordering Info rmation

tACC

(ns)

ICC (mA)

Ordering Code Package Operation RangeActive Standby

55 25 0.1 AT49F002A-55JI

AT49F002A-55PI

AT49F002A-55TI

AT49F002A-55VI

32J

32P6

32T

32V

Industrial

(-40° to 85°C)

AT49F002AN Ordering Information

tACC

(ns)

ICC (mA)

Ordering Code Package Operation RangeActive Standby

55 25 0.1 AT49F002AN-55JI

AT49F002AN-55PI

AT49F002AN-55TI

AT49F002AN-55VI

32J

32P6

32T

32V

Industrial

(-40° to 85°C)

AT49F 0 02 AT Order ing In format i on

tACC

(ns)

ICC (mA)

Ordering Code Package Operation RangeActive Standby

55 25 0.1 AT49F002AT-55JI

AT49F002AT-55PI

AT49F002AT-55TI

AT49F002AT-55VI

32J

32P6

32T

32V

Industrial

(-40° to 85°C)

AT49F002ANT Ordering Information

tACC

(ns)

ICC (mA)

Ordering Code Package Operation RangeActive Standby

55 25 0.1 AT49F002ANT-55JI

AT49F002ANT-55PI

AT49F002ANT-55TI

AT49F002ANT-55VI

32J

32P6

32T

32V

Industrial

(-40° to 85°C)

Package Type

32J 32-lead, Plastic J-leaded Chip Carrier Package (PLCC)

32P6 32-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP)

32T 32-lea d, Pl astic Thin Small Outline Package (TSOP) (8 x 20 mm)

32V 32-lea d, Pl astic Thi n Small Outline Package (VSOP) (8 x 14 mm)

AT49F002A(N)(T)

3354D–FLASH–8/03

Packaging Informa t ion

32J – PLCC

DRAWING NO. REV.

2325 Orchard Parkway

San Jose, CA 95131

TITLE

32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) B

32J

10/04/01

1.14(0.045) X 45˚ PIN NO. 1

IDENTIFIER 1.14(0.045) X 45˚

0.51(0.020)MAX

0.318(0.0125)

0.191(0.0075)

45˚ MAX (3X)

B1 E2

E1 E

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

Notes: 1. This package conforms to JEDEC reference MS-016, Variation AE.

2. Dimensions D1 and E1 do not include mold protrusion.

Allowable protrusion is .010"(0.254 mm) per side. Dimension D1

and E1 include mold mismatch and are measured at the extreme

material condition at the upper or lower parting line.

3. Lead coplanarity is 0.004" (0.102 mm) maximum.

A 3.175 – 3.556

A1 1.524 – 2.413

A2 0.381 – –

D 12.319 – 12.573

D1 11.354 – 11.506 Note 2

D2 9.906 – 10.922

E 14.859 – 15.113

E1 13.894 – 14.046 Note 2

E2 12.471 – 13.487

B 0.660 – 0.813

B1 0.330 – 0.533

e 1.270 TYP

16 AT49F002A(N)(T) 3354D–FLASH–8/03

32P6 – PDIP

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

32P6, 32-lead (0.600"/15.24 mm Wide) Plastic Dual

Inline Package (PDIP) B

32P6

09/28/01

REF

SEATING PLANE

0º ~ 15º

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A – – 4.826

A1 0.381 – –

D 41.783 – 42.291 Note 1

E 15.240 – 15.875

E1 13.462 – 13.970 Note 1

B 0.356 – 0.559

B1 1.041 – 1.651

L 3.048 – 3.556

C 0.203 – 0.381

eB 15.494 – 17.526

e 2.540 TYP

Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion.

Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").

AT49F002A(N)(T)

3354D–FLASH–8/03

32T – TSOP

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

32T, 32-lead (8 x 20 mm Package) Plastic Thin Small Outline

Package, Type I (TSOP) B

32T

10/18/01

PIN 1

D1 D

Pin 1 Identifier

0º ~ 8º c

GAGE PLANE

SEATING PLANE

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

Notes: 1. This package conforms to JEDEC reference MO-142, Variation BD.

2. Dimensions D1 and E do not include mold protrusion. Allowable

protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.

3. Lead coplanarity is 0.10 mm maximum.

A – – 1.20

A1 0.05 – 0.15

A2 0.95 1.00 1.05

D 19.80 20.00 20.20

D1 18.30 18.40 18.50 Note 2

E 7.90 8.00 8.10 Note 2

L 0.50 0.60 0.70

L1 0.25 BASIC

b 0.17 0.22 0.27

c 0.10 – 0.21

e 0.50 BASIC

18 AT49F002A(N)(T) 3354D–FLASH–8/03

32V – VSOP

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

32V, 32-lead (8 x 14 mm Package) Plastic Thin Small Outline

Package, Type I (VSOP) B

32V

10/18/01

PIN 1

D1 D

Pin 1 Identifier

0º ~ 8º c

GAGE PLANE

SEATING PLANE

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

Notes: 1. This package conforms to JEDEC reference MO-142, Variation BA.

2. Dimensions D1 and E do not include mold protrusion. Allowable

protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.

3. Lead coplanarity is 0.10 mm maximum.

A – – 1.20

A1 0.05 – 0.15

A2 0.95 1.00 1.05

D 13.80 14.00 14.20

D1 12.30 12.40 12.50 Note 2

E 7.90 8.00 8.10 Note 2

L 0.50 0.60 0.70

L1 0.25 BASIC

b 0.17 0.22 0.27

c 0.10 – 0.21

e 0.50 BASIC

Printed on recycled paper.

3354D–FLASH–8/03 xM

Disclaimer: Atmel Cor poration makes no warranty for the use of its produc ts, other than those expressly contained in t he Company’s standard

warranty which is detailed in Atmel’s Ter ms and Conditions located on the Company’s web site. The Company assumes no responsibility for any

errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and

does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are

granted by the Company in connection with the sale of Atmel produc ts, expressly or by implication. Atmel’s products are not aut horized for use

as critical components in life suppor t devices or systems.

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Tel: 1(408) 441-0311

Fax: 1(408) 487-2600

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Fax: 1(719) 540-1759

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East Kilbride G75 0QR, Scotland

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