LM49251
LM49251 Stereo Audio Subsystem with Class G Headphone Amplifier and Class
DSpeaker Amplifier with Speaker Protection
Literature Number: SNAS498
LM49251 February 8, 2011
Stereo Audio Subsystem with Class G Headphone
Amplifier and Class D Speaker Amplifier with Speaker
Protection
General Description
The LM49251 is a fully integrated audio subsystem designed
for portable handheld applications such as cellular phones.
Part of National’s PowerWise family of products, the
LM49251 utilizes a high efficiency class G headphone ampli-
fier topology as well as a high efficiency class D loudspeaker.
The headphone amplifiers feature National’s class G ground
referenced architecture that creates a ground-referenced out-
put with dynamic supply rails for optimum efficiency. The
stereo class D speaker amplifier provides both a no-clip fea-
ture and speaker protection. The Enhanced Emission Sup-
pression (E2S) outputs feature a patented, ultra low EMI PWM
architecture that significantly reduces RF emissions.
The LM49251 features separate volume controls for the mono
and stereo inputs. Mode selection, shutdown control, and vol-
ume are controlled through an I2C compatible interface.
Click and pop suppression eliminates audible transients on
power-up/down and during shutdown. The LM49251 is avail-
able in an ultra-small 30-bump micro SMD package
(2.55mmx3.02mm)
Key Specifications
■ Class G Headphone Amplifier, HPVDD = 1.8V, RL = 32Ω
IDDQHP
Output Power, THD+N ≤ 1%
1.15mA (typ)
20mW (typ)
■ Stereo Class D Speaker Amplifier RL = 8Ω
Output Power, THD+N ≤ 1%,
LSVDD = 5.0V 1.37W (typ)
Output Power, THD+N ≤ 1%,
LSVDD = 3.6V 680mW (typ)
Efficiency 90% (typ)
Features
■Class G Ground Referenced Headphone Outputs
■E2S Class D Amplifier
■No Clip Function
■Power Limiter Speaker Protection
■I2C Volume and Mode Control
■Advanced Click-and-Pop Suppression
■Micro-power shutdown
Applications
■Feature Phones
■Smart phones
Simplified Block Diagram
30121825
FIGURE 1. LM49251 Simplified Block Diagram
Boomer® is a registered trademark of National Semiconductor Corporation.
© 2011 National Semiconductor Corporation 301218 www.national.com
LM49251 Stereo Audio Subsystem with Class G Headphone Amplifier and Class D Speaker
Amplifier with Speaker Protection
Typical Application
30121826
FIGURE 2. Typical Audio Amplifier Application Circuit
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LM49251
Connection Diagrams
30121861
Top View
Order Number LM49251TL
See NS Package Number TLA30B1A
30 – Bump micro SMD Marking
30121850
Top View
XY = Date Code
TT = Die Traceability
G = Boomer Family
N9 = LM49251TL
Ordering Information
Order Number Package Package DWG # Transport Media MSL Level Green Status
LM49251TL Micro SMD TLA30B1A 250 units on tape and reel 1 RoHS
LM49251TLX Micro SMD TLA30B1A 3000 units on tape and reel 1 RoHS
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LM49251
TABLE 1. Bump Description
Bump Name Description
A1 I2CVDD I2C Power Supply
A2 GND Ground
A3 INM+ Mono Channel Non-Inverting Input
A4 VDD Loudspeaker Power Supply
A5 LSOUTR+ Right Loudspeaker Non-Inverting Output
B1 VDD Loudspeaker Power Supply
B2 SDA I2C Serial Data Input
B3 INM- Mono Channel Inverting Input
B4 RIN2 Right Channel Input 2
B5 LSOUTR- Right Loudspeaker Inverting Output
C1 CPVDD Charge Pump Supply (internally generated)
C2 SCL I2C Serial Clock Input
C3 RIN1 Right Channel Input 1
C4 LIN2 Left Channel Input 2
C5 GND Ground
D1 HPR Right Channel Headphone Output
D2 C1- Charge Pump Flying Capacitor Negative Terminal
D3 LIN1 Left Channel Input 1
D4 BYPASS Mid-Rail Bias Bypass Node
D5 GND Ground
E1 HPL Left Channel Headphone Output
E2 C1+ Charge Pump Flying Capacitor Positive Terminal
E3 HP SENSE GND Headphone Ground Sense
E4 SET ALC Timing Set
E5 LSOUTL- Left Loudspeaker Inverting Output
F1 CPGND Charge Pump Ground
F2 HPVDD Headphone Power Supply
F3 CPVSS Charge Pump Output
F4 VDD Loudspeaker Power Supply
F5 LSOUTL+ Left Loudspeaker Non-Inverting Output
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LM49251
Absolute Maximum Ratings (Note 1, Note
2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (Note 1)
VDD, I2CVDD 6V
HPVDD 3V
Storage Temperature −65°C to +150°C
Input Voltage −0.3V to VDD +0.3V
Power Dissipation (Note 3) Internally Limited
ESD HBM(Note 4) 2000V
ESD MM(Note 5) 150V
ESD CDM (Note 10) 750V
Junction Temperature 150°C
Thermal Resistance
θJA (TLA30B1A) 90°C/W
Soldering Information
See AN-1112 “Micro SMD Wafer Level Chip Scale
Package”
Operating Ratings
Temperature Range
TMIN ≤ TA ≤ TMAX −40°C ≤ TA ≤ +85°C
Supply Voltage
VDD 2.7V ≤ VDD ≤ 5.5V
HPVDD 1.6V ≤ HPVDD ≤ 2.0V
I2CDD 1.7V ≤ I2CVDD ≤ 5.5V
Electrical Characteristics (Note 1, Note 2) The following specifications apply for AV = 0dB, RL = 15μH+8Ω
+15μH (Loudspeaker), RL = 32Ω (Headphone), CSET = 100nF, f = 1kHz, ALC off, unless otherwise specified. Limits apply for TA =
25°C.
Symbol Parameter Conditions
LM49251 Units
(Limits)
Typical Limit
(Note 6) (Note 7)
IDD
Quiescent Power Supply Current
(LSVDD + VDD)
VIN = 0, No Load
LS Mode (stereo input), mode 2 5.6 6.25 mA (max)
LS Mode (mono input), mode 3 5.3 6.0 mA (max)
HP Mode (stereo input), mode 6 2.1 2.4 mA (max)
HP Mode (mono input), mode 4 1.8 2.0 mA (max)
LS+HP Mode (stereo input), mode 8 6.1 6.8 mA (max)
LS+HP Mode (mono input), mode 5 5.8 6.5 mA (max)
LS Mode (stereo input, ALC on), mode 2 5.9
IDD(HP)
Quiescent Power Supply Current
(HPVDD)
VIN = 0, No Load
Mode 6 1.15 1.45 mA (max)
Operating Power Supply Current
(HPVDD)
POUT = 0.5mW, GAMP_SD = 0,
RL = 32Ω, Mode 6 4.3 4.6 mA (max)
POUT = 1mW, GAMP_SD = 0,
RL = 32Ω, Mode 6 5.8 6.15 mA (max)
ISD Shutdown Current 0.02 1 μA (max)
VOS Output Offset Voltage
VIN = 0
Mode 3, mono input, AV = 6dB
Mode 4, mono input
Mode 2, stereo input, AV = 6dB
Mode 6, stereo input
12
1.1
12
1.1
mV (max)
mV (max)
mV (max)
mV (max)
TWU Wake Up Time
HP mode, CBYPASS = 2.2μF
Normal turn on time 31 ms
Fast turn on time 16 ms
AVOL Volume Control
Minimum Gain Setting (mono input),
Mode 3 –86 dB (max)
dB (min)
Maximum Gain Setting (mono input),
Mode 3 12 13
11.5
dB (max)
dB (min)
Minimum Gain Setting (stereo input),
Mode 6 –80 dB (max)
dB (min)
Maximum Gain Setting (stereo input),
Mode 6 18 19
17.5
dB (max)
dB (min)
Volume Control Step Error ±0.2 dB
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LM49251
Symbol Parameter Conditions
LM49251 Units
(Limits)
Typical Limit
(Note 6) (Note 7)
AVGain
LS Mode
Gain 0 12 11.5
12.5
dB (min)
dB (max)
Gain 1 18 17.5
19
dB (min)
dB (max)
HP Mode
Gain 0 0 –0.5
0.5
dB (min)
dB (max)
Gain 1 –1.7 dB
Gain 2 –3 dB
Gain 3 –6 dB
Gain 4 –9 dB
Gain 5 –12 dB
Gain 6 –15 dB
Gain 7 –18 –18.5
–17.5
dB (min)
dB (max)
AV(MUTE) Mute Attenuation LS Output
HP Output
–93
–98 dB
dB
RIN Input Resistance
MONO, RIN, LIN inputs
Maximum Gain Setting 13 9.5
15.5
kΩ min)
kΩ (max)
Minimum Gain Setting 110 97
122
kΩ (min)
kΩ (max)
POOutput Power
Mode 3, AV = 18dB, RL = 8Ω
LSVDD = 3.3V 570 mW
LSVDD = 3.6V 680 600 mW (min)
LSVDD = 4.2V 955 mW
LSVDD = 5.0V 1370 mW
Mode 6
RL = 16Ω 20 mW
RL= 32Ω 20 16 mW (min)
THD+N Total Harmonic Distortion + Noise
f = 1kHz, Mode 3
Mono Input, PO = 250mW 0.02 %
f = 1kHz, Mode 6
Stereo Input, PO = 12mW 0.02 %
PSRR Power Supply Rejection Ratio
f = 217Hz, VRIPPLE = 200mVP-P,
Inputs AC GND, CB = 2.2μF
Mode 3, mono input, AV = 6dB 77 dB
Mode 2, stereo input, AV = 6dB 65 dB
Mode 4, ripple on VDD,
mono input 93 dB
Mode 4, ripple on HPVDD,
mono input 83 dB
Mode 6, ripple on VDD,
stereo input 80 dB
Mode 6, ripple on HPVDD,
stereo input 80 dB
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LM49251
Symbol Parameter Conditions
LM49251 Units
(Limits)
Typical Limit
(Note 6) (Note 7)
CMRR Common Mode Rejection Ratio
VRIPPLE = 1VP-P, fRIPPLE = 217Hz, mono input
Mode 3
Mode 4
52
63 dB
dB
ηEfficiency LS Mode, PO = 680mW 90 %
XTALK Crosstalk PO = 12mW, f = 1kHz, Mode 6 84 dB
∈OS Output Noise
A-weighted, Inputs AC GND
Mode 3, mono input
Mode 2, stereo input
Mode 4, mono input
Mode 6, stereo input
44
45
8
10.2
μV
μV
μV
μV
SNR Signal-To-Noise-Ratio Mode 3, PO = 680mW
Mode 6, PO = 20mW
94
98
dB
dB
tAAttack Time Step 1, Mode 1 0.75 ms
tRRelease Time Step 1, Mode 1 1 s
VLIMIT Output Voltage Limit
Mode 3, THD+N ≤ 1%, Note 9
Voltage Level
Step 1 001
Step 2 010
Step 3 011
Step 4 100
Step 5 101
Step 6 110
3.9
4.7
5.4
6.2
7.0
7.8
VP-P
VP-P
VP-P
VP-P
VP-P
VP-P
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LM49251
I2C Interface Characteristics VDD = 5V, 2.2V ≤ I2CVDD ≤ 5.5V (Note 1, Note 2)The following
specifications apply for AV = 0dB, RL = 8Ω, f = 1kHz, unless otherwise specified. Limits apply for TA = A = 25°C.
Symbol Parameter Conditions
LM49251 Units
(Limits)
Typical Limit
(Note 6) (Note 7)
t1SCL Period 2.5 μs (min)
t2SDA Set-up Time 100 ns (min)
t3SDA Stable Time 0 ns (min)
t4Start Condition Time 100 ns (min)
t5Stop Condition Time 100 ns (min)
t6SDA Hold time 100 ns (min)
VIH Input High Voltage 0.7*I2CVDD V (min)
VIL Input Low Voltage 0.3*I2CVDD V (max)
I2C Interface Characteristics VDD = 5V, 1.8V ≤ I2CVDD ≤ 2.2V (Note 1, Note 2)The following
specifications apply for AV = 0dB, RL = 8Ω, f = 1kHz, unless otherwise specified. Limits apply for TA = 25°C.
Symbol Parameter Conditions
LM49251 Units
(Limits)
Typical Limit
(Note 6) (Note 7)
t1SCL Period 2.5 μs (min)
t2SDA Set-up Time 250 ns (min)
t3SDA Stable Time 0 ns (min)
t4Start Condition Time 250 ns (min)
t5Stop Condition Time 250 ns (min)
t6SDA Hold Time 250 ns (min)
VIH Digital Input High Voltage 0.7*I2CVDD V (min)
VIL Digital Input Low Voltage 0.3*I2CVDD V (max)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified
Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum
allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings, whichever is lower.
Note 4: Human body model, applicable std. JESD22-A114C.
Note 5: Machine model, applicable std. JESD22-A115-A.
Note 6: Typical values represent most likely parametric norms at TA = +25ºC, and at the Recommended Operation Conditions at the time of product
characterization and are not guaranteed.
Note 7: Datasheet min/max specification limits are guaranteed by test or statistical analysis.
Note 8: Loudspeaker RL is a resistive load in series with two inductors to simulate an actual speaker load. For RL = 8Ω, the load is 15μH + 8Ω +15μH. For RL =
4Ω, the load is 15μH + 4Ω + 15μH.
Note 9: The LM49251 ALC limits the output power to which ever is lower, the supply voltage or output power limit.
Note 10: Charge device model, applicable std. JESD22–C101D.
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LM49251
Typical Performance Characteristics
THD+N vs Frequency
VDD = 3.6V, RL = 15μH+8Ω+15μH
POUT = 450mW, Mode 2
30121865
THD+N vs Frequency
VDD = 3.6V, RL = 15μH+8Ω+15μH
POUT = 450mW, Mode 3
30121866
THD+N vs Frequency
VDD = 3.6V, RL = 15μH+4Ω+15μH
POUT = 650mW, Mode 2
30121867
THD+N vs Frequency
VDD = 3.6V, RL = 15μH+4Ω+15μH
POUT = 650mW, Mode 3
30121868
THD+N vs Frequency
VDD = 5V, RL = 15μH+4Ω+15μH
POUT = 1.2W, Mode 2
30121869
THD+N vs Frequency
VDD = 5V, RL = 15μH+4Ω+15μH
POUT = 1.2W, Mode 3
30121870
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LM49251
THD+N vs Frequency
VDD = 5V, RL = 15μH+8Ω+15μH
POUT = 50mW, Mode 3
30121871
THD+N vs Frequency
VDD = 5V, RL = 5μH+8Ω+15μH
POUT = 750mW, Mode 2
30121872
THD+N vs Frequency
RL = 32Ω
POUT = 14mW, Mode 4
30121873
THD+N vs Frequency
RL = 16Ω
POUT = 14mW, Mode 4
30121874
THD+N vs Frequency
RL = 32Ω
POUT = 14mW, Mode 6
30121875
THD+N vs Output Power
VDD = 3.6V, RL = 15μH+4Ω+15μH
f = 1kHz, Mode 2
30121876
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LM49251
THD+N vs Output Power
VDD = 3.6V, RL = 15μH+8Ω+15μH
f = 1kHz, Mode 2
30121877
THD+N vs Output Power
VDD = 3.6V, RL = 15μH+8Ω+15μH
f = 1kHz, Mode 3
30121878
THD+N vs Output Power
VDD = 3.6V, RL = 15μH+4Ω+15μH
f = 1kHz, Mode 3
30121879
THD+N vs Output Power
VDD = 5V, RL = 15μH+4Ω+15μH
f = 1kHz, Mode 2
30121880
THD+N vs Output Power
VDD = 5V, RL = 15μH+8Ω+15μH
f = 1kHz, Mode 2
30121881
THD+N vs Output Power
VDD = 5V, RL = 15μH+4Ω+15μH
f = 1kHz, Mode 3
30121882
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LM49251
THD+N vs Output Power
VDD = 5V, RL = 15μH+8Ω+15μH
f = 1kHz, Mode 3
30121883
THD+N vs Output Power
RL = 32Ω, f = 1kHz, Mode 4
30121801
THD+N vs Output Power
RL = 16Ω, f = 1kHz, Mode 4
30121802
THD+N vs Output Power
RL = 16Ω, f = 1kHz, Mode 6
30121803
THD+N vs Output Power
RL = 32Ω, f = 1kHz, Mode 6
30121804
Power Dissipation vs Output Power
RL = 15μH+4Ω+15μH, f = 1kHz, VDD = 3.6V
30121892
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LM49251
Power Dissipation vs Output Power
RL = 15μH+4Ω+15μH, f = 1kHz, VDD = 5V
30121893
Power Dissipation vs Output Power
RL = 15μH+8Ω+15μH, f = 1kHz, VDD = 3.6V
30121894
Power Dissipation vs Output Power
RL = 15μH+8Ω+15μH, f = 1kHz, VDD = 5V
30121895
Power Dissipation vs Output Power
RL = 16Ω, f = 1kHz, VDD = 1.8V
30121896
Power Dissipation vs Output Power
RL = 32Ω, f = 1kHz, VDD = 1.8V
30121897
Efficiency vs Output Power
RL = 15μH+4Ω+15μH, f = 1kHz, VDD = 3.6V
30121888
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LM49251
Efficiency vs Output Power
RL = 15μH+4Ω+15μH, f = 1kHz, VDD = 5V
30121889
Efficiency vs Output Power
RL = 15μH+8Ω+15μH, f = 1kHz, VDD = 3.6V
30121890
Efficiency vs Output Power
RL = 15μH+8Ω+15μH, f = 1kHz, VDD = 5V
30121891
PSRR vs Frequency
RL = 15μH+8Ω+15μH, f = 1kHz, VDD = 3.6V
AV = 6dB, Mode 2
30121805
PSRR vs Frequency
RL = 15μH+8Ω+15μH, VDD = 5V
AV = 6dB, Mode 2
30121806
PSRR vs Frequency
RL = 15μH+8Ω+15μH, VDD = 3.6V
AV = 6dB, Mode 3
30121807
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LM49251
PSRR vs Frequency
RL = 15μH+8Ω+15μH, VDD = 5V
AV = 6dB, Mode 3
30121808
PSRR vs Frequency
RL = 32Ω, HPVDD = 1.8V, VDD = 5V
AV = 6dB, Mode 4
301218a2
PSRR vs Frequency
RL = 32Ω, HPVDD = 1.8V, VDD = 5V
AV = 6dB, Mode 6
301218a3
CMRR vs Frequency
HP Mode
30121809
CMRR vs Frequency
LS Mode
30121810
Supply Current vs Supply Voltage
Mode 2, Stereo Inputs
301218a6
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LM49251
Supply Current vs Supply Voltage
Mode 8, Stereo Inputs
301218a8
Supply Current vs Supply Voltage
Mode 3, Mono Inputs
301218a7
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LM49251
System Control
I2C SIGNALS
In I2C mode the LM49251 pin SCL is used for the I2C clock
SCL and the pin SDA is used for the I2C data signal SDA. Both
of these signals need a pull-up resistor according to I2C spec-
ification. The 7-bits I2C slave address for LM49251 is
1111100.
I2C DATA VALIDITY
The data on SDA line must be stable during the HIGH period
of the clock signal (SCL). In other words, state of the data line
can only be changed when SCL is LOW.
301218b5
FIGURE 3. I2C Signals: Data Validity
I2C START AND STOP CONDITIONS
START and STOP bits classify the beginning and the end of
the I2C session. START condition is defined as SDA signal
transitioning from HIGH to LOW while SCL line is HIGH.
STOP condition is defined as the SDA transitioning from LOW
to HIGH while SCL is HIGH. The I2C master always generates
START and STOP bits. The I2C bus is considered to be busy
after START condition and free after STOP condition. During
data transmission, I2C master can generate repeated START
conditions. First START and repeated START conditions are
equivalent, function-wise.
301218b6
FIGURE 4. I2C Start and Stop Conditions
TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. Each
byte of data has to be followed by an acknowledge bit. The
acknowledge related clock pulse is generated by the master.
The transmitter releases the SDA line (HIGH) during the ac-
knowledge clock pulse. The receiver must pull down the SDA
line during the 9th clock pulse, signifying an acknowledge. A
receiver which has been addressed must generate an ac-
knowledge after each byte has been received. After the
START condition, the I2C master sends a chip address. This
address is seven bits long followed by an eight bit which is a
data direction bit (R/W). The LM49251 address is 11111000.
For the eighth bit, a “0” indicates a WRITE and a “1” indicates
a READ. The second byte selects the register to which the
data will be written. The third byte contains data to write to the
selected register.
301218b7
FIGURE 5. I2C Chip Address
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LM49251
301218b8
FIGURE 6. Example I2C Write Cycle
When a READ function is to be accomplished, a WRITE func-
tion must precede the READ function, as shown in the Read
Cycle waveform.
301218b9
w = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by slave)
rs = repeated start
FIGURE 7. Example I2C Read Cycle
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LM49251
TABLE 2. Device Address
B7 B6 B5 B4 B3 B2 B1 B0
Device Address 1 1 1 1 1 0 0 0
TABLE 3. I2C Control Registers
Register Name B7 B6 B5 B4 B3 B2 B1 B0
SHUTDOWN
CONTROL 0 0 0 1 GAMP__ON HPR_ SD Class G _SD SD
MODE
CONTROL 0 0 1 HP_ST HP_M SPK_ L+R SPK_ST SPK_M
POWER
LIMITER
CONTROL
0 1 0 ATK1 ATK0 PLEV2 PLEV1 PLEV0
NO CLIP
CONTROL 0 1 1 RLT1 RLT0 OCP2 OCP1 OCP0
GAIN
CONTROL 1 0 0 LSGAINL LSGAINR HPGAIN2 HPGAIN1 HPGAIN0
MONO
VOLUME
CONTROL
1 0 1 MG4 MG3 MG2 MG1 MG0
STEREO
VOLUME
CONTROL
1 1 0 SG4 SG3 SG2 SG1 SG0
CLASS D
CONTROL 1 1 1 0 0 0 ER_CNTRL SS_EN
LS CONTROL 1 1 1 0 1 0 ST_SEL LSR_SD
CLASS G
CONTROL 1 1 1 1 0 0 TLEV1 TLEV2
OTHER
CONTROL 1 1 1 1 1 I2CVDD SD RAIL_SW TURN_ON
TIME
TABLE 4. Shutdown Control
BIT NAME VALUE DESCRIPTION
B3 GAMP_ON
This disables the gain amplifiers that are not in use to minimize IDD.
0 Normal Operation
1 Unused gain amplifiers disabled
B2 HPR_SD
This disables the right headphone output.
0 Normal operation
1 Right headphone amplifier disabled
B1 Class G_SD
This disables the Class G.
0 Class G enabled
1 Class G disabled
B0 SD
LM49251 Shutdown
0 LM49251 Disabled
1 LM49251 Enabled
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LM49251
TABLE 5. Output Mode Selection
HP (ST) HP (M) SPK (L
+R)
SPK
(ST)
SPK
(M) SPK(L) SPK(R) HP(L) HP(R) Datasheet
0 0 0 0 0 SD SD SD SD Mode 0
0 0 1 1 0 GST X (L + R) GST X (L + R) SD SD Mode 1
0 0 0 1 0 GST X L GST X R SD SD Mode 2
0 0 0 0 1 GM X M GM X M SD SD Mode 3
0 1 0 0 0 SD SD GM X M GM X M Mode 4
0 1 0 0 1 GM X M GM X M GM X M GM X M Mode 5
1 0 0 0 0 SD SD GSTX L GST X R Mode 6
1 0 1 1 0 GST X (L + R) GST X (L + R) GSTX L GST X R Mode 7
1 0 0 1 0 GST X L GST X R GSTX L GST X R Mode 8
TABLE 6. Voltage Limit Control Register
BIT NAME VALUE DESCRIPTION
B4:B3 ATK1
ATK2
B4 B3 Sets Attack Time based on CSET and RSET
0 0 tATK
0 1 1.3 x tATK
1 0 2 x tATK
1 1 2.7 x tATK
B2:B0
PLEV2
PLEV1
PLEV0
B2 B1 B0 Sets output power limit level
0 0 0 Voltage Limit disabled
0 0 1 VTH(VLIM) = 3.9VP-P
0 1 0 VTH(VLIM)) = 4.7VP-P
0 1 1 VTH(VLIM)= 5.4VP-P
1 0 0 VTH(VLIM) = 6.2VP-P
1 0 1 VTH(VLIM) = 7.0VP-P
1 1 0 VTH(VLIM) = 7.8VP-P
1 1 1 Voltage Limit disabled
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LM49251
TABLE 7. No Clip Control Register
BIT NAME VALUE DESCRIPTION
B2:B0
OCP2
OCP1
OCP0
B2 B1 B0 This sets the output clip limit level
0 0 0 NO_CLIP = disabled, OUTPUT_CLIP =
disabled
0 0 1 Test Mode
0 1 0 NO_CLIP = enabled, OUTPUT_CLIP = disabled
0 1 1 low
1 0 0 medium
1 0 1 medium high
1 1 0 high
1 1 1 maximum
B4:B3 RLT1
RTL0
B1 B0 This sets the release time of the automatic
limiter control circuit.
0 0 1s
0 1 0.8s
1 0 0.65s
1 1 0.4s
TABLE 8. Gain Control Register
BIT NAME VALUE DESCRIPTION
B4 LSGAINL 0 6dB Loudspeaker gain
1 12dB Loudspeaker gain
B3 LSGAINR 0 6dB Loudspeaker gain
1 12dB Loudspeaker gain
B2:B0
HPGAIN2 (B2)
HPGAIN1 (B1)
HPGAIN0 (B0)
B2 B1 B0 Headphone Gain
0 0 0 0dB
0 0 1 -1.5db
0 1 0 -3dB
0 1 1 -6dB
1 0 0 -9dB
1 0 1 -12dB
1 1 0 -15dB
1 1 1 -18dB
21 www.national.com
LM49251
General Amplifier Function
TABLE 9. Volume Control Table
VOLUME STEP _G4 _G3 _G2 _G1 _G0 GAIN (dB)
1 0 0 0 0 0 -80
2 0 0 0 0 1 -46.5
3 0 0 0 1 0 -40.5
4 0 0 0 1 1 -34.5
5 0 0 1 0 0 -30
6 0 0 1 0 1 -27
7 0 0 1 1 0 -24
8 0 0 1 1 1 -21
9 0 1 0 0 0 -18
10 0 1 0 0 1 -15
11 0 1 0 1 0 -13.5
12 0 1 0 1 1 -12
13 0 1 1 0 0 -10.5
14 0 1 1 0 1 -9
15 0 1 1 1 0 -7.5
16 0 1 1 1 1 -6
17 1 0 0 0 0 -4.5
18 1 0 0 0 1 -3
19 1 0 0 1 0 1.5
20 1 0 0 1 1 0
21 1 0 1 0 0 1.5
22 1 0 1 0 1 3
23 1 0 1 1 0 4.5
24 1 0 1 1 1 6
25 1 1 0 0 0 7.5
26 1 1 0 0 1 9
27 1 1 0 1 0 10.5
28 1 1 0 1 1 12
29 1 1 1 0 0 X
30 1 1 1 0 1 X
31 1 1 1 1 0 X
32 1 1 1 1 1 X
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LM49251
TABLE 10. Class D Control
BIT NAME VALUE DESCRIPTION
B1 ER_CNTRL
This enables edge rate control.
0 Edge Rate Control Disabled
1 Edge Rate Control Enabled
B0 SS_EN
This enables Spread Spectrum.
0 Spread Spectrum Disabled
1 Spread Spectrum Enabled
TABLE 11. Loudspeaker (LS) Control
BIT NAME VALUE DESCRIPTION
B1 ST_SEL
This allows selection between two Stereo Inputs.
0 LIN1/RIN1
1 LIN2/RIN2
B0 LSR_SD
This disables the Left Loudspeaker.
0 Left Loudspeaker enabled
1 Left Loudspeaker disabled
TABLE 12. Class G Control
BIT NAME VALUE DESCRIPTION
B1:B0 TLEV1
TLEV0
B1 B0 This sets the Trip Level.
0 0 High (default)
0 1 High-Medium
1 0 Low-Medium
1 1 Low
TABLE 13. Other Control
BIT NAME VALUE DESCRIPTION
B1 RAIL_SW
This switches between two HP voltage rails*
0 High Rail
1 Low Rail
B0 TURN_ON_TIME
This allows fast turn on time
0 Normal Turn-On Time
1 Fast Turn-On Time
*This option is only available when the Class G is disabled.
23 www.national.com
LM49251
Application Information
DIFFERENTIAL AMPLIFIER EXPLANATION
The LM49251 features a differential input stage, which offers
improved noise rejection compared to a single-ended input
amplifier. Because a differential input amplifier amplifies the
difference between the two input signals, any component
common to both signals is cancelled. An additional benefit of
the differential input structure is the possible elimination of the
DC input blocking capacitors. Since the DC component is
common to both inputs, and thus cancelled by the amplifier,
the LM49251 can be used without input coupling capacitors
when configured with a differential input signal.
INPUT MIXER/MULTIPLEXER
The LM49251 includes a comprehensive mixer multiplexer
controlled through the I2C interface. The mixer/multiplexer al-
lows any input combination to appear on any output of
LM49251. Table 5 (MODE CONTROL) shows how the input
signals are routed together for each possible input selection.
SHUTDOWN FUNCTION
The LM49251 features the following shutdown controls: Bit
B4 (GAMP_SD) of the SHUTDOWN CONTROL register con-
trols the gain amplifiers. When GAMP_SD = 1, it disables the
gain amplifiers that are not in use. For example, in Modes 1,
4 and 5, the Mono inputs are in use, so the Left and Right
input gain amplifiers are disabled, causing the IDD to be min-
imized. Bit B0 (PWR_ON) of the SHUTDOWN CONTROL
register is the global shutdown control for the entire device.
Set PWR_ON = 0 for normal operation. PWR_ON = 1 over-
rides any other shutdown control bit.
CLASS D AMPLIFIER
The LM49251 features a mono class D audio power amplifier
with a filterless modulation scheme that reduces external
component count, conserving board space and reducing sys-
tem cost. With no signal applied, the outputs (LSOUT+ and
LSOUT-) switch between VDD and GND with 50% duty cycle,
in phase, causing the two outputs to cancel. This cancellation
results in no net voltage across the speaker, thus there is no
current to the load in the idle state.
With an input signal applied, the duty cycle (pulse width) of
the class D output changes. For increasing output voltage, the
duty cycle of LSOUT+ increases, while the duty cycle of
LSOUT- decreases. For decreasing output voltages, the con-
verse occurs. The difference between the two pulse widths
yields the differential output voltage.
ENHANCED EMISSIONS SUPPRESSION (E2S)
The LM49251 class D amplifier features National’s patent-
pending E2S system that reduces EMI, while maintaining high
quality audio reproduction and efficiency. The E2S system
features selectable spread spectrum and advanced edge rate
control (ERC). The LM49251 class D ERC greatly reduces
the high frequency components of the output square waves
by controlling the output rise and fall times, slowing the tran-
sitions to reduces RF emissions, while maximizing THD+N
and efficiency performance.
FIXED FREQUENCY
The LM49251 class D amplifier features two modulation
schemes, a fixed frequency mode and a spread spectrum
mode. Select the fixed frequency mode by setting bit B0
(SS_EN) of the SS Control register to 0. In fixed frequency
mode, the loudspeaker outputs switch at a constant 300kHz.
The output spectrum consists of the 300kHz fundamental and
its associated harmonics.
SPREAD SPECTRUM
The selectable spread spectrum mode minimizes the need for
output filters, ferrite beads or chokes. In spread spectrum
mode, the switching frequency varies randomly by 30% about
a 300kHz center frequency, reducing the wideband spectral
content, improving EMI emission radiated by the speaker and
associated cables and traces. Where a fixed frequency class
D exhibits large amounts of spectral energy at multiples of the
switching frequency, the spread spectrum architecture
spreads that energy over a larger bandwidth. The cycle-to-
cycle variation of the switching period does not affect the
audio reproduction, efficiency, or PSRR. Set bit B0 (SS_EN)
of the SS Control register to 1 to enable spread spectrum
mode.
GROUND REFERENCED HEADPHONE AMPLIFIER
The LM49251 features a low noise inverting charge pump that
generates an internal negative supply voltage. This allows the
headphone outputs to be biased about GND instead of a
nominal DC voltage, like traditional headphone amplifiers.
Because there is no DC component, the large DC blocking
capacitors (typically 220μF) at the headphone outputs are not
necessary. The coupling capacitors are replaced by two small
ceramic charge pump capacitors, saving board space and
cost. Eliminating the output coupling capacitors also improves
low frequency response. In traditional headphone amplifiers,
the headphone impedance and the output capacitor form a
high-pass filter that not only blocks the DC component of the
output, but also attenuates low frequencies, impacting the
bass response. Because the LM49251 does not require the
output coupling capacitors, the low frequency response of the
device is not degraded by external components. In addition
to eliminating the output coupling capacitors, the ground ref-
erenced output nearly doubles the available dynamic range
of the LM49251 headphone amplifiers when compared to a
traditional headphone amplifier operating from the same sup-
ply voltage.
CLASS G OPERATION
The LM49251 features a ground referenced class G head-
phone amplifier for increased efficiency and decreased power
dissipation. This particular architecture creates a ground-ref-
erenced output with dynamic supply rails for optimum effi-
ciency. Music and voice signals have a high peak-to-mean
ratio with the majority of the signal content at low levels, class
G amplifiers take advantage of this behavior. Class G ampli-
fiers have multiple voltage supplies to decrease power dissi-
pation. The LM49251 has two discrete supply rails: ±0.9V and
±1.8V. The device switches from ±0.9V to ±1.8V when the
output signal reaches the selectable threshold level to switch
to the higher voltage rails. When the output falls below the
required voltage for a set period of time, it will switch back to
the lower rail until the next time the threshold is reached. The
threshold level has 4 selectable levels that can be set through
the Class G Control I2C control register <B1:B2>. With this
topology power dissipation is reduced for typical music or
voice sources. Figure 8 below shows how a music output may
look.
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LM49251
301218c1
FIGURE 8. Class G Operation
Disabling the Class G
The Class G feature can be disabled via I2C Shutdown Con-
trol Register B1. When the Class G is disabled the headphone
supply rails are selectable. In the Other Control register B1 =
0 sets the headphone supply rails at ±1.8V (high) and B1 = 1
sets the supply to ±0.9V (low). Figure 9 below shows a curve
of THD+N vs Output Power for the two supply rails.
30121824
FIGURE 9. Class G Disabled (Low/High Supply Rails)
AUTOMATIC LIMITER CONTROL (ALC)
When enabled, the ALC continuously monitors and adjusts
the gain of the loudspeaker amplifier signal path if necessary.
The ALC serves two functions: voltage limiter/speaker pro-
tection and output clip prevention (No-Clip) with three clip
controls levels. The voltage limiter/speaker protection pre-
vents an output overload condition by maintaining the loud-
speaker output signal below a preset amplitude (See voltage
Limiter section). The No Clip feature monitors the output sig-
nal and maintains audio quality by preventing the loudspeaker
output from exceeding the amplifier’s headroom (see No Clip/
Output Clip Control section). The voltage limiter thresholds,
clip control levels, attack and release times are configured
through the I2C interface.
25 www.national.com
LM49251
VOLTAGE LIMITER
The voltage limiter function of the ALC monitors and prevents
the audio signal from exceeding the voltage limit threshold.
The voltage limit threshold (VTH(VLIM)) is set by bits B2:B0 in
the “Voltage Limit Threshold Register” (see Table 6). Al-
though the ALC reduces the gain of the speaker path to
maintain the audio signal below the voltage limit threshold, it
is still possible to overdrive the speaker output in which case
loudspeaker output will exceed the voltage limit threshold and
cause clipping on the output, and speaker damage is possi-
ble. Please see the ALC headroom section for further details.
301218a9
FIGURE 10. Voltage Limit Output Level
NO CLIP/OUTPUT CLIP CONTROL
The LM49251 No Clip circuitry detects when the loudspeaker
output is near clipping and reduces the signal gain to prevent
output clipping and preserve audio quality (Figure 6). Al-
though the ALC reduces the gain of the speaker path to
prevent output clipping, it is still possible to overdrive the
speaker output. Please see the ALC headroom section for
further details.
301218b0
FIGURE 11. No Clip Function
The LM49251 also features an output clip control that allows
a certain amount of clipping at the output in order to increase
the loudspeaker output power. The clip level is set by B2:B0
in the No Clip Control Register (see Table 7). The clip control
works by allowing the output to enter clipping before the ALC
turns on and maintains the output level. The clip control has
three levels: low, medium, and high. The low and max clip
level control settings give the lowest distortion and highest
distortion respectively on the output (see Figure 12). The ac-
tual output level of the device will depend upon the supply
voltage, and the output power will depend upon the load
impedance.
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LM49251
301218b1
FIGURE 12. Clip Control Levels
VDD = 3.3V, VIN = 8VPP Shaped Burst, 1kHz
Blue = No Clip Disabled, Gray = Low, Light Green = Medium
Green = High, Yellow = Max
ALC HEADROOM
When either voltage limiter or no clip is enabled, it is still pos-
sible to drive LM49251 into clipping by over driving the input
volume stage of the signal path beyond its output dynamic
range. In this case, clipping occurs at the input volume stage,
and although ALC is active, the gain reduction will have no
effect on the output clipping. The maximum input that can
safely pass through the input volume stage can be calculated
by following formula:
(1)
So in the case of 0 dB volume gain, audio input has to be less
than VDD for both voltage limiter or No clip settings.
When voltage limiter is enabled, ALC can reach its max at-
tenuation for lower voltage limit levels as shown in Figure
13. Typically, after the ALC started working, with 6 dB of audio
input change ALC is well within its regulation. Voltage limiter
Input headroom can be increased by switching to the
LS_GAIN to 18dB in the Gain Control Register (see Table
8).
301218b2
FIGURE 13. Voltage Limiter Function
VDD = 3.3V, RL = 15μH+8Ω+15μH
fIN = 1kHz, LS_GAIN = 0
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LM49251
301218b3
FIGURE 14. No Clip Function
VDD = 3.3V, RL = 15μH+8Ω+15μH
fIN = 1kHz, LS_GAIN = 0
Blue, Green = Output Power vs Input Voltage
Gray, Yellow = THD+N vs Input Voltage
When No Clip is enabled, class D speaker output reduces
when it’s about to enter clipping region and power stay con-
stant as long as VIN is less than VDD for 0 dB volume gain (see
figure 9). For example, in the case of VDD = 3.3V, there is a 6
dB of headroom for the change in input. Please see the ALC
typical performance curves for additional plots relating to dif-
ferent supply voltages and LS_GAIN settings for specific
application parameters.
ATTACK TIME
Attack time (tATK) is the time it takes for the gain to be reduced
by 6dB (LS_GAIN=0) once the audio signal exceeds the ALC
threshold. Fast attack times allow the ALC to react quickly and
prevent transients such as symbol crashes from being dis-
torted. However, fast attack times can lead to volume pump-
ing, where the gain reduction and release becomes notice-
able, as the ALC cycles quickly. Slower attack times cause
the ALC to ignore the fast transients, and instead act upon
longer, louder passages. Selecting an attack time that is too
slow can lead to increased distortion in the case of the No Clip
function, and possible output overload conditions in the case
of the Voltage limiter. The attack time is set by a combination
of the value of CSET and the attack time coefficient as given
by equation (2):
tATK = 20kΩCSET / αATK (s) (2)
Where αATK is the attack time coefficient (Table 14) set by bits
B4:B3 in the Voltage Limit Control Register (see Table 6). The
attack time coefficient allows the user to set a nominal attack
time. The internal 20kΩ resistor is subject to temperature
change, and it has tolerance between -11% to +20%.
TABLE 14. Attack Time Coefficient
B4 B3 αATK
0 0 2.667
0 1 2
1 0 1.333
1 1 1
RELEASE TIME
Release time (tRL) is the time it takes for the gain to return
from 6dB (LS_GAIN=0) to its normal level once the audio sig-
nal returns below the ALC threshold. A fast release time
allows the ALC to react quickly to transients, preserving the
original dynamics of the audio source. However, similar to a
fast attack time, a fast release time contributes to volume
pumping. A slow release time reduces the effect of volume
pumping. The release time is set by a combination of the value
of CSET and release time coefficient as given by equation (3):
tRL = 20MΩCSET / αRL (s) (3)
where αRL is the release time coefficient (Table 14) set by bits
B4:B3 in the No Clip Control Register. The release time co-
efficient allows the user to set a nominal release time. The
internal 20MΩ is subject to temperature change, and it has
tolerance between -11% to +20%.
TABLE 15. Release Time Coefficient
B4 B3 αRL
0 0 2
0 1 2.5
1 0 3
1 1 5
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LM49251
A-WEIGHTED FILTER
The human ear is sensitive for acoustic signals within a fre-
quency range from about 20Hz to 20kHz. Within this range
the sensitivity of the human ear is not equal for each frequen-
cy. To approach the hearing response, weighting filters are
introduced. One of those filters is the A-weighted filter.
The A-weighted filter is used in signal to noise measurements,
where the wanted audio signal is compared to device noise
and distortion.
The use of this filter improves the correlation of the measured
values to the way these ratios are perceived by the human
ear.
301218b4
FIGURE 15. A-Weighted Filter
PROPER SELECTION OF EXTERNAL COMPONENTS
ALC Timing (CSET) Capacitor Selection
The recommended range value of CSET is between .01μF to
1μF. Lowering the value below .01μF can increase the attack
time but LM49251 ALC ability to regulate its output can be
disrupted and approaches the hard limiter circuit. This in turn
increases the THD+N and audio quality will be severely af-
fected.
Charge Pump Capacitor Selection
Use low ESR ceramic capacitors (less than 100mΩ) for opti-
mum performance.
Charge Pump Flying Capacitor (C1)
The flying capacitor (C1), see Figure 2, affects the load regu-
lation and output impedance of the charge pump. A C1 value
that is too low results in a loss of current drive, leading to a
loss of amplifier headroom. A higher valued C1 improves load
regulation and lowers charge pump output impedance to an
extent. Above 2.2µF, the RDS(ON) of the charge pump switch-
es and the ESR of C1 and CPVSS dominate the output
impedance. A lower value capacitor can be used in systems
with low maximum output power requirements.
Charge Pump Hold Capacitor (CPVSS)
The value and ESR of the hold capacitor (CPVSS) directly af-
fects the ripple on CPVSS (see Figure 2). Increasing the value
of CPVSS reduces output ripple. Decreasing the ESR of
CPVSS reduces both output ripple and charge pump output
impedance. A lower value capacitor can be used in systems
with low maximum output power requirements.
Input Capacitor Selection
Input capacitors may be required for some applications, or
when the audio source is single-ended. Input capacitors block
the DC component of the audio signal, eliminating any conflict
between the DC component of the audio source and the bias
voltage of the LM49251. The input capacitors create a high-
pass filter with the input resistors RIN. The -3dB point of the
high-pass filter is found using Equation (4) below.
f = 1/ 2πRINCIN (Hz) (4)
Where the value of RIN is given in the Electrical Characteris-
tics Table.
High-pass filtering the audio signal helps protect the speak-
ers. When the LM49251 is using a single-ended source,
power supply noise on the ground is seen as an input signal.
Setting the high-pass filter point above the power supply noise
frequencies, 217Hz in a GSM phone, for example, filters out
the noise such that it is not amplified and heard on the output.
Capacitors with a tolerance of 10% or better are recommend-
ed for impedance matching and improved CMRR and PSRR.
29 www.national.com
LM49251
Demo Board User Guide
Quick Start Guide:
1. Connect a shunt across pin 1 and pin 2 of JUI to provide
3.3V to I2CVDD.
2. Connect a shunt across JU3 to provide 1.8V to VDDHP
from on board regulator.
3. Connect a 4Ω or 8Ω speaker across LSOUTL (left loud-
speaker output) and LSOUTR (right loudspeaker output).
4. Connect stereo headphones to the headphone jack J1.
5. Connect a 3.6V power supply to the VDD pin of J3 and
the ground source to the GND pin.
6. Apply audio input signal to any of the stereo (IN1/IN2) or
mono (MONO_IN) inputs.
7. Turn on power supply.
8. Connect the mini USB cable to J29 and the other end of
the cable to a PC.
9. Open the LM49251 I2C control software.
10. Verify that the device has been acknowledged by look-
ing at bottom left corner of GUI (see Figure 16 and Figure
17).
11. On GUI:
a. Set POWER: on
b. Set MODE SELECT to desired position (see Table
16).
c. Set all VOLUME CONTROL to 0dB by clicking on Set
0dB button.
30121822
FIGURE 16. Software Graphic user Interface (GUI)
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LM49251
30121823
FIGURE 17. Error Message displayed on GUI if device is NOT acknowledged (I2C Error)
or if there is an USB error (USB I/O error)
TABLE 16. Mode Table
SPK(L) SPK(R) HP(L) HP(R) Datasheet
SD SD SD SD Mode 0
GST X (L + R) GST X (L + R) SD SD Mode 1
GST X L GST X R SD SD Mode 2
GM X M GM X M SD SD Mode 3
SD SD GM X M GM X M Mode 4
GM X M GM X M GM X M GM X M Mode 5
SD SD GST X L GST X R Mode 6
GST X (L + R) GST X (L + R) GST X L GST X R Mode 7
GST X L GST X R GSTX L GST X R Mode 8
31 www.national.com
LM49251
TABLE 17. Board Connectors
Designator Function Comments
J1 (HPOUT)
Headphone Output Ring - Right Channel, Tip - Left Channel
J3
(VDD/GND)
Loudspeaker Power
Supply
J4
(VDDHP/GND)
Headphone Power
Supply
Apply voltage on J4 when JU3 is open. DO NOT apply voltage if JU3 is
closed
J29 Mini USB
JU1 I2CVDD Select Pin 1 = 3.3V, Pin 2 = I2CVDD, Pin 3 = GND Short Pin 1 and Pin 2 for
I2CVDD = 3.3V
JU2 (HPOUT)
Headphone Output Left and Right Channel
JU3 VDDHP = 1.8V Short JU3 for VDDHP = 1.8V from on board regulator
JU4 5V Access to 5V from USB
JU6 I2C Clock/Data GND, SDA, SCL connections
JU7 To program USB controller
LSOUTL Left Loudspeaker Out
LSOUTR Right Loudspeaker Out
MONO_IN Mono Input
IN1 Stereo Input 1
IN2 Stereo Input 2
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LM49251
Bill of Materials
Bill of Materials
Ref Designator Part Description Manufacturer Part Number
LM49251TL DEMO BOARD PCB, RevA NSC
U1 LM49251TL NSC LM49251TL
U2 USB, 25 MIPS, 16 kB Flash, 10-Bit ADC, 32-Pin
Mixed-Signal MCU Silicon Labs C8051F320-GQ
U3
Ultra Low Noise, 150mA Linear Regulator for
RF/Analog Circuits Requires No Bypass
Capacitor
NSC LP5900TL-1.8/NOPB
C12, C13, C14,
C39, C40 CAP CER 4.7UF 10V X5R 0603 10% Taiyo Yuden LMK107BJ475KA-T
C10, C38, C41 CAP .1UF 25V CERAMIC X7R 0603 5% Kemet C0603C104J3RACTU
R3 NO LOAD NO LOAD NO LOAD
C11, C9, C15,
C8,C7 CAP CER 2.2UF 10V X7R 0603 10% Murata GRM188R71A225KE15D
L1, L2 FERRITE CHIP 30 OHM 2200MA 0402 Murata BLM15PD300SN1D
C22, C37 CAP CERM .47UF 16V X7R 0603 10% Kemet C0603C474K4RACTU
C1,
C2,C3,C4,C5,C
6
CAP CER .22UF 10V 10% X7R 0603 Murata GRM188R71A224KA01D
R1, R2 R4, R5 RES 10.0K OHM 1/10W 1% 0603 SMD Panasonic ERJ-3EKF1002V
J29 CONN RECEPT MINI USB2.0 5POS Hirose UX60-MB-5ST
JU1, JU6, JU7 CONN HEADR BRKWAY .100 03POS STR Tyco 9-146285-0-03
J3, J4, JU2,
LSOUTL,
LSOUTR, Jw
CONN HEADR BRKWAY .100 02POS STR Tyco 9-146285-0-02
Mono_IN, In, In1 CONN HDR BRKWAY .100 04POS VERT Tyco 9-146282-0-04
J1 CONN JACK STEREO 3.5MM HORIZONTAL Switchcraft 35RAPC4BH3
JU3, JU7, JU1, Jumper Shunt w/handle, 30μin gold plated,
0.100in pitch Tyco/AMP 881545-2
33 www.national.com
LM49251
Demo Board Schematic Diagram
30121812
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LM49251
Demo Board Layout
30121821
Top Layer
30121815
Layer 2
30121816
Layer 3
30121814
Bottom Layer
30121820
Top Silkscreen
30121819
Bottom Silkscreen
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LM49251
30121818
Paste Mask Top Layer
30121817
Past Mask Bottom Layer
30121813
Drill Drawing
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LM49251
Revision History
Rev Date Description
1.0 02/08/11 Initial Web released.
37 www.national.com
LM49251
Physical Dimensions inches (millimeters) unless otherwise noted
micro SMD Package
Order Number LM49251TL
NS Package Number TLA30XXX
X1 = 2.557mm X2 = 3.021mm X3 = 0.6mm
www.national.com 38
LM49251
Notes
39 www.national.com
LM49251
Notes
LM49251 Stereo Audio Subsystem with Class G Headphone Amplifier and Class D Speaker
Amplifier with Speaker Protection
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