SL74HCT132
System Logic
Semiconductor
SLS
Quad 2-Input NAND Gate
with Schmitt-Trigger Inputs
High-Performance Silicon-Gate CMOS
The SL74HCT132 is identical in pinout to the LS/ALS132. The
SL74HCT132 may be used as a level converter for interfacing TTL or
NMOS outputs to High Speed CMOS inputs.
• TTL/NMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA
ORDERING INFORMATION
SL74HCT132N Plastic
SL74HCT132D SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN 14 =VCC
PIN 7 = GND
PIN ASSIGNMENT
FUNCTION TABLE
Inputs Output
A B Y
L L H
L H H
H L H
H H L
SL74HCT132
System Logic
Semiconductor
SLS
MAXIMUM RATINGS*
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V
VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
IIN DC Input Current, per Pin ±20 mA
IOUT DC Output Current, per Pin ±25 mA
ICC DC Supply Current, VCC and GND Pins ±50 mA
PD Power Dissipation in Still Air, Plastic DIP+
SOIC Package+ 750
500 mW
Tstg Storage Temperature -65 to +150 °C
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package) 260 °C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
VCC DC Supply Voltage (Referenced to GND) 4.5 5.5 V
VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V
TA Operating Temperature, All Package Types -55 +125 °C
tr, tf Input Rise and Fall Time (Figure 1) - no
limit* ns
*When VIN ≈ 0.5VCC, ICC> > quiescent current.
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range
GND≤(VIN or VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC).
Unused outputs must be left open.
SL74HCT132
System Logic
Semiconductor
SLS
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC Guaranteed Limit
Symbol Parameter Test Conditions V 25 °C
to
-55°C
≤85
°C ≤125
°C Unit
VT+max Maximum Positive-
Going Input Threshold
Voltage
VOUT=0.1 V
IOUT≤ 20 µA 4.5
5.5 1.9
2.1 1.9
2.1 1.9
2.1 V
VT+min Minimum Positive-
Going Input Threshold
Voltage
VOUT=0.1 V
IOUT ≤ 20 µA 4.5
5.5 1.2
1.4 1.2
1.4 1.2
1.4 V
VT-max Maximum Negative-
Going Input Threshold
Voltage
VOUT=VCC-0.1 V
IOUT≤ 20 µA 4.5
5.5 1.2
1.4 1.2
1.4 1.2
1.4 V
VT-min Minimum Negative-
Going Input Threshold
Voltage
VOUT=VCC-0.1 V
IOUT ≤ 20 µA 4.5
5.5 0.5
0.6 0.5
0.6 0.5
0.6 V
VHmax
Note Maximum Hysteresis
Voltage VOUT=0.1 V or VCC-0.1 V
IOUT ≤ 20 µA 4.5
5.5 1.4
1.5 1.4
1.5 1.4
1.5 V
VHmin
Note Minimum Hysteresis
Voltage VOUT=0.1 V or VCC-0.1 V
IOUT ≤ 20 µA 4.5
5.5 0.4
0.4 0.4
0.4 0.4
0.4 V
VOH Minimum High-Level
Output Voltage VIN≤VT-min or VT+max
Iout ≤ 20 µA 4.5
5.5 4.4
5.4 4.4
5.4 4.4
5.4 V
VIN≤VT-min or VT+max
IOUT ≤ 4.0 mA
IOUT ≤ 5.2 mA
4.5
3.98
3.84
3.7
VOL Maximum Low-Level
Output Voltage VIN ≥VT+max
IOUT ≤ 20 µA 4.5
5.5 0.1
0.1 0.1
0.1 0.1
0.1 V
VIN≥ VT+max
IOUT ≤ 4.0 mA
IOUT ≤ 5.2 mA
4.5
0.26
0.33
0.4
IIN Maximum Input
Leakage Current VIN=VCC or GND 5.5 ±0.1 ±1.0 ±1.0 µA
ICC Maximum Quiescent
Supply Current
(per Package)
VIN=VCC or GND
IOUT=0µA 5.5 1.0 10 40 µA
∆ICC Additional Quiescent
Supply Current VIN = 2.4 V, Any One Input
VIN=VCC or GND, Other
Inputs
≥-55°C 25°C to
125°C mA
IOUT=0µA 5.5 2.9 2.4
Note. VHmin>(VT+min)-(VT-max); VHmax=(VT+max)+(VT-min).
SL74HCT132
System Logic
Semiconductor
SLS
AC ELECTRICAL CHARACTERISTICS(VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=6.0 ns)
Guaranteed Limit
Symbol Parameter 25 °C to
-55°C ≤85°C ≤125°C Unit
tPLH, tPHL Maximum Propagation Delay, Input A or B to
Output Y (Figures 1 and 2) 25 31 38 ns
tTLH, tTHL Maximum Output Transition Time, Any Output
(Figures 1 and 2) 15 19 22 ns
CIN Maximum Input Capacitance 10 10 10 pF
Power Dissipation Capacitance (Per Gate) Typical @25°C,VCC=5.0 V
CPD Used to determine the no-load dynamic power
consumption: PD=CPDVCC2f+ICCVCC 27 pF
SL74HCT132
System Logic
Semiconductor
SLS
SL74HCT132
System Logic
Semiconductor
SLS
Figure 1. Switching Waveforms
Figure 2. Test Circuit
