PF1286-02 S1R72901 Single chip LSI for high-speed interface IEEE1394a-2000 DESCRIPTIONS The S1R72901 is the single chip controller that bridges the IEEE1394 interface conforming to 1394-1995 and 1394a-2000 of the IEEE standard, with the IDE interface conforming to the ATA5. The following components are integrated into single chip; two-port cable PHY, the LINK/Transaction controller most suitable to the SBP-2 protocol, Seiko Epson original 32-bit RISC processor and the Flash memory for Firmware storage. Hardware includes a part of transaction functions that allows automatic PageTable fetch and the data transfer once the PageTable address and size for the SBP-2 protocol are set. The S1R72901 provides the IEEE1394 interface to the computer peripheral devices, especially to the storage devices that are most suitable. FEATURES z Cable PHY Transceiver/Arbitor Built-in 2 port high-precision small amplitude differential high-speed transceiver. Built-in on-chip 400MHz PLL that realizes the S400/S200/S100 transmission and reception, and the 50MHz SCLK output. Cable Power Status function that detects the cable power drop. z Link/Transaction Controller Realizes duplex data transfer including Asynchronous and Isochronous transfer. Realizes stable duplex data transfer up to the Maxpayload at 100Mbps, 200Mbps and 400Mbps with the built-in SRAM. z SBP-2 Support A part of transactions is realized by hardware (a dedicated area is secured) to prevent actual transfer rate drop due to the overhead. The header area and the data area are separated to simplify the communication with the upper layers. The data area is divided into the stream area and the ORB area. The ring buffer is applied to the receiving header area, the receiving data area (receiving stream area, receiving ORB area) and sending data area (sending stream area). Sizes of the respective areas can be set as desired, independently. The busy status is automatically controlled by hardware when receiving a signal. Once the PageTable address and size in the SBP-2 are set, the PageTable fetch and the data transfer can be done automatically. z IDE interface Compatible with PIO mode 0/1/2/3/4, multiword DMA mode 0/1/2 and Ultra-DMA mode 0/1/2/3/4/5 3.3V single power source is applicable with the 5V tolerant cell. z C33 RISC CPU 32-bit RISC CPU EIAC332x501 operating at 25MHz (CPU cycle minimum 2 operation) Built-in SRAM: 8KB, no wait operation Built-in Flash ROM: 64KB, no wait operation Programmable timer: built-in 3-channel timers z Flash ROM Built-in 64KB Flash ROM, no need of external Flash ROM z ICD33 interface Incorporates the ICD33 interface that facilitates development of Firmware to operate the CPU. The ICD33 can be connected with as few as six pins. This terminal can be used as a JTAG terminal to rewrite the data in the built-in Flash ROM easily. z Power voltage 3.3V0.3V z 100-pin flat package (pin pitch is 0.5 mm). Radiation-proof design is not done. SEIKO EPSON CORPORATION S1R72901 BLOCK DIAGRAM Internal Packet Memory (8KByte) Cable Power Status HDD[15:0] HDMARQ LPS Buffer Manager xHIOR xHIOW HINTRQ xHPDIAG TpBias Gen. DS-Link xHDMACK HIORDY IDE Interface IDE Control HDA[2:0] SBP2 & TRAN Control LINK & TRAN Core xCS[1:0] xHDASP PHY Interface SCLK LREQ Link Interface Encoder/Decoder DCLK/TCK DPCO/TMS DST2/TDI DST1/TDO Peripheral TpBias1 R1 R0 D[0:7] LINKON Flash Control TpBias0 VoltageCurrent Gen. CTL[0:1] xHRST xRESET xNMI xINT0 xINT1 CPS S1C33 Mini Core PHY Control Unit Transmitter & Receiver TpA0_P TpA0_N TpB0_P TpB0_N Transmitter & Receiver TpA1_P TpA1_N TpB1_P TpB1_N PS0,PS1,PS2 FlashROM (64KByte) DST0 DSIO GPIO[3:0] xSBRI PLL XI,XO 393.216MHz CLK TESTMD TEST0 TEST1 TEST2 TVEP NOTICE: No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Control Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from anther government agency. All other product names mentioned herein are trademarks and/or registered trademarks of their respective companies. This product uses SuperFlash(R) technology licensed from Silicon Storage Technology, Inc. (c)Seiko Epson Corporation 2003, All rights reserved. SEIKO EPSON CORPORATION ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic devices Website http://www.epsondevice.com/ IC Marketing & Engineering Group ED International Marketing Department 421-8 Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: 042-587-5814 FAX: 042-587-5117 First issue June, 2002 Printed June, 2003 in Japan H