0 XA2C256 CoolRunner-II Automotive CPLD R DS555 (v1.2) June 22, 2009 0 0 Product Specification Features - * AEC-Q100 device qualification and full PPAP support available in both I-grade and extended temperature Q-grade WARNING: Programming temperature range of TA = 0C to +70C. * Guaranteed to meet full electrical specifications over TA = -40C to +105C with TJ Maximum = +125C (Q-grade) Optimized for 1.8V systems Industry's best 0.18 micron CMOS CPLD - Optimized architecture for effective logic synthesis. Refer to the CoolRunnerTM-II family data sheet for architecture description. - Multi-voltage I/O operation -- 1.5V to 3.3V Available in multiple package options - 100-pin VQFP with 80 user I/O - 144-pin TQFP with 118 user I/O - Pb-free only for all packages Advanced system features - Fastest in system programming * 1.8V ISP using IEEE 1532 (JTAG) interface - IEEE1149.1 JTAG Boundary Scan Test - Optional Schmitt-trigger input (per pin) - Unsurpassed low power management * DataGATE enable (DGE) signal control - Two separate I/O banks - RealDigital 100% CMOS product term generation - Flexible clocking modes * Optional DualEDGE triggered registers * Clock divider (divide by 2, 4, 6, 8, 10, 12, 14, 16) * CoolCLOCK - Global signal options with macrocell control * Multiple global clocks with phase selection per macrocell * Multiple global output enables * Global set/reset - Advanced design security - PLA architecture * Superior pinout retention * 100% product term routability across function block - Open-drain output option for Wired-OR and LED drive - Optional bus-hold, 3-state or weak pull-up on selected I/O pins - Optional configurable grounds on unused I/Os - Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels * * * * Hot pluggable Description The CoolRunner-II Automotive 256-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved. This device consists of sixteen Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation. Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. A Schmitt-trigger input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be configured as "direct input" registers to store signals directly from input pins. Clocking is available on a global or Function Block basis. Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state. A global set/reset control line is also available to asynchronously set or reset selected registers during operation. Additional local clock, synchronous clock-enable, asynchronous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-Function Block basis. A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature allows high performance synchronous operation based on lower frequency clocking to help reduce the total power consumption of the device. Circuitry has also been included to divide one externally supplied global clock (GCK2) by eight different selections. This yields divide by even and odd clock frequencies. (c) 2006-2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. DS555 (v1.2) June 22, 2009 Product Specification www.xilinx.com 1 R XA2C256 CoolRunner-II Automotive CPLD The use of the clock divide (division by 2) and DualEDGE flip-flop gives the resultant CoolCLOCK feature. DataGATE is a method to selectively disable inputs of the CPLD that are not of interest during certain points in time. By mapping a signal to the DataGATE function, lower power can be achieved due to reduction in signal switching. Another feature that eases voltage translation is I/O banking. Two I/O banks are available on the CoolRunner-II Automotive 256-macrocell device that permit easy interfacing to 3.3V, 2.5V, 1.8V, and 1.5V devices. The CoolRunner-II Automotive 256-macrocell CPLD is I/O compatible with various I/O standards (see Table 1). This device is also 1.5V I/O compatible with the use of Schmitttrigger inputs. Due to this technology, Xilinx CoolRunner-II Automotive CPLDs achieve both high-performance and low power operation. Supported I/O Standards The CoolRunner-II Automotive 256-macrocell device features LVCMOS and LVTTL I/O implementations. See Table 1 for I/O standard voltages. The LVTTL I/O standard is a general-purpose EIA/JEDEC standard for 3.3V applications that use an LVTTL input buffer and Push-Pull output buffer. The LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications. CoolRunner-II Automotive CPLDs are also 1.5V I/O compatible with the use of Schmitt-trigger inputs. Table 1: I/O Standards for XA2C256 IOSTANDARD Attribute RealDigital Design Technology Xilinx(R) CoolRunner-II Automotive CPLDs are fabricated on a 0.18 micron process technology which is derived from leading edge FPGA product development. CoolRunner-II Automotive CPLDs employ RealDigital, a design technique that makes use of CMOS technology in both the fabrication and design methodology. RealDigital design technology employs a cascade of CMOS gates to implement sum of products instead of traditional sense amplifier methodology. Output VCCIO Input VCCIO LVTTL 3.3 3.3 LVCMOS33 3.3 3.3 LVCMOS25 2.5 2.5 1.8 1.8 1.5 1.5 LVCMOS18 LVCMOS15 (1) (1) LVCMOS15 requires Schmitt-trigger inputs. ICC (mA) 75 50 25 0 0 50 100 150 Frequency (MHz) DS555_01_092106 Figure 1: ICC vs Frequency Table 2: ICC vs Frequency (LVCMOS 1.8V TA = 25C)(1) Frequency (MHz) Typical ICC (mA) 0 30 50 70 100 120 150 0.021 11.68 19.40 27.01 38.18 45.54 56.32 Notes: 1. 16-bit up/down, resettable binary counter (one counter per function block). DS555 (v1.2) June 22, 2009 Product Specification www.xilinx.com 2 R XA2C256 CoolRunner-II Automotive CPLD Absolute Maximum Ratings Symbol Description Value Units VCC Supply voltage relative to ground -0.5 to 2.0 V VCCIO Supply voltage for output drivers -0.5 to 4.0 V VJTAG(2) JTAG input voltage limits -0.5 to 4.0 V VCCAUX JTAG input supply voltage -0.5 to 4.0 V VIN(1) Input voltage relative to ground -0.5 to 4.0 V VTS(1) Voltage applied to 3-state output -0.5 to 4.0 V TSTG(3) Storage Temperature (ambient) -65 to +150 C +125 C TJ Junction Temperature Notes: 1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easiest to achieve. During transitions, the device pins may undershoot to -2.0v or overshoot to +4.5V, provided this over or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. 2. Valid over commercial temperature range. 3. For soldering guidelines and thermal considerations, see the Device Package User Guide. For Pb-free packages, see XAPP427. Recommended Operating Conditions Symbol VCC VCCIO VCCAUX Parameter Min Max Units Industrial TA = -40C to +85C 1.7 1.9 V Q-Grade TA = -40C to +105C TJ Maximum = +125C 1.7 1.9 V Supply voltage for output drivers @ 3.3V operation 3.0 3.6 V Supply voltage for output drivers @ 2.5V operation 2.3 2.7 V Supply voltage for output drivers @ 1.8V operation 1.7 1.9 V Supply voltage for output drivers @ 1.5V operation 1.4 1.6 V JTAG programming 1.7 3.6 V Supply voltage for internal logic and input buffers DC Electrical Characteristics (Over Recommended Operating Conditions) Symbol Parameter Test Conditions Typical Max. Units ICCSB Standby current Industrial VCC = 1.9V, VCCIO = 3.6V 54 300 A ICCSB Standby current Q-grade VCC = 1.9V, VCCIO = 3.6V 54 2.5 mA ICC Dynamic current f = 1 MHz - 3.0 mA f = 50 MHz - 30 mA CJTAG JTAG input capacitance f = 1 MHz - 10 pF CCLK Global clock input capacitance f = 1 MHz - 12 pF CIO I/O capacitance f = 1 MHz - 10 pF IIL (2) Input leakage current VIN = 0V or VCCIO to 3.9V - 10 A (2) I/O High-Z leakage VIN = 0V or VCCIO to 3.9V - 10 A IIH Notes: 1. 16-bit up/down, resettable binary counter (one counter per function block) tested at VCC= VCCIO = 1.9V DS555 (v1.2) June 22, 2009 Product Specification www.xilinx.com 3 R XA2C256 CoolRunner-II Automotive CPLD LVCMOS 3.3V and LVTTL 3.3V DC Voltage Specifications Symbol Parameter Test Conditions Min. Max. Units VCCIO Input source voltage - 3.0 3.6 V VIH High level input voltage - 2 3.9 V VIL Low level input voltage - -0.3 0.8 V VOH High level output voltage, Industrial grade IOH = -8 mA, VCCIO = 3V VCCIO - 0.4V - V IOH = -0.1 mA, VCCIO = 3V VCCIO - 0.2V - V IOH = -4 mA, VCCIO = 3V VCCIO - 0.4V - V IOH = -0.1 mA, VCCIO = 3V VCCIO - 0.2V - V IOL = 8 mA, VCCIO = 3V - 0.4 V IOL = 0.1 mA, VCCIO = 3V - 0.2 V IOL = 4 mA, VCCIO = 3V - 0.4 V IOL = 0.1 mA, VCCIO = 3V - 0.2 V High level output voltage, Q-grade VOL High level output voltage, Industrial grade High level output voltage, Q-grade LVCMOS 2.5V DC Voltage Specifications Symbol VCCIO Parameter Test Conditions Min. Max. Units - 2.3 2.7 V Input source voltage 0.3(1) VIH High level input voltage - 1.7 VIL Low level input voltage - -0.3 0.7 V VOH High level output voltage, Industrial grade IOH = -8 mA, VCCIO = 2.3V VCCIO - 0.4V - V IOH = -0.1 mA, VCCIO = 2.3V VCCIO - 0.2V - V IOH = -4 mA, VCCIO = 2.3V VCCIO - 0.4V - V IOH = -0.1 mA, VCCIO = 2.3V VCCIO - 0.2V - V IOL = 8 mA, VCCIO = 2.3V - 0.4 V IOL = 0.1 mA, VCCIO = 2.3V - 0.2 V IOL = 4 mA, VCCIO = 2.3V - 0.4 V IOL = 0.1 mA, VCCIO = 2.3V - 0.2 V High level output voltage, Q-grade VOL High level output voltage, Industrial grade High level output voltage, Q-grade VCCIO + V 1. The VIH Max value represents the JEDEC specification for LVCMOS25. The CoolRunner-II input buffer can tolerate up to 3.9V without physical damage. LVCMOS 1.8V DC Voltage Specifications Symbol Parameter Test Conditions Min. Max. Units VCCIO Input source voltage - 1.7 1.9 V VIH High level input voltage - 0.65 x VCCIO VCCIO + 0.3(1) V VIL Low level input voltage - -0.3 0.35 x VCCIO V VOH High level output voltage, Industrial grade IOH = -8 mA, VCCIO = 1.7V VCCIO - 0.45 - V IOH = -0.1 mA, VCCIO = 1.7V VCCIO - 0.2 - V IOH = -4 mA, VCCIO = 1.7V VCCIO - 0.45 - V IOH = -0.1 mA, VCCIO = 1.7V VCCIO - 0.2 - V High level output voltage, Q-grade DS555 (v1.2) June 22, 2009 Product Specification www.xilinx.com 4 R XA2C256 CoolRunner-II Automotive CPLD Symbol VOL Parameter Test Conditions Min. Max. Units High level output voltage, Industrial grade IOL = 8 mA, VCCIO = 1.7V - 0.45 V IOL = 0.1 mA, VCCIO = 1.7V - 0.2 V IOL = 4 mA, VCCIO = 1.7V - 0.45 V IOL = 0.1 mA, VCCIO = 1.7V - 0.2 V High level output voltage, Q-grade 1. The VIH Max value represents the JEDEC specification for LVCMOS18. The CoolRunner-II input buffer can tolerate up to 3.9V without physical damage. LVCMOS 1.5V DC Voltage Specifications(1) Symbol Parameter Test Conditions Min. Max. Units VCCIO Input source voltage - 1.4 1.6 V VT+ Input hysteresis threshold voltage - 0.5 x VCCIO 0.8 x VCCIO V - 0.2 x VCCIO 0.5 x VCCIO V IOH = -8 mA, VCCIO = 1.4V VCCIO - 0.45 - V IOH = -0.1 mA, VCCIO = 1.4V VCCIO - 0.2 - V IOH = -4 mA, VCCIO = 1.4V VCCIO - 0.45 - V IOH = -0.1 mA, VCCIO = 1.4V VCCIO - 0.2 - V IOL = 8 mA, VCCIO = 1.4V - 0.4 V IOL = 0.1 mA, VCCIO = 1.4V - 0.2 V IOL = 4 mA, VCCIO = 1.4V - 0.4 V IOL = 0.1 mA, VCCIO = 1.4V - 0.2 V Test Conditions Min. Max. Units VTVOH High level output voltage, Industrial grade High level output voltage, Q-grade VOL High level output voltage, Industrial grade High level output voltage, Q-grade Notes: 1. Hysteresis used on 1.5V inputs. Schmitt Trigger Input DC Voltage Specifications Symbol Parameter VCCIO Input source voltage - 1.4 3.9 V VT+ Input hysteresis threshold voltage - 0.5 x VCCIO 0.8 x VCCIO V - 0.2 x VCCIO 0.5 x VCCIO V VT- AC Electrical Characteristics Over Recommended Operating Conditions -7 Symbol Parameter -8 Min. Max. Min. Max. Units TPD1 Propagation delay single p-term - 7.0 - 7.0 ns TPD2 Propagation delay OR array - 7.5 - 7.5 ns TSUD Direct input register clock setup time 3.0 - 3.0 - ns TSU1 Setup time (single p-term) 2.8 - 3.4 - ns TSU2 Setup time (OR array) 3.3 - 3.9 - ns THD Direct input register hold time 0 - 0.4 - ns TH P-term hold time 0 - 0.4 - ns TCO Clock to output - 6.0 - 6.0 ns DS555 (v1.2) June 22, 2009 Product Specification www.xilinx.com 5 R XA2C256 CoolRunner-II Automotive CPLD -7 Symbol FTOGGLE (1) Parameter -8 Min. Max. Min. Max. Units Internal toggle rate - 300 - 300 MHz FSYSTEM1 (2) Maximum system frequency - 152 - 139 MHz FSYSTEM2 (2) Maximum system frequency - 141 - 130 MHz FEXT1 (3) Maximum external frequency - 114 - 106 MHz FEXT2 (3) Maximum external frequency - 108 - 101 MHz TPSUD Direct input register p-term clock setup time 1.7 - 2.0 - ns TPSU1 P-term clock setup time (single p-term) 1.5 - 1.9 - ns TPSU2 P-term clock setup time (OR array) 2.0 - 2.4 - ns TPHD Direct input register p-term clock hold time 1.2 - 1.8 - ns TPH P-term clock hold 1.0 - 1.3 - ns TPCO P-term clock to output - 7.3 8.4 ns TOE/TOD Global OE to output enable/disable - 7.0 - 7.0 ns TPOE/TPOD P-term OE to output enable/disable - 8.0 - 9.1 ns TMOE/TMOD Macrocell driven OE to output enable/disable - 9.9 - 9.9 ns TPAO P-term set/reset to output valid - 8.1 - 8.6 ns TAO Global set/reset to output valid - 7.6 - 7.6 ns TSUEC Register clock enable setup time 3.1 - 3.5 - ns THEC Register clock enable hold time 0.0 - 0.0 - ns TCW Global clock pulse width High or Low 1.6 - 1.6 - ns TPCW P-term pulse width High or Low 7.5 - 7.5 - ns TAPRPW Asynchronous preset/reset pulse width (High or Low) 7.5 - 7.5 - ns TDGSU Set-up before DataGATE latch assertion 0.0 - 0.0 - ns TDGH Hold to DataGATE latch assertion 6.0 - 6.0 - ns TDGR DataGATE recovery to new data - 9.0 - 9.3 ns TDGW DataGATE low pulse width 3.5 - 3.5 - ns TCDRSU CDRST setup time before falling edge GCLK2 2.0 - 2.0 - ns Hold time CDRST after falling edge GCLK2 0.0 - 0.0 - ns - 150 - 150 s TCDRH TCONFIG (4) Configuration time Notes: 1. FTOGGLE is the maximum clock frequency to which a T flip-flop can reliably toggle (see the CoolRunner-II Automotive CPLD family data sheet for more information). 2. FSYSTEM1 (1/TCYCLE) is the internal operating frequency for a device fully populated with one 16-bit counter through one p-term per macrocell while FSYSTEM2 is through the OR array. 3. FEXT1 (1/TSU1+TCO) is the maximum external frequency using one p-term while FEXT2 is through the OR array. 4. Typical configuration current during TCONFIG is approximately 7.7 mA. DS555 (v1.2) June 22, 2009 Product Specification www.xilinx.com 6 R XA2C256 CoolRunner-II Automotive CPLD ( Internal Timing Parameters -7 Parameter(2) Symbol -8 Min. Max. Min. Max. Units Buffer Delays TIN Input buffer delay - 2.6 - 2.6 ns TDIN Direct data register input delay - 3.9 - 3.3 ns TGCK Global Clock buffer delay - 2.7 - 2.7 ns TGSR Global set/reset buffer delay - 3.5 - 4.1 ns TGTS Global 3-state buffer delay - 3.0 - 3.0 ns TOUT Output buffer delay - 2.6 - 2.6 ns TEN Output buffer enable/disable delay - 4.0 - 4.0 ns TCT Control term delay - 1.4 - 2.5 ns TLOGI1 Single P-term delay adder - 1.1 - 1.1 ns TLOGI2 Multiple P-term delay adder - 0.5 - 0.5 ns TPDI Input to output valid - 0.7 - 0.7 ns TLDI Setup before clock (transparent latch) - 2.5 - 2.5 ns TSUI Setup before clock 1.8 - 2.4 - ns THI Hold after clock 0.0 - 0.0 - ns TECSU Enable clock setup time 1.8 - 1.1 - ns TECHO Enable clock hold time 0.0 - 0.0 - ns TCOI Clock to output valid - 0.7 - 0.7 ns TAOI Set/reset to output valid - 1.5 - 0.9 ns TF Feedback delay - 3.0 - 3.0 ns TOEM Macrocell to global OE delay - 2.5 - 2.5 ns P-term Delays Macrocell Delay Feedback Delays I/O Standard Time Adder Delays 1.5V CMOS THYS15 Hysteresis input adder - 4.0 - 4.0 ns TOUT15 Output adder - 1.0 - 1.0 ns TSLEW15 Output slew rate adder - 5.0 - 5.0 ns I/O Standard Time Adder Delays 1.8V CMOS THYS18 Hysteresis input adder - 3.0 - 3.0 ns TOUT18 Output adder - 0.0 - 0.0 ns TSLEW Output slew rate adder - 4.0 - 4.0 ns DS555 (v1.2) June 22, 2009 Product Specification www.xilinx.com 7 R XA2C256 CoolRunner-II Automotive CPLD Internal Timing Parameters (Continued) -7 Parameter(2) Symbol -8 Min. Max. Min. Max. Units I/O Standard Time Adder Delays 2.5V CMOS TIN25 Standard input adder - 0.7 - 0.7 ns THYS25 Hysteresis input adder - 3.0 - 3.0 ns TOUT25 Output adder - 1.0 - 1.0 ns TSLEW25 Output slew rate adder - 4.0 - 4.0 ns I/O Standard Time Adder Delays 3.3V CMOS/TTL TIN33 Standard input adder - 0.7 - 0.7 ns THYS33 Hysteresis input adder - 3.0 - 3.0 ns TOUT33 Output adder - 1.6 - 1.6 ns TSLEW33 Output slew rate adder - 4.0 - 4.0 ns Notes: 1. 1.5 ns input pin signal rise/fall. Switching Characteristics AC Test Circuit VCC VCC = VCCIO = 1.8V, T = 25oC 5.5 R1 Device Under Test 5.0 Test Point R2 CL TPD2 (ns) 4.5 R1 R2 CL 268 235 35 pF LVCMOS33 275 275 35 pF LVCMOS25 188 188 35pF LVCMOS18 112.5 112.5 35pF LVCMOS15 150 150 35pF Output Type LVTTL33 4.0 3.5 CL includes test fixtures and probe capacitance. 3.0 1 2 4 8 16 1.5 nsec maximum rise/fall times on inputs. DS ACT 08 14 02 Figure 3: AC Load Circuit Number of Outputs Switching DS092_02_092302 Figure 2: Derating Curve for TPD DS555 (v1.2) June 22, 2009 Product Specification www.xilinx.com 8 R XA2C256 CoolRunner-II Automotive CPLD 3.3V 60 IO (Output Current mA) 50 2.5V 40 1.8V Iol 30 20 1.5V 10 0 0 .5 1.0 1.5 2.0 VO (Output Volts) 2.5 3.0 3.5 XC256_VoIo_all_020703 Figure 4: Typical I/V Curve for XA2C256 DS555 (v1.2) June 22, 2009 Product Specification www.xilinx.com 9 R XA2C256 CoolRunner-II Automotive CPLD Pin Descriptions (Continued) 11 Pin Descriptions Function Block Macrocell VQG100 TQG144 I/O Bank Function Block Macrocell VQG100 TQG144 I/O Bank 1 1 - - 2 3 1 - 136 2 1 2 - - 2 3 2 - 135 2 1(GSR) 3 99 143 2 3 3 - 134 2 1 4 - 142 2 3 4 - - 2 1 5 - - 2 3 5 93 133 2 1 6 97 140 2 3 6 1 7 - - - 3 7 - - - 1 8 - - - 3 8 - - - 1 9 - - - 3 9 - - - 1 10 - - - 3 10 - - - 1 11 - - - 3 11 - - - 1 12 96 139 2 3 12 92 - 2 1 13 95 138 2 3 13 - - 2 1 14 94 137 2 3 14 91 132 2 1 15 - - 2 3 15 - - 2 1 16 - - 2 3 16 90 131 2 2(GTS2) 1 1 2 2 4 1 8 11 2 2 2 - - 2 4 2 9 12 2 2(GTS3) 3 2 3 2 4 3 10 13 2 2 4 - 4 2 4 4 - 14 2 2(GTS0) 5 3 5 2 4 5 11 15 2 2 6 - - 2 4 6 12 16 2 2 7 - - - 4 7 - - - 2 8 - - - 4 8 - - - 2 9 - - - 4 9 - - - 2 10 - - - 4 10 - - - 2 11 - - - 4 11 - - - 2(GTS1) 12 4 6 2 4 12 - 17 2 2 13 - 7 2 4 13 13 - 2 2 14 6 9 2 4 14 - 18 2 2 15 7 10 2 4 15 - - 2 2 16 - - 2 4 16 - - 2 DS555 (v1.2) June 22, 2009 Product Specification 2 www.xilinx.com 10 R XA2C256 CoolRunner-II Automotive CPLD Pin Descriptions (Continued) Pin Descriptions (Continued) Function Block Macrocell VQG100 TQG144 I/O Bank Function Block Macrocell VQG100 TQG144 I/O Bank 5 1 - - 1 7 1 - - 1 5 2 - 33 1 7 2 - - 1 5 3 - - 1 7 3 - - 1 5(GCK1) 4 23 32 1 7 4 - - 1 5 5 31 1 7 5 19 26 1 5(GCK0) 6 22 30 1 7 6 18 25 1 5 7 - - - 7 7 - - - 5 8 - - - 7 8 - - - 5 9 - - - 7 9 - - - 5 10 - - - 7 10 - - - 5 11 - - - 7 11 17 24 1 5 12 - - 1 7 12 16 23 1 5 13 - - 1 7 13 15 22 1 5 14 - 28 1 7 14 14 21 1 5 15 - - 1 7 15 - 20 1 5 16 - - 1 7 16 - 19 1 6 1 - 34 1 8 1 - 44 1 6 (CDRST) 2 24 35 1 8 2 - 45 1 6 3 - - 1 8 3 - 46 1 6(GCK2) 4 27 38 1 8 4 - - 1 6 5 - - 1 8 5 - 48 1 6 6 - - 1 8 6 32 49 1 6 7 - - - 8 7 - - - 6 8 - - - 8 8 - - - 6 9 - - - 8 9 - - - 6 10 - - - 8 10 - - - 6 11 - - - 8 11 33 50 1 6(DGE) 12 28 39 1 8 12 34 51 1 6 13 - 40 1 8 13 35 52 1 6 14 29 41 1 8 14 36 - 1 6 15 - 42 1 8 15 37 - 1 6 16 30 43 1 8 16 - - 1 DS555 (v1.2) June 22, 2009 Product Specification www.xilinx.com 11 R XA2C256 CoolRunner-II Automotive CPLD Pin Descriptions (Continued) Pin Descriptions (Continued) Function Block Macrocell VQG100 TQG144 I/O Bank Function Block Macrocell VQG100 TQG144 I/O Bank 9 1 78 112 2 11 1 - - 2 9 2 79 113 2 11 2 - - 2 9 3 - - 2 11 3 - - 2 9 4 80 114 2 11 4 - - 2 9 5 2 11 5 - 120 2 9 6 81 115 2 11 6 - 121 2 9 7 - - - 11 7 - - - 9 8 - - - 11 8 - - - 9 9 - - - 11 9 - - - 9 10 - - - 11 10 - - - 9 11 - - 2 11 11 85 124 2 9 12 82 116 2 11 12 86 125 2 9 13 - 117 2 11 13 87 126 2 9 14 - 118 2 11 14 89 128 2 9 15 - 119 2 11 15 - 129 2 9 16 - - 2 11 16 - 130 2 10 1 77 111 2 12 1 - - 2 10 2 76 110 2 12 2 - 100 2 10 3 74 107 2 12 3 - - 2 10 4 73 106 2 12 4 - - 2 10 5 72 105 2 12 5 - - 2 10 6 71 104 2 12 6 - - 2 10 7 - - - 12 7 - - - 10 8 - - - 12 8 - - - 10 9 - - - 12 9 - - - 10 10 - - - 12 10 - - - 10 11 2 12 11 68 98 2 10 12 70 103 2 12 12 - 97 2 10 13 - - 2 12 13 67 96 2 10 14 - 102 2 12 14 66 95 2 10 15 - - 2 12 15 65 94 2 10 16 - 101 2 12 16 - - 2 DS555 (v1.2) June 22, 2009 Product Specification www.xilinx.com 12 R XA2C256 CoolRunner-II Automotive CPLD Pin Descriptions (Continued) Pin Descriptions (Continued) Function Block Macrocell VQG100 TQG144 I/O Bank Function Block Macrocell VQG100 TQG144 I/O Bank 13 1 - 75 1 15 1 - - 1 13 2 53 76 1 15 2 - 83 1 13 3 - 77 1 15 3 - - 1 13 4 54 - 1 15 4 - - 1 13 5 - 78 1 15 5 - - 1 13 6 55 79 1 15 6 - - 1 13 7 - - - 15 7 - - - 13 8 - - - 15 8 - - - 13 9 - - - 15 9 - - - 13 10 - - - 15 10 - - - 13 11 - - - 15 11 58 85 1 13 12 - 80 1 15 12 59 86 1 13 13 56 81 1 15 13 60 87 1 13 14 - 82 1 15 14 61 88 1 13 15 - - 1 15 15 63 91 1 13 16 - - 1 15 16 64 92 1 14 1 52 74 1 16 1 - - 1 14 2 - 71 1 16 2 - - 1 14 3 50 70 1 16 3 - - 1 14 4 - 69 1 16 4 - - 1 14 5 49 - 1 16 5 43 60 1 14 6 - 68 1 16 6 42 59 1 14 7 - - - 16 7 - - - 14 8 - - - 16 8 - - - 14 9 - - - 16 9 - - - 14 10 - - - 16 10 - - - 14 11 - - - 16 11 41 58 1 14 12 - - 1 16 12 40 57 1 14 13 - 66 1 16 13 39 56 1 14 14 46 64 1 16 14 - - 1 14 15 44 - 1 16 15 - 54 1 14 16 - 61 1 16 16 - 53 1 Notes: 1. GTS = global output enable, GSR = global reset/set, GCK = global clock, CDRST = clock divide reset, DGE = DataGATE enable. 2. GTS, GSR and GCK pins can be used for general purpose I/O. DS555 (v1.2) June 22, 2009 Product Specification www.xilinx.com 13 R XA2C256 CoolRunner-II Automotive CPLD XA2C256 JTAG, Power/Ground, No Connect Pins and Total User I/O Pin Type VQG100 TQG144 TCK 48 67 TDI 45 63 TDO 83 122 TMS 47 65 VCCAUX (JTAG supply voltage) 5 8 26, 57 1, 37, 84 Power Bank 1 I/O (VCCIO1) 20, 38, 51 27, 55, 73, 93 Power Bank 2 I/O (VCCIO2) 88, 98 109, 127, 141 21, 25, 31, 62, 69, 75, 84, 100 29, 36, 47, 62, 72, 89, 90, 99, 108, 123, 144 No connects - - Total user I/O 80 118 Power internal (VCC) Ground Ordering Information Part Number Pin/Ball Spacing JC JA (C/Watt) (C/Watt) Package Type Industrial (I)(1) Package Body Dimensions I/O Hi-T (Q) XA2C256-7VQG100I 0.5mm 43.1 10.9 Very Thin Quad Flat Pack; Pb-free 14mm x 14mm 80 I XA2C256-8VQG100Q 0.5mm 43.1 10.9 Very Thin Quad Flat Pack; Pb-free 14mm x 14mm 80 Q XA2C256-7TQG144I 0.5mm 37.2 7.2 Thin Quad Flat Pack; Pb-free 20mm x 20mm 118 I XA2C256-8TQG144Q 0.5mm 37.2 7.2 Thin Quad Flat Pack; Pb-free 20mm x 20mm 118 Q Notes: 1. I = Industrial (TA = -40C to +85C); Q = Automotive (TA = -40C to +105C with TJ Maximum = +125C). Pb-Free Example: XA2C256 -7 TQ G 144 I Device Speed Grade Package Type Pb-Free Number of Pins Temperature Range DS555 (v1.2) June 22, 2009 Product Specification www.xilinx.com 14 R XA2C256 CoolRunner-II Automotive CPLD Device Part Marking R Device Type Package Speed Operating Range XA2Cxxx TQG144 7I This line not related to device part number Part Marking for all non chip scale packages Figure 5: Sample Package with Part Marking DS555 (v1.2) June 22, 2009 Product Specification www.xilinx.com 15 R VCCIO2 I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO2 I/O I/O I/O GND TDO I/O I/O I/O I/O I/O I/O I/O 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VQG100 Top View 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 GND I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O VCCIO1 VCC I/O(2) I/O(5) I/O I/O GND I/O I/O I/O I/O I/O I/O VCCIO1 I/O I/O I/O I/O I/O I/O TDI I/O TMS TCK I/O I/O I/O(1) I/O(1) I/O(1) I/O(1) VAUX I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO1 GND I/O(2) I/O(2) I/O(4) GND 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 GND I/O(3) XA2C256 CoolRunner-II Automotive CPLD (1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset (4) - Clock Divide Reset (5) - Data Gate Figure 6: VQG100 Very Thin Quad Flat Pack DS555 (v1.2) June 22, 2009 Product Specification www.xilinx.com 16 R 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 GND I/O(3) I/O VCCIO2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO2 I/O I/O I/O GND TDO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO2 XA2C256 CoolRunner-II Automotive CPLD VCC I/O(1) I/O(1) I/O I/O(1) I/O(1) I/O VAUX I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 TQG144 Top View GND I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O VCCIO1 I/O I/O GND GND I/O I/O I/O I/O VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCCIO1 VCCIO1 I/O I/O I/O I/O I/O I/O GND TDI I/O TMS I/O TCK I/O I/O I/O I/O GND VCC I/O(2) I/O(5) I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 VCCIO1 I/O GND I/O(2) I/O I/O(2) I/O I/O I/O(4) GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 (1) - Global Output Enable (2) - Global Clock (3) - Global Set/Reset (4) - Clock Divide Reset (5) - DataGATE Enable Figure 7: TQG144 Thin Quad Flat Pack CoolRunner-II Automotive Requirements and Recommendations Requirements The following requirements are for all automotive applications: 1. Use a monotonic, fast ramp power supply to power up CoolRunner-II. A VCC ramp time of less than 1 ms is required. 2. Do not float I/O pins during device operation. Floating I/O pins can increase ICC as input buffers will draw 1-2 mA per floating input. In addition, when I/O pins are floated, noise can propagate to the center of the CPLD. DS555 (v1.2) June 22, 2009 Product Specification I/O pins should be appropriately terminated with bushold or pull-up. Unused I/Os can also be configured as CGND (programmable GND). 3. Do not drive I/O pins without VCC/VCCIO powered. 4. Sink current when driving LEDs. Because all Xilinx CPLDs have N-channel pull-down transistors on outputs, it is required that an LED anode is sourced through a resistor externally to VCC. Consequently, this will give the brightest solution. www.xilinx.com 17 R XA2C256 CoolRunner-II Automotive CPLD 5. Avoid pull-down resistors. Always use external pull-up resistors if external termination is required. This is because the CoolRunner-II Automotive CPLD, which includes some I/O driving circuits beyond the input and output buffers, may have contention with external pulldown resistors, and, consequently, the I/O will not switch as expected. 6. Do not drive I/Os pins above the VCCIO assigned to its I/O bank. a. The current flow can go into VCCIO and affect a user voltage regulator. b. c. It can also increase undesired leakage current associated with the device. If done for too long, it can reduce the life of the device. 7. Do not rely on the I/O states before the CPLD configures. During power up, the CPLD I/Os may be affected by internal or external signals. 8. Use a voltage regulator which can provide sufficient current during device power up. As a rule of thumb, the regulator needs to provide at least three times the peak current while powering up a CPLD in order to guarantee the CPLD can configure successfully. 9. Ensure external JTAG terminations for TMS, TCK, TDI, TDO should comply with the IEEE 1149.1. All Xilinx CPLDs have internal weak pull-ups on TDI, TMS, and TCK. 10. Attach all CPLD VCC and GND pins in order to have necessary power and ground supplies around the CPLD. 11. Decouple all VCC and VCCIO pins with capacitors of 0.01 F and 0.1 F closest to the pins for each VCC/VCCIO-GND pair. 12. Configure I/Os properly. CoolRunner-II Automotive CPLDs have I/O banks; therefore, signals must be assigned to appropriate banks (LVCMOS33, LVCMOS18 ...). Recommendations 1. Use strict synchronous design (only one clocking event) if possible. A synchronous system is more robust than an asynchronous one. 2. Include JTAG stakes on the PCB. JTAG stakes can be used to test the part on the PCB. They add benefit in reprogramming part on the PCB, inspecting chip internals with INTEST, identifying stuck pins, and inspecting programming patterns (if not secured). 3. CoolRunner-II Automotive CPLDs work with any power sequence, but it is preferable to power the VCCI (internal VCC) before the VCCIO for the applications in which any glitches from device I/Os are unwanted. 4. Do not disregard report file warnings. Software identifies potential problems when compiling, so the report file is worth inspecting to see exactly how your design is mapped onto the logic. 5. Understand the Timing Report. This report file provides a speed summary along with warnings. Read the timing file (*.tim) carefully. Analyze key signal chains to determine limits to given clock(s) based on logic analysis. 6. Review Fitter Report equations. Equations can be shown in ABEL-like format, or can also be displayed in Verilog or VHDL formats. The Fitter Report also includes switch settings that are very informative of other device behaviors. 7. Let design software define pinouts if possible. Xilinx CPLD software works best when it selects the I/O pins and manages resources for users. It can spread signals around and improve pin-locking. If users must define pins, plan resources in advance. 8. Perform a post-fit simulation for all speeds to identify any possible problems (such as race conditions) that might occur when fast-speed silicon is used instead of slow-speed silicon. 9. Distribute SSOs (Simultaneously Switching Outputs) evenly around the CPLD to reduce switching noise. 10. Terminate high speed outputs to eliminate noise caused by very fast rising/falling edges. The following recommendations are for all automotive applications. Additional Information Additional information is available for the following CoolRunner-II topics: * * * * * * XAPP784: Bulletproof CPLD Design Practices XAPP375: Timing Model XAPP376: Logic Engine XAPP378: Advanced Features XAPP382: I/O Characteristics XAPP389: Powering CoolRunner-II * XAPP399: Assigning VREF Pins DS555 (v1.2) June 22, 2009 Product Specification These and other application notes can be accessed at: CoolRunner-II Documentation Package specifications can be accessed at: Device Packages www.xilinx.com 18 R XA2C256 CoolRunner-II Automotive CPLD Revision History The following table shows the revision history for this document. Date Version Revision 10/31/06 1.0 Initial Xilinx release. 05/05/07 1.1 Change to VIH specification for 3.3V, 2.5V and 1.8V LVCMOS. 06/22/09 1.2 Updated Figure 7. Notice of Disclaimer THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS") ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO APPLICABLE LAWS AND REGULATIONS. Automotive Applications Disclaimer XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III) USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN SUCH APPLICATIONS. DS555 (v1.2) June 22, 2009 Product Specification www.xilinx.com 19